Revision d537cf6c hw/pl050.c

b/hw/pl050.c
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    uint32_t cr;
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    uint32_t clk;
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    uint32_t last;
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    void *pic;
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    int pending;
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    int irq;
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    qemu_irq irq;
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    int is_mouse;
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} pl050_state;
23 22 

  		





  ......




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    s->pending = level;


  		





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    raise = (s->pending && (s->cr & 0x10) != 0)


  		





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            || (s->cr & 0x08) != 0;


  		





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    pic_set_irq_new(s->pic, s->irq, raise);


  		





  
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    qemu_set_irq(s->irq, raise);


  		





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}


  		





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static uint32_t pl050_read(void *opaque, target_phys_addr_t offset)


  		





  ......




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   pl050_write


  		





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};


  		





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void pl050_init(uint32_t base, void *pic, int irq, int is_mouse)


  		





  
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void pl050_init(uint32_t base, qemu_irq irq, int is_mouse)


  		





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{


  		





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    int iomemtype;


  		





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    pl050_state *s;


  		





  ......




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                                       pl050_writefn, s);


  		





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    cpu_register_physical_memory(base, 0x00000fff, iomemtype);


  		





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    s->base = base;


  		





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    s->pic = pic;


  		





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    s->irq = irq;


  		





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    s->is_mouse = is_mouse;


  		





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    if (is_mouse)


  		












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