| 278 |
278 |
tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
|
| 279 |
279 |
}
|
| 280 |
280 |
|
| 281 |
|
static inline void store_reg16(int reg, TCGv_i32 v)
|
| 282 |
|
{
|
| 283 |
|
/* 16 bit register writes keep the upper bytes */
|
| 284 |
|
#if HOST_LONG_BITS == 32
|
| 285 |
|
tcg_gen_deposit_i32(TCGV_LOW(regs[reg]), TCGV_LOW(regs[reg]), v, 0, 16);
|
| 286 |
|
#else
|
| 287 |
|
tcg_gen_deposit_i64(regs[reg], regs[reg],
|
| 288 |
|
MAKE_TCGV_I64(GET_TCGV_I32(v)), 0, 16);
|
| 289 |
|
#endif
|
| 290 |
|
}
|
| 291 |
|
|
| 292 |
281 |
static inline void store_freg32(int reg, TCGv_i32 v)
|
| 293 |
282 |
{
|
| 294 |
283 |
/* 32 bit register writes keep the lower half */
|
| ... | ... | |
| 1022 |
1011 |
op, r1, x2, b2, d2);
|
| 1023 |
1012 |
addr = get_address(s, x2, b2, d2);
|
| 1024 |
1013 |
switch (op) {
|
| 1025 |
|
case 0xf: /* LRVG R1,D2(X2,B2) [RXE] */
|
| 1026 |
|
tmp2 = tcg_temp_new_i64();
|
| 1027 |
|
tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
|
| 1028 |
|
tcg_gen_bswap64_i64(tmp2, tmp2);
|
| 1029 |
|
store_reg(r1, tmp2);
|
| 1030 |
|
tcg_temp_free_i64(tmp2);
|
| 1031 |
|
break;
|
| 1032 |
1014 |
case 0x17: /* LLGT R1,D2(X2,B2) [RXY] */
|
| 1033 |
1015 |
tmp2 = tcg_temp_new_i64();
|
| 1034 |
1016 |
tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
|
| ... | ... | |
| 1036 |
1018 |
store_reg(r1, tmp2);
|
| 1037 |
1019 |
tcg_temp_free_i64(tmp2);
|
| 1038 |
1020 |
break;
|
| 1039 |
|
case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
|
| 1040 |
|
tmp2 = tcg_temp_new_i64();
|
| 1041 |
|
tmp32_1 = tcg_temp_new_i32();
|
| 1042 |
|
tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
|
| 1043 |
|
tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
|
| 1044 |
|
tcg_temp_free_i64(tmp2);
|
| 1045 |
|
tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
|
| 1046 |
|
store_reg32(r1, tmp32_1);
|
| 1047 |
|
tcg_temp_free_i32(tmp32_1);
|
| 1048 |
|
break;
|
| 1049 |
|
case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
|
| 1050 |
|
tmp2 = tcg_temp_new_i64();
|
| 1051 |
|
tmp32_1 = tcg_temp_new_i32();
|
| 1052 |
|
tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
|
| 1053 |
|
tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
|
| 1054 |
|
tcg_temp_free_i64(tmp2);
|
| 1055 |
|
tcg_gen_bswap16_i32(tmp32_1, tmp32_1);
|
| 1056 |
|
store_reg16(r1, tmp32_1);
|
| 1057 |
|
tcg_temp_free_i32(tmp32_1);
|
| 1058 |
|
break;
|
| 1059 |
1021 |
case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
|
| 1060 |
1022 |
tmp32_1 = load_reg32(r1);
|
| 1061 |
1023 |
tmp2 = tcg_temp_new_i64();
|
| ... | ... | |
| 1861 |
1823 |
tcg_temp_free_i32(tmp32_1);
|
| 1862 |
1824 |
tcg_temp_free_i64(tmp);
|
| 1863 |
1825 |
break;
|
| 1864 |
|
case 0x0f: /* LRVGR R1,R2 [RRE] */
|
| 1865 |
|
tcg_gen_bswap64_i64(regs[r1], regs[r2]);
|
| 1866 |
|
break;
|
| 1867 |
|
case 0x1f: /* LRVR R1,R2 [RRE] */
|
| 1868 |
|
tmp32_1 = load_reg32(r2);
|
| 1869 |
|
tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
|
| 1870 |
|
store_reg32(r1, tmp32_1);
|
| 1871 |
|
tcg_temp_free_i32(tmp32_1);
|
| 1872 |
|
break;
|
| 1873 |
1826 |
case 0x83: /* FLOGR R1,R2 [RRE] */
|
| 1874 |
1827 |
tmp = load_reg(r2);
|
| 1875 |
1828 |
tmp32_1 = tcg_const_i32(r1);
|
| ... | ... | |
| 3023 |
2976 |
return NO_EXIT;
|
| 3024 |
2977 |
}
|
| 3025 |
2978 |
|
|
2979 |
static ExitStatus op_rev16(DisasContext *s, DisasOps *o)
|
|
2980 |
{
|
|
2981 |
tcg_gen_bswap16_i64(o->out, o->in2);
|
|
2982 |
return NO_EXIT;
|
|
2983 |
}
|
|
2984 |
|
|
2985 |
static ExitStatus op_rev32(DisasContext *s, DisasOps *o)
|
|
2986 |
{
|
|
2987 |
tcg_gen_bswap32_i64(o->out, o->in2);
|
|
2988 |
return NO_EXIT;
|
|
2989 |
}
|
|
2990 |
|
|
2991 |
static ExitStatus op_rev64(DisasContext *s, DisasOps *o)
|
|
2992 |
{
|
|
2993 |
tcg_gen_bswap64_i64(o->out, o->in2);
|
|
2994 |
return NO_EXIT;
|
|
2995 |
}
|
|
2996 |
|
| 3026 |
2997 |
static ExitStatus op_rll32(DisasContext *s, DisasOps *o)
|
| 3027 |
2998 |
{
|
| 3028 |
2999 |
TCGv_i32 t1 = tcg_temp_new_i32();
|
| ... | ... | |
| 3576 |
3547 |
tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
|
| 3577 |
3548 |
}
|
| 3578 |
3549 |
|
|
3550 |
static void wout_r1_16(DisasContext *s, DisasFields *f, DisasOps *o)
|
|
3551 |
{
|
|
3552 |
int r1 = get_field(f, r1);
|
|
3553 |
tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
|
|
3554 |
}
|
|
3555 |
|
| 3579 |
3556 |
static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o)
|
| 3580 |
3557 |
{
|
| 3581 |
3558 |
store_reg32_i64(get_field(f, r1), o->out);
|
| ... | ... | |
| 3918 |
3895 |
tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
|
| 3919 |
3896 |
}
|
| 3920 |
3897 |
|
|
3898 |
static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
|
|
3899 |
{
|
|
3900 |
in2_a2(s, f, o);
|
|
3901 |
tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
|
|
3902 |
}
|
|
3903 |
|
| 3921 |
3904 |
static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
|
| 3922 |
3905 |
{
|
| 3923 |
3906 |
in2_a2(s, f, o);
|