root / hw / musicpal.c @ d60efc6b
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1 | 24859b68 | balrog | /*
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2 | 24859b68 | balrog | * Marvell MV88W8618 / Freecom MusicPal emulation.
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3 | 24859b68 | balrog | *
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4 | 24859b68 | balrog | * Copyright (c) 2008 Jan Kiszka
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5 | 24859b68 | balrog | *
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6 | 24859b68 | balrog | * This code is licenced under the GNU GPL v2.
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7 | 24859b68 | balrog | */
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8 | 24859b68 | balrog | |
9 | b47b50fa | Paul Brook | #include "sysbus.h" |
10 | 24859b68 | balrog | #include "arm-misc.h" |
11 | 24859b68 | balrog | #include "devices.h" |
12 | 24859b68 | balrog | #include "net.h" |
13 | 24859b68 | balrog | #include "sysemu.h" |
14 | 24859b68 | balrog | #include "boards.h" |
15 | 24859b68 | balrog | #include "pc.h" |
16 | 24859b68 | balrog | #include "qemu-timer.h" |
17 | 24859b68 | balrog | #include "block.h" |
18 | 24859b68 | balrog | #include "flash.h" |
19 | 24859b68 | balrog | #include "console.h" |
20 | 24859b68 | balrog | #include "i2c.h" |
21 | 24859b68 | balrog | |
22 | 718ec0be | malc | #define MP_MISC_BASE 0x80002000 |
23 | 718ec0be | malc | #define MP_MISC_SIZE 0x00001000 |
24 | 718ec0be | malc | |
25 | 24859b68 | balrog | #define MP_ETH_BASE 0x80008000 |
26 | 24859b68 | balrog | #define MP_ETH_SIZE 0x00001000 |
27 | 24859b68 | balrog | |
28 | 718ec0be | malc | #define MP_WLAN_BASE 0x8000C000 |
29 | 718ec0be | malc | #define MP_WLAN_SIZE 0x00000800 |
30 | 718ec0be | malc | |
31 | 24859b68 | balrog | #define MP_UART1_BASE 0x8000C840 |
32 | 24859b68 | balrog | #define MP_UART2_BASE 0x8000C940 |
33 | 24859b68 | balrog | |
34 | 718ec0be | malc | #define MP_GPIO_BASE 0x8000D000 |
35 | 718ec0be | malc | #define MP_GPIO_SIZE 0x00001000 |
36 | 718ec0be | malc | |
37 | 24859b68 | balrog | #define MP_FLASHCFG_BASE 0x90006000 |
38 | 24859b68 | balrog | #define MP_FLASHCFG_SIZE 0x00001000 |
39 | 24859b68 | balrog | |
40 | 24859b68 | balrog | #define MP_AUDIO_BASE 0x90007000 |
41 | 24859b68 | balrog | |
42 | 24859b68 | balrog | #define MP_PIC_BASE 0x90008000 |
43 | 24859b68 | balrog | #define MP_PIC_SIZE 0x00001000 |
44 | 24859b68 | balrog | |
45 | 24859b68 | balrog | #define MP_PIT_BASE 0x90009000 |
46 | 24859b68 | balrog | #define MP_PIT_SIZE 0x00001000 |
47 | 24859b68 | balrog | |
48 | 24859b68 | balrog | #define MP_LCD_BASE 0x9000c000 |
49 | 24859b68 | balrog | #define MP_LCD_SIZE 0x00001000 |
50 | 24859b68 | balrog | |
51 | 24859b68 | balrog | #define MP_SRAM_BASE 0xC0000000 |
52 | 24859b68 | balrog | #define MP_SRAM_SIZE 0x00020000 |
53 | 24859b68 | balrog | |
54 | 24859b68 | balrog | #define MP_RAM_DEFAULT_SIZE 32*1024*1024 |
55 | 24859b68 | balrog | #define MP_FLASH_SIZE_MAX 32*1024*1024 |
56 | 24859b68 | balrog | |
57 | 24859b68 | balrog | #define MP_TIMER1_IRQ 4 |
58 | b47b50fa | Paul Brook | #define MP_TIMER2_IRQ 5 |
59 | b47b50fa | Paul Brook | #define MP_TIMER3_IRQ 6 |
60 | 24859b68 | balrog | #define MP_TIMER4_IRQ 7 |
61 | 24859b68 | balrog | #define MP_EHCI_IRQ 8 |
62 | 24859b68 | balrog | #define MP_ETH_IRQ 9 |
63 | 24859b68 | balrog | #define MP_UART1_IRQ 11 |
64 | 24859b68 | balrog | #define MP_UART2_IRQ 11 |
65 | 24859b68 | balrog | #define MP_GPIO_IRQ 12 |
66 | 24859b68 | balrog | #define MP_RTC_IRQ 28 |
67 | 24859b68 | balrog | #define MP_AUDIO_IRQ 30 |
68 | 24859b68 | balrog | |
69 | 24859b68 | balrog | /* Wolfson 8750 I2C address */
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70 | 24859b68 | balrog | #define MP_WM_ADDR 0x34 |
71 | 24859b68 | balrog | |
72 | 24859b68 | balrog | /* Ethernet register offsets */
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73 | 24859b68 | balrog | #define MP_ETH_SMIR 0x010 |
74 | 24859b68 | balrog | #define MP_ETH_PCXR 0x408 |
75 | 24859b68 | balrog | #define MP_ETH_SDCMR 0x448 |
76 | 24859b68 | balrog | #define MP_ETH_ICR 0x450 |
77 | 24859b68 | balrog | #define MP_ETH_IMR 0x458 |
78 | 24859b68 | balrog | #define MP_ETH_FRDP0 0x480 |
79 | 24859b68 | balrog | #define MP_ETH_FRDP1 0x484 |
80 | 24859b68 | balrog | #define MP_ETH_FRDP2 0x488 |
81 | 24859b68 | balrog | #define MP_ETH_FRDP3 0x48C |
82 | 24859b68 | balrog | #define MP_ETH_CRDP0 0x4A0 |
83 | 24859b68 | balrog | #define MP_ETH_CRDP1 0x4A4 |
84 | 24859b68 | balrog | #define MP_ETH_CRDP2 0x4A8 |
85 | 24859b68 | balrog | #define MP_ETH_CRDP3 0x4AC |
86 | 24859b68 | balrog | #define MP_ETH_CTDP0 0x4E0 |
87 | 24859b68 | balrog | #define MP_ETH_CTDP1 0x4E4 |
88 | 24859b68 | balrog | #define MP_ETH_CTDP2 0x4E8 |
89 | 24859b68 | balrog | #define MP_ETH_CTDP3 0x4EC |
90 | 24859b68 | balrog | |
91 | 24859b68 | balrog | /* MII PHY access */
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92 | 24859b68 | balrog | #define MP_ETH_SMIR_DATA 0x0000FFFF |
93 | 24859b68 | balrog | #define MP_ETH_SMIR_ADDR 0x03FF0000 |
94 | 24859b68 | balrog | #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ |
95 | 24859b68 | balrog | #define MP_ETH_SMIR_RDVALID (1 << 27) |
96 | 24859b68 | balrog | |
97 | 24859b68 | balrog | /* PHY registers */
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98 | 24859b68 | balrog | #define MP_ETH_PHY1_BMSR 0x00210000 |
99 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID1 0x00410000 |
100 | 24859b68 | balrog | #define MP_ETH_PHY1_PHYSID2 0x00610000 |
101 | 24859b68 | balrog | |
102 | 24859b68 | balrog | #define MP_PHY_BMSR_LINK 0x0004 |
103 | 24859b68 | balrog | #define MP_PHY_BMSR_AUTONEG 0x0008 |
104 | 24859b68 | balrog | |
105 | 24859b68 | balrog | #define MP_PHY_88E3015 0x01410E20 |
106 | 24859b68 | balrog | |
107 | 24859b68 | balrog | /* TX descriptor status */
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108 | 24859b68 | balrog | #define MP_ETH_TX_OWN (1 << 31) |
109 | 24859b68 | balrog | |
110 | 24859b68 | balrog | /* RX descriptor status */
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111 | 24859b68 | balrog | #define MP_ETH_RX_OWN (1 << 31) |
112 | 24859b68 | balrog | |
113 | 24859b68 | balrog | /* Interrupt cause/mask bits */
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114 | 24859b68 | balrog | #define MP_ETH_IRQ_RX_BIT 0 |
115 | 24859b68 | balrog | #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) |
116 | 24859b68 | balrog | #define MP_ETH_IRQ_TXHI_BIT 2 |
117 | 24859b68 | balrog | #define MP_ETH_IRQ_TXLO_BIT 3 |
118 | 24859b68 | balrog | |
119 | 24859b68 | balrog | /* Port config bits */
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120 | 24859b68 | balrog | #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ |
121 | 24859b68 | balrog | |
122 | 24859b68 | balrog | /* SDMA command bits */
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123 | 24859b68 | balrog | #define MP_ETH_CMD_TXHI (1 << 23) |
124 | 24859b68 | balrog | #define MP_ETH_CMD_TXLO (1 << 22) |
125 | 24859b68 | balrog | |
126 | 24859b68 | balrog | typedef struct mv88w8618_tx_desc { |
127 | 24859b68 | balrog | uint32_t cmdstat; |
128 | 24859b68 | balrog | uint16_t res; |
129 | 24859b68 | balrog | uint16_t bytes; |
130 | 24859b68 | balrog | uint32_t buffer; |
131 | 24859b68 | balrog | uint32_t next; |
132 | 24859b68 | balrog | } mv88w8618_tx_desc; |
133 | 24859b68 | balrog | |
134 | 24859b68 | balrog | typedef struct mv88w8618_rx_desc { |
135 | 24859b68 | balrog | uint32_t cmdstat; |
136 | 24859b68 | balrog | uint16_t bytes; |
137 | 24859b68 | balrog | uint16_t buffer_size; |
138 | 24859b68 | balrog | uint32_t buffer; |
139 | 24859b68 | balrog | uint32_t next; |
140 | 24859b68 | balrog | } mv88w8618_rx_desc; |
141 | 24859b68 | balrog | |
142 | 24859b68 | balrog | typedef struct mv88w8618_eth_state { |
143 | b47b50fa | Paul Brook | SysBusDevice busdev; |
144 | 24859b68 | balrog | qemu_irq irq; |
145 | 24859b68 | balrog | uint32_t smir; |
146 | 24859b68 | balrog | uint32_t icr; |
147 | 24859b68 | balrog | uint32_t imr; |
148 | b946a153 | aliguori | int mmio_index;
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149 | 24859b68 | balrog | int vlan_header;
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150 | 930c8682 | pbrook | uint32_t tx_queue[2];
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151 | 930c8682 | pbrook | uint32_t rx_queue[4];
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152 | 930c8682 | pbrook | uint32_t frx_queue[4];
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153 | 930c8682 | pbrook | uint32_t cur_rx[4];
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154 | 24859b68 | balrog | VLANClientState *vc; |
155 | 24859b68 | balrog | } mv88w8618_eth_state; |
156 | 24859b68 | balrog | |
157 | 930c8682 | pbrook | static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
158 | 930c8682 | pbrook | { |
159 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
160 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
161 | 930c8682 | pbrook | cpu_to_le16s(&desc->buffer_size); |
162 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
163 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
164 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
165 | 930c8682 | pbrook | } |
166 | 930c8682 | pbrook | |
167 | 930c8682 | pbrook | static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) |
168 | 930c8682 | pbrook | { |
169 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
170 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
171 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
172 | 930c8682 | pbrook | le16_to_cpus(&desc->buffer_size); |
173 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
174 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
175 | 930c8682 | pbrook | } |
176 | 930c8682 | pbrook | |
177 | e3f5ec2b | Mark McLoughlin | static int eth_can_receive(VLANClientState *vc) |
178 | 24859b68 | balrog | { |
179 | 24859b68 | balrog | return 1; |
180 | 24859b68 | balrog | } |
181 | 24859b68 | balrog | |
182 | 4f1c942b | Mark McLoughlin | static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
183 | 24859b68 | balrog | { |
184 | e3f5ec2b | Mark McLoughlin | mv88w8618_eth_state *s = vc->opaque; |
185 | 930c8682 | pbrook | uint32_t desc_addr; |
186 | 930c8682 | pbrook | mv88w8618_rx_desc desc; |
187 | 24859b68 | balrog | int i;
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188 | 24859b68 | balrog | |
189 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
190 | 930c8682 | pbrook | desc_addr = s->cur_rx[i]; |
191 | 930c8682 | pbrook | if (!desc_addr)
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192 | 24859b68 | balrog | continue;
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193 | 24859b68 | balrog | do {
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194 | 930c8682 | pbrook | eth_rx_desc_get(desc_addr, &desc); |
195 | 930c8682 | pbrook | if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
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196 | 930c8682 | pbrook | cpu_physical_memory_write(desc.buffer + s->vlan_header, |
197 | 930c8682 | pbrook | buf, size); |
198 | 930c8682 | pbrook | desc.bytes = size + s->vlan_header; |
199 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_RX_OWN; |
200 | 930c8682 | pbrook | s->cur_rx[i] = desc.next; |
201 | 24859b68 | balrog | |
202 | 24859b68 | balrog | s->icr |= MP_ETH_IRQ_RX; |
203 | 24859b68 | balrog | if (s->icr & s->imr)
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204 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
205 | 930c8682 | pbrook | eth_rx_desc_put(desc_addr, &desc); |
206 | 4f1c942b | Mark McLoughlin | return size;
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207 | 24859b68 | balrog | } |
208 | 930c8682 | pbrook | desc_addr = desc.next; |
209 | 930c8682 | pbrook | } while (desc_addr != s->rx_queue[i]);
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210 | 24859b68 | balrog | } |
211 | 4f1c942b | Mark McLoughlin | return size;
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212 | 24859b68 | balrog | } |
213 | 24859b68 | balrog | |
214 | 930c8682 | pbrook | static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
215 | 930c8682 | pbrook | { |
216 | 930c8682 | pbrook | cpu_to_le32s(&desc->cmdstat); |
217 | 930c8682 | pbrook | cpu_to_le16s(&desc->res); |
218 | 930c8682 | pbrook | cpu_to_le16s(&desc->bytes); |
219 | 930c8682 | pbrook | cpu_to_le32s(&desc->buffer); |
220 | 930c8682 | pbrook | cpu_to_le32s(&desc->next); |
221 | 930c8682 | pbrook | cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
222 | 930c8682 | pbrook | } |
223 | 930c8682 | pbrook | |
224 | 930c8682 | pbrook | static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) |
225 | 930c8682 | pbrook | { |
226 | 930c8682 | pbrook | cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
227 | 930c8682 | pbrook | le32_to_cpus(&desc->cmdstat); |
228 | 930c8682 | pbrook | le16_to_cpus(&desc->res); |
229 | 930c8682 | pbrook | le16_to_cpus(&desc->bytes); |
230 | 930c8682 | pbrook | le32_to_cpus(&desc->buffer); |
231 | 930c8682 | pbrook | le32_to_cpus(&desc->next); |
232 | 930c8682 | pbrook | } |
233 | 930c8682 | pbrook | |
234 | 24859b68 | balrog | static void eth_send(mv88w8618_eth_state *s, int queue_index) |
235 | 24859b68 | balrog | { |
236 | 930c8682 | pbrook | uint32_t desc_addr = s->tx_queue[queue_index]; |
237 | 930c8682 | pbrook | mv88w8618_tx_desc desc; |
238 | 930c8682 | pbrook | uint8_t buf[2048];
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239 | 930c8682 | pbrook | int len;
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240 | 930c8682 | pbrook | |
241 | 24859b68 | balrog | |
242 | 24859b68 | balrog | do {
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243 | 930c8682 | pbrook | eth_tx_desc_get(desc_addr, &desc); |
244 | 930c8682 | pbrook | if (desc.cmdstat & MP_ETH_TX_OWN) {
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245 | 930c8682 | pbrook | len = desc.bytes; |
246 | 930c8682 | pbrook | if (len < 2048) { |
247 | 930c8682 | pbrook | cpu_physical_memory_read(desc.buffer, buf, len); |
248 | 930c8682 | pbrook | qemu_send_packet(s->vc, buf, len); |
249 | 930c8682 | pbrook | } |
250 | 930c8682 | pbrook | desc.cmdstat &= ~MP_ETH_TX_OWN; |
251 | 24859b68 | balrog | s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
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252 | 930c8682 | pbrook | eth_tx_desc_put(desc_addr, &desc); |
253 | 24859b68 | balrog | } |
254 | 930c8682 | pbrook | desc_addr = desc.next; |
255 | 930c8682 | pbrook | } while (desc_addr != s->tx_queue[queue_index]);
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256 | 24859b68 | balrog | } |
257 | 24859b68 | balrog | |
258 | 24859b68 | balrog | static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
259 | 24859b68 | balrog | { |
260 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
261 | 24859b68 | balrog | |
262 | 24859b68 | balrog | switch (offset) {
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263 | 24859b68 | balrog | case MP_ETH_SMIR:
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264 | 24859b68 | balrog | if (s->smir & MP_ETH_SMIR_OPCODE) {
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265 | 24859b68 | balrog | switch (s->smir & MP_ETH_SMIR_ADDR) {
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266 | 24859b68 | balrog | case MP_ETH_PHY1_BMSR:
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267 | 24859b68 | balrog | return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
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268 | 24859b68 | balrog | MP_ETH_SMIR_RDVALID; |
269 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID1:
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270 | 24859b68 | balrog | return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; |
271 | 24859b68 | balrog | case MP_ETH_PHY1_PHYSID2:
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272 | 24859b68 | balrog | return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; |
273 | 24859b68 | balrog | default:
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274 | 24859b68 | balrog | return MP_ETH_SMIR_RDVALID;
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275 | 24859b68 | balrog | } |
276 | 24859b68 | balrog | } |
277 | 24859b68 | balrog | return 0; |
278 | 24859b68 | balrog | |
279 | 24859b68 | balrog | case MP_ETH_ICR:
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280 | 24859b68 | balrog | return s->icr;
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281 | 24859b68 | balrog | |
282 | 24859b68 | balrog | case MP_ETH_IMR:
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283 | 24859b68 | balrog | return s->imr;
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284 | 24859b68 | balrog | |
285 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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286 | 930c8682 | pbrook | return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
287 | 24859b68 | balrog | |
288 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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289 | 930c8682 | pbrook | return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
290 | 24859b68 | balrog | |
291 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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292 | 930c8682 | pbrook | return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
293 | 24859b68 | balrog | |
294 | 24859b68 | balrog | default:
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295 | 24859b68 | balrog | return 0; |
296 | 24859b68 | balrog | } |
297 | 24859b68 | balrog | } |
298 | 24859b68 | balrog | |
299 | 24859b68 | balrog | static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
300 | 24859b68 | balrog | uint32_t value) |
301 | 24859b68 | balrog | { |
302 | 24859b68 | balrog | mv88w8618_eth_state *s = opaque; |
303 | 24859b68 | balrog | |
304 | 24859b68 | balrog | switch (offset) {
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305 | 24859b68 | balrog | case MP_ETH_SMIR:
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306 | 24859b68 | balrog | s->smir = value; |
307 | 24859b68 | balrog | break;
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308 | 24859b68 | balrog | |
309 | 24859b68 | balrog | case MP_ETH_PCXR:
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310 | 24859b68 | balrog | s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; |
311 | 24859b68 | balrog | break;
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312 | 24859b68 | balrog | |
313 | 24859b68 | balrog | case MP_ETH_SDCMR:
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314 | 24859b68 | balrog | if (value & MP_ETH_CMD_TXHI)
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315 | 24859b68 | balrog | eth_send(s, 1);
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316 | 24859b68 | balrog | if (value & MP_ETH_CMD_TXLO)
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317 | 24859b68 | balrog | eth_send(s, 0);
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318 | 24859b68 | balrog | if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
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319 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
320 | 24859b68 | balrog | break;
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321 | 24859b68 | balrog | |
322 | 24859b68 | balrog | case MP_ETH_ICR:
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323 | 24859b68 | balrog | s->icr &= value; |
324 | 24859b68 | balrog | break;
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325 | 24859b68 | balrog | |
326 | 24859b68 | balrog | case MP_ETH_IMR:
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327 | 24859b68 | balrog | s->imr = value; |
328 | 24859b68 | balrog | if (s->icr & s->imr)
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329 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
330 | 24859b68 | balrog | break;
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331 | 24859b68 | balrog | |
332 | 24859b68 | balrog | case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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333 | 930c8682 | pbrook | s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
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334 | 24859b68 | balrog | break;
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335 | 24859b68 | balrog | |
336 | 24859b68 | balrog | case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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337 | 24859b68 | balrog | s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
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338 | 930c8682 | pbrook | s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
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339 | 24859b68 | balrog | break;
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340 | 24859b68 | balrog | |
341 | 24859b68 | balrog | case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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342 | 930c8682 | pbrook | s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
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343 | 24859b68 | balrog | break;
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344 | 24859b68 | balrog | } |
345 | 24859b68 | balrog | } |
346 | 24859b68 | balrog | |
347 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = { |
348 | 24859b68 | balrog | mv88w8618_eth_read, |
349 | 24859b68 | balrog | mv88w8618_eth_read, |
350 | 24859b68 | balrog | mv88w8618_eth_read |
351 | 24859b68 | balrog | }; |
352 | 24859b68 | balrog | |
353 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = { |
354 | 24859b68 | balrog | mv88w8618_eth_write, |
355 | 24859b68 | balrog | mv88w8618_eth_write, |
356 | 24859b68 | balrog | mv88w8618_eth_write |
357 | 24859b68 | balrog | }; |
358 | 24859b68 | balrog | |
359 | b946a153 | aliguori | static void eth_cleanup(VLANClientState *vc) |
360 | b946a153 | aliguori | { |
361 | b946a153 | aliguori | mv88w8618_eth_state *s = vc->opaque; |
362 | b946a153 | aliguori | |
363 | b946a153 | aliguori | cpu_unregister_io_memory(s->mmio_index); |
364 | b946a153 | aliguori | |
365 | b946a153 | aliguori | qemu_free(s); |
366 | b946a153 | aliguori | } |
367 | b946a153 | aliguori | |
368 | b47b50fa | Paul Brook | static void mv88w8618_eth_init(SysBusDevice *dev) |
369 | 24859b68 | balrog | { |
370 | b47b50fa | Paul Brook | mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev); |
371 | 0ae18cee | aliguori | |
372 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->irq); |
373 | b47b50fa | Paul Brook | s->vc = qdev_get_vlan_client(&dev->qdev, |
374 | 463af534 | Mark McLoughlin | eth_can_receive, eth_receive, NULL,
|
375 | b946a153 | aliguori | eth_cleanup, s); |
376 | 1eed09cb | Avi Kivity | s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, |
377 | b946a153 | aliguori | mv88w8618_eth_writefn, s); |
378 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); |
379 | 24859b68 | balrog | } |
380 | 24859b68 | balrog | |
381 | 24859b68 | balrog | /* LCD register offsets */
|
382 | 24859b68 | balrog | #define MP_LCD_IRQCTRL 0x180 |
383 | 24859b68 | balrog | #define MP_LCD_IRQSTAT 0x184 |
384 | 24859b68 | balrog | #define MP_LCD_SPICTRL 0x1ac |
385 | 24859b68 | balrog | #define MP_LCD_INST 0x1bc |
386 | 24859b68 | balrog | #define MP_LCD_DATA 0x1c0 |
387 | 24859b68 | balrog | |
388 | 24859b68 | balrog | /* Mode magics */
|
389 | 24859b68 | balrog | #define MP_LCD_SPI_DATA 0x00100011 |
390 | 24859b68 | balrog | #define MP_LCD_SPI_CMD 0x00104011 |
391 | 24859b68 | balrog | #define MP_LCD_SPI_INVALID 0x00000000 |
392 | 24859b68 | balrog | |
393 | 24859b68 | balrog | /* Commmands */
|
394 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE0 0xB0 |
395 | 24859b68 | balrog | /* ... */
|
396 | 24859b68 | balrog | #define MP_LCD_INST_SETPAGE7 0xB7 |
397 | 24859b68 | balrog | |
398 | 24859b68 | balrog | #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ |
399 | 24859b68 | balrog | |
400 | 24859b68 | balrog | typedef struct musicpal_lcd_state { |
401 | b47b50fa | Paul Brook | SysBusDevice busdev; |
402 | 343ec8e4 | Benoit Canet | uint32_t brightness; |
403 | 24859b68 | balrog | uint32_t mode; |
404 | 24859b68 | balrog | uint32_t irqctrl; |
405 | 24859b68 | balrog | int page;
|
406 | 24859b68 | balrog | int page_off;
|
407 | 24859b68 | balrog | DisplayState *ds; |
408 | 24859b68 | balrog | uint8_t video_ram[128*64/8]; |
409 | 24859b68 | balrog | } musicpal_lcd_state; |
410 | 24859b68 | balrog | |
411 | 343ec8e4 | Benoit Canet | static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
|
412 | 24859b68 | balrog | { |
413 | 343ec8e4 | Benoit Canet | switch (s->brightness) {
|
414 | 343ec8e4 | Benoit Canet | case 7: |
415 | 343ec8e4 | Benoit Canet | return col;
|
416 | 343ec8e4 | Benoit Canet | case 0: |
417 | 24859b68 | balrog | return 0; |
418 | 24859b68 | balrog | default:
|
419 | 343ec8e4 | Benoit Canet | return (col * s->brightness) / 7; |
420 | 24859b68 | balrog | } |
421 | 24859b68 | balrog | } |
422 | 24859b68 | balrog | |
423 | 0266f2c7 | balrog | #define SET_LCD_PIXEL(depth, type) \
|
424 | 0266f2c7 | balrog | static inline void glue(set_lcd_pixel, depth) \ |
425 | 0266f2c7 | balrog | (musicpal_lcd_state *s, int x, int y, type col) \ |
426 | 0266f2c7 | balrog | { \ |
427 | 0266f2c7 | balrog | int dx, dy; \
|
428 | 0e1f5a0c | aliguori | type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
429 | 0266f2c7 | balrog | \ |
430 | 0266f2c7 | balrog | for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ |
431 | 0266f2c7 | balrog | for (dx = 0; dx < 3; dx++, pixel++) \ |
432 | 0266f2c7 | balrog | *pixel = col; \ |
433 | 24859b68 | balrog | } |
434 | 0266f2c7 | balrog | SET_LCD_PIXEL(8, uint8_t)
|
435 | 0266f2c7 | balrog | SET_LCD_PIXEL(16, uint16_t)
|
436 | 0266f2c7 | balrog | SET_LCD_PIXEL(32, uint32_t)
|
437 | 0266f2c7 | balrog | |
438 | 0266f2c7 | balrog | #include "pixel_ops.h" |
439 | 24859b68 | balrog | |
440 | 24859b68 | balrog | static void lcd_refresh(void *opaque) |
441 | 24859b68 | balrog | { |
442 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
443 | 0266f2c7 | balrog | int x, y, col;
|
444 | 24859b68 | balrog | |
445 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
446 | 0266f2c7 | balrog | case 0: |
447 | 0266f2c7 | balrog | return;
|
448 | 0266f2c7 | balrog | #define LCD_REFRESH(depth, func) \
|
449 | 0266f2c7 | balrog | case depth: \
|
450 | 343ec8e4 | Benoit Canet | col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
451 | 343ec8e4 | Benoit Canet | scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ |
452 | 343ec8e4 | Benoit Canet | scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
|
453 | 0266f2c7 | balrog | for (x = 0; x < 128; x++) \ |
454 | 0266f2c7 | balrog | for (y = 0; y < 64; y++) \ |
455 | 0266f2c7 | balrog | if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \ |
456 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, col); \ |
457 | 0266f2c7 | balrog | else \
|
458 | 0266f2c7 | balrog | glue(set_lcd_pixel, depth)(s, x, y, 0); \
|
459 | 0266f2c7 | balrog | break;
|
460 | 0266f2c7 | balrog | LCD_REFRESH(8, rgb_to_pixel8)
|
461 | 0266f2c7 | balrog | LCD_REFRESH(16, rgb_to_pixel16)
|
462 | bf9b48af | aliguori | LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
|
463 | bf9b48af | aliguori | rgb_to_pixel32bgr : rgb_to_pixel32)) |
464 | 0266f2c7 | balrog | default:
|
465 | 2ac71179 | Paul Brook | hw_error("unsupported colour depth %i\n",
|
466 | 0e1f5a0c | aliguori | ds_get_bits_per_pixel(s->ds)); |
467 | 0266f2c7 | balrog | } |
468 | 24859b68 | balrog | |
469 | 24859b68 | balrog | dpy_update(s->ds, 0, 0, 128*3, 64*3); |
470 | 24859b68 | balrog | } |
471 | 24859b68 | balrog | |
472 | 167bc3d2 | balrog | static void lcd_invalidate(void *opaque) |
473 | 167bc3d2 | balrog | { |
474 | 167bc3d2 | balrog | } |
475 | 167bc3d2 | balrog | |
476 | 343ec8e4 | Benoit Canet | static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) |
477 | 343ec8e4 | Benoit Canet | { |
478 | 343ec8e4 | Benoit Canet | musicpal_lcd_state *s = (musicpal_lcd_state *) opaque; |
479 | 343ec8e4 | Benoit Canet | s->brightness &= ~(1 << irq);
|
480 | 343ec8e4 | Benoit Canet | s->brightness |= level << irq; |
481 | 343ec8e4 | Benoit Canet | } |
482 | 343ec8e4 | Benoit Canet | |
483 | 24859b68 | balrog | static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
484 | 24859b68 | balrog | { |
485 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
486 | 24859b68 | balrog | |
487 | 24859b68 | balrog | switch (offset) {
|
488 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
489 | 24859b68 | balrog | return s->irqctrl;
|
490 | 24859b68 | balrog | |
491 | 24859b68 | balrog | default:
|
492 | 24859b68 | balrog | return 0; |
493 | 24859b68 | balrog | } |
494 | 24859b68 | balrog | } |
495 | 24859b68 | balrog | |
496 | 24859b68 | balrog | static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
497 | 24859b68 | balrog | uint32_t value) |
498 | 24859b68 | balrog | { |
499 | 24859b68 | balrog | musicpal_lcd_state *s = opaque; |
500 | 24859b68 | balrog | |
501 | 24859b68 | balrog | switch (offset) {
|
502 | 24859b68 | balrog | case MP_LCD_IRQCTRL:
|
503 | 24859b68 | balrog | s->irqctrl = value; |
504 | 24859b68 | balrog | break;
|
505 | 24859b68 | balrog | |
506 | 24859b68 | balrog | case MP_LCD_SPICTRL:
|
507 | 24859b68 | balrog | if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
|
508 | 24859b68 | balrog | s->mode = value; |
509 | 24859b68 | balrog | else
|
510 | 24859b68 | balrog | s->mode = MP_LCD_SPI_INVALID; |
511 | 24859b68 | balrog | break;
|
512 | 24859b68 | balrog | |
513 | 24859b68 | balrog | case MP_LCD_INST:
|
514 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
|
515 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
516 | 24859b68 | balrog | s->page_off = 0;
|
517 | 24859b68 | balrog | } |
518 | 24859b68 | balrog | break;
|
519 | 24859b68 | balrog | |
520 | 24859b68 | balrog | case MP_LCD_DATA:
|
521 | 24859b68 | balrog | if (s->mode == MP_LCD_SPI_CMD) {
|
522 | 24859b68 | balrog | if (value >= MP_LCD_INST_SETPAGE0 &&
|
523 | 24859b68 | balrog | value <= MP_LCD_INST_SETPAGE7) { |
524 | 24859b68 | balrog | s->page = value - MP_LCD_INST_SETPAGE0; |
525 | 24859b68 | balrog | s->page_off = 0;
|
526 | 24859b68 | balrog | } |
527 | 24859b68 | balrog | } else if (s->mode == MP_LCD_SPI_DATA) { |
528 | 24859b68 | balrog | s->video_ram[s->page*128 + s->page_off] = value;
|
529 | 24859b68 | balrog | s->page_off = (s->page_off + 1) & 127; |
530 | 24859b68 | balrog | } |
531 | 24859b68 | balrog | break;
|
532 | 24859b68 | balrog | } |
533 | 24859b68 | balrog | } |
534 | 24859b68 | balrog | |
535 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = { |
536 | 24859b68 | balrog | musicpal_lcd_read, |
537 | 24859b68 | balrog | musicpal_lcd_read, |
538 | 24859b68 | balrog | musicpal_lcd_read |
539 | 24859b68 | balrog | }; |
540 | 24859b68 | balrog | |
541 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = { |
542 | 24859b68 | balrog | musicpal_lcd_write, |
543 | 24859b68 | balrog | musicpal_lcd_write, |
544 | 24859b68 | balrog | musicpal_lcd_write |
545 | 24859b68 | balrog | }; |
546 | 24859b68 | balrog | |
547 | b47b50fa | Paul Brook | static void musicpal_lcd_init(SysBusDevice *dev) |
548 | 24859b68 | balrog | { |
549 | b47b50fa | Paul Brook | musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); |
550 | 24859b68 | balrog | int iomemtype;
|
551 | 24859b68 | balrog | |
552 | 343ec8e4 | Benoit Canet | s->brightness = 7;
|
553 | 343ec8e4 | Benoit Canet | |
554 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, |
555 | 24859b68 | balrog | musicpal_lcd_writefn, s); |
556 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); |
557 | 24859b68 | balrog | |
558 | 3023f332 | aliguori | s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
559 | 3023f332 | aliguori | NULL, NULL, s); |
560 | 3023f332 | aliguori | qemu_console_resize(s->ds, 128*3, 64*3); |
561 | 343ec8e4 | Benoit Canet | |
562 | 343ec8e4 | Benoit Canet | qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
|
563 | 24859b68 | balrog | } |
564 | 24859b68 | balrog | |
565 | 24859b68 | balrog | /* PIC register offsets */
|
566 | 24859b68 | balrog | #define MP_PIC_STATUS 0x00 |
567 | 24859b68 | balrog | #define MP_PIC_ENABLE_SET 0x08 |
568 | 24859b68 | balrog | #define MP_PIC_ENABLE_CLR 0x0C |
569 | 24859b68 | balrog | |
570 | 24859b68 | balrog | typedef struct mv88w8618_pic_state |
571 | 24859b68 | balrog | { |
572 | b47b50fa | Paul Brook | SysBusDevice busdev; |
573 | 24859b68 | balrog | uint32_t level; |
574 | 24859b68 | balrog | uint32_t enabled; |
575 | 24859b68 | balrog | qemu_irq parent_irq; |
576 | 24859b68 | balrog | } mv88w8618_pic_state; |
577 | 24859b68 | balrog | |
578 | 24859b68 | balrog | static void mv88w8618_pic_update(mv88w8618_pic_state *s) |
579 | 24859b68 | balrog | { |
580 | 24859b68 | balrog | qemu_set_irq(s->parent_irq, (s->level & s->enabled)); |
581 | 24859b68 | balrog | } |
582 | 24859b68 | balrog | |
583 | 24859b68 | balrog | static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) |
584 | 24859b68 | balrog | { |
585 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
586 | 24859b68 | balrog | |
587 | 24859b68 | balrog | if (level)
|
588 | 24859b68 | balrog | s->level |= 1 << irq;
|
589 | 24859b68 | balrog | else
|
590 | 24859b68 | balrog | s->level &= ~(1 << irq);
|
591 | 24859b68 | balrog | mv88w8618_pic_update(s); |
592 | 24859b68 | balrog | } |
593 | 24859b68 | balrog | |
594 | 24859b68 | balrog | static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
595 | 24859b68 | balrog | { |
596 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
597 | 24859b68 | balrog | |
598 | 24859b68 | balrog | switch (offset) {
|
599 | 24859b68 | balrog | case MP_PIC_STATUS:
|
600 | 24859b68 | balrog | return s->level & s->enabled;
|
601 | 24859b68 | balrog | |
602 | 24859b68 | balrog | default:
|
603 | 24859b68 | balrog | return 0; |
604 | 24859b68 | balrog | } |
605 | 24859b68 | balrog | } |
606 | 24859b68 | balrog | |
607 | 24859b68 | balrog | static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
608 | 24859b68 | balrog | uint32_t value) |
609 | 24859b68 | balrog | { |
610 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
611 | 24859b68 | balrog | |
612 | 24859b68 | balrog | switch (offset) {
|
613 | 24859b68 | balrog | case MP_PIC_ENABLE_SET:
|
614 | 24859b68 | balrog | s->enabled |= value; |
615 | 24859b68 | balrog | break;
|
616 | 24859b68 | balrog | |
617 | 24859b68 | balrog | case MP_PIC_ENABLE_CLR:
|
618 | 24859b68 | balrog | s->enabled &= ~value; |
619 | 24859b68 | balrog | s->level &= ~value; |
620 | 24859b68 | balrog | break;
|
621 | 24859b68 | balrog | } |
622 | 24859b68 | balrog | mv88w8618_pic_update(s); |
623 | 24859b68 | balrog | } |
624 | 24859b68 | balrog | |
625 | 24859b68 | balrog | static void mv88w8618_pic_reset(void *opaque) |
626 | 24859b68 | balrog | { |
627 | 24859b68 | balrog | mv88w8618_pic_state *s = opaque; |
628 | 24859b68 | balrog | |
629 | 24859b68 | balrog | s->level = 0;
|
630 | 24859b68 | balrog | s->enabled = 0;
|
631 | 24859b68 | balrog | } |
632 | 24859b68 | balrog | |
633 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = { |
634 | 24859b68 | balrog | mv88w8618_pic_read, |
635 | 24859b68 | balrog | mv88w8618_pic_read, |
636 | 24859b68 | balrog | mv88w8618_pic_read |
637 | 24859b68 | balrog | }; |
638 | 24859b68 | balrog | |
639 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = { |
640 | 24859b68 | balrog | mv88w8618_pic_write, |
641 | 24859b68 | balrog | mv88w8618_pic_write, |
642 | 24859b68 | balrog | mv88w8618_pic_write |
643 | 24859b68 | balrog | }; |
644 | 24859b68 | balrog | |
645 | b47b50fa | Paul Brook | static void mv88w8618_pic_init(SysBusDevice *dev) |
646 | 24859b68 | balrog | { |
647 | b47b50fa | Paul Brook | mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev); |
648 | 24859b68 | balrog | int iomemtype;
|
649 | 24859b68 | balrog | |
650 | 067a3ddc | Paul Brook | qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
|
651 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->parent_irq); |
652 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, |
653 | 24859b68 | balrog | mv88w8618_pic_writefn, s); |
654 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); |
655 | 24859b68 | balrog | |
656 | a08d4367 | Jan Kiszka | qemu_register_reset(mv88w8618_pic_reset, s); |
657 | 24859b68 | balrog | } |
658 | 24859b68 | balrog | |
659 | 24859b68 | balrog | /* PIT register offsets */
|
660 | 24859b68 | balrog | #define MP_PIT_TIMER1_LENGTH 0x00 |
661 | 24859b68 | balrog | /* ... */
|
662 | 24859b68 | balrog | #define MP_PIT_TIMER4_LENGTH 0x0C |
663 | 24859b68 | balrog | #define MP_PIT_CONTROL 0x10 |
664 | 24859b68 | balrog | #define MP_PIT_TIMER1_VALUE 0x14 |
665 | 24859b68 | balrog | /* ... */
|
666 | 24859b68 | balrog | #define MP_PIT_TIMER4_VALUE 0x20 |
667 | 24859b68 | balrog | #define MP_BOARD_RESET 0x34 |
668 | 24859b68 | balrog | |
669 | 24859b68 | balrog | /* Magic board reset value (probably some watchdog behind it) */
|
670 | 24859b68 | balrog | #define MP_BOARD_RESET_MAGIC 0x10000 |
671 | 24859b68 | balrog | |
672 | 24859b68 | balrog | typedef struct mv88w8618_timer_state { |
673 | b47b50fa | Paul Brook | ptimer_state *ptimer; |
674 | 24859b68 | balrog | uint32_t limit; |
675 | 24859b68 | balrog | int freq;
|
676 | 24859b68 | balrog | qemu_irq irq; |
677 | 24859b68 | balrog | } mv88w8618_timer_state; |
678 | 24859b68 | balrog | |
679 | 24859b68 | balrog | typedef struct mv88w8618_pit_state { |
680 | b47b50fa | Paul Brook | SysBusDevice busdev; |
681 | b47b50fa | Paul Brook | mv88w8618_timer_state timer[4];
|
682 | 24859b68 | balrog | uint32_t control; |
683 | 24859b68 | balrog | } mv88w8618_pit_state; |
684 | 24859b68 | balrog | |
685 | 24859b68 | balrog | static void mv88w8618_timer_tick(void *opaque) |
686 | 24859b68 | balrog | { |
687 | 24859b68 | balrog | mv88w8618_timer_state *s = opaque; |
688 | 24859b68 | balrog | |
689 | 24859b68 | balrog | qemu_irq_raise(s->irq); |
690 | 24859b68 | balrog | } |
691 | 24859b68 | balrog | |
692 | b47b50fa | Paul Brook | static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
693 | b47b50fa | Paul Brook | uint32_t freq) |
694 | 24859b68 | balrog | { |
695 | 24859b68 | balrog | QEMUBH *bh; |
696 | 24859b68 | balrog | |
697 | b47b50fa | Paul Brook | sysbus_init_irq(dev, &s->irq); |
698 | 24859b68 | balrog | s->freq = freq; |
699 | 24859b68 | balrog | |
700 | 24859b68 | balrog | bh = qemu_bh_new(mv88w8618_timer_tick, s); |
701 | b47b50fa | Paul Brook | s->ptimer = ptimer_init(bh); |
702 | 24859b68 | balrog | } |
703 | 24859b68 | balrog | |
704 | 24859b68 | balrog | static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
705 | 24859b68 | balrog | { |
706 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
707 | 24859b68 | balrog | mv88w8618_timer_state *t; |
708 | 24859b68 | balrog | |
709 | 24859b68 | balrog | switch (offset) {
|
710 | 24859b68 | balrog | case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
|
711 | b47b50fa | Paul Brook | t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
|
712 | b47b50fa | Paul Brook | return ptimer_get_count(t->ptimer);
|
713 | 24859b68 | balrog | |
714 | 24859b68 | balrog | default:
|
715 | 24859b68 | balrog | return 0; |
716 | 24859b68 | balrog | } |
717 | 24859b68 | balrog | } |
718 | 24859b68 | balrog | |
719 | 24859b68 | balrog | static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
720 | 24859b68 | balrog | uint32_t value) |
721 | 24859b68 | balrog | { |
722 | 24859b68 | balrog | mv88w8618_pit_state *s = opaque; |
723 | 24859b68 | balrog | mv88w8618_timer_state *t; |
724 | 24859b68 | balrog | int i;
|
725 | 24859b68 | balrog | |
726 | 24859b68 | balrog | switch (offset) {
|
727 | 24859b68 | balrog | case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
|
728 | b47b50fa | Paul Brook | t = &s->timer[offset >> 2];
|
729 | 24859b68 | balrog | t->limit = value; |
730 | b47b50fa | Paul Brook | ptimer_set_limit(t->ptimer, t->limit, 1);
|
731 | 24859b68 | balrog | break;
|
732 | 24859b68 | balrog | |
733 | 24859b68 | balrog | case MP_PIT_CONTROL:
|
734 | 24859b68 | balrog | for (i = 0; i < 4; i++) { |
735 | 24859b68 | balrog | if (value & 0xf) { |
736 | b47b50fa | Paul Brook | t = &s->timer[i]; |
737 | b47b50fa | Paul Brook | ptimer_set_limit(t->ptimer, t->limit, 0);
|
738 | b47b50fa | Paul Brook | ptimer_set_freq(t->ptimer, t->freq); |
739 | b47b50fa | Paul Brook | ptimer_run(t->ptimer, 0);
|
740 | 24859b68 | balrog | } |
741 | 24859b68 | balrog | value >>= 4;
|
742 | 24859b68 | balrog | } |
743 | 24859b68 | balrog | break;
|
744 | 24859b68 | balrog | |
745 | 24859b68 | balrog | case MP_BOARD_RESET:
|
746 | 24859b68 | balrog | if (value == MP_BOARD_RESET_MAGIC)
|
747 | 24859b68 | balrog | qemu_system_reset_request(); |
748 | 24859b68 | balrog | break;
|
749 | 24859b68 | balrog | } |
750 | 24859b68 | balrog | } |
751 | 24859b68 | balrog | |
752 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = { |
753 | 24859b68 | balrog | mv88w8618_pit_read, |
754 | 24859b68 | balrog | mv88w8618_pit_read, |
755 | 24859b68 | balrog | mv88w8618_pit_read |
756 | 24859b68 | balrog | }; |
757 | 24859b68 | balrog | |
758 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = { |
759 | 24859b68 | balrog | mv88w8618_pit_write, |
760 | 24859b68 | balrog | mv88w8618_pit_write, |
761 | 24859b68 | balrog | mv88w8618_pit_write |
762 | 24859b68 | balrog | }; |
763 | 24859b68 | balrog | |
764 | b47b50fa | Paul Brook | static void mv88w8618_pit_init(SysBusDevice *dev) |
765 | 24859b68 | balrog | { |
766 | 24859b68 | balrog | int iomemtype;
|
767 | b47b50fa | Paul Brook | mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev); |
768 | b47b50fa | Paul Brook | int i;
|
769 | 24859b68 | balrog | |
770 | 24859b68 | balrog | /* Letting them all run at 1 MHz is likely just a pragmatic
|
771 | 24859b68 | balrog | * simplification. */
|
772 | b47b50fa | Paul Brook | for (i = 0; i < 4; i++) { |
773 | b47b50fa | Paul Brook | mv88w8618_timer_init(dev, &s->timer[i], 1000000);
|
774 | b47b50fa | Paul Brook | } |
775 | 24859b68 | balrog | |
776 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, |
777 | 24859b68 | balrog | mv88w8618_pit_writefn, s); |
778 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); |
779 | 24859b68 | balrog | } |
780 | 24859b68 | balrog | |
781 | 24859b68 | balrog | /* Flash config register offsets */
|
782 | 24859b68 | balrog | #define MP_FLASHCFG_CFGR0 0x04 |
783 | 24859b68 | balrog | |
784 | 24859b68 | balrog | typedef struct mv88w8618_flashcfg_state { |
785 | b47b50fa | Paul Brook | SysBusDevice busdev; |
786 | 24859b68 | balrog | uint32_t cfgr0; |
787 | 24859b68 | balrog | } mv88w8618_flashcfg_state; |
788 | 24859b68 | balrog | |
789 | 24859b68 | balrog | static uint32_t mv88w8618_flashcfg_read(void *opaque, |
790 | 24859b68 | balrog | target_phys_addr_t offset) |
791 | 24859b68 | balrog | { |
792 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
793 | 24859b68 | balrog | |
794 | 24859b68 | balrog | switch (offset) {
|
795 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
796 | 24859b68 | balrog | return s->cfgr0;
|
797 | 24859b68 | balrog | |
798 | 24859b68 | balrog | default:
|
799 | 24859b68 | balrog | return 0; |
800 | 24859b68 | balrog | } |
801 | 24859b68 | balrog | } |
802 | 24859b68 | balrog | |
803 | 24859b68 | balrog | static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
804 | 24859b68 | balrog | uint32_t value) |
805 | 24859b68 | balrog | { |
806 | 24859b68 | balrog | mv88w8618_flashcfg_state *s = opaque; |
807 | 24859b68 | balrog | |
808 | 24859b68 | balrog | switch (offset) {
|
809 | 24859b68 | balrog | case MP_FLASHCFG_CFGR0:
|
810 | 24859b68 | balrog | s->cfgr0 = value; |
811 | 24859b68 | balrog | break;
|
812 | 24859b68 | balrog | } |
813 | 24859b68 | balrog | } |
814 | 24859b68 | balrog | |
815 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = { |
816 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
817 | 24859b68 | balrog | mv88w8618_flashcfg_read, |
818 | 24859b68 | balrog | mv88w8618_flashcfg_read |
819 | 24859b68 | balrog | }; |
820 | 24859b68 | balrog | |
821 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = { |
822 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
823 | 24859b68 | balrog | mv88w8618_flashcfg_write, |
824 | 24859b68 | balrog | mv88w8618_flashcfg_write |
825 | 24859b68 | balrog | }; |
826 | 24859b68 | balrog | |
827 | b47b50fa | Paul Brook | static void mv88w8618_flashcfg_init(SysBusDevice *dev) |
828 | 24859b68 | balrog | { |
829 | 24859b68 | balrog | int iomemtype;
|
830 | b47b50fa | Paul Brook | mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev); |
831 | 24859b68 | balrog | |
832 | 24859b68 | balrog | s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
833 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, |
834 | 24859b68 | balrog | mv88w8618_flashcfg_writefn, s); |
835 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); |
836 | 24859b68 | balrog | } |
837 | 24859b68 | balrog | |
838 | 718ec0be | malc | /* Misc register offsets */
|
839 | 718ec0be | malc | #define MP_MISC_BOARD_REVISION 0x18 |
840 | 718ec0be | malc | |
841 | 718ec0be | malc | #define MP_BOARD_REVISION 0x31 |
842 | 718ec0be | malc | |
843 | 718ec0be | malc | static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) |
844 | 718ec0be | malc | { |
845 | 718ec0be | malc | switch (offset) {
|
846 | 718ec0be | malc | case MP_MISC_BOARD_REVISION:
|
847 | 718ec0be | malc | return MP_BOARD_REVISION;
|
848 | 718ec0be | malc | |
849 | 718ec0be | malc | default:
|
850 | 718ec0be | malc | return 0; |
851 | 718ec0be | malc | } |
852 | 718ec0be | malc | } |
853 | 718ec0be | malc | |
854 | 718ec0be | malc | static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, |
855 | 718ec0be | malc | uint32_t value) |
856 | 718ec0be | malc | { |
857 | 718ec0be | malc | } |
858 | 718ec0be | malc | |
859 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_misc_readfn[] = { |
860 | 718ec0be | malc | musicpal_misc_read, |
861 | 718ec0be | malc | musicpal_misc_read, |
862 | 718ec0be | malc | musicpal_misc_read, |
863 | 718ec0be | malc | }; |
864 | 718ec0be | malc | |
865 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = { |
866 | 718ec0be | malc | musicpal_misc_write, |
867 | 718ec0be | malc | musicpal_misc_write, |
868 | 718ec0be | malc | musicpal_misc_write, |
869 | 718ec0be | malc | }; |
870 | 718ec0be | malc | |
871 | 718ec0be | malc | static void musicpal_misc_init(void) |
872 | 718ec0be | malc | { |
873 | 718ec0be | malc | int iomemtype;
|
874 | 718ec0be | malc | |
875 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_misc_readfn, |
876 | 718ec0be | malc | musicpal_misc_writefn, NULL);
|
877 | 718ec0be | malc | cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); |
878 | 718ec0be | malc | } |
879 | 718ec0be | malc | |
880 | 718ec0be | malc | /* WLAN register offsets */
|
881 | 718ec0be | malc | #define MP_WLAN_MAGIC1 0x11c |
882 | 718ec0be | malc | #define MP_WLAN_MAGIC2 0x124 |
883 | 718ec0be | malc | |
884 | 718ec0be | malc | static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) |
885 | 718ec0be | malc | { |
886 | 718ec0be | malc | switch (offset) {
|
887 | 718ec0be | malc | /* Workaround to allow loading the binary-only wlandrv.ko crap
|
888 | 718ec0be | malc | * from the original Freecom firmware. */
|
889 | 718ec0be | malc | case MP_WLAN_MAGIC1:
|
890 | 718ec0be | malc | return ~3; |
891 | 718ec0be | malc | case MP_WLAN_MAGIC2:
|
892 | 718ec0be | malc | return -1; |
893 | 718ec0be | malc | |
894 | 718ec0be | malc | default:
|
895 | 718ec0be | malc | return 0; |
896 | 718ec0be | malc | } |
897 | 718ec0be | malc | } |
898 | 718ec0be | malc | |
899 | 718ec0be | malc | static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, |
900 | 718ec0be | malc | uint32_t value) |
901 | 718ec0be | malc | { |
902 | 718ec0be | malc | } |
903 | 718ec0be | malc | |
904 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = { |
905 | 718ec0be | malc | mv88w8618_wlan_read, |
906 | 718ec0be | malc | mv88w8618_wlan_read, |
907 | 718ec0be | malc | mv88w8618_wlan_read, |
908 | 718ec0be | malc | }; |
909 | 718ec0be | malc | |
910 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = { |
911 | 718ec0be | malc | mv88w8618_wlan_write, |
912 | 718ec0be | malc | mv88w8618_wlan_write, |
913 | 718ec0be | malc | mv88w8618_wlan_write, |
914 | 718ec0be | malc | }; |
915 | 718ec0be | malc | |
916 | b47b50fa | Paul Brook | static void mv88w8618_wlan_init(SysBusDevice *dev) |
917 | 718ec0be | malc | { |
918 | 718ec0be | malc | int iomemtype;
|
919 | 24859b68 | balrog | |
920 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, |
921 | 718ec0be | malc | mv88w8618_wlan_writefn, NULL);
|
922 | b47b50fa | Paul Brook | sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); |
923 | 718ec0be | malc | } |
924 | 24859b68 | balrog | |
925 | 718ec0be | malc | /* GPIO register offsets */
|
926 | 718ec0be | malc | #define MP_GPIO_OE_LO 0x008 |
927 | 718ec0be | malc | #define MP_GPIO_OUT_LO 0x00c |
928 | 718ec0be | malc | #define MP_GPIO_IN_LO 0x010 |
929 | 718ec0be | malc | #define MP_GPIO_ISR_LO 0x020 |
930 | 718ec0be | malc | #define MP_GPIO_OE_HI 0x508 |
931 | 718ec0be | malc | #define MP_GPIO_OUT_HI 0x50c |
932 | 718ec0be | malc | #define MP_GPIO_IN_HI 0x510 |
933 | 718ec0be | malc | #define MP_GPIO_ISR_HI 0x520 |
934 | 24859b68 | balrog | |
935 | 24859b68 | balrog | /* GPIO bits & masks */
|
936 | 24859b68 | balrog | #define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
937 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA_BIT 29 |
938 | 24859b68 | balrog | #define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT) |
939 | 24859b68 | balrog | #define MP_GPIO_I2C_CLOCK_BIT 30 |
940 | 24859b68 | balrog | |
941 | 24859b68 | balrog | /* LCD brightness bits in GPIO_OE_HI */
|
942 | 24859b68 | balrog | #define MP_OE_LCD_BRIGHTNESS 0x0007 |
943 | 24859b68 | balrog | |
944 | 343ec8e4 | Benoit Canet | typedef struct musicpal_gpio_state { |
945 | 343ec8e4 | Benoit Canet | SysBusDevice busdev; |
946 | 343ec8e4 | Benoit Canet | uint32_t lcd_brightness; |
947 | 343ec8e4 | Benoit Canet | uint32_t out_state; |
948 | 343ec8e4 | Benoit Canet | uint32_t in_state; |
949 | 343ec8e4 | Benoit Canet | uint32_t isr; |
950 | d074769c | Andrzej Zaborowski | uint32_t i2c_read_data; |
951 | 343ec8e4 | Benoit Canet | uint32_t key_released; |
952 | 343ec8e4 | Benoit Canet | uint32_t keys_event; /* store the received key event */
|
953 | 343ec8e4 | Benoit Canet | qemu_irq irq; |
954 | d074769c | Andrzej Zaborowski | qemu_irq out[5];
|
955 | 343ec8e4 | Benoit Canet | } musicpal_gpio_state; |
956 | 343ec8e4 | Benoit Canet | |
957 | 343ec8e4 | Benoit Canet | static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { |
958 | 343ec8e4 | Benoit Canet | int i;
|
959 | 343ec8e4 | Benoit Canet | uint32_t brightness; |
960 | 343ec8e4 | Benoit Canet | |
961 | 343ec8e4 | Benoit Canet | /* compute brightness ratio */
|
962 | 343ec8e4 | Benoit Canet | switch (s->lcd_brightness) {
|
963 | 343ec8e4 | Benoit Canet | case 0x00000007: |
964 | 343ec8e4 | Benoit Canet | brightness = 0;
|
965 | 343ec8e4 | Benoit Canet | break;
|
966 | 343ec8e4 | Benoit Canet | |
967 | 343ec8e4 | Benoit Canet | case 0x00020000: |
968 | 343ec8e4 | Benoit Canet | brightness = 1;
|
969 | 343ec8e4 | Benoit Canet | break;
|
970 | 343ec8e4 | Benoit Canet | |
971 | 343ec8e4 | Benoit Canet | case 0x00020001: |
972 | 343ec8e4 | Benoit Canet | brightness = 2;
|
973 | 343ec8e4 | Benoit Canet | break;
|
974 | 343ec8e4 | Benoit Canet | |
975 | 343ec8e4 | Benoit Canet | case 0x00040000: |
976 | 343ec8e4 | Benoit Canet | brightness = 3;
|
977 | 343ec8e4 | Benoit Canet | break;
|
978 | 343ec8e4 | Benoit Canet | |
979 | 343ec8e4 | Benoit Canet | case 0x00010006: |
980 | 343ec8e4 | Benoit Canet | brightness = 4;
|
981 | 343ec8e4 | Benoit Canet | break;
|
982 | 343ec8e4 | Benoit Canet | |
983 | 343ec8e4 | Benoit Canet | case 0x00020005: |
984 | 343ec8e4 | Benoit Canet | brightness = 5;
|
985 | 343ec8e4 | Benoit Canet | break;
|
986 | 343ec8e4 | Benoit Canet | |
987 | 343ec8e4 | Benoit Canet | case 0x00040003: |
988 | 343ec8e4 | Benoit Canet | brightness = 6;
|
989 | 343ec8e4 | Benoit Canet | break;
|
990 | 343ec8e4 | Benoit Canet | |
991 | 343ec8e4 | Benoit Canet | case 0x00030004: |
992 | 343ec8e4 | Benoit Canet | default:
|
993 | 343ec8e4 | Benoit Canet | brightness = 7;
|
994 | 343ec8e4 | Benoit Canet | } |
995 | 343ec8e4 | Benoit Canet | |
996 | 343ec8e4 | Benoit Canet | /* set lcd brightness GPIOs */
|
997 | 343ec8e4 | Benoit Canet | for (i = 0; i <= 2; i++) |
998 | 343ec8e4 | Benoit Canet | qemu_set_irq(s->out[i], (brightness >> i) & 1);
|
999 | 343ec8e4 | Benoit Canet | } |
1000 | 343ec8e4 | Benoit Canet | |
1001 | 343ec8e4 | Benoit Canet | static void musicpal_gpio_keys_update(musicpal_gpio_state *s) |
1002 | 343ec8e4 | Benoit Canet | { |
1003 | 343ec8e4 | Benoit Canet | int gpio_mask = 0; |
1004 | 343ec8e4 | Benoit Canet | |
1005 | 343ec8e4 | Benoit Canet | /* transform the key state for GPIO usage */
|
1006 | 343ec8e4 | Benoit Canet | gpio_mask |= (s->keys_event & 15) << 8; |
1007 | 343ec8e4 | Benoit Canet | gpio_mask |= ((s->keys_event >> 4) & 15) << 19; |
1008 | 343ec8e4 | Benoit Canet | |
1009 | 343ec8e4 | Benoit Canet | /* update GPIO state */
|
1010 | 343ec8e4 | Benoit Canet | if (s->key_released) {
|
1011 | 343ec8e4 | Benoit Canet | s->in_state |= gpio_mask; |
1012 | 343ec8e4 | Benoit Canet | } else {
|
1013 | 343ec8e4 | Benoit Canet | s->in_state &= ~gpio_mask; |
1014 | 343ec8e4 | Benoit Canet | s->isr = gpio_mask; |
1015 | 343ec8e4 | Benoit Canet | qemu_irq_raise(s->irq); |
1016 | 343ec8e4 | Benoit Canet | } |
1017 | 343ec8e4 | Benoit Canet | } |
1018 | 343ec8e4 | Benoit Canet | |
1019 | 343ec8e4 | Benoit Canet | static void musicpal_gpio_irq(void *opaque, int irq, int level) |
1020 | 343ec8e4 | Benoit Canet | { |
1021 | 343ec8e4 | Benoit Canet | musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; |
1022 | 343ec8e4 | Benoit Canet | |
1023 | d074769c | Andrzej Zaborowski | if (irq == 10) { |
1024 | d074769c | Andrzej Zaborowski | s->i2c_read_data = level; |
1025 | d074769c | Andrzej Zaborowski | } |
1026 | d074769c | Andrzej Zaborowski | |
1027 | 343ec8e4 | Benoit Canet | /* receives keys bits */
|
1028 | 343ec8e4 | Benoit Canet | if (irq <= 7) { |
1029 | 343ec8e4 | Benoit Canet | s->keys_event &= ~(1 << irq);
|
1030 | 343ec8e4 | Benoit Canet | s->keys_event |= level << irq; |
1031 | 343ec8e4 | Benoit Canet | return;
|
1032 | 343ec8e4 | Benoit Canet | } |
1033 | 343ec8e4 | Benoit Canet | |
1034 | 343ec8e4 | Benoit Canet | /* receives key press/release */
|
1035 | 343ec8e4 | Benoit Canet | if (irq == 8) { |
1036 | 343ec8e4 | Benoit Canet | s->key_released = level; |
1037 | 343ec8e4 | Benoit Canet | return;
|
1038 | 343ec8e4 | Benoit Canet | } |
1039 | 343ec8e4 | Benoit Canet | |
1040 | 343ec8e4 | Benoit Canet | /* a key has been transmited */
|
1041 | 343ec8e4 | Benoit Canet | if (irq == 9 && level == 1) |
1042 | 343ec8e4 | Benoit Canet | musicpal_gpio_keys_update(s); |
1043 | 343ec8e4 | Benoit Canet | } |
1044 | 343ec8e4 | Benoit Canet | |
1045 | 718ec0be | malc | static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
1046 | 24859b68 | balrog | { |
1047 | 343ec8e4 | Benoit Canet | musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; |
1048 | 343ec8e4 | Benoit Canet | |
1049 | 24859b68 | balrog | switch (offset) {
|
1050 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1051 | 343ec8e4 | Benoit Canet | return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
|
1052 | 24859b68 | balrog | |
1053 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1054 | 343ec8e4 | Benoit Canet | return s->out_state & 0xFFFF; |
1055 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1056 | 343ec8e4 | Benoit Canet | return s->out_state >> 16; |
1057 | 24859b68 | balrog | |
1058 | 24859b68 | balrog | case MP_GPIO_IN_LO:
|
1059 | 343ec8e4 | Benoit Canet | return s->in_state & 0xFFFF; |
1060 | 24859b68 | balrog | case MP_GPIO_IN_HI:
|
1061 | 24859b68 | balrog | /* Update received I2C data */
|
1062 | 343ec8e4 | Benoit Canet | s->in_state = (s->in_state & ~MP_GPIO_I2C_DATA) | |
1063 | d074769c | Andrzej Zaborowski | (s->i2c_read_data << MP_GPIO_I2C_DATA_BIT); |
1064 | 343ec8e4 | Benoit Canet | return s->in_state >> 16; |
1065 | 24859b68 | balrog | |
1066 | 24859b68 | balrog | case MP_GPIO_ISR_LO:
|
1067 | 343ec8e4 | Benoit Canet | return s->isr & 0xFFFF; |
1068 | 24859b68 | balrog | case MP_GPIO_ISR_HI:
|
1069 | 343ec8e4 | Benoit Canet | return s->isr >> 16; |
1070 | 24859b68 | balrog | |
1071 | 24859b68 | balrog | default:
|
1072 | 24859b68 | balrog | return 0; |
1073 | 24859b68 | balrog | } |
1074 | 24859b68 | balrog | } |
1075 | 24859b68 | balrog | |
1076 | 718ec0be | malc | static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
1077 | 718ec0be | malc | uint32_t value) |
1078 | 24859b68 | balrog | { |
1079 | 343ec8e4 | Benoit Canet | musicpal_gpio_state *s = (musicpal_gpio_state *) opaque; |
1080 | 24859b68 | balrog | switch (offset) {
|
1081 | 24859b68 | balrog | case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1082 | 343ec8e4 | Benoit Canet | s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
1083 | 24859b68 | balrog | (value & MP_OE_LCD_BRIGHTNESS); |
1084 | 343ec8e4 | Benoit Canet | musicpal_gpio_brightness_update(s); |
1085 | 24859b68 | balrog | break;
|
1086 | 24859b68 | balrog | |
1087 | 24859b68 | balrog | case MP_GPIO_OUT_LO:
|
1088 | 343ec8e4 | Benoit Canet | s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
1089 | 24859b68 | balrog | break;
|
1090 | 24859b68 | balrog | case MP_GPIO_OUT_HI:
|
1091 | 343ec8e4 | Benoit Canet | s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1092 | 343ec8e4 | Benoit Canet | s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
|
1093 | 343ec8e4 | Benoit Canet | (s->out_state & MP_GPIO_LCD_BRIGHTNESS); |
1094 | 343ec8e4 | Benoit Canet | musicpal_gpio_brightness_update(s); |
1095 | d074769c | Andrzej Zaborowski | qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1096 | d074769c | Andrzej Zaborowski | qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); |
1097 | 24859b68 | balrog | break;
|
1098 | 24859b68 | balrog | |
1099 | 24859b68 | balrog | } |
1100 | 24859b68 | balrog | } |
1101 | 24859b68 | balrog | |
1102 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = { |
1103 | 718ec0be | malc | musicpal_gpio_read, |
1104 | 718ec0be | malc | musicpal_gpio_read, |
1105 | 718ec0be | malc | musicpal_gpio_read, |
1106 | 718ec0be | malc | }; |
1107 | 718ec0be | malc | |
1108 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = { |
1109 | 718ec0be | malc | musicpal_gpio_write, |
1110 | 718ec0be | malc | musicpal_gpio_write, |
1111 | 718ec0be | malc | musicpal_gpio_write, |
1112 | 718ec0be | malc | }; |
1113 | 718ec0be | malc | |
1114 | 343ec8e4 | Benoit Canet | static void musicpal_gpio_reset(musicpal_gpio_state *s) |
1115 | 718ec0be | malc | { |
1116 | 343ec8e4 | Benoit Canet | s->in_state = 0xffffffff;
|
1117 | d074769c | Andrzej Zaborowski | s->i2c_read_data = 1;
|
1118 | 343ec8e4 | Benoit Canet | s->key_released = 0;
|
1119 | 343ec8e4 | Benoit Canet | s->keys_event = 0;
|
1120 | 343ec8e4 | Benoit Canet | s->isr = 0;
|
1121 | 343ec8e4 | Benoit Canet | } |
1122 | 343ec8e4 | Benoit Canet | |
1123 | 343ec8e4 | Benoit Canet | static void musicpal_gpio_init(SysBusDevice *dev) |
1124 | 343ec8e4 | Benoit Canet | { |
1125 | 343ec8e4 | Benoit Canet | musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev); |
1126 | 718ec0be | malc | int iomemtype;
|
1127 | 718ec0be | malc | |
1128 | 343ec8e4 | Benoit Canet | sysbus_init_irq(dev, &s->irq); |
1129 | 343ec8e4 | Benoit Canet | |
1130 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, |
1131 | 343ec8e4 | Benoit Canet | musicpal_gpio_writefn, s); |
1132 | 343ec8e4 | Benoit Canet | sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); |
1133 | 343ec8e4 | Benoit Canet | |
1134 | 343ec8e4 | Benoit Canet | musicpal_gpio_reset(s); |
1135 | 343ec8e4 | Benoit Canet | |
1136 | d074769c | Andrzej Zaborowski | /* 3 brightness out + 2 lcd (data and clock ) */
|
1137 | d074769c | Andrzej Zaborowski | qdev_init_gpio_out(&dev->qdev, s->out, 5);
|
1138 | d074769c | Andrzej Zaborowski | /* 10 gpio button input + 1 I2C data input */
|
1139 | d074769c | Andrzej Zaborowski | qdev_init_gpio_in(&dev->qdev, musicpal_gpio_irq, 11);
|
1140 | 718ec0be | malc | } |
1141 | 718ec0be | malc | |
1142 | 24859b68 | balrog | /* Keyboard codes & masks */
|
1143 | 7c6ce4ba | balrog | #define KEY_RELEASED 0x80 |
1144 | 24859b68 | balrog | #define KEY_CODE 0x7f |
1145 | 24859b68 | balrog | |
1146 | 24859b68 | balrog | #define KEYCODE_TAB 0x0f |
1147 | 24859b68 | balrog | #define KEYCODE_ENTER 0x1c |
1148 | 24859b68 | balrog | #define KEYCODE_F 0x21 |
1149 | 24859b68 | balrog | #define KEYCODE_M 0x32 |
1150 | 24859b68 | balrog | |
1151 | 24859b68 | balrog | #define KEYCODE_EXTENDED 0xe0 |
1152 | 24859b68 | balrog | #define KEYCODE_UP 0x48 |
1153 | 24859b68 | balrog | #define KEYCODE_DOWN 0x50 |
1154 | 24859b68 | balrog | #define KEYCODE_LEFT 0x4b |
1155 | 24859b68 | balrog | #define KEYCODE_RIGHT 0x4d |
1156 | 24859b68 | balrog | |
1157 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_VOL (1) |
1158 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1159 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_NAV (1 << 2) |
1160 | 343ec8e4 | Benoit Canet | #define MP_KEY_WHEEL_NAV_INV (1 << 3) |
1161 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_FAVORITS (1 << 4) |
1162 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_MENU (1 << 5) |
1163 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_VOLUME (1 << 6) |
1164 | 343ec8e4 | Benoit Canet | #define MP_KEY_BTN_NAVIGATION (1 << 7) |
1165 | 343ec8e4 | Benoit Canet | |
1166 | 343ec8e4 | Benoit Canet | typedef struct musicpal_key_state { |
1167 | 343ec8e4 | Benoit Canet | SysBusDevice busdev; |
1168 | 343ec8e4 | Benoit Canet | uint32_t kbd_extended; |
1169 | 343ec8e4 | Benoit Canet | uint32_t keys_state; |
1170 | 343ec8e4 | Benoit Canet | qemu_irq out[10];
|
1171 | 343ec8e4 | Benoit Canet | } musicpal_key_state; |
1172 | 343ec8e4 | Benoit Canet | |
1173 | 24859b68 | balrog | static void musicpal_key_event(void *opaque, int keycode) |
1174 | 24859b68 | balrog | { |
1175 | 343ec8e4 | Benoit Canet | musicpal_key_state *s = (musicpal_key_state *) opaque; |
1176 | 24859b68 | balrog | uint32_t event = 0;
|
1177 | 343ec8e4 | Benoit Canet | int i;
|
1178 | 24859b68 | balrog | |
1179 | 24859b68 | balrog | if (keycode == KEYCODE_EXTENDED) {
|
1180 | 343ec8e4 | Benoit Canet | s->kbd_extended = 1;
|
1181 | 24859b68 | balrog | return;
|
1182 | 24859b68 | balrog | } |
1183 | 24859b68 | balrog | |
1184 | 343ec8e4 | Benoit Canet | if (s->kbd_extended)
|
1185 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1186 | 24859b68 | balrog | case KEYCODE_UP:
|
1187 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
1188 | 24859b68 | balrog | break;
|
1189 | 24859b68 | balrog | |
1190 | 24859b68 | balrog | case KEYCODE_DOWN:
|
1191 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_NAV; |
1192 | 24859b68 | balrog | break;
|
1193 | 24859b68 | balrog | |
1194 | 24859b68 | balrog | case KEYCODE_LEFT:
|
1195 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
1196 | 24859b68 | balrog | break;
|
1197 | 24859b68 | balrog | |
1198 | 24859b68 | balrog | case KEYCODE_RIGHT:
|
1199 | 343ec8e4 | Benoit Canet | event = MP_KEY_WHEEL_VOL; |
1200 | 24859b68 | balrog | break;
|
1201 | 24859b68 | balrog | } |
1202 | 7c6ce4ba | balrog | else {
|
1203 | 24859b68 | balrog | switch (keycode & KEY_CODE) {
|
1204 | 24859b68 | balrog | case KEYCODE_F:
|
1205 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_FAVORITS; |
1206 | 24859b68 | balrog | break;
|
1207 | 24859b68 | balrog | |
1208 | 24859b68 | balrog | case KEYCODE_TAB:
|
1209 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_VOLUME; |
1210 | 24859b68 | balrog | break;
|
1211 | 24859b68 | balrog | |
1212 | 24859b68 | balrog | case KEYCODE_ENTER:
|
1213 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_NAVIGATION; |
1214 | 24859b68 | balrog | break;
|
1215 | 24859b68 | balrog | |
1216 | 24859b68 | balrog | case KEYCODE_M:
|
1217 | 343ec8e4 | Benoit Canet | event = MP_KEY_BTN_MENU; |
1218 | 24859b68 | balrog | break;
|
1219 | 24859b68 | balrog | } |
1220 | 7c6ce4ba | balrog | /* Do not repeat already pressed buttons */
|
1221 | 343ec8e4 | Benoit Canet | if (!(keycode & KEY_RELEASED) && !(s->keys_state & event))
|
1222 | 7c6ce4ba | balrog | event = 0;
|
1223 | 7c6ce4ba | balrog | } |
1224 | 24859b68 | balrog | |
1225 | 7c6ce4ba | balrog | if (event) {
|
1226 | 343ec8e4 | Benoit Canet | |
1227 | 343ec8e4 | Benoit Canet | /* transmit key event on GPIOS */
|
1228 | 343ec8e4 | Benoit Canet | for (i = 0; i <= 7; i++) |
1229 | 343ec8e4 | Benoit Canet | qemu_set_irq(s->out[i], (event >> i) & 1);
|
1230 | 343ec8e4 | Benoit Canet | |
1231 | 343ec8e4 | Benoit Canet | /* handle key press/release */
|
1232 | 7c6ce4ba | balrog | if (keycode & KEY_RELEASED) {
|
1233 | 343ec8e4 | Benoit Canet | s->keys_state |= event; |
1234 | 343ec8e4 | Benoit Canet | qemu_irq_raise(s->out[8]);
|
1235 | 7c6ce4ba | balrog | } else {
|
1236 | 343ec8e4 | Benoit Canet | s->keys_state &= ~event; |
1237 | 343ec8e4 | Benoit Canet | qemu_irq_lower(s->out[8]);
|
1238 | 7c6ce4ba | balrog | } |
1239 | 343ec8e4 | Benoit Canet | |
1240 | 343ec8e4 | Benoit Canet | /* signal that a key event occured */
|
1241 | 343ec8e4 | Benoit Canet | qemu_irq_pulse(s->out[9]);
|
1242 | 24859b68 | balrog | } |
1243 | 24859b68 | balrog | |
1244 | 343ec8e4 | Benoit Canet | s->kbd_extended = 0;
|
1245 | 343ec8e4 | Benoit Canet | } |
1246 | 343ec8e4 | Benoit Canet | |
1247 | 343ec8e4 | Benoit Canet | static void musicpal_key_init(SysBusDevice *dev) |
1248 | 343ec8e4 | Benoit Canet | { |
1249 | 343ec8e4 | Benoit Canet | musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev); |
1250 | 343ec8e4 | Benoit Canet | |
1251 | 343ec8e4 | Benoit Canet | sysbus_init_mmio(dev, 0x0, 0); |
1252 | 343ec8e4 | Benoit Canet | |
1253 | 343ec8e4 | Benoit Canet | s->kbd_extended = 0;
|
1254 | 343ec8e4 | Benoit Canet | s->keys_state = 0;
|
1255 | 343ec8e4 | Benoit Canet | |
1256 | 343ec8e4 | Benoit Canet | /* 8 key event GPIO + 1 key press/release + 1 strobe */
|
1257 | 343ec8e4 | Benoit Canet | qdev_init_gpio_out(&dev->qdev, s->out, 10);
|
1258 | 343ec8e4 | Benoit Canet | |
1259 | 343ec8e4 | Benoit Canet | qemu_add_kbd_event_handler(musicpal_key_event, s); |
1260 | 24859b68 | balrog | } |
1261 | 24859b68 | balrog | |
1262 | 24859b68 | balrog | static struct arm_boot_info musicpal_binfo = { |
1263 | 24859b68 | balrog | .loader_start = 0x0,
|
1264 | 24859b68 | balrog | .board_id = 0x20e,
|
1265 | 24859b68 | balrog | }; |
1266 | 24859b68 | balrog | |
1267 | fbe1b595 | Paul Brook | static void musicpal_init(ram_addr_t ram_size, |
1268 | 3023f332 | aliguori | const char *boot_device, |
1269 | 24859b68 | balrog | const char *kernel_filename, const char *kernel_cmdline, |
1270 | 24859b68 | balrog | const char *initrd_filename, const char *cpu_model) |
1271 | 24859b68 | balrog | { |
1272 | 24859b68 | balrog | CPUState *env; |
1273 | b47b50fa | Paul Brook | qemu_irq *cpu_pic; |
1274 | b47b50fa | Paul Brook | qemu_irq pic[32];
|
1275 | b47b50fa | Paul Brook | DeviceState *dev; |
1276 | d074769c | Andrzej Zaborowski | DeviceState *i2c_dev; |
1277 | 343ec8e4 | Benoit Canet | DeviceState *lcd_dev; |
1278 | 343ec8e4 | Benoit Canet | DeviceState *key_dev; |
1279 | d074769c | Andrzej Zaborowski | #ifdef HAS_AUDIO
|
1280 | d074769c | Andrzej Zaborowski | DeviceState *wm8750_dev; |
1281 | d074769c | Andrzej Zaborowski | SysBusDevice *s; |
1282 | d074769c | Andrzej Zaborowski | #endif
|
1283 | d074769c | Andrzej Zaborowski | i2c_bus *i2c; |
1284 | b47b50fa | Paul Brook | int i;
|
1285 | 24859b68 | balrog | unsigned long flash_size; |
1286 | 751c6a17 | Gerd Hoffmann | DriveInfo *dinfo; |
1287 | 13f59cbf | Andrzej Zaborowski | ram_addr_t sram_off; |
1288 | 24859b68 | balrog | |
1289 | 24859b68 | balrog | if (!cpu_model)
|
1290 | 24859b68 | balrog | cpu_model = "arm926";
|
1291 | 24859b68 | balrog | |
1292 | 24859b68 | balrog | env = cpu_init(cpu_model); |
1293 | 24859b68 | balrog | if (!env) {
|
1294 | 24859b68 | balrog | fprintf(stderr, "Unable to find CPU definition\n");
|
1295 | 24859b68 | balrog | exit(1);
|
1296 | 24859b68 | balrog | } |
1297 | b47b50fa | Paul Brook | cpu_pic = arm_pic_init_cpu(env); |
1298 | 24859b68 | balrog | |
1299 | 24859b68 | balrog | /* For now we use a fixed - the original - RAM size */
|
1300 | 24859b68 | balrog | cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
|
1301 | 24859b68 | balrog | qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); |
1302 | 24859b68 | balrog | |
1303 | 24859b68 | balrog | sram_off = qemu_ram_alloc(MP_SRAM_SIZE); |
1304 | 24859b68 | balrog | cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); |
1305 | 24859b68 | balrog | |
1306 | b47b50fa | Paul Brook | dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
|
1307 | b47b50fa | Paul Brook | cpu_pic[ARM_PIC_CPU_IRQ]); |
1308 | b47b50fa | Paul Brook | for (i = 0; i < 32; i++) { |
1309 | 067a3ddc | Paul Brook | pic[i] = qdev_get_gpio_in(dev, i); |
1310 | b47b50fa | Paul Brook | } |
1311 | b47b50fa | Paul Brook | sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
|
1312 | b47b50fa | Paul Brook | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
1313 | b47b50fa | Paul Brook | pic[MP_TIMER4_IRQ], NULL);
|
1314 | 24859b68 | balrog | |
1315 | 24859b68 | balrog | if (serial_hds[0]) |
1316 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1317 | 24859b68 | balrog | serial_hds[0], 1); |
1318 | 24859b68 | balrog | if (serial_hds[1]) |
1319 | b6cd0ea1 | aurel32 | serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1320 | 24859b68 | balrog | serial_hds[1], 1); |
1321 | 24859b68 | balrog | |
1322 | 24859b68 | balrog | /* Register flash */
|
1323 | 751c6a17 | Gerd Hoffmann | dinfo = drive_get(IF_PFLASH, 0, 0); |
1324 | 751c6a17 | Gerd Hoffmann | if (dinfo) {
|
1325 | 751c6a17 | Gerd Hoffmann | flash_size = bdrv_getlength(dinfo->bdrv); |
1326 | 24859b68 | balrog | if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1327 | 24859b68 | balrog | flash_size != 32*1024*1024) { |
1328 | 24859b68 | balrog | fprintf(stderr, "Invalid flash image size\n");
|
1329 | 24859b68 | balrog | exit(1);
|
1330 | 24859b68 | balrog | } |
1331 | 24859b68 | balrog | |
1332 | 24859b68 | balrog | /*
|
1333 | 24859b68 | balrog | * The original U-Boot accesses the flash at 0xFE000000 instead of
|
1334 | 24859b68 | balrog | * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
|
1335 | 24859b68 | balrog | * image is smaller than 32 MB.
|
1336 | 24859b68 | balrog | */
|
1337 | 24859b68 | balrog | pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
|
1338 | 751c6a17 | Gerd Hoffmann | dinfo->bdrv, 0x10000,
|
1339 | 24859b68 | balrog | (flash_size + 0xffff) >> 16, |
1340 | 24859b68 | balrog | MP_FLASH_SIZE_MAX / flash_size, |
1341 | 24859b68 | balrog | 2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1342 | 24859b68 | balrog | 0x5555, 0x2AAA); |
1343 | 24859b68 | balrog | } |
1344 | b47b50fa | Paul Brook | sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); |
1345 | 24859b68 | balrog | |
1346 | b47b50fa | Paul Brook | qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1347 | b47b50fa | Paul Brook | dev = qdev_create(NULL, "mv88w8618_eth"); |
1348 | ee6847d1 | Gerd Hoffmann | dev->nd = &nd_table[0];
|
1349 | b47b50fa | Paul Brook | qdev_init(dev); |
1350 | b47b50fa | Paul Brook | sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
|
1351 | b47b50fa | Paul Brook | sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
|
1352 | 24859b68 | balrog | |
1353 | b47b50fa | Paul Brook | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
1354 | 718ec0be | malc | |
1355 | 718ec0be | malc | musicpal_misc_init(); |
1356 | 343ec8e4 | Benoit Canet | |
1357 | 343ec8e4 | Benoit Canet | dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
|
1358 | d074769c | Andrzej Zaborowski | i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL); |
1359 | d074769c | Andrzej Zaborowski | i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
|
1360 | d074769c | Andrzej Zaborowski | |
1361 | 343ec8e4 | Benoit Canet | lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL); |
1362 | 343ec8e4 | Benoit Canet | key_dev = sysbus_create_simple("musicpal_key", 0, NULL); |
1363 | 343ec8e4 | Benoit Canet | |
1364 | d074769c | Andrzej Zaborowski | /* I2C read data */
|
1365 | d074769c | Andrzej Zaborowski | qdev_connect_gpio_out(i2c_dev, 0, qdev_get_gpio_in(dev, 10)); |
1366 | d074769c | Andrzej Zaborowski | /* I2C data */
|
1367 | d074769c | Andrzej Zaborowski | qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); |
1368 | d074769c | Andrzej Zaborowski | /* I2C clock */
|
1369 | d074769c | Andrzej Zaborowski | qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); |
1370 | d074769c | Andrzej Zaborowski | |
1371 | 343ec8e4 | Benoit Canet | for (i = 0; i < 3; i++) |
1372 | 343ec8e4 | Benoit Canet | qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
1373 | 343ec8e4 | Benoit Canet | |
1374 | 343ec8e4 | Benoit Canet | for (i = 0; i < 10; i++) |
1375 | 343ec8e4 | Benoit Canet | qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i)); |
1376 | 24859b68 | balrog | |
1377 | d074769c | Andrzej Zaborowski | #ifdef HAS_AUDIO
|
1378 | d074769c | Andrzej Zaborowski | wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
|
1379 | d074769c | Andrzej Zaborowski | dev = qdev_create(NULL, "mv88w8618_audio"); |
1380 | d074769c | Andrzej Zaborowski | s = sysbus_from_qdev(dev); |
1381 | d074769c | Andrzej Zaborowski | qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
|
1382 | d074769c | Andrzej Zaborowski | qdev_init(dev); |
1383 | d074769c | Andrzej Zaborowski | sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
|
1384 | d074769c | Andrzej Zaborowski | sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
|
1385 | d074769c | Andrzej Zaborowski | #endif
|
1386 | d074769c | Andrzej Zaborowski | |
1387 | 24859b68 | balrog | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1388 | 24859b68 | balrog | musicpal_binfo.kernel_filename = kernel_filename; |
1389 | 24859b68 | balrog | musicpal_binfo.kernel_cmdline = kernel_cmdline; |
1390 | 24859b68 | balrog | musicpal_binfo.initrd_filename = initrd_filename; |
1391 | b0f6edb1 | balrog | arm_load_kernel(env, &musicpal_binfo); |
1392 | 24859b68 | balrog | } |
1393 | 24859b68 | balrog | |
1394 | f80f9ec9 | Anthony Liguori | static QEMUMachine musicpal_machine = {
|
1395 | 4b32e168 | aliguori | .name = "musicpal",
|
1396 | 4b32e168 | aliguori | .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
|
1397 | 4b32e168 | aliguori | .init = musicpal_init, |
1398 | 24859b68 | balrog | }; |
1399 | b47b50fa | Paul Brook | |
1400 | f80f9ec9 | Anthony Liguori | static void musicpal_machine_init(void) |
1401 | f80f9ec9 | Anthony Liguori | { |
1402 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&musicpal_machine); |
1403 | f80f9ec9 | Anthony Liguori | } |
1404 | f80f9ec9 | Anthony Liguori | |
1405 | f80f9ec9 | Anthony Liguori | machine_init(musicpal_machine_init); |
1406 | f80f9ec9 | Anthony Liguori | |
1407 | b47b50fa | Paul Brook | static void musicpal_register_devices(void) |
1408 | b47b50fa | Paul Brook | { |
1409 | b47b50fa | Paul Brook | sysbus_register_dev("mv88w8618_pic", sizeof(mv88w8618_pic_state), |
1410 | b47b50fa | Paul Brook | mv88w8618_pic_init); |
1411 | b47b50fa | Paul Brook | sysbus_register_dev("mv88w8618_pit", sizeof(mv88w8618_pit_state), |
1412 | b47b50fa | Paul Brook | mv88w8618_pit_init); |
1413 | b47b50fa | Paul Brook | sysbus_register_dev("mv88w8618_flashcfg", sizeof(mv88w8618_flashcfg_state), |
1414 | b47b50fa | Paul Brook | mv88w8618_flashcfg_init); |
1415 | b47b50fa | Paul Brook | sysbus_register_dev("mv88w8618_eth", sizeof(mv88w8618_eth_state), |
1416 | b47b50fa | Paul Brook | mv88w8618_eth_init); |
1417 | b47b50fa | Paul Brook | sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice), |
1418 | b47b50fa | Paul Brook | mv88w8618_wlan_init); |
1419 | b47b50fa | Paul Brook | sysbus_register_dev("musicpal_lcd", sizeof(musicpal_lcd_state), |
1420 | b47b50fa | Paul Brook | musicpal_lcd_init); |
1421 | 343ec8e4 | Benoit Canet | sysbus_register_dev("musicpal_gpio", sizeof(musicpal_gpio_state), |
1422 | 343ec8e4 | Benoit Canet | musicpal_gpio_init); |
1423 | 343ec8e4 | Benoit Canet | sysbus_register_dev("musicpal_key", sizeof(musicpal_key_state), |
1424 | 343ec8e4 | Benoit Canet | musicpal_key_init); |
1425 | b47b50fa | Paul Brook | } |
1426 | b47b50fa | Paul Brook | |
1427 | b47b50fa | Paul Brook | device_init(musicpal_register_devices) |