Revision d63001d1 target-ppc/op_helper.c

b/target-ppc/op_helper.c
1061 1061
    switch (T0) {
1062 1062
    case 0x0CUL:
1063 1063
        /* Instruction cache line size */
1064
        T0 = ICACHE_LINE_SIZE;
1064
        T0 = env->icache_line_size;
1065 1065
        break;
1066 1066
    case 0x0DUL:
1067 1067
        /* Data cache line size */
1068
        T0 = DCACHE_LINE_SIZE;
1068
        T0 = env->dcache_line_size;
1069 1069
        break;
1070 1070
    case 0x0EUL:
1071 1071
        /* Minimum cache line size */
1072
        T0 = ICACHE_LINE_SIZE < DCACHE_LINE_SIZE ?
1073
            ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
1072
        T0 = env->icache_line_size < env->dcache_line_size ?
1073
            env->icache_line_size : env->dcache_line_size;
1074 1074
        break;
1075 1075
    case 0x0FUL:
1076 1076
        /* Maximum cache line size */
1077
        T0 = ICACHE_LINE_SIZE > DCACHE_LINE_SIZE ?
1078
            ICACHE_LINE_SIZE : DCACHE_LINE_SIZE;
1077
        T0 = env->icache_line_size > env->dcache_line_size ?
1078
            env->icache_line_size : env->dcache_line_size;
1079 1079
        break;
1080 1080
    default:
1081 1081
        /* Undefined */

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