Revision d63001d1 target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 169 | 169 |
#endif |
| 170 | 170 |
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
| 171 | 171 |
int singlestep_enabled; |
| 172 |
int dcache_line_size; |
|
| 172 | 173 |
} DisasContext; |
| 173 | 174 |
|
| 174 | 175 |
struct opc_handler_t {
|
| ... | ... | |
| 482 | 483 |
PPC_WAIT = 0x0000100000000000ULL, |
| 483 | 484 |
/* New 64 bits extensions (PowerPC 2.0x) */ |
| 484 | 485 |
PPC_64BX = 0x0000200000000000ULL, |
| 486 |
/* dcbz instruction with fixed cache line size */ |
|
| 487 |
PPC_CACHE_DCBZ = 0x0000400000000000ULL, |
|
| 488 |
/* dcbz instruction with tunable cache line size */ |
|
| 489 |
PPC_CACHE_DCBZT = 0x0000800000000000ULL, |
|
| 485 | 490 |
}; |
| 486 | 491 |
|
| 487 | 492 |
/*****************************************************************************/ |
| ... | ... | |
| 3623 | 3628 |
} |
| 3624 | 3629 |
|
| 3625 | 3630 |
/* dcbz */ |
| 3626 |
#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
|
|
| 3631 |
#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
|
|
| 3627 | 3632 |
#if defined(CONFIG_USER_ONLY) |
| 3628 | 3633 |
/* User-mode only */ |
| 3629 |
static GenOpFunc *gen_op_dcbz[] = {
|
|
| 3630 |
&gen_op_dcbz_raw, |
|
| 3631 |
&gen_op_dcbz_raw, |
|
| 3634 |
static GenOpFunc *gen_op_dcbz[4][4] = {
|
|
| 3635 |
{
|
|
| 3636 |
&gen_op_dcbz_l32_raw, |
|
| 3637 |
&gen_op_dcbz_l32_raw, |
|
| 3632 | 3638 |
#if defined(TARGET_PPC64) |
| 3633 |
&gen_op_dcbz_64_raw,
|
|
| 3634 |
&gen_op_dcbz_64_raw,
|
|
| 3639 |
&gen_op_dcbz_l32_64_raw,
|
|
| 3640 |
&gen_op_dcbz_l32_64_raw,
|
|
| 3635 | 3641 |
#endif |
| 3642 |
}, |
|
| 3643 |
{
|
|
| 3644 |
&gen_op_dcbz_l64_raw, |
|
| 3645 |
&gen_op_dcbz_l64_raw, |
|
| 3646 |
#if defined(TARGET_PPC64) |
|
| 3647 |
&gen_op_dcbz_l64_64_raw, |
|
| 3648 |
&gen_op_dcbz_l64_64_raw, |
|
| 3649 |
#endif |
|
| 3650 |
}, |
|
| 3651 |
{
|
|
| 3652 |
&gen_op_dcbz_l128_raw, |
|
| 3653 |
&gen_op_dcbz_l128_raw, |
|
| 3654 |
#if defined(TARGET_PPC64) |
|
| 3655 |
&gen_op_dcbz_l128_64_raw, |
|
| 3656 |
&gen_op_dcbz_l128_64_raw, |
|
| 3657 |
#endif |
|
| 3658 |
}, |
|
| 3659 |
{
|
|
| 3660 |
&gen_op_dcbz_raw, |
|
| 3661 |
&gen_op_dcbz_raw, |
|
| 3662 |
#if defined(TARGET_PPC64) |
|
| 3663 |
&gen_op_dcbz_64_raw, |
|
| 3664 |
&gen_op_dcbz_64_raw, |
|
| 3665 |
#endif |
|
| 3666 |
}, |
|
| 3636 | 3667 |
}; |
| 3637 | 3668 |
#else |
| 3638 | 3669 |
#if defined(TARGET_PPC64) |
| 3639 | 3670 |
/* Full system - 64 bits mode */ |
| 3640 |
static GenOpFunc *gen_op_dcbz[] = {
|
|
| 3641 |
&gen_op_dcbz_user, |
|
| 3642 |
&gen_op_dcbz_user, |
|
| 3643 |
&gen_op_dcbz_64_user, |
|
| 3644 |
&gen_op_dcbz_64_user, |
|
| 3645 |
&gen_op_dcbz_kernel, |
|
| 3646 |
&gen_op_dcbz_kernel, |
|
| 3647 |
&gen_op_dcbz_64_kernel, |
|
| 3648 |
&gen_op_dcbz_64_kernel, |
|
| 3671 |
static GenOpFunc *gen_op_dcbz[4][12] = {
|
|
| 3672 |
{
|
|
| 3673 |
&gen_op_dcbz_l32_user, |
|
| 3674 |
&gen_op_dcbz_l32_user, |
|
| 3675 |
&gen_op_dcbz_l32_64_user, |
|
| 3676 |
&gen_op_dcbz_l32_64_user, |
|
| 3677 |
&gen_op_dcbz_l32_kernel, |
|
| 3678 |
&gen_op_dcbz_l32_kernel, |
|
| 3679 |
&gen_op_dcbz_l32_64_kernel, |
|
| 3680 |
&gen_op_dcbz_l32_64_kernel, |
|
| 3681 |
#if defined(TARGET_PPC64H) |
|
| 3682 |
&gen_op_dcbz_l32_hypv, |
|
| 3683 |
&gen_op_dcbz_l32_hypv, |
|
| 3684 |
&gen_op_dcbz_l32_64_hypv, |
|
| 3685 |
&gen_op_dcbz_l32_64_hypv, |
|
| 3686 |
#endif |
|
| 3687 |
}, |
|
| 3688 |
{
|
|
| 3689 |
&gen_op_dcbz_l64_user, |
|
| 3690 |
&gen_op_dcbz_l64_user, |
|
| 3691 |
&gen_op_dcbz_l64_64_user, |
|
| 3692 |
&gen_op_dcbz_l64_64_user, |
|
| 3693 |
&gen_op_dcbz_l64_kernel, |
|
| 3694 |
&gen_op_dcbz_l64_kernel, |
|
| 3695 |
&gen_op_dcbz_l64_64_kernel, |
|
| 3696 |
&gen_op_dcbz_l64_64_kernel, |
|
| 3649 | 3697 |
#if defined(TARGET_PPC64H) |
| 3650 |
&gen_op_dcbz_hypv, |
|
| 3651 |
&gen_op_dcbz_hypv, |
|
| 3652 |
&gen_op_dcbz_64_hypv, |
|
| 3653 |
&gen_op_dcbz_64_hypv, |
|
| 3698 |
&gen_op_dcbz_l64_hypv, |
|
| 3699 |
&gen_op_dcbz_l64_hypv, |
|
| 3700 |
&gen_op_dcbz_l64_64_hypv, |
|
| 3701 |
&gen_op_dcbz_l64_64_hypv, |
|
| 3702 |
#endif |
|
| 3703 |
}, |
|
| 3704 |
{
|
|
| 3705 |
&gen_op_dcbz_l128_user, |
|
| 3706 |
&gen_op_dcbz_l128_user, |
|
| 3707 |
&gen_op_dcbz_l128_64_user, |
|
| 3708 |
&gen_op_dcbz_l128_64_user, |
|
| 3709 |
&gen_op_dcbz_l128_kernel, |
|
| 3710 |
&gen_op_dcbz_l128_kernel, |
|
| 3711 |
&gen_op_dcbz_l128_64_kernel, |
|
| 3712 |
&gen_op_dcbz_l128_64_kernel, |
|
| 3713 |
#if defined(TARGET_PPC64H) |
|
| 3714 |
&gen_op_dcbz_l128_hypv, |
|
| 3715 |
&gen_op_dcbz_l128_hypv, |
|
| 3716 |
&gen_op_dcbz_l128_64_hypv, |
|
| 3717 |
&gen_op_dcbz_l128_64_hypv, |
|
| 3718 |
#endif |
|
| 3719 |
}, |
|
| 3720 |
{
|
|
| 3721 |
&gen_op_dcbz_user, |
|
| 3722 |
&gen_op_dcbz_user, |
|
| 3723 |
&gen_op_dcbz_64_user, |
|
| 3724 |
&gen_op_dcbz_64_user, |
|
| 3725 |
&gen_op_dcbz_kernel, |
|
| 3726 |
&gen_op_dcbz_kernel, |
|
| 3727 |
&gen_op_dcbz_64_kernel, |
|
| 3728 |
&gen_op_dcbz_64_kernel, |
|
| 3729 |
#if defined(TARGET_PPC64H) |
|
| 3730 |
&gen_op_dcbz_hypv, |
|
| 3731 |
&gen_op_dcbz_hypv, |
|
| 3732 |
&gen_op_dcbz_64_hypv, |
|
| 3733 |
&gen_op_dcbz_64_hypv, |
|
| 3654 | 3734 |
#endif |
| 3735 |
}, |
|
| 3655 | 3736 |
}; |
| 3656 | 3737 |
#else |
| 3657 | 3738 |
/* Full system - 32 bits mode */ |
| 3658 |
static GenOpFunc *gen_op_dcbz[] = {
|
|
| 3659 |
&gen_op_dcbz_user, |
|
| 3660 |
&gen_op_dcbz_user, |
|
| 3661 |
&gen_op_dcbz_kernel, |
|
| 3662 |
&gen_op_dcbz_kernel, |
|
| 3739 |
static GenOpFunc *gen_op_dcbz[4][4] = {
|
|
| 3740 |
{
|
|
| 3741 |
&gen_op_dcbz_l32_user, |
|
| 3742 |
&gen_op_dcbz_l32_user, |
|
| 3743 |
&gen_op_dcbz_l32_kernel, |
|
| 3744 |
&gen_op_dcbz_l32_kernel, |
|
| 3745 |
}, |
|
| 3746 |
{
|
|
| 3747 |
&gen_op_dcbz_l64_user, |
|
| 3748 |
&gen_op_dcbz_l64_user, |
|
| 3749 |
&gen_op_dcbz_l64_kernel, |
|
| 3750 |
&gen_op_dcbz_l64_kernel, |
|
| 3751 |
}, |
|
| 3752 |
{
|
|
| 3753 |
&gen_op_dcbz_l128_user, |
|
| 3754 |
&gen_op_dcbz_l128_user, |
|
| 3755 |
&gen_op_dcbz_l128_kernel, |
|
| 3756 |
&gen_op_dcbz_l128_kernel, |
|
| 3757 |
}, |
|
| 3758 |
{
|
|
| 3759 |
&gen_op_dcbz_user, |
|
| 3760 |
&gen_op_dcbz_user, |
|
| 3761 |
&gen_op_dcbz_kernel, |
|
| 3762 |
&gen_op_dcbz_kernel, |
|
| 3763 |
}, |
|
| 3663 | 3764 |
}; |
| 3664 | 3765 |
#endif |
| 3665 | 3766 |
#endif |
| 3666 | 3767 |
|
| 3667 |
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE) |
|
| 3768 |
static inline void handler_dcbz (DisasContext *ctx, int dcache_line_size) |
|
| 3769 |
{
|
|
| 3770 |
int n; |
|
| 3771 |
|
|
| 3772 |
switch (dcache_line_size) {
|
|
| 3773 |
case 32: |
|
| 3774 |
n = 0; |
|
| 3775 |
break; |
|
| 3776 |
case 64: |
|
| 3777 |
n = 1; |
|
| 3778 |
break; |
|
| 3779 |
case 128: |
|
| 3780 |
n = 2; |
|
| 3781 |
break; |
|
| 3782 |
default: |
|
| 3783 |
n = 3; |
|
| 3784 |
break; |
|
| 3785 |
} |
|
| 3786 |
op_dcbz(n); |
|
| 3787 |
} |
|
| 3788 |
|
|
| 3789 |
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ) |
|
| 3668 | 3790 |
{
|
| 3669 | 3791 |
gen_addr_reg_index(ctx); |
| 3670 |
op_dcbz(); |
|
| 3792 |
handler_dcbz(ctx, ctx->dcache_line_size); |
|
| 3793 |
gen_op_check_reservation(); |
|
| 3794 |
} |
|
| 3795 |
|
|
| 3796 |
GEN_HANDLER(dcbz_970, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT) |
|
| 3797 |
{
|
|
| 3798 |
gen_addr_reg_index(ctx); |
|
| 3799 |
if (ctx->opcode & 0x00200000) |
|
| 3800 |
handler_dcbz(ctx, ctx->dcache_line_size); |
|
| 3801 |
else |
|
| 3802 |
handler_dcbz(ctx, -1); |
|
| 3671 | 3803 |
gen_op_check_reservation(); |
| 3672 | 3804 |
} |
| 3673 | 3805 |
|
| ... | ... | |
| 6341 | 6473 |
#else |
| 6342 | 6474 |
ctx.mem_idx = (supervisor << 1) | msr_le; |
| 6343 | 6475 |
#endif |
| 6476 |
ctx.dcache_line_size = env->dcache_line_size; |
|
| 6344 | 6477 |
ctx.fpu_enabled = msr_fp; |
| 6345 | 6478 |
#if defined(TARGET_PPCEMB) |
| 6346 | 6479 |
ctx.spe_enabled = msr_spe; |
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