Revision d656469f

b/cpu-defs.h
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#define CPU_TLB_BITS 8
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#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
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#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
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#define CPU_TLB_ENTRY_BITS 4
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#else
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#define CPU_TLB_ENTRY_BITS 5
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#endif
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typedef struct CPUTLBEntry {
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    /* bit 31 to TARGET_PAGE_BITS : virtual address
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       bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
......
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    target_ulong addr_write;
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    target_ulong addr_code;
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    /* addend to virtual address to get physical address */
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#if TARGET_PHYS_ADDR_BITS == 64
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    /* on i386 Linux make sure it is aligned */
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    target_phys_addr_t addend __attribute__((aligned(8)));
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#else
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    target_phys_addr_t addend;
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#endif
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    /* padding to get a power of two size */
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    uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 
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                  (sizeof(target_ulong) * 3 + 
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                   ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + 
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                   sizeof(target_phys_addr_t))];
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} CPUTLBEntry;
118 134

  
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#define CPU_COMMON                                                      \
b/osdep.h
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#define inline always_inline
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#ifdef __i386__
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#define REGPARM(n) __attribute((regparm(n)))
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#define REGPARM __attribute((regparm(3)))
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#else
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#define REGPARM(n)
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#define REGPARM
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#endif
43 43

  
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#define qemu_printf printf
b/softmmu_header.h
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#define ADDR_READ addr_read
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#endif
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DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                         int mmu_idx);
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void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
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void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
76 76

  
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#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
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    (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
79 79

  
80
#define CPU_TLB_ENTRY_BITS 4
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static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
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{
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    int res;
......
92 90
                  "cmpl (%%edx), %%eax\n"
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                  "movl %1, %%eax\n"
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                  "je 1f\n"
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                  "pushl %6\n"
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                  "movl %6, %%edx\n"
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                  "call %7\n"
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                  "popl %%edx\n"
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                  "movl %%eax, %0\n"
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                  "jmp 2f\n"
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                  "1:\n"
......
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                  "cmpl (%%edx), %%eax\n"
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                  "movl %1, %%eax\n"
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                  "je 1f\n"
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                  "pushl %6\n"
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                  "movl %6, %%edx\n"
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                  "call %7\n"
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                  "popl %%edx\n"
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#if DATA_SIZE == 1
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                  "movsbl %%al, %0\n"
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#elif DATA_SIZE == 2
......
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#else
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#error unsupported size
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#endif
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                  "pushl %6\n"
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                  "movl %6, %%ecx\n"
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                  "call %7\n"
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                  "popl %%eax\n"
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                  "jmp 2f\n"
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                  "1:\n"
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                  "addl 8(%%edx), %%eax\n"
b/softmmu_template.h
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}
76 76

  
77 77
/* handle all cases except unaligned access which span two pages */
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DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                         int mmu_idx)
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DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                      int mmu_idx)
80 80
{
81 81
    DATA_TYPE res;
82 82
    int index;
......
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#endif
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}
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void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                    DATA_TYPE val,
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                                                    int mmu_idx)
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void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
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                                                 DATA_TYPE val,
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                                                 int mmu_idx)
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{
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    target_phys_addr_t physaddr;
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    target_ulong tlb_addr;

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