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1 | 94cff60a | ths | /*
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2 | 94cff60a | ths | * CRIS mmu emulation.
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3 | 94cff60a | ths | *
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4 | 94cff60a | ths | * Copyright (c) 2007 AXIS Communications AB
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5 | 94cff60a | ths | * Written by Edgar E. Iglesias.
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6 | 94cff60a | ths | *
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7 | 94cff60a | ths | * This library is free software; you can redistribute it and/or
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8 | 94cff60a | ths | * modify it under the terms of the GNU Lesser General Public
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9 | 94cff60a | ths | * License as published by the Free Software Foundation; either
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10 | 94cff60a | ths | * version 2 of the License, or (at your option) any later version.
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11 | 94cff60a | ths | *
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12 | 94cff60a | ths | * This library is distributed in the hope that it will be useful,
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13 | 94cff60a | ths | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 94cff60a | ths | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 94cff60a | ths | * Lesser General Public License for more details.
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16 | 94cff60a | ths | *
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17 | 94cff60a | ths | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 94cff60a | ths | */
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20 | 94cff60a | ths | |
21 | 94cff60a | ths | #ifndef CONFIG_USER_ONLY
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22 | 94cff60a | ths | |
23 | 94cff60a | ths | #include <stdio.h> |
24 | 94cff60a | ths | #include <string.h> |
25 | 94cff60a | ths | #include <stdlib.h> |
26 | 94cff60a | ths | |
27 | 94cff60a | ths | #include "config.h" |
28 | 94cff60a | ths | #include "cpu.h" |
29 | 94cff60a | ths | #include "mmu.h" |
30 | 94cff60a | ths | #include "exec-all.h" |
31 | 94cff60a | ths | |
32 | d297f464 | edgar_igl | #ifdef DEBUG
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33 | d297f464 | edgar_igl | #define D(x) x
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34 | 02021c3f | Riccardo Magliocchetti | #define D_LOG(...) qemu_log(__VA_ARGS__)
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35 | d297f464 | edgar_igl | #else
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36 | 3ffd710e | Blue Swirl | #define D(x) do { } while (0) |
37 | d12d51d5 | aliguori | #define D_LOG(...) do { } while (0) |
38 | d297f464 | edgar_igl | #endif
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39 | 94cff60a | ths | |
40 | 44cd42ee | edgar_igl | void cris_mmu_init(CPUState *env)
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41 | 44cd42ee | edgar_igl | { |
42 | 44cd42ee | edgar_igl | env->mmu_rand_lfsr = 0xcccc;
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43 | 44cd42ee | edgar_igl | } |
44 | 44cd42ee | edgar_igl | |
45 | 44cd42ee | edgar_igl | #define SR_POLYNOM 0x8805 |
46 | 44cd42ee | edgar_igl | static inline unsigned int compute_polynom(unsigned int sr) |
47 | 44cd42ee | edgar_igl | { |
48 | 44cd42ee | edgar_igl | unsigned int i; |
49 | 44cd42ee | edgar_igl | unsigned int f; |
50 | 44cd42ee | edgar_igl | |
51 | 44cd42ee | edgar_igl | f = 0;
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52 | 44cd42ee | edgar_igl | for (i = 0; i < 16; i++) |
53 | 44cd42ee | edgar_igl | f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1); |
54 | 44cd42ee | edgar_igl | |
55 | 44cd42ee | edgar_igl | return f;
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56 | 44cd42ee | edgar_igl | } |
57 | 44cd42ee | edgar_igl | |
58 | 253248a3 | Edgar E. Iglesias | static void cris_mmu_update_rand_lfsr(CPUState *env) |
59 | 253248a3 | Edgar E. Iglesias | { |
60 | 253248a3 | Edgar E. Iglesias | unsigned int f; |
61 | 253248a3 | Edgar E. Iglesias | |
62 | 253248a3 | Edgar E. Iglesias | /* Update lfsr at every fault. */
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63 | 253248a3 | Edgar E. Iglesias | f = compute_polynom(env->mmu_rand_lfsr); |
64 | 253248a3 | Edgar E. Iglesias | env->mmu_rand_lfsr >>= 1;
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65 | 253248a3 | Edgar E. Iglesias | env->mmu_rand_lfsr |= (f << 15);
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66 | 253248a3 | Edgar E. Iglesias | env->mmu_rand_lfsr &= 0xffff;
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67 | 253248a3 | Edgar E. Iglesias | } |
68 | 253248a3 | Edgar E. Iglesias | |
69 | ef29a70d | edgar_igl | static inline int cris_mmu_enabled(uint32_t rw_gc_cfg) |
70 | 94cff60a | ths | { |
71 | 94cff60a | ths | return (rw_gc_cfg & 12) != 0; |
72 | 94cff60a | ths | } |
73 | 94cff60a | ths | |
74 | ef29a70d | edgar_igl | static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg) |
75 | 94cff60a | ths | { |
76 | 94cff60a | ths | return (1 << seg) & rw_mm_cfg; |
77 | 94cff60a | ths | } |
78 | 94cff60a | ths | |
79 | 94cff60a | ths | static uint32_t cris_mmu_translate_seg(CPUState *env, int seg) |
80 | 94cff60a | ths | { |
81 | 94cff60a | ths | uint32_t base; |
82 | 94cff60a | ths | int i;
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83 | 94cff60a | ths | |
84 | 94cff60a | ths | if (seg < 8) |
85 | 94cff60a | ths | base = env->sregs[SFR_RW_MM_KBASE_LO]; |
86 | 94cff60a | ths | else
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87 | 94cff60a | ths | base = env->sregs[SFR_RW_MM_KBASE_HI]; |
88 | 94cff60a | ths | |
89 | 94cff60a | ths | i = seg & 7;
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90 | 94cff60a | ths | base >>= i * 4;
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91 | 94cff60a | ths | base &= 15;
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92 | 94cff60a | ths | |
93 | 94cff60a | ths | base <<= 28;
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94 | 94cff60a | ths | return base;
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95 | 94cff60a | ths | } |
96 | 94cff60a | ths | /* Used by the tlb decoder. */
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97 | 94cff60a | ths | #define EXTRACT_FIELD(src, start, end) \
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98 | 786c02f1 | edgar_igl | (((src) >> start) & ((1 << (end - start + 1)) - 1)) |
99 | 786c02f1 | edgar_igl | |
100 | 786c02f1 | edgar_igl | static inline void set_field(uint32_t *dst, unsigned int val, |
101 | 786c02f1 | edgar_igl | unsigned int offset, unsigned int width) |
102 | 786c02f1 | edgar_igl | { |
103 | 786c02f1 | edgar_igl | uint32_t mask; |
104 | 786c02f1 | edgar_igl | |
105 | 786c02f1 | edgar_igl | mask = (1 << width) - 1; |
106 | 786c02f1 | edgar_igl | mask <<= offset; |
107 | 786c02f1 | edgar_igl | val <<= offset; |
108 | 786c02f1 | edgar_igl | |
109 | 786c02f1 | edgar_igl | val &= mask; |
110 | 786c02f1 | edgar_igl | *dst &= ~(mask); |
111 | 786c02f1 | edgar_igl | *dst |= val; |
112 | 786c02f1 | edgar_igl | } |
113 | 94cff60a | ths | |
114 | d297f464 | edgar_igl | #ifdef DEBUG
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115 | b41f7df0 | edgar_igl | static void dump_tlb(CPUState *env, int mmu) |
116 | b41f7df0 | edgar_igl | { |
117 | b41f7df0 | edgar_igl | int set;
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118 | b41f7df0 | edgar_igl | int idx;
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119 | b41f7df0 | edgar_igl | uint32_t hi, lo, tlb_vpn, tlb_pfn; |
120 | b41f7df0 | edgar_igl | |
121 | b41f7df0 | edgar_igl | for (set = 0; set < 4; set++) { |
122 | b41f7df0 | edgar_igl | for (idx = 0; idx < 16; idx++) { |
123 | b41f7df0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo; |
124 | b41f7df0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi; |
125 | b41f7df0 | edgar_igl | tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
126 | b41f7df0 | edgar_igl | tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
127 | b41f7df0 | edgar_igl | |
128 | b41f7df0 | edgar_igl | printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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129 | b41f7df0 | edgar_igl | set, idx, hi, lo, tlb_vpn, tlb_pfn); |
130 | b41f7df0 | edgar_igl | } |
131 | b41f7df0 | edgar_igl | } |
132 | b41f7df0 | edgar_igl | } |
133 | d297f464 | edgar_igl | #endif
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134 | b41f7df0 | edgar_igl | |
135 | b41f7df0 | edgar_igl | /* rw 0 = read, 1 = write, 2 = exec. */
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136 | 2fa73ec8 | Edgar E. Iglesias | static int cris_mmu_translate_page(struct cris_mmu_result *res, |
137 | 94cff60a | ths | CPUState *env, uint32_t vaddr, |
138 | 9f5a1fae | Edgar E. Iglesias | int rw, int usermode, int debug) |
139 | 94cff60a | ths | { |
140 | 94cff60a | ths | unsigned int vpage; |
141 | 94cff60a | ths | unsigned int idx; |
142 | b23761f9 | edgar_igl | uint32_t pid, lo, hi; |
143 | 786c02f1 | edgar_igl | uint32_t tlb_vpn, tlb_pfn = 0;
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144 | 786c02f1 | edgar_igl | int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
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145 | 786c02f1 | edgar_igl | int cfg_v, cfg_k, cfg_w, cfg_x;
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146 | b41f7df0 | edgar_igl | int set, match = 0; |
147 | 786c02f1 | edgar_igl | uint32_t r_cause; |
148 | 786c02f1 | edgar_igl | uint32_t r_cfg; |
149 | 786c02f1 | edgar_igl | int rwcause;
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150 | b41f7df0 | edgar_igl | int mmu = 1; /* Data mmu is default. */ |
151 | b41f7df0 | edgar_igl | int vect_base;
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152 | 786c02f1 | edgar_igl | |
153 | 786c02f1 | edgar_igl | r_cause = env->sregs[SFR_R_MM_CAUSE]; |
154 | 786c02f1 | edgar_igl | r_cfg = env->sregs[SFR_RW_MM_CFG]; |
155 | 28de16da | edgar_igl | pid = env->pregs[PR_PID] & 0xff;
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156 | b41f7df0 | edgar_igl | |
157 | b41f7df0 | edgar_igl | switch (rw) {
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158 | b41f7df0 | edgar_igl | case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break; |
159 | b41f7df0 | edgar_igl | case 1: rwcause = CRIS_MMU_ERR_WRITE; break; |
160 | b41f7df0 | edgar_igl | default:
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161 | b41f7df0 | edgar_igl | case 0: rwcause = CRIS_MMU_ERR_READ; break; |
162 | b41f7df0 | edgar_igl | } |
163 | b41f7df0 | edgar_igl | |
164 | b41f7df0 | edgar_igl | /* I exception vectors 4 - 7, D 8 - 11. */
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165 | b41f7df0 | edgar_igl | vect_base = (mmu + 1) * 4; |
166 | 94cff60a | ths | |
167 | 94cff60a | ths | vpage = vaddr >> 13;
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168 | 94cff60a | ths | |
169 | 94cff60a | ths | /* We know the index which to check on each set.
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170 | 94cff60a | ths | Scan both I and D. */
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171 | 786c02f1 | edgar_igl | #if 0
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172 | b41f7df0 | edgar_igl | for (set = 0; set < 4; set++) {
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173 | b41f7df0 | edgar_igl | for (idx = 0; idx < 16; idx++) {
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174 | b41f7df0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo;
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175 | b41f7df0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi;
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176 | 786c02f1 | edgar_igl | tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
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177 | 786c02f1 | edgar_igl | tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
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178 | 786c02f1 | edgar_igl | |
179 | 786c02f1 | edgar_igl | printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
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180 | b41f7df0 | edgar_igl | set, idx, hi, lo, tlb_vpn, tlb_pfn);
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181 | 786c02f1 | edgar_igl | }
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182 | 786c02f1 | edgar_igl | }
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183 | 786c02f1 | edgar_igl | #endif
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184 | b41f7df0 | edgar_igl | |
185 | b41f7df0 | edgar_igl | idx = vpage & 15;
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186 | b41f7df0 | edgar_igl | for (set = 0; set < 4; set++) |
187 | 94cff60a | ths | { |
188 | b41f7df0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo; |
189 | b41f7df0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi; |
190 | 94cff60a | ths | |
191 | b23761f9 | edgar_igl | tlb_vpn = hi >> 13;
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192 | 44cd42ee | edgar_igl | tlb_pid = EXTRACT_FIELD(hi, 0, 7); |
193 | 44cd42ee | edgar_igl | tlb_g = EXTRACT_FIELD(lo, 4, 4); |
194 | 94cff60a | ths | |
195 | d12d51d5 | aliguori | D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
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196 | d12d51d5 | aliguori | mmu, set, idx, tlb_vpn, vpage, lo, hi); |
197 | b23761f9 | edgar_igl | if ((tlb_g || (tlb_pid == pid))
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198 | 44cd42ee | edgar_igl | && tlb_vpn == vpage) { |
199 | 94cff60a | ths | match = 1;
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200 | 94cff60a | ths | break;
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201 | 94cff60a | ths | } |
202 | 94cff60a | ths | } |
203 | 94cff60a | ths | |
204 | b41f7df0 | edgar_igl | res->bf_vec = vect_base; |
205 | 94cff60a | ths | if (match) {
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206 | 786c02f1 | edgar_igl | cfg_w = EXTRACT_FIELD(r_cfg, 19, 19); |
207 | 786c02f1 | edgar_igl | cfg_k = EXTRACT_FIELD(r_cfg, 18, 18); |
208 | 786c02f1 | edgar_igl | cfg_x = EXTRACT_FIELD(r_cfg, 17, 17); |
209 | 786c02f1 | edgar_igl | cfg_v = EXTRACT_FIELD(r_cfg, 16, 16); |
210 | 786c02f1 | edgar_igl | |
211 | 786c02f1 | edgar_igl | tlb_pfn = EXTRACT_FIELD(lo, 13, 31); |
212 | 786c02f1 | edgar_igl | tlb_v = EXTRACT_FIELD(lo, 3, 3); |
213 | 786c02f1 | edgar_igl | tlb_k = EXTRACT_FIELD(lo, 2, 2); |
214 | 786c02f1 | edgar_igl | tlb_w = EXTRACT_FIELD(lo, 1, 1); |
215 | 786c02f1 | edgar_igl | tlb_x = EXTRACT_FIELD(lo, 0, 0); |
216 | 786c02f1 | edgar_igl | |
217 | 786c02f1 | edgar_igl | /*
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218 | 786c02f1 | edgar_igl | set_exception_vector(0x04, i_mmu_refill);
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219 | 786c02f1 | edgar_igl | set_exception_vector(0x05, i_mmu_invalid);
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220 | 786c02f1 | edgar_igl | set_exception_vector(0x06, i_mmu_access);
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221 | 786c02f1 | edgar_igl | set_exception_vector(0x07, i_mmu_execute);
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222 | 786c02f1 | edgar_igl | set_exception_vector(0x08, d_mmu_refill);
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223 | 786c02f1 | edgar_igl | set_exception_vector(0x09, d_mmu_invalid);
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224 | 786c02f1 | edgar_igl | set_exception_vector(0x0a, d_mmu_access);
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225 | 786c02f1 | edgar_igl | set_exception_vector(0x0b, d_mmu_write);
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226 | 786c02f1 | edgar_igl | */
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227 | 44cd42ee | edgar_igl | if (cfg_k && tlb_k && usermode) {
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228 | ef29a70d | edgar_igl | D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
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229 | ef29a70d | edgar_igl | vaddr, lo, env->pc)); |
230 | ef29a70d | edgar_igl | match = 0;
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231 | ef29a70d | edgar_igl | res->bf_vec = vect_base + 2;
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232 | b41f7df0 | edgar_igl | } else if (rw == 1 && cfg_w && !tlb_w) { |
233 | ef29a70d | edgar_igl | D(printf ("tlb: write protected %x lo=%x pc=%x\n",
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234 | ef29a70d | edgar_igl | vaddr, lo, env->pc)); |
235 | ef29a70d | edgar_igl | match = 0;
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236 | ef29a70d | edgar_igl | /* write accesses never go through the I mmu. */
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237 | ef29a70d | edgar_igl | res->bf_vec = vect_base + 3;
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238 | ef29a70d | edgar_igl | } else if (rw == 2 && cfg_x && !tlb_x) { |
239 | ef29a70d | edgar_igl | D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
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240 | ef29a70d | edgar_igl | vaddr, lo, env->pc)); |
241 | 786c02f1 | edgar_igl | match = 0;
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242 | b41f7df0 | edgar_igl | res->bf_vec = vect_base + 3;
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243 | b41f7df0 | edgar_igl | } else if (cfg_v && !tlb_v) { |
244 | b41f7df0 | edgar_igl | D(printf ("tlb: invalid %x\n", vaddr));
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245 | 786c02f1 | edgar_igl | match = 0;
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246 | b41f7df0 | edgar_igl | res->bf_vec = vect_base + 1;
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247 | 786c02f1 | edgar_igl | } |
248 | 786c02f1 | edgar_igl | |
249 | b41f7df0 | edgar_igl | res->prot = 0;
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250 | b41f7df0 | edgar_igl | if (match) {
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251 | b41f7df0 | edgar_igl | res->prot |= PAGE_READ; |
252 | b41f7df0 | edgar_igl | if (tlb_w)
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253 | b41f7df0 | edgar_igl | res->prot |= PAGE_WRITE; |
254 | 58aebb94 | Edgar E. Iglesias | if (mmu == 0 && (cfg_x || tlb_x)) |
255 | b41f7df0 | edgar_igl | res->prot |= PAGE_EXEC; |
256 | b41f7df0 | edgar_igl | } |
257 | b41f7df0 | edgar_igl | else
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258 | b41f7df0 | edgar_igl | D(dump_tlb(env, mmu)); |
259 | 44cd42ee | edgar_igl | } else {
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260 | 44cd42ee | edgar_igl | /* If refill, provide a randomized set. */
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261 | 44cd42ee | edgar_igl | set = env->mmu_rand_lfsr & 3;
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262 | 786c02f1 | edgar_igl | } |
263 | 786c02f1 | edgar_igl | |
264 | 9f5a1fae | Edgar E. Iglesias | if (!match && !debug) {
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265 | 253248a3 | Edgar E. Iglesias | cris_mmu_update_rand_lfsr(env); |
266 | 253248a3 | Edgar E. Iglesias | |
267 | 44cd42ee | edgar_igl | /* Compute index. */
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268 | b41f7df0 | edgar_igl | idx = vpage & 15;
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269 | b41f7df0 | edgar_igl | |
270 | b41f7df0 | edgar_igl | /* Update RW_MM_TLB_SEL. */
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271 | b41f7df0 | edgar_igl | env->sregs[SFR_RW_MM_TLB_SEL] = 0;
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272 | b41f7df0 | edgar_igl | set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4); |
273 | 44cd42ee | edgar_igl | set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2); |
274 | b41f7df0 | edgar_igl | |
275 | b41f7df0 | edgar_igl | /* Update RW_MM_CAUSE. */
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276 | b41f7df0 | edgar_igl | set_field(&r_cause, rwcause, 8, 2); |
277 | 786c02f1 | edgar_igl | set_field(&r_cause, vpage, 13, 19); |
278 | 28de16da | edgar_igl | set_field(&r_cause, pid, 0, 8); |
279 | 786c02f1 | edgar_igl | env->sregs[SFR_R_MM_CAUSE] = r_cause; |
280 | b41f7df0 | edgar_igl | D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
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281 | 94cff60a | ths | } |
282 | b41f7df0 | edgar_igl | |
283 | b41f7df0 | edgar_igl | D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
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284 | b41f7df0 | edgar_igl | " %x cause=%x sel=%x sp=%x %x %x\n",
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285 | b41f7df0 | edgar_igl | __func__, rw, match, env->pc, |
286 | 786c02f1 | edgar_igl | vaddr, vpage, |
287 | 786c02f1 | edgar_igl | tlb_vpn, tlb_pfn, tlb_pid, |
288 | 28de16da | edgar_igl | pid, |
289 | 786c02f1 | edgar_igl | r_cause, |
290 | 786c02f1 | edgar_igl | env->sregs[SFR_RW_MM_TLB_SEL], |
291 | b41f7df0 | edgar_igl | env->regs[R_SP], env->pregs[PR_USP], env->ksp)); |
292 | 786c02f1 | edgar_igl | |
293 | bf91ada5 | edgar_igl | res->phy = tlb_pfn << TARGET_PAGE_BITS; |
294 | 94cff60a | ths | return !match;
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295 | 94cff60a | ths | } |
296 | 94cff60a | ths | |
297 | cf1d97f0 | edgar_igl | void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
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298 | 786c02f1 | edgar_igl | { |
299 | cf1d97f0 | edgar_igl | target_ulong vaddr; |
300 | cf1d97f0 | edgar_igl | unsigned int idx; |
301 | cf1d97f0 | edgar_igl | uint32_t lo, hi; |
302 | cf1d97f0 | edgar_igl | uint32_t tlb_vpn; |
303 | 80e1b265 | edgar_igl | int tlb_pid, tlb_g, tlb_v;
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304 | cf1d97f0 | edgar_igl | unsigned int set; |
305 | cf1d97f0 | edgar_igl | unsigned int mmu; |
306 | cf1d97f0 | edgar_igl | |
307 | cf1d97f0 | edgar_igl | pid &= 0xff;
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308 | cf1d97f0 | edgar_igl | for (mmu = 0; mmu < 2; mmu++) { |
309 | cf1d97f0 | edgar_igl | for (set = 0; set < 4; set++) |
310 | cf1d97f0 | edgar_igl | { |
311 | cf1d97f0 | edgar_igl | for (idx = 0; idx < 16; idx++) { |
312 | cf1d97f0 | edgar_igl | lo = env->tlbsets[mmu][set][idx].lo; |
313 | cf1d97f0 | edgar_igl | hi = env->tlbsets[mmu][set][idx].hi; |
314 | cf1d97f0 | edgar_igl | |
315 | cf1d97f0 | edgar_igl | tlb_vpn = EXTRACT_FIELD(hi, 13, 31); |
316 | cf1d97f0 | edgar_igl | tlb_pid = EXTRACT_FIELD(hi, 0, 7); |
317 | cf1d97f0 | edgar_igl | tlb_g = EXTRACT_FIELD(lo, 4, 4); |
318 | cf1d97f0 | edgar_igl | tlb_v = EXTRACT_FIELD(lo, 3, 3); |
319 | cf1d97f0 | edgar_igl | |
320 | 80e1b265 | edgar_igl | if (tlb_v && !tlb_g && (tlb_pid == pid)) {
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321 | cf1d97f0 | edgar_igl | vaddr = tlb_vpn << TARGET_PAGE_BITS; |
322 | d12d51d5 | aliguori | D_LOG("flush pid=%x vaddr=%x\n",
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323 | d12d51d5 | aliguori | pid, vaddr); |
324 | cf1d97f0 | edgar_igl | tlb_flush_page(env, vaddr); |
325 | cf1d97f0 | edgar_igl | } |
326 | cf1d97f0 | edgar_igl | } |
327 | cf1d97f0 | edgar_igl | } |
328 | cf1d97f0 | edgar_igl | } |
329 | 786c02f1 | edgar_igl | } |
330 | 786c02f1 | edgar_igl | |
331 | 2fa73ec8 | Edgar E. Iglesias | int cris_mmu_translate(struct cris_mmu_result *res, |
332 | 94cff60a | ths | CPUState *env, uint32_t vaddr, |
333 | 9f5a1fae | Edgar E. Iglesias | int rw, int mmu_idx, int debug) |
334 | 94cff60a | ths | { |
335 | 94cff60a | ths | int seg;
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336 | 94cff60a | ths | int miss = 0; |
337 | 786c02f1 | edgar_igl | int is_user = mmu_idx == MMU_USER_IDX;
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338 | b41f7df0 | edgar_igl | uint32_t old_srs; |
339 | b41f7df0 | edgar_igl | |
340 | b41f7df0 | edgar_igl | old_srs= env->pregs[PR_SRS]; |
341 | b41f7df0 | edgar_igl | |
342 | b41f7df0 | edgar_igl | /* rw == 2 means exec, map the access to the insn mmu. */
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343 | b41f7df0 | edgar_igl | env->pregs[PR_SRS] = rw == 2 ? 1 : 2; |
344 | 94cff60a | ths | |
345 | 94cff60a | ths | if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
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346 | 94cff60a | ths | res->phy = vaddr; |
347 | b23761f9 | edgar_igl | res->prot = PAGE_BITS; |
348 | b41f7df0 | edgar_igl | goto done;
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349 | 94cff60a | ths | } |
350 | 94cff60a | ths | |
351 | 94cff60a | ths | seg = vaddr >> 28;
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352 | 218951ef | Edgar E. Iglesias | if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
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353 | 94cff60a | ths | { |
354 | 94cff60a | ths | uint32_t base; |
355 | 94cff60a | ths | |
356 | 94cff60a | ths | miss = 0;
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357 | 94cff60a | ths | base = cris_mmu_translate_seg(env, seg); |
358 | 0d84be5b | Blue Swirl | res->phy = base | (0x0fffffff & vaddr);
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359 | b23761f9 | edgar_igl | res->prot = PAGE_BITS; |
360 | 9f5a1fae | Edgar E. Iglesias | } else {
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361 | 9f5a1fae | Edgar E. Iglesias | miss = cris_mmu_translate_page(res, env, vaddr, rw, |
362 | 9f5a1fae | Edgar E. Iglesias | is_user, debug); |
363 | 94cff60a | ths | } |
364 | b41f7df0 | edgar_igl | done:
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365 | b41f7df0 | edgar_igl | env->pregs[PR_SRS] = old_srs; |
366 | 94cff60a | ths | return miss;
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367 | 94cff60a | ths | } |
368 | 94cff60a | ths | #endif |