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/*
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* QEMU 8253/8254 interval timer emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "qemu-timer.h" |
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//#define DEBUG_PIT
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#define RW_STATE_LSB 1 |
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#define RW_STATE_MSB 2 |
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#define RW_STATE_WORD0 3 |
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#define RW_STATE_WORD1 4 |
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typedef struct PITChannelState { |
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int count; /* can be 65536 */ |
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uint16_t latched_count; |
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uint8_t count_latched; |
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uint8_t status_latched; |
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uint8_t status; |
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uint8_t read_state; |
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uint8_t write_state; |
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uint8_t write_latch; |
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uint8_t rw_mode; |
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uint8_t mode; |
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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int64_t count_load_time; |
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/* irq handling */
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int64_t next_transition_time; |
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QEMUTimer *irq_timer; |
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qemu_irq irq; |
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} PITChannelState; |
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struct PITState {
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PITChannelState channels[3];
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}; |
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static PITState pit_state;
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
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static int pit_get_count(PITChannelState *s) |
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{ |
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uint64_t d; |
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int counter;
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d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, |
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get_ticks_per_sec()); |
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switch(s->mode) {
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case 0: |
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case 1: |
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case 4: |
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case 5: |
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counter = (s->count - d) & 0xffff;
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break;
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case 3: |
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/* XXX: may be incorrect for odd counts */
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counter = s->count - ((2 * d) % s->count);
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break;
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default:
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counter = s->count - (d % s->count); |
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break;
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} |
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return counter;
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} |
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/* get pit output bit */
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static int pit_get_out1(PITChannelState *s, int64_t current_time) |
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{ |
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uint64_t d; |
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int out;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
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get_ticks_per_sec()); |
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switch(s->mode) {
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default:
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case 0: |
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out = (d >= s->count); |
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break;
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case 1: |
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out = (d < s->count); |
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break;
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case 2: |
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if ((d % s->count) == 0 && d != 0) |
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out = 1;
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else
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out = 0;
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break;
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case 3: |
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out = (d % s->count) < ((s->count + 1) >> 1); |
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break;
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case 4: |
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case 5: |
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out = (d == s->count); |
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break;
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} |
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return out;
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} |
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int pit_get_out(PITState *pit, int channel, int64_t current_time) |
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{ |
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PITChannelState *s = &pit->channels[channel]; |
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return pit_get_out1(s, current_time);
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} |
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/* return -1 if no transition will occur. */
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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int64_t current_time) |
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{ |
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uint64_t d, next_time, base; |
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int period2;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, |
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get_ticks_per_sec()); |
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switch(s->mode) {
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default:
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case 0: |
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case 1: |
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if (d < s->count)
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next_time = s->count; |
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else
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return -1; |
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break;
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case 2: |
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base = (d / s->count) * s->count; |
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if ((d - base) == 0 && d != 0) |
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next_time = base + s->count; |
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else
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next_time = base + s->count + 1;
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break;
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case 3: |
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base = (d / s->count) * s->count; |
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period2 = ((s->count + 1) >> 1); |
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if ((d - base) < period2)
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next_time = base + period2; |
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else
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next_time = base + s->count; |
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break;
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case 4: |
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case 5: |
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if (d < s->count)
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next_time = s->count; |
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else if (d == s->count) |
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next_time = s->count + 1;
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else
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return -1; |
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break;
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} |
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/* convert to timer units */
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next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(), |
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PIT_FREQ); |
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/* fix potential rounding problems */
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/* XXX: better solution: use a clock at PIT_FREQ Hz */
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if (next_time <= current_time)
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next_time = current_time + 1;
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return next_time;
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} |
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/* val must be 0 or 1 */
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void pit_set_gate(PITState *pit, int channel, int val) |
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{ |
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PITChannelState *s = &pit->channels[channel]; |
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switch(s->mode) {
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default:
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case 0: |
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case 4: |
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/* XXX: just disable/enable counting */
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break;
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case 1: |
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case 5: |
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock(vm_clock); |
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pit_irq_timer_update(s, s->count_load_time); |
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} |
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break;
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case 2: |
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case 3: |
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock(vm_clock); |
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pit_irq_timer_update(s, s->count_load_time); |
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} |
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/* XXX: disable/enable counting */
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break;
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} |
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s->gate = val; |
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} |
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int pit_get_gate(PITState *pit, int channel) |
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{ |
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PITChannelState *s = &pit->channels[channel]; |
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return s->gate;
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} |
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int pit_get_initial_count(PITState *pit, int channel) |
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{ |
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PITChannelState *s = &pit->channels[channel]; |
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return s->count;
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} |
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int pit_get_mode(PITState *pit, int channel) |
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{ |
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PITChannelState *s = &pit->channels[channel]; |
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return s->mode;
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} |
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static inline void pit_load_count(PITChannelState *s, int val) |
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{ |
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if (val == 0) |
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val = 0x10000;
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s->count_load_time = qemu_get_clock(vm_clock); |
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s->count = val; |
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pit_irq_timer_update(s, s->count_load_time); |
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} |
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/* if already latched, do not latch again */
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static void pit_latch_count(PITChannelState *s) |
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{ |
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if (!s->count_latched) {
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s->latched_count = pit_get_count(s); |
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s->count_latched = s->rw_mode; |
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} |
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} |
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PITState *pit = opaque; |
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int channel, access;
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PITChannelState *s; |
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addr &= 3;
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if (addr == 3) { |
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channel = val >> 6;
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if (channel == 3) { |
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/* read back command */
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for(channel = 0; channel < 3; channel++) { |
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s = &pit->channels[channel]; |
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if (val & (2 << channel)) { |
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if (!(val & 0x20)) { |
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pit_latch_count(s); |
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} |
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if (!(val & 0x10) && !s->status_latched) { |
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/* status latch */
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/* XXX: add BCD and null count */
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s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
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(s->rw_mode << 4) |
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(s->mode << 1) |
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s->bcd; |
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s->status_latched = 1;
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} |
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} |
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} |
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} else {
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s = &pit->channels[channel]; |
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access = (val >> 4) & 3; |
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if (access == 0) { |
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pit_latch_count(s); |
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} else {
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s->rw_mode = access; |
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s->read_state = access; |
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s->write_state = access; |
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s->mode = (val >> 1) & 7; |
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s->bcd = val & 1;
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/* XXX: update irq timer ? */
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} |
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} |
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} else {
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s = &pit->channels[addr]; |
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switch(s->write_state) {
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default:
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case RW_STATE_LSB:
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pit_load_count(s, val); |
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break;
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case RW_STATE_MSB:
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pit_load_count(s, val << 8);
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break;
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case RW_STATE_WORD0:
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s->write_latch = val; |
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s->write_state = RW_STATE_WORD1; |
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break;
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case RW_STATE_WORD1:
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pit_load_count(s, s->write_latch | (val << 8));
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s->write_state = RW_STATE_WORD0; |
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break;
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} |
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} |
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} |
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static uint32_t pit_ioport_read(void *opaque, uint32_t addr) |
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{ |
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PITState *pit = opaque; |
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int ret, count;
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PITChannelState *s; |
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addr &= 3;
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s = &pit->channels[addr]; |
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if (s->status_latched) {
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s->status_latched = 0;
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ret = s->status; |
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} else if (s->count_latched) { |
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switch(s->count_latched) {
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default:
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case RW_STATE_LSB:
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ret = s->latched_count & 0xff;
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s->count_latched = 0;
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break;
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case RW_STATE_MSB:
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ret = s->latched_count >> 8;
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s->count_latched = 0;
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break;
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case RW_STATE_WORD0:
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ret = s->latched_count & 0xff;
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s->count_latched = RW_STATE_MSB; |
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break;
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} |
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} else {
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switch(s->read_state) {
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default:
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case RW_STATE_LSB:
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count = pit_get_count(s); |
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ret = count & 0xff;
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break;
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case RW_STATE_MSB:
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count = pit_get_count(s); |
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ret = (count >> 8) & 0xff; |
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break;
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case RW_STATE_WORD0:
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count = pit_get_count(s); |
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ret = count & 0xff;
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s->read_state = RW_STATE_WORD1; |
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break;
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case RW_STATE_WORD1:
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count = pit_get_count(s); |
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ret = (count >> 8) & 0xff; |
360 |
s->read_state = RW_STATE_WORD0; |
361 |
break;
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} |
363 |
} |
364 |
return ret;
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} |
366 |
|
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
368 |
{ |
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int64_t expire_time; |
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int irq_level;
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|
372 |
if (!s->irq_timer)
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return;
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expire_time = pit_get_next_transition_time(s, current_time); |
375 |
irq_level = pit_get_out1(s, current_time); |
376 |
qemu_set_irq(s->irq, irq_level); |
377 |
#ifdef DEBUG_PIT
|
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printf("irq_level=%d next_delay=%f\n",
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irq_level, |
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(double)(expire_time - current_time) / get_ticks_per_sec());
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#endif
|
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s->next_transition_time = expire_time; |
383 |
if (expire_time != -1) |
384 |
qemu_mod_timer(s->irq_timer, expire_time); |
385 |
else
|
386 |
qemu_del_timer(s->irq_timer); |
387 |
} |
388 |
|
389 |
static void pit_irq_timer(void *opaque) |
390 |
{ |
391 |
PITChannelState *s = opaque; |
392 |
|
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pit_irq_timer_update(s, s->next_transition_time); |
394 |
} |
395 |
|
396 |
static const VMStateDescription vmstate_pit_channel = { |
397 |
.name = "pit channel",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField []) { |
402 |
VMSTATE_INT32(count, PITChannelState), |
403 |
VMSTATE_UINT16(latched_count, PITChannelState), |
404 |
VMSTATE_UINT8(count_latched, PITChannelState), |
405 |
VMSTATE_UINT8(status_latched, PITChannelState), |
406 |
VMSTATE_UINT8(status, PITChannelState), |
407 |
VMSTATE_UINT8(read_state, PITChannelState), |
408 |
VMSTATE_UINT8(write_state, PITChannelState), |
409 |
VMSTATE_UINT8(write_latch, PITChannelState), |
410 |
VMSTATE_UINT8(rw_mode, PITChannelState), |
411 |
VMSTATE_UINT8(mode, PITChannelState), |
412 |
VMSTATE_UINT8(bcd, PITChannelState), |
413 |
VMSTATE_UINT8(gate, PITChannelState), |
414 |
VMSTATE_INT64(count_load_time, PITChannelState), |
415 |
VMSTATE_INT64(next_transition_time, PITChannelState), |
416 |
VMSTATE_END_OF_LIST() |
417 |
} |
418 |
}; |
419 |
|
420 |
static int pit_load_old(QEMUFile *f, void *opaque, int version_id) |
421 |
{ |
422 |
PITState *pit = opaque; |
423 |
PITChannelState *s; |
424 |
int i;
|
425 |
|
426 |
if (version_id != 1) |
427 |
return -EINVAL;
|
428 |
|
429 |
for(i = 0; i < 3; i++) { |
430 |
s = &pit->channels[i]; |
431 |
s->count=qemu_get_be32(f); |
432 |
qemu_get_be16s(f, &s->latched_count); |
433 |
qemu_get_8s(f, &s->count_latched); |
434 |
qemu_get_8s(f, &s->status_latched); |
435 |
qemu_get_8s(f, &s->status); |
436 |
qemu_get_8s(f, &s->read_state); |
437 |
qemu_get_8s(f, &s->write_state); |
438 |
qemu_get_8s(f, &s->write_latch); |
439 |
qemu_get_8s(f, &s->rw_mode); |
440 |
qemu_get_8s(f, &s->mode); |
441 |
qemu_get_8s(f, &s->bcd); |
442 |
qemu_get_8s(f, &s->gate); |
443 |
s->count_load_time=qemu_get_be64(f); |
444 |
if (s->irq_timer) {
|
445 |
s->next_transition_time=qemu_get_be64(f); |
446 |
qemu_get_timer(f, s->irq_timer); |
447 |
} |
448 |
} |
449 |
return 0; |
450 |
} |
451 |
|
452 |
static const VMStateDescription vmstate_pit = { |
453 |
.name = "i8254",
|
454 |
.version_id = 2,
|
455 |
.minimum_version_id = 2,
|
456 |
.minimum_version_id_old = 1,
|
457 |
.load_state_old = pit_load_old, |
458 |
.fields = (VMStateField []) { |
459 |
VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState), |
460 |
VMSTATE_TIMER(channels[0].irq_timer, PITState),
|
461 |
VMSTATE_END_OF_LIST() |
462 |
} |
463 |
}; |
464 |
|
465 |
static void pit_reset(void *opaque) |
466 |
{ |
467 |
PITState *pit = opaque; |
468 |
PITChannelState *s; |
469 |
int i;
|
470 |
|
471 |
for(i = 0;i < 3; i++) { |
472 |
s = &pit->channels[i]; |
473 |
s->mode = 3;
|
474 |
s->gate = (i != 2);
|
475 |
pit_load_count(s, 0);
|
476 |
} |
477 |
} |
478 |
|
479 |
/* When HPET is operating in legacy mode, i8254 timer0 is disabled */
|
480 |
void hpet_pit_disable(void) { |
481 |
PITChannelState *s; |
482 |
s = &pit_state.channels[0];
|
483 |
if (s->irq_timer)
|
484 |
qemu_del_timer(s->irq_timer); |
485 |
} |
486 |
|
487 |
/* When HPET is reset or leaving legacy mode, it must reenable i8254
|
488 |
* timer 0
|
489 |
*/
|
490 |
|
491 |
void hpet_pit_enable(void) |
492 |
{ |
493 |
PITState *pit = &pit_state; |
494 |
PITChannelState *s; |
495 |
s = &pit->channels[0];
|
496 |
s->mode = 3;
|
497 |
s->gate = 1;
|
498 |
pit_load_count(s, 0);
|
499 |
} |
500 |
|
501 |
PITState *pit_init(int base, qemu_irq irq)
|
502 |
{ |
503 |
PITState *pit = &pit_state; |
504 |
PITChannelState *s; |
505 |
|
506 |
s = &pit->channels[0];
|
507 |
/* the timer 0 is connected to an IRQ */
|
508 |
s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); |
509 |
s->irq = irq; |
510 |
|
511 |
vmstate_register(base, &vmstate_pit, pit); |
512 |
qemu_register_reset(pit_reset, pit); |
513 |
register_ioport_write(base, 4, 1, pit_ioport_write, pit); |
514 |
register_ioport_read(base, 3, 1, pit_ioport_read, pit); |
515 |
|
516 |
pit_reset(pit); |
517 |
|
518 |
return pit;
|
519 |
} |