Revision d6a6d362
| b/hw/ac97.c | ||
|---|---|---|
| 1226 | 1226 |
} |
| 1227 | 1227 |
}; |
| 1228 | 1228 |
|
| 1229 |
static const MemoryRegionPortio nam_portio[] = {
|
|
| 1230 |
{ 0, 256 * 1, 1, .read = nam_readb, },
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|
| 1231 |
{ 0, 256 * 2, 2, .read = nam_readw, },
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|
| 1232 |
{ 0, 256 * 4, 4, .read = nam_readl, },
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|
| 1233 |
{ 0, 256 * 1, 1, .write = nam_writeb, },
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|
| 1234 |
{ 0, 256 * 2, 2, .write = nam_writew, },
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|
| 1235 |
{ 0, 256 * 4, 4, .write = nam_writel, },
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|
| 1236 |
PORTIO_END_OF_LIST (), |
|
| 1237 |
}; |
|
| 1229 |
static uint64_t nam_read(void *opaque, hwaddr addr, unsigned size) |
|
| 1230 |
{
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|
| 1231 |
if ((addr / size) > 256) {
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|
| 1232 |
return -1; |
|
| 1233 |
} |
|
| 1234 |
|
|
| 1235 |
switch (size) {
|
|
| 1236 |
case 1: |
|
| 1237 |
return nam_readb(opaque, addr); |
|
| 1238 |
case 2: |
|
| 1239 |
return nam_readw(opaque, addr); |
|
| 1240 |
case 4: |
|
| 1241 |
return nam_readl(opaque, addr); |
|
| 1242 |
default: |
|
| 1243 |
return -1; |
|
| 1244 |
} |
|
| 1245 |
} |
|
| 1246 |
|
|
| 1247 |
static void nam_write(void *opaque, hwaddr addr, uint64_t val, |
|
| 1248 |
unsigned size) |
|
| 1249 |
{
|
|
| 1250 |
if ((addr / size) > 256) {
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|
| 1251 |
return; |
|
| 1252 |
} |
|
| 1253 |
|
|
| 1254 |
switch (size) {
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|
| 1255 |
case 1: |
|
| 1256 |
nam_writeb(opaque, addr, val); |
|
| 1257 |
break; |
|
| 1258 |
case 2: |
|
| 1259 |
nam_writew(opaque, addr, val); |
|
| 1260 |
break; |
|
| 1261 |
case 4: |
|
| 1262 |
nam_writel(opaque, addr, val); |
|
| 1263 |
break; |
|
| 1264 |
} |
|
| 1265 |
} |
|
| 1238 | 1266 |
|
| 1239 | 1267 |
static const MemoryRegionOps ac97_io_nam_ops = {
|
| 1240 |
.old_portio = nam_portio, |
|
| 1268 |
.read = nam_read, |
|
| 1269 |
.write = nam_write, |
|
| 1270 |
.impl = {
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|
| 1271 |
.min_access_size = 1, |
|
| 1272 |
.max_access_size = 4, |
|
| 1273 |
}, |
|
| 1274 |
.endianness = DEVICE_LITTLE_ENDIAN, |
|
| 1241 | 1275 |
}; |
| 1242 | 1276 |
|
| 1243 |
static const MemoryRegionPortio nabm_portio[] = {
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|
| 1244 |
{ 0, 64 * 1, 1, .read = nabm_readb, },
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|
| 1245 |
{ 0, 64 * 2, 2, .read = nabm_readw, },
|
|
| 1246 |
{ 0, 64 * 4, 4, .read = nabm_readl, },
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|
| 1247 |
{ 0, 64 * 1, 1, .write = nabm_writeb, },
|
|
| 1248 |
{ 0, 64 * 2, 2, .write = nabm_writew, },
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|
| 1249 |
{ 0, 64 * 4, 4, .write = nabm_writel, },
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|
| 1250 |
PORTIO_END_OF_LIST () |
|
| 1251 |
}; |
|
| 1277 |
static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size) |
|
| 1278 |
{
|
|
| 1279 |
if ((addr / size) > 64) {
|
|
| 1280 |
return -1; |
|
| 1281 |
} |
|
| 1282 |
|
|
| 1283 |
switch (size) {
|
|
| 1284 |
case 1: |
|
| 1285 |
return nabm_readb(opaque, addr); |
|
| 1286 |
case 2: |
|
| 1287 |
return nabm_readw(opaque, addr); |
|
| 1288 |
case 4: |
|
| 1289 |
return nabm_readl(opaque, addr); |
|
| 1290 |
default: |
|
| 1291 |
return -1; |
|
| 1292 |
} |
|
| 1293 |
} |
|
| 1294 |
|
|
| 1295 |
static void nabm_write(void *opaque, hwaddr addr, uint64_t val, |
|
| 1296 |
unsigned size) |
|
| 1297 |
{
|
|
| 1298 |
if ((addr / size) > 64) {
|
|
| 1299 |
return; |
|
| 1300 |
} |
|
| 1301 |
|
|
| 1302 |
switch (size) {
|
|
| 1303 |
case 1: |
|
| 1304 |
nabm_writeb(opaque, addr, val); |
|
| 1305 |
break; |
|
| 1306 |
case 2: |
|
| 1307 |
nabm_writew(opaque, addr, val); |
|
| 1308 |
break; |
|
| 1309 |
case 4: |
|
| 1310 |
nabm_writel(opaque, addr, val); |
|
| 1311 |
break; |
|
| 1312 |
} |
|
| 1313 |
} |
|
| 1314 |
|
|
| 1252 | 1315 |
|
| 1253 | 1316 |
static const MemoryRegionOps ac97_io_nabm_ops = {
|
| 1254 |
.old_portio = nabm_portio, |
|
| 1317 |
.read = nabm_read, |
|
| 1318 |
.write = nabm_write, |
|
| 1319 |
.impl = {
|
|
| 1320 |
.min_access_size = 1, |
|
| 1321 |
.max_access_size = 4, |
|
| 1322 |
}, |
|
| 1323 |
.endianness = DEVICE_LITTLE_ENDIAN, |
|
| 1255 | 1324 |
}; |
| 1256 | 1325 |
|
| 1257 | 1326 |
static void ac97_on_reset (void *opaque) |
Also available in: Unified diff