Revision d7156f7c tcg/README
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All this opcodes assume that the pointed host memory doesn't correspond |
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to a global. In the latter case the behaviour is unpredictable. |
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********* Multiword arithmetic support |
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* add2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high |
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* sub2_i32/i64 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high |
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Similar to add/sub, except that the double-word inputs T1 and T2 are |
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formed from two single-word arguments, and the double-word output T0 |
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is returned in two single-word outputs. |
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* mulu2_i32/i64 t0_low, t0_high, t1, t2 |
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Similar to mul, except two unsigned inputs T1 and T2 yielding the full |
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double-word product T0. The later is returned in two single-word outputs. |
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********* 64-bit target on 32-bit host support |
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The following opcodes are internal to TCG. Thus they are to be implemented by |
| ... | ... | |
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Similar to brcond, except that the 64-bit values T0 and T1 |
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are formed from two 32-bit arguments. |
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* add2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high |
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* sub2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high |
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Similar to add/sub, except that the 64-bit inputs T1 and T2 are |
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formed from two 32-bit arguments, and the 64-bit output T0 |
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is returned in two 32-bit outputs. |
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* mulu2_i32 t0_low, t0_high, t1, t2 |
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Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding |
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the full 64-bit product T0. The later is returned in two 32-bit outputs. |
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* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond |
| 388 | 390 |
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Similar to setcond, except that the 64-bit values T1 and T2 are |
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