root / target-sparc / cpu.h @ d720b93d
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
5 | 3cf1e035 | bellard | |
6 | 7a3f1944 | bellard | #include "cpu-defs.h" |
7 | 7a3f1944 | bellard | |
8 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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9 | 7a3f1944 | bellard | |
10 | cf495bcf | bellard | /* trap definitions */
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11 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
12 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
13 | cf495bcf | bellard | #define TT_WIN_UNF 0x06 |
14 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
15 | cf495bcf | bellard | #define TT_TRAP 0x80 |
16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | #define PSR_NEG (1<<23) |
18 | 7a3f1944 | bellard | #define PSR_ZERO (1<<22) |
19 | 7a3f1944 | bellard | #define PSR_OVF (1<<21) |
20 | 7a3f1944 | bellard | #define PSR_CARRY (1<<20) |
21 | 7a3f1944 | bellard | |
22 | cf495bcf | bellard | #define NWINDOWS 32 |
23 | cf495bcf | bellard | |
24 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
25 | cf495bcf | bellard | uint32_t gregs[8]; /* general registers */ |
26 | cf495bcf | bellard | uint32_t *regwptr; /* pointer to current register window */
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27 | cf495bcf | bellard | double *regfptr; /* floating point registers */ |
28 | cf495bcf | bellard | uint32_t pc; /* program counter */
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29 | cf495bcf | bellard | uint32_t npc; /* next program counter */
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30 | cf495bcf | bellard | uint32_t sp; /* stack pointer */
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31 | cf495bcf | bellard | uint32_t y; /* multiply/divide register */
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32 | cf495bcf | bellard | uint32_t psr; /* processor state register */
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33 | cf495bcf | bellard | uint32_t T2; |
34 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
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35 | cf495bcf | bellard | from PSR) */
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36 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
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37 | cf495bcf | bellard | jmp_buf jmp_env; |
38 | cf495bcf | bellard | int user_mode_only;
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39 | cf495bcf | bellard | int exception_index;
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40 | cf495bcf | bellard | int interrupt_index;
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41 | cf495bcf | bellard | int interrupt_request;
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42 | cf495bcf | bellard | struct TranslationBlock *current_tb;
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43 | cf495bcf | bellard | void *opaque;
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44 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
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45 | cf495bcf | bellard | uint32_t regbase[NWINDOWS * 16 + 8]; |
46 | d720b93d | bellard | |
47 | d720b93d | bellard | /* in order to avoid passing too many arguments to the memory
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48 | d720b93d | bellard | write helpers, we store some rarely used information in the CPU
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49 | d720b93d | bellard | context) */
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50 | d720b93d | bellard | unsigned long mem_write_pc; /* host pc at which the memory was |
51 | d720b93d | bellard | written */
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52 | d720b93d | bellard | unsigned long mem_write_vaddr; /* target virtual addr at which the |
53 | d720b93d | bellard | memory was written */
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54 | 7a3f1944 | bellard | } CPUSPARCState; |
55 | 7a3f1944 | bellard | |
56 | 7a3f1944 | bellard | CPUSPARCState *cpu_sparc_init(void);
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57 | 7a3f1944 | bellard | int cpu_sparc_exec(CPUSPARCState *s);
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58 | 7a3f1944 | bellard | int cpu_sparc_close(CPUSPARCState *s);
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59 | 7a3f1944 | bellard | |
60 | 7a3f1944 | bellard | struct siginfo;
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61 | 7a3f1944 | bellard | int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc); |
62 | 7a3f1944 | bellard | void cpu_sparc_dump_state(CPUSPARCState *env, FILE *f, int flags); |
63 | 7a3f1944 | bellard | |
64 | 7a3f1944 | bellard | #define TARGET_PAGE_BITS 13 |
65 | 7a3f1944 | bellard | #include "cpu-all.h" |
66 | 7a3f1944 | bellard | |
67 | 7a3f1944 | bellard | #endif |