tcg/i386: Add shortcuts for registers used in L constraint
While 64 bit hosts use the first three registers which are also usedas function input parameters, 32 bit hosts use TCG_REG_EAX andTCG_REG_EDX which are not used in parameter passing.
After defining new register macros for the registers used in L...
tcg/i386: Remove unused registers from tcg_target_call_iarg_regs
32 bit x86 hosts don't need registers for helper function argumentsbecause they use the default stack based calling convention.
Removing the registers allows simpler code for functiontcg_target_get_call_iarg_regs_count....
tcg-hppa: Implement movcond
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/README: document tcg_gen_goto_tb restrictions
Seehttp://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.htmlfor the whole story.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
w64: Fix TCG helper functions with 5 arguments
TCG uses 6 registers for function arguments on 64 bit Linux hosts,but only 4 registers on W64 hosts.
Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the numberof arguments for some important helper functions from 4 to 5...
tcg/optimize: rework copy progagation
The copy propagation pass tries to keep track what is a copy of whatand what has copy of what, and in addition it keep a circular list ofof all the copies. Unfortunately this doesn't fully work: a mov froma temp which has a state "COPY" changed it into a state "HAS_COPY"....
tcg/optimize: do copy propagation for all operations
It is possible to due copy propagation for all operations, even the onethat have side effects or clobber arguments (it only concerns inputarguments). That said, the call operation should be handled differently...
tcg/optimize: optimize "op r, a, a => mov r, a"
Now that we can easily detect all copies, we can optimize the"op r, a, a => mov r, a" case a bit more.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/optimize: optimize "op r, a, a => movi r, 0"
Now that it's possible to detect copies, we can optimize the casethe "op r, a, a => movi r, 0". This helps in the computation ofoverflow flags when one of the two args is 0.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg/optimize: further optimize brcond/movcond/setcond
When both argument of brcond/movcond/setcond are the same or when oneof the two values is a constant equal to zero, it's possible to dofurther optimizations.
tcg/optimize: prefer the "op a, a, b" form for commutative ops
The "op a, a, b" form is better handled on non-RISC host than the "opa, b, a" form, so swap the arguments to this form when possible, andwhen b is not a constant.
This reduces the number of generated instructions by a tiny bit....
tcg: remove #ifdef #endif around TCGOpcode tests
Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don'tneed to #ifdef #endif the one that are available only on some targets.This makes the code easier to read.
tcg/optimize: add constant folding for deposit
tcg/mips: optimize brcond arg, 0
MIPS has some conditional branch instructions when comparing with zero.Use them.
tcg/mips: optimize bswap{16,16s,32} on MIPS32R2
bswap operations can be optimized on MIPS32 Release 2 using the ROTR,WSBH and SEH instructions. We can't use the non-R2 code to implement theops due to registers constraints, so don't define the corresponding...
tcg/mips: implement rotl/rotr ops on MIPS32R2
rotr operations can be optimized on MIPS32 Release 2 using the ROTR andROTRV instructions. Also implemented rotl operations by subtracting theshift from 32.
tcg/mips: implement deposit op on MIPS32R2
deposit operations can be optimized on MIPS32 Release 2 using the INSinstruction.
tcg/mips: implement movcond op on MIPS32R2
movcond operation can be implemented on MIPS32 Release 2 using the MOVN,MOVZ, SLT and SLTU instructions.
tcg/optimize: remove TCG_TEMP_ANY
TCG_TEMP_ANY has no different meaning than TCG_TEMP_UNDEF, so usethe later instead.
tcg/optimize: check types in copy propagation
The copy propagation doesn't check the types of the temps during copypropagation. However TCG is using the mov_i32 for the i64 to i32conversion and thus the two are not equivalent.
With this patch tcg_opt_gen_mov() doesn't consider two temps of...
tcg-mips: fix wrong usage of 'Z' constraint
The 'Z' constraint has been introduced to map the zero register. Howeverwhen the op also accept a constant, there is no point to accept the zeroregister in addition.
tcg/mips: kill warnings in user mode
Recent versions of GCC emit warnings when compiling user mode targets.Kill them by reordering a bit the #ifdef.
tcg/mips: use TCGArg or TCGReg instead of int
Instead of int, use the correct TCGArg and TCGReg type: TCGReg whenrepresenting a TCG target register, TCGArg when representing the latteror a constant.
tcg/mips: don't use global pointer
Don't use the global pointer in TCG, in case helpers try access globalvariables.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/mips: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCGtemps.
tcg-hppa: Fix broken load/store helpers
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helperswas not respecting the ABI requirement for 64-bit valuesbeing aligned in registers.
Mirror the ARM port in use of helper functions to marshalarguments into the correct registers....
tcg-i386: Implement movcond
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Optimize movcond for constant comparisons
tcg: Optimize two-address commutative operations
While swapping constants to the second operand, swapsources matching destinations to the first operand.
tcg: Fix !USE_DIRECT_JUMP
Commit 6375e09e changed the type of TranslationBlock.tb_next,but failed to change the type of TCGContext.tb_next.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-hppa: Fix brcond2 and setcond2
Neither of these functions were performing double-wordcompares properly.
tcg: Introduce movcond
Implemented with setcond if the target does not providethe optional opcode.
tcg/optimize: fix end of basic block detection
Commit e31b0a7c050711884ad570fe73df806520953618 fixed copy propagation on32-bit host by restricting the copy between different types. This was thewrong fix.
The real problem is that the all temps states should be reset at the end...
revert "TCG: fix copy propagation"
Given the copy propagation breakage on 32-bit hosts has been fixedcommit e31b0a7c050711884ad570fe73df806520953618 can be reverted.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/i386: allow constants in load/store ops
On x86, it is possible to move a constant value to memory. Add code tohandle a constant argument to load/store ops.
tcg: mark set_label with TCG_OPF_BB_END flag
set_label is effectively the end of a basic block, as no optimizationcan be made accross it. It was treated as such in the liveness analysiscode, but as a special case.
Mark it with TCG_OPF_BB_END flag so that this information can be used...
Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
Remove dyngen-exec.h and all references to it. Although included byhw/spapr_hcall.c, it does not seem to use it....
tcg/optimize: fix if/else/break coding style
optimizer.c contains some cases were the break is appearing in both theif and the else parts. Fix that by moving it to the outer part. Alsomove some common code there.
tcg/optimize: add constant folding for brcond
tcg/optimize: add constant folding for setcond
tcg/optimize: swap brcond/setcond arguments when possible
brcond and setcond ops are not commutative, but it's easy to compute thenew condition after swapping the arguments. Try to always put the constantargument in second position like for commutative ops, to help backends to...
tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
shift/rot r, 0, a is equivalent to movi r, 0.
tcg/optimize: simplify and r, a, 0 cases
and r, a, 0 is equivalent to a movi r, 0.
tcg/optimize: simplify or/xor r, a, 0 cases
or/xor r, a, 0 is equivalent to a mov r, a.
tcg/optimize: split expression simplification
Split expression simplification in multiple parts so that a given opcan appear multiple times. This patch should not change anything.
tcg: improve profiler
Now that there are two passes of optimization (optimize.c, liveness)there is no point of outputing the statistics of the liveness partonly. Update the code to take into account both optimizations.
tcg/s390: fix ld/st with CONFIG_TCG_PASS_AREG0
The load/store slow path has been broken in e141ab52d:- We need to move 4 registers for store functions and 3 registers for load functions and not the reverse.- According to the s390x calling convention the arguments of a function...
tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 code
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers wasbroken in that it did not respect the ABI requirement that 64bit values were passed in even-odd register pairs. The simplestway to fix this is to implement some new utility functions...
tcg/ia64: fix and optimize ld/st slow path
Store slow path has been broken in e141ab52d:- the arguments are shifted before the last one (mem_index) is written.- the shift is done for both slow and fast paths.
Fix that. Also optimize a bit by bundling the move together. This still...
tcg/ia64: fix prologue/epilogue
Prologue and epilogue code has been broken in cea5f9a28.
tcg/arm: Fix broken CONFIG_TCG_PASS_AREG0 code
tci: don't write zero for reloc in tci_out_label
If tci_out_label is called in the context of tcg_gen_code_search_pc, wecould be overwriting an already patched relocation with zero -- and notrepatch it because the set_label is past search_pc, causing a QEMU crash...
TCG: Fix compile breakage in tcg_dump_ops
Commit eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convertall users (notably missing the ppc ones) to it. Fix them to the new syntax.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: malc <av1474@comtv.ru>
qemu-log: cleanup
Don't use global variables directly but via accessor functions. Rename globals.
Convert macros to functions, add GCC format attributes.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/ppc: Handle _CALL_DARWIN being undefined on Darwin
powerpc-apple-darwin9-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5577)does not define _CALL_DARWIN, leading to unexpected behavior w.r.t.register clobbering and stack frame layout.
Since _CALL_DARWIN is a reserved identifier, define a custom...
tcg/ppc64: Don't hardcode register numbers for qemu_ld/st
Facilitates using r3 for prepended AREG0.
Signed-off-by: Andreas F?rber <afaerber@suse.de>Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0
In qemu_ld/st load the registers for the helper calls directly ratherthan rotating them around afterwards for AREG0.
Also clobber the additional register.
tcg/ppc: Don't hardcode register numbers
Also assure i64 alignment where necessary.
Alignment code optimization suggested by malc.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
tcg/ppc: Clobber r5 for 64-bit qemu_ld
This accounts for the additional addr_reg2 register.
tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode
Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,based on patches by malc.
Also adjust the registers clobbered, based on patch by Alex.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>...
tcg/ppc: Do not overwrite lower address word on Darwin and AIX
For targets where TARGET_LONG_BITS != 32, i.e. 64-bit guests,addr_reg is moved to r4. For hosts without TCG_TARGET_CALL_ALIGN_ARGSeither data_reg2 or data_reg or a masked version thereof would overwrite...
Bail out if CONFIG_TCG_PASS_AREG0 is defined
Signed-off-by: malc <av1474@comtv.ru>
Restore consistent formatting
tcg/i386: Use GDB JIT debugging interface only for hosts with ELF
Not all i386 / x86_64 hosts use ELF.Ask the compiler whether ELF is used.
On w64, gdb crashes when ELF_HOST_MACHINE is defined.
Cc: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>...
tcg/i386: Add support for w64 ABI
w64 uses the registers rcx, rdx, r8 and r9 for function arguments,so it needs a different declaration of tcg_target_call_iarg_regs.
rax, rcx, rdx, r8, r9, r10 and r11 may be changed by function calls.
rbx, rbp, rdi, rsi, r12, r13, r14 and r15 remain unchanged by function calls....
qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs
There two entries of INDEX_op_ld_i64 in the ppc_op_defs. That causes anassertion failure in tcg_add_target_add_op_defs() when --enable-debug isused on a ppc64 backend (that's ppc64 host, not target)....
tcg-sparc: Add debug_frame support.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-hppa: Add debug_frame support.
tcg: Allow ELF_HOST_FLAGS and ELF_OSABI overrides in gdb-jit.
tcg: Add debug_info to JIT ELF image.
This allows us to actually supply a function name in softmmu builds;gdb doesn't pick up the minimal symbol table otherwise. Also add abit of documentation and statically generate more of the ELF image.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg: Use the GDB JIT debugging interface.
This allows us to generate unwind info for the dynamicly generatedcode in the code_gen_buffer. Only i386 is converted at this point.
tcg: fix sparc host for AREG0 free operation
e141ab52d2ea5d0bc6ad3b1ad32841127ca04adc didn't handlethe other memory access helper case, fix.
softmmu templates: optionally pass CPUState to memory access functions
Optionally, make memory access helpers take a parameter for CPUStateinstead of relying on global env.
On most targets, perform simple moves to reorder registers. On i386,switch from regparm(3) calling convention to standard stack-based...
i386: Remove REGPARM
Use stack based calling convention (GCC default) for interfacing withgenerated code instead of register based convention (regparm(3)).
w64: Fix data type of next_tb and tcg_qemu_tb_exec
next_tb is the numeric value of a tcg target (= QEMU host) address.
Using tcg_target_ulong instead of unsigned long shows this and makesthe code portable for hosts with an unusual size of long (w64).
The type cast '(long)(next_tb & ~3)' was not needed (casting...
Fix large memory chunks allocation with tcg_malloc.
An attempt to allocate a large memory chunk after a small one resulted incircular links in list of pools. It caused the same memory beingallocated twice for different arrays.
Now pools for large memory chunks are kept in separate list and are...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
tcg: Improve tcg_out_label and fix its usage for w64
tcg_out_label is always called with a third argument of pointer typewhich was casted to tcg_target_long.
These casts can be avoided by changing the prototype of tcg_out_label.
There was also a cast to long. For most hosts with...
w64: fix type casts when calling flush_icache_range
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
w64: Change data type of parameters for flush_icache_range
The TCG targets i386 and tci needed a change of the functionprototype for w64.
This change is currently not needed for the other TCG targets,but it can be applied to avoid code differences.
Cc: Blue Swirl <blauwirbel@gmail.com>...
w64: Fix data type of parameters for flush_icache_range
flush_icache_range takes two address parameters which must be largeenough to address any address of the host.
For hosts with sizeof(unsigned long) == sizeof(void *), this patchchanges nothing. All currently supported hosts fall into this category....
tcg: Rearrange definitions and include statements
This change makes tcg_target_ulong available in tcg-target.h.
tcg: Remove unneeded include statements
The standard include files are already included in qemu-common.h.
malloc.h and alloca.h were needed for alloca() which was removedfrom TCG code some years ago when switching from dyngen to TCG(see commit 49516bc0d622112caac9df628caf19010fda8b67)....
tcg-arm: fix a typo in comments
ARM still doesn't support 16GB buffers in 32-bit modes, replace the16GB by 16MB in the comment.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
tcg/arm: Use r6 as TCG_AREG0 to avoid clash with Thumb framepointer
On ARM, in Thumb mode r7 is used for the framepointer; this meantthat we would fail to compile in debug mode because we were using r7for TCG_AREG0. Shift to r6 instead to avoid this clash....
tcg/arm: remove fixed map code buffer restriction
On ARM, don't map the code buffer at a fixed location, and fix up thecall/goto tcg routines to let it do long jumps.
Mapping the code buffer at a fixed address could sometimes result in it beingmapped over the top of the heap with pretty random results....
tcg: make tcg_const_ptr actually accept a pointer argument
Make tcg_const_ptr() include a cast so that you can pass it apointer. This allows us to drop the casts we had in all the placesthat use this macro.
Acked-by: Andreas Färber <andreas.faerber@web.de>...
tcg: Remove redundant declarations of TCG_TARGET_REG_BITS
TCG_TARGET_REG_BITS is declared in tcg.h for all TCG targets.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
fix spelling in tcg sub directory
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
tci: Make flush_icache_range() inline
This is standard for other tcg targets and improves tci, too.
Signed-off-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
tcg-sparc: Fix set-but-not used warnings.
In both cases, val is computed, but then not used in thesubsequent line, which then re-computes the quantity ina different type (int32_t vs unsigned long).
Keep the computation type that's been working so far....
Merge branch 's390-1.0' of git://repo.or.cz/qemu/agraf
tcg: Use TCGReg for standard tcg-target entry points.
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Stefan Weil <sw@weilnetz.de>...
tcg: Standardize on TCGReg as the enum for hard registers
Most targets did not name the enum; tci used TCGRegister.
tcg-ppc64: Fix compile errors for userspace only builds with gcc 4.6
tcg/ppc64/tcg-target.c has a couple of places where variables are setunconditionally, but otherwise used only for softmmu builds, notuserspace only builds. This causes compiler warnings (which are fatal...
Merge branch 'tci' of git://qemu.weilnetz.de/qemu
tcg: Fix whitespace in tcg-op.h.
Removing the only tabs in the file.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: malc <av1474@comtv.ru>
tcg: Fix regression in tcg_gen_deposit_i64.
The error being caused by the failure to copy the other half ofthe input to the output after having narrowed the deposit operation.
tcg: Make ARRAY_SIZE(tcg_op_defs) globally available
tcg_op_defs was already a global array.
The tci disassembler also needs ARRAY_SIZE(tcg_op_defs),so add a new global constant with this value.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
tcg: Add bytecode generator for tcg interpreter
Unlike other tcg target code generators, this one does not generatemachine code for some cpu. It generates machine independent bytecodewhich is interpreted later.
This allows running QEMU on any host.
Interpreted bytecode is slower than direct execution of generated...