Revision d7585251
| b/hw/mips_malta.c | ||
|---|---|---|
| 521 | 521 |
a3 - RAM size in bytes |
| 522 | 522 |
*/ |
| 523 | 523 |
|
| 524 |
static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry) |
|
| 524 |
static void write_bootloader (CPUState *env, uint8_t *base, |
|
| 525 |
int64_t kernel_entry) |
|
| 525 | 526 |
{
|
| 526 | 527 |
uint32_t *p; |
| 527 | 528 |
|
| 528 | 529 |
/* Small bootloader */ |
| 529 |
p = (uint32_t *) (phys_ram_base + bios_offset);
|
|
| 530 |
p = (uint32_t *)base;
|
|
| 530 | 531 |
stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */ |
| 531 | 532 |
stl_raw(p++, 0x00000000); /* nop */ |
| 532 | 533 |
|
| 533 | 534 |
/* YAMON service vector */ |
| 534 |
stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
|
|
| 535 |
stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
|
|
| 536 |
stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
|
|
| 537 |
stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
|
|
| 538 |
stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
|
|
| 539 |
stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
|
|
| 540 |
stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
|
|
| 541 |
stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
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|
| 542 |
stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
|
|
| 543 |
stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
|
|
| 544 |
stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
|
|
| 545 |
stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
|
|
| 546 |
stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
|
|
| 535 |
stl_raw(base + 0x500, 0xbfc00580); /* start: */
|
|
| 536 |
stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
|
|
| 537 |
stl_raw(base + 0x520, 0xbfc00580); /* start: */
|
|
| 538 |
stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
|
|
| 539 |
stl_raw(base + 0x534, 0xbfc00808); /* print: */
|
|
| 540 |
stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
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| 541 |
stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
|
|
| 542 |
stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
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| 543 |
stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
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| 544 |
stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
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| 545 |
stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
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| 546 |
stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
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| 547 |
stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
|
|
| 547 | 548 |
|
| 548 | 549 |
|
| 549 | 550 |
/* Second part of the bootloader */ |
| 550 |
p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
|
|
| 551 |
p = (uint32_t *) (base + 0x580);
|
|
| 551 | 552 |
stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */ |
| 552 | 553 |
stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */ |
| 553 | 554 |
stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */ |
| ... | ... | |
| 616 | 617 |
stl_raw(p++, 0x00000000); /* nop */ |
| 617 | 618 |
|
| 618 | 619 |
/* YAMON subroutines */ |
| 619 |
p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
|
|
| 620 |
p = (uint32_t *) (base + 0x800);
|
|
| 620 | 621 |
stl_raw(p++, 0x03e00008); /* jr ra */ |
| 621 | 622 |
stl_raw(p++, 0x24020000); /* li v0,0 */ |
| 622 | 623 |
/* 808 YAMON print */ |
| ... | ... | |
| 662 | 663 |
|
| 663 | 664 |
static void prom_set(int index, const char *string, ...) |
| 664 | 665 |
{
|
| 666 |
char buf[ENVP_ENTRY_SIZE]; |
|
| 667 |
target_phys_addr_t p; |
|
| 665 | 668 |
va_list ap; |
| 666 |
int32_t *p; |
|
| 667 | 669 |
int32_t table_addr; |
| 668 |
char *s; |
|
| 669 | 670 |
|
| 670 | 671 |
if (index >= ENVP_NB_ENTRIES) |
| 671 | 672 |
return; |
| 672 | 673 |
|
| 673 |
p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND); |
|
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p += index; |
|
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p = ENVP_ADDR + VIRT_TO_PHYS_ADDEND + index * 4; |
|
| 675 | 675 |
|
| 676 | 676 |
if (string == NULL) {
|
| 677 |
stl_raw(p, 0);
|
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| 677 |
stl_phys(p, 0);
|
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| 678 | 678 |
return; |
| 679 | 679 |
} |
| 680 | 680 |
|
| 681 |
table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; |
|
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s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr); |
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| 683 |
|
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| 681 |
table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES |
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| 682 |
+ index * ENVP_ENTRY_SIZE + VIRT_TO_PHYS_ADDEND; |
|
| 684 | 683 |
stl_raw(p, table_addr); |
| 685 | 684 |
|
| 686 | 685 |
va_start(ap, string); |
| 687 |
vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
|
|
| 686 |
vsnprintf(buf, ENVP_ENTRY_SIZE, string, ap);
|
|
| 688 | 687 |
va_end(ap); |
| 688 |
pstrcpy_targphys(table_addr, ENVP_ENTRY_SIZE, buf); |
|
| 689 | 689 |
} |
| 690 | 690 |
|
| 691 | 691 |
/* Kernel */ |
| ... | ... | |
| 834 | 834 |
loaderparams.initrd_filename = initrd_filename; |
| 835 | 835 |
kernel_entry = load_kernel(env); |
| 836 | 836 |
env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); |
| 837 |
write_bootloader(env, bios_offset, kernel_entry);
|
|
| 837 |
write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
|
|
| 838 | 838 |
} else {
|
| 839 | 839 |
index = drive_get_index(IF_PFLASH, 0, fl_idx); |
| 840 | 840 |
if (index != -1) {
|
| ... | ... | |
| 868 | 868 |
a neat trick which allows bi-endian firmware. */ |
| 869 | 869 |
#ifndef TARGET_WORDS_BIGENDIAN |
| 870 | 870 |
{
|
| 871 |
uint32_t *addr; |
|
| 872 |
for (addr = (uint32_t *)(phys_ram_base + bios_offset); |
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| 873 |
addr < (uint32_t *)(phys_ram_base + bios_offset + bios_size); |
|
| 874 |
addr++) {
|
|
| 875 |
*addr = bswap32(*addr); |
|
| 871 |
uint32_t *addr = qemu_get_ram_ptr(bios_offset);; |
|
| 872 |
uint32_t *end = addr + bios_size; |
|
| 873 |
while (addr < end) {
|
|
| 874 |
bswap32s(addr); |
|
| 876 | 875 |
} |
| 877 | 876 |
} |
| 878 | 877 |
#endif |
| ... | ... | |
| 881 | 880 |
/* Board ID = 0x420 (Malta Board with CoreLV) |
| 882 | 881 |
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should |
| 883 | 882 |
map to the board ID. */ |
| 884 |
stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
|
|
| 883 |
stl_phys(0x1fc00010LL, 0x00000420);
|
|
| 885 | 884 |
|
| 886 | 885 |
/* Init internal devices */ |
| 887 | 886 |
cpu_mips_irq_init_cpu(env); |
| b/hw/mips_r4k.c | ||
|---|---|---|
| 80 | 80 |
int64_t entry, kernel_low, kernel_high; |
| 81 | 81 |
long kernel_size, initrd_size; |
| 82 | 82 |
ram_addr_t initrd_offset; |
| 83 |
int ret; |
|
| 83 | 84 |
|
| 84 | 85 |
kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
| 85 | 86 |
(uint64_t *)&entry, (uint64_t *)&kernel_low, |
| ... | ... | |
| 120 | 121 |
|
| 121 | 122 |
/* Store command line. */ |
| 122 | 123 |
if (initrd_size > 0) {
|
| 123 |
int ret; |
|
| 124 |
ret = sprintf((char *)(phys_ram_base + (16 << 20) - 256), |
|
| 125 |
"rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
|
| 126 |
PHYS_TO_VIRT((uint32_t)initrd_offset), |
|
| 127 |
initrd_size); |
|
| 128 |
strcpy ((char *)(phys_ram_base + (16 << 20) - 256 + ret), |
|
| 129 |
loaderparams.kernel_cmdline); |
|
| 130 |
} |
|
| 131 |
else {
|
|
| 132 |
strcpy ((char *)(phys_ram_base + (16 << 20) - 256), |
|
| 133 |
loaderparams.kernel_cmdline); |
|
| 124 |
char buf[64]; |
|
| 125 |
ret = snprintf(buf, 64, "rd_start=0x" TARGET_FMT_lx " rd_size=%li ", |
|
| 126 |
PHYS_TO_VIRT((uint32_t)initrd_offset), |
|
| 127 |
initrd_size); |
|
| 128 |
cpu_physical_memory_write((16 << 20) - 256, (void *)buf, 64); |
|
| 129 |
} else {
|
|
| 130 |
ret = 0; |
|
| 134 | 131 |
} |
| 132 |
pstrcpy_targphys((16 << 20) - 256 + ret, 256, |
|
| 133 |
loaderparams.kernel_cmdline); |
|
| 135 | 134 |
|
| 136 |
*(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
|
|
| 137 |
*(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
|
|
| 135 |
stl_phys((16 << 20) - 260, 0x12345678);
|
|
| 136 |
stl_phys((16 << 20) - 264, ram_size);
|
|
| 138 | 137 |
} |
| 139 | 138 |
|
| 140 | 139 |
static void main_cpu_reset(void *opaque) |
| b/hw/ppce500_mpc8544ds.c | ||
|---|---|---|
| 182 | 182 |
ram_size &= ~(RAM_SIZES_ALIGN - 1); |
| 183 | 183 |
|
| 184 | 184 |
/* Register Memory */ |
| 185 |
cpu_register_physical_memory(0, ram_size, 0);
|
|
| 185 |
cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(ram_size));
|
|
| 186 | 186 |
|
| 187 | 187 |
/* MPIC */ |
| 188 | 188 |
irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); |
| ... | ... | |
| 247 | 247 |
|
| 248 | 248 |
/* Load initrd. */ |
| 249 | 249 |
if (initrd_filename) {
|
| 250 |
initrd_size = load_image(initrd_filename, phys_ram_base + initrd_base); |
|
| 250 |
initrd_size = load_image_targphys(initrd_filename, initrd_base, |
|
| 251 |
ram_size - initrd_base); |
|
| 251 | 252 |
|
| 252 | 253 |
if (initrd_size < 0) {
|
| 253 | 254 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
| b/hw/pxa2xx_lcd.c | ||
|---|---|---|
| 283 | 283 |
/* Load new Frame Descriptors from DMA */ |
| 284 | 284 |
static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s) |
| 285 | 285 |
{
|
| 286 |
struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
|
|
| 286 |
struct pxa_frame_descriptor_s desc;
|
|
| 287 | 287 |
target_phys_addr_t descptr; |
| 288 | 288 |
int i; |
| 289 | 289 |
|
| 290 | 290 |
for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
|
| 291 |
desc[i] = 0; |
|
| 292 | 291 |
s->dma_ch[i].source = 0; |
| 293 | 292 |
|
| 294 | 293 |
if (!s->dma_ch[i].up) |
| ... | ... | |
| 303 | 302 |
descptr = s->dma_ch[i].descriptor; |
| 304 | 303 |
|
| 305 | 304 |
if (!(descptr >= PXA2XX_SDRAM_BASE && descptr + |
| 306 |
sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
|
|
| 305 |
sizeof(desc) <= PXA2XX_SDRAM_BASE + phys_ram_size))
|
|
| 307 | 306 |
continue; |
| 308 | 307 |
|
| 309 |
descptr -= PXA2XX_SDRAM_BASE; |
|
| 310 |
desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr); |
|
| 311 |
s->dma_ch[i].descriptor = desc[i]->fdaddr; |
|
| 312 |
s->dma_ch[i].source = desc[i]->fsaddr; |
|
| 313 |
s->dma_ch[i].id = desc[i]->fidr; |
|
| 314 |
s->dma_ch[i].command = desc[i]->ldcmd; |
|
| 308 |
cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc)); |
|
| 309 |
s->dma_ch[i].descriptor = tswap32(desc.fdaddr); |
|
| 310 |
s->dma_ch[i].source = tswap32(desc.fsaddr); |
|
| 311 |
s->dma_ch[i].id = tswap32(desc.fidr); |
|
| 312 |
s->dma_ch[i].command = tswap32(desc.ldcmd); |
|
| 315 | 313 |
} |
| 316 | 314 |
} |
| 317 | 315 |
|
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