Revision d77953b9 cputlb.c

b/cputlb.c
54 54
 */
55 55
void tlb_flush(CPUArchState *env, int flush_global)
56 56
{
57
    CPUState *cpu = ENV_GET_CPU(env);
57 58
    int i;
58 59

  
59 60
#if defined(DEBUG_TLB)
......
61 62
#endif
62 63
    /* must reset current TB so that interrupts cannot modify the
63 64
       links while we are modifying them */
64
    env->current_tb = NULL;
65
    cpu->current_tb = NULL;
65 66

  
66 67
    for (i = 0; i < CPU_TLB_SIZE; i++) {
67 68
        int mmu_idx;
......
92 93

  
93 94
void tlb_flush_page(CPUArchState *env, target_ulong addr)
94 95
{
96
    CPUState *cpu = ENV_GET_CPU(env);
95 97
    int i;
96 98
    int mmu_idx;
97 99

  
......
110 112
    }
111 113
    /* must reset current TB so that interrupts cannot modify the
112 114
       links while we are modifying them */
113
    env->current_tb = NULL;
115
    cpu->current_tb = NULL;
114 116

  
115 117
    addr &= TARGET_PAGE_MASK;
116 118
    i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

Also available in: Unified diff