Statistics
| Branch: | Revision:

root / target-cris / op_helper.c @ d78f3995

History | View | Annotate | Download (13.5 kB)

1 81fdc5f8 ths
/*
2 81fdc5f8 ths
 *  CRIS helper routines
3 81fdc5f8 ths
 *
4 81fdc5f8 ths
 *  Copyright (c) 2007 AXIS Communications
5 81fdc5f8 ths
 *  Written by Edgar E. Iglesias
6 81fdc5f8 ths
 *
7 81fdc5f8 ths
 * This library is free software; you can redistribute it and/or
8 81fdc5f8 ths
 * modify it under the terms of the GNU Lesser General Public
9 81fdc5f8 ths
 * License as published by the Free Software Foundation; either
10 81fdc5f8 ths
 * version 2 of the License, or (at your option) any later version.
11 81fdc5f8 ths
 *
12 81fdc5f8 ths
 * This library is distributed in the hope that it will be useful,
13 81fdc5f8 ths
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 81fdc5f8 ths
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 81fdc5f8 ths
 * Lesser General Public License for more details.
16 81fdc5f8 ths
 *
17 81fdc5f8 ths
 * You should have received a copy of the GNU Lesser General Public
18 81fdc5f8 ths
 * License along with this library; if not, write to the Free Software
19 fad6cb1a aurel32
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
20 81fdc5f8 ths
 */
21 81fdc5f8 ths
22 81fdc5f8 ths
#include <assert.h>
23 81fdc5f8 ths
#include "exec.h"
24 786c02f1 edgar_igl
#include "mmu.h"
25 30abcfc7 edgar_igl
#include "helper.h"
26 c38ac98d edgar_igl
#include "host-utils.h"
27 81fdc5f8 ths
28 d12d51d5 aliguori
//#define CRIS_OP_HELPER_DEBUG
29 d12d51d5 aliguori
30 d12d51d5 aliguori
31 d12d51d5 aliguori
#ifdef CRIS_OP_HELPER_DEBUG
32 d12d51d5 aliguori
#define D(x) x
33 93fcfe39 aliguori
#define D_LOG(...) qemu_log(__VA__ARGS__)
34 d12d51d5 aliguori
#else
35 e2eef170 pbrook
#define D(x)
36 d12d51d5 aliguori
#define D_LOG(...) do { } while (0)
37 d12d51d5 aliguori
#endif
38 e2eef170 pbrook
39 e2eef170 pbrook
#if !defined(CONFIG_USER_ONLY)
40 e2eef170 pbrook
41 81fdc5f8 ths
#define MMUSUFFIX _mmu
42 81fdc5f8 ths
43 81fdc5f8 ths
#define SHIFT 0
44 81fdc5f8 ths
#include "softmmu_template.h"
45 81fdc5f8 ths
46 81fdc5f8 ths
#define SHIFT 1
47 81fdc5f8 ths
#include "softmmu_template.h"
48 81fdc5f8 ths
49 81fdc5f8 ths
#define SHIFT 2
50 81fdc5f8 ths
#include "softmmu_template.h"
51 81fdc5f8 ths
52 81fdc5f8 ths
#define SHIFT 3
53 81fdc5f8 ths
#include "softmmu_template.h"
54 81fdc5f8 ths
55 81fdc5f8 ths
/* Try to fill the TLB and return an exception if error. If retaddr is
56 81fdc5f8 ths
   NULL, it means that the function was called in C code (i.e. not
57 81fdc5f8 ths
   from generated code or from helper.c) */
58 81fdc5f8 ths
/* XXX: fix it to restore all registers */
59 6ebbf390 j_mayer
void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
60 81fdc5f8 ths
{
61 81fdc5f8 ths
    TranslationBlock *tb;
62 81fdc5f8 ths
    CPUState *saved_env;
63 44f8625d bellard
    unsigned long pc;
64 81fdc5f8 ths
    int ret;
65 81fdc5f8 ths
66 81fdc5f8 ths
    /* XXX: hack to restore env in all cases, even if not called from
67 81fdc5f8 ths
       generated code */
68 81fdc5f8 ths
    saved_env = env;
69 81fdc5f8 ths
    env = cpu_single_env;
70 b41f7df0 edgar_igl
71 d12d51d5 aliguori
    D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__, 
72 d12d51d5 aliguori
             env->pc, env->debug1, retaddr);
73 6ebbf390 j_mayer
    ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
74 551bd27f ths
    if (unlikely(ret)) {
75 81fdc5f8 ths
        if (retaddr) {
76 81fdc5f8 ths
            /* now we have a real cpu fault */
77 44f8625d bellard
            pc = (unsigned long)retaddr;
78 81fdc5f8 ths
            tb = tb_find_pc(pc);
79 81fdc5f8 ths
            if (tb) {
80 81fdc5f8 ths
                /* the PC is inside the translated code. It means that we have
81 81fdc5f8 ths
                   a virtual CPU fault */
82 81fdc5f8 ths
                cpu_restore_state(tb, env, pc, NULL);
83 30abcfc7 edgar_igl
84 30abcfc7 edgar_igl
                /* Evaluate flags after retranslation.  */
85 30abcfc7 edgar_igl
                helper_top_evaluate_flags();
86 81fdc5f8 ths
            }
87 81fdc5f8 ths
        }
88 81fdc5f8 ths
        cpu_loop_exit();
89 81fdc5f8 ths
    }
90 81fdc5f8 ths
    env = saved_env;
91 81fdc5f8 ths
}
92 81fdc5f8 ths
93 e2eef170 pbrook
#endif
94 e2eef170 pbrook
95 dceaf394 edgar_igl
void helper_raise_exception(uint32_t index)
96 786c02f1 edgar_igl
{
97 dceaf394 edgar_igl
        env->exception_index = index;
98 dceaf394 edgar_igl
        cpu_loop_exit();
99 786c02f1 edgar_igl
}
100 786c02f1 edgar_igl
101 cf1d97f0 edgar_igl
void helper_tlb_flush_pid(uint32_t pid)
102 cf1d97f0 edgar_igl
{
103 cf1d97f0 edgar_igl
#if !defined(CONFIG_USER_ONLY)
104 28de16da edgar_igl
        pid &= 0xff;
105 28de16da edgar_igl
        if (pid != (env->pregs[PR_PID] & 0xff))
106 28de16da edgar_igl
                cris_mmu_flush_pid(env, env->pregs[PR_PID]);
107 cf1d97f0 edgar_igl
#endif
108 cf1d97f0 edgar_igl
}
109 cf1d97f0 edgar_igl
110 a1aebcb8 edgar_igl
void helper_spc_write(uint32_t new_spc)
111 a1aebcb8 edgar_igl
{
112 a1aebcb8 edgar_igl
#if !defined(CONFIG_USER_ONLY)
113 a1aebcb8 edgar_igl
        tlb_flush_page(env, env->pregs[PR_SPC]);
114 a1aebcb8 edgar_igl
        tlb_flush_page(env, new_spc);
115 a1aebcb8 edgar_igl
#endif
116 a1aebcb8 edgar_igl
}
117 a1aebcb8 edgar_igl
118 30abcfc7 edgar_igl
void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
119 b41f7df0 edgar_igl
{
120 93fcfe39 aliguori
        qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
121 b41f7df0 edgar_igl
}
122 b41f7df0 edgar_igl
123 cf1d97f0 edgar_igl
/* Used by the tlb decoder.  */
124 cf1d97f0 edgar_igl
#define EXTRACT_FIELD(src, start, end) \
125 cf1d97f0 edgar_igl
            (((src) >> start) & ((1 << (end - start + 1)) - 1))
126 cf1d97f0 edgar_igl
127 dceaf394 edgar_igl
void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
128 dceaf394 edgar_igl
{
129 dceaf394 edgar_igl
        uint32_t srs;
130 dceaf394 edgar_igl
        srs = env->pregs[PR_SRS];
131 dceaf394 edgar_igl
        srs &= 3;
132 dceaf394 edgar_igl
        env->sregs[srs][sreg] = env->regs[reg];
133 dceaf394 edgar_igl
134 dceaf394 edgar_igl
#if !defined(CONFIG_USER_ONLY)
135 dceaf394 edgar_igl
        if (srs == 1 || srs == 2) {
136 dceaf394 edgar_igl
                if (sreg == 6) {
137 dceaf394 edgar_igl
                        /* Writes to tlb-hi write to mm_cause as a side 
138 dceaf394 edgar_igl
                           effect.  */
139 6913ba56 edgar_igl
                        env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
140 6913ba56 edgar_igl
                        env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
141 dceaf394 edgar_igl
                }
142 dceaf394 edgar_igl
                else if (sreg == 5) {
143 dceaf394 edgar_igl
                        uint32_t set;
144 dceaf394 edgar_igl
                        uint32_t idx;
145 dceaf394 edgar_igl
                        uint32_t lo, hi;
146 dceaf394 edgar_igl
                        uint32_t vaddr;
147 cf1d97f0 edgar_igl
                        int tlb_v;
148 dceaf394 edgar_igl
149 dceaf394 edgar_igl
                        idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
150 dceaf394 edgar_igl
                        set >>= 4;
151 dceaf394 edgar_igl
                        set &= 3;
152 dceaf394 edgar_igl
153 dceaf394 edgar_igl
                        idx &= 15;
154 dceaf394 edgar_igl
                        /* We've just made a write to tlb_lo.  */
155 dceaf394 edgar_igl
                        lo = env->sregs[SFR_RW_MM_TLB_LO];
156 dceaf394 edgar_igl
                        /* Writes are done via r_mm_cause.  */
157 dceaf394 edgar_igl
                        hi = env->sregs[SFR_R_MM_CAUSE];
158 cf1d97f0 edgar_igl
159 cf1d97f0 edgar_igl
                        vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
160 cf1d97f0 edgar_igl
                                              13, 31);
161 cf1d97f0 edgar_igl
                        vaddr <<= TARGET_PAGE_BITS;
162 cf1d97f0 edgar_igl
                        tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
163 cf1d97f0 edgar_igl
                                            3, 3);
164 dceaf394 edgar_igl
                        env->tlbsets[srs - 1][set][idx].lo = lo;
165 dceaf394 edgar_igl
                        env->tlbsets[srs - 1][set][idx].hi = hi;
166 cf1d97f0 edgar_igl
167 d12d51d5 aliguori
                        D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
168 d12d51d5 aliguori
                                  vaddr, tlb_v, env->pc);
169 cf1d97f0 edgar_igl
                        tlb_flush_page(env, vaddr);
170 dceaf394 edgar_igl
                }
171 dceaf394 edgar_igl
        }
172 dceaf394 edgar_igl
#endif
173 dceaf394 edgar_igl
}
174 dceaf394 edgar_igl
175 dceaf394 edgar_igl
void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
176 dceaf394 edgar_igl
{
177 dceaf394 edgar_igl
        uint32_t srs;
178 dceaf394 edgar_igl
        env->pregs[PR_SRS] &= 3;
179 dceaf394 edgar_igl
        srs = env->pregs[PR_SRS];
180 dceaf394 edgar_igl
        
181 dceaf394 edgar_igl
#if !defined(CONFIG_USER_ONLY)
182 dceaf394 edgar_igl
        if (srs == 1 || srs == 2)
183 dceaf394 edgar_igl
        {
184 dceaf394 edgar_igl
                uint32_t set;
185 dceaf394 edgar_igl
                uint32_t idx;
186 dceaf394 edgar_igl
                uint32_t lo, hi;
187 dceaf394 edgar_igl
188 dceaf394 edgar_igl
                idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
189 dceaf394 edgar_igl
                set >>= 4;
190 dceaf394 edgar_igl
                set &= 3;
191 dceaf394 edgar_igl
                idx &= 15;
192 dceaf394 edgar_igl
193 dceaf394 edgar_igl
                /* Update the mirror regs.  */
194 dceaf394 edgar_igl
                hi = env->tlbsets[srs - 1][set][idx].hi;
195 dceaf394 edgar_igl
                lo = env->tlbsets[srs - 1][set][idx].lo;
196 dceaf394 edgar_igl
                env->sregs[SFR_RW_MM_TLB_HI] = hi;
197 dceaf394 edgar_igl
                env->sregs[SFR_RW_MM_TLB_LO] = lo;
198 dceaf394 edgar_igl
        }
199 dceaf394 edgar_igl
#endif
200 dceaf394 edgar_igl
        env->regs[reg] = env->sregs[srs][sreg];
201 dceaf394 edgar_igl
}
202 dceaf394 edgar_igl
203 dceaf394 edgar_igl
static void cris_ccs_rshift(CPUState *env)
204 dceaf394 edgar_igl
{
205 dceaf394 edgar_igl
        uint32_t ccs;
206 dceaf394 edgar_igl
207 dceaf394 edgar_igl
        /* Apply the ccs shift.  */
208 dceaf394 edgar_igl
        ccs = env->pregs[PR_CCS];
209 dceaf394 edgar_igl
        ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
210 dceaf394 edgar_igl
        if (ccs & U_FLAG)
211 dceaf394 edgar_igl
        {
212 dceaf394 edgar_igl
                /* Enter user mode.  */
213 dceaf394 edgar_igl
                env->ksp = env->regs[R_SP];
214 dceaf394 edgar_igl
                env->regs[R_SP] = env->pregs[PR_USP];
215 dceaf394 edgar_igl
        }
216 dceaf394 edgar_igl
217 dceaf394 edgar_igl
        env->pregs[PR_CCS] = ccs;
218 dceaf394 edgar_igl
}
219 dceaf394 edgar_igl
220 b41f7df0 edgar_igl
void helper_rfe(void)
221 b41f7df0 edgar_igl
{
222 bf443337 edgar_igl
        int rflag = env->pregs[PR_CCS] & R_FLAG;
223 bf443337 edgar_igl
224 d12d51d5 aliguori
        D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
225 b41f7df0 edgar_igl
                 env->pregs[PR_ERP], env->pregs[PR_PID],
226 b41f7df0 edgar_igl
                 env->pregs[PR_CCS],
227 d12d51d5 aliguori
                 env->btarget);
228 dceaf394 edgar_igl
229 dceaf394 edgar_igl
        cris_ccs_rshift(env);
230 dceaf394 edgar_igl
231 dceaf394 edgar_igl
        /* RFE sets the P_FLAG only if the R_FLAG is not set.  */
232 bf443337 edgar_igl
        if (!rflag)
233 dceaf394 edgar_igl
                env->pregs[PR_CCS] |= P_FLAG;
234 b41f7df0 edgar_igl
}
235 b41f7df0 edgar_igl
236 5bf8f1ab edgar_igl
void helper_rfn(void)
237 5bf8f1ab edgar_igl
{
238 5bf8f1ab edgar_igl
        int rflag = env->pregs[PR_CCS] & R_FLAG;
239 5bf8f1ab edgar_igl
240 d12d51d5 aliguori
        D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
241 5bf8f1ab edgar_igl
                 env->pregs[PR_ERP], env->pregs[PR_PID],
242 5bf8f1ab edgar_igl
                 env->pregs[PR_CCS],
243 d12d51d5 aliguori
                 env->btarget);
244 5bf8f1ab edgar_igl
245 5bf8f1ab edgar_igl
        cris_ccs_rshift(env);
246 5bf8f1ab edgar_igl
247 5bf8f1ab edgar_igl
        /* Set the P_FLAG only if the R_FLAG is not set.  */
248 5bf8f1ab edgar_igl
        if (!rflag)
249 5bf8f1ab edgar_igl
                env->pregs[PR_CCS] |= P_FLAG;
250 5bf8f1ab edgar_igl
251 5bf8f1ab edgar_igl
    /* Always set the M flag.  */
252 5bf8f1ab edgar_igl
    env->pregs[PR_CCS] |= M_FLAG;
253 5bf8f1ab edgar_igl
}
254 5bf8f1ab edgar_igl
255 c38ac98d edgar_igl
uint32_t helper_lz(uint32_t t0)
256 c38ac98d edgar_igl
{
257 c38ac98d edgar_igl
        return clz32(t0);
258 c38ac98d edgar_igl
}
259 c38ac98d edgar_igl
260 abd5c94e edgar_igl
uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
261 abd5c94e edgar_igl
{
262 abd5c94e edgar_igl
        /* FIXME: clean this up.  */
263 abd5c94e edgar_igl
264 abd5c94e edgar_igl
        /* des ref:
265 abd5c94e edgar_igl
           The N flag is set according to the selected bit in the dest reg.
266 abd5c94e edgar_igl
           The Z flag is set if the selected bit and all bits to the right are
267 abd5c94e edgar_igl
           zero.
268 abd5c94e edgar_igl
           The X flag is cleared.
269 abd5c94e edgar_igl
           Other flags are left untouched.
270 abd5c94e edgar_igl
           The destination reg is not affected.*/
271 abd5c94e edgar_igl
        unsigned int fz, sbit, bset, mask, masked_t0;
272 abd5c94e edgar_igl
273 abd5c94e edgar_igl
        sbit = t1 & 31;
274 abd5c94e edgar_igl
        bset = !!(t0 & (1 << sbit));
275 abd5c94e edgar_igl
        mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
276 abd5c94e edgar_igl
        masked_t0 = t0 & mask;
277 abd5c94e edgar_igl
        fz = !(masked_t0 | bset);
278 abd5c94e edgar_igl
279 abd5c94e edgar_igl
        /* Clear the X, N and Z flags.  */
280 abd5c94e edgar_igl
        ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
281 abd5c94e edgar_igl
        /* Set the N and Z flags accordingly.  */
282 abd5c94e edgar_igl
        ccs |= (bset << 3) | (fz << 2);
283 abd5c94e edgar_igl
        return ccs;
284 abd5c94e edgar_igl
}
285 abd5c94e edgar_igl
286 6231868b edgar_igl
static inline uint32_t evaluate_flags_writeback(uint32_t flags, uint32_t ccs)
287 b41f7df0 edgar_igl
{
288 a8cf66bb edgar_igl
        unsigned int x, z, mask;
289 b41f7df0 edgar_igl
290 b41f7df0 edgar_igl
        /* Extended arithmetics, leave the z flag alone.  */
291 30abcfc7 edgar_igl
        x = env->cc_x;
292 a8cf66bb edgar_igl
        mask = env->cc_mask | X_FLAG;
293 a8cf66bb edgar_igl
        if (x) {
294 a8cf66bb edgar_igl
                z = flags & Z_FLAG;
295 a8cf66bb edgar_igl
                mask = mask & ~z;
296 a8cf66bb edgar_igl
        }
297 a8cf66bb edgar_igl
        flags &= mask;
298 b41f7df0 edgar_igl
299 b41f7df0 edgar_igl
        /* all insn clear the x-flag except setf or clrf.  */
300 6231868b edgar_igl
        ccs &= ~mask;
301 6231868b edgar_igl
        ccs |= flags;
302 6231868b edgar_igl
        return ccs;
303 b41f7df0 edgar_igl
}
304 b41f7df0 edgar_igl
305 6231868b edgar_igl
uint32_t helper_evaluate_flags_muls(uint32_t ccs, uint32_t res, uint32_t mof)
306 b41f7df0 edgar_igl
{
307 b41f7df0 edgar_igl
        uint32_t flags = 0;
308 dceaf394 edgar_igl
        int64_t tmp;
309 b41f7df0 edgar_igl
        int dneg;
310 b41f7df0 edgar_igl
311 b41f7df0 edgar_igl
        dneg = ((int32_t)res) < 0;
312 b41f7df0 edgar_igl
313 dceaf394 edgar_igl
        tmp = mof;
314 dceaf394 edgar_igl
        tmp <<= 32;
315 dceaf394 edgar_igl
        tmp |= res;
316 b41f7df0 edgar_igl
        if (tmp == 0)
317 b41f7df0 edgar_igl
                flags |= Z_FLAG;
318 b41f7df0 edgar_igl
        else if (tmp < 0)
319 b41f7df0 edgar_igl
                flags |= N_FLAG;
320 b41f7df0 edgar_igl
        if ((dneg && mof != -1)
321 b41f7df0 edgar_igl
            || (!dneg && mof != 0))
322 b41f7df0 edgar_igl
                flags |= V_FLAG;
323 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
324 b41f7df0 edgar_igl
}
325 b41f7df0 edgar_igl
326 6231868b edgar_igl
uint32_t helper_evaluate_flags_mulu(uint32_t ccs, uint32_t res, uint32_t mof)
327 b41f7df0 edgar_igl
{
328 b41f7df0 edgar_igl
        uint32_t flags = 0;
329 dceaf394 edgar_igl
        uint64_t tmp;
330 b41f7df0 edgar_igl
331 dceaf394 edgar_igl
        tmp = mof;
332 dceaf394 edgar_igl
        tmp <<= 32;
333 dceaf394 edgar_igl
        tmp |= res;
334 b41f7df0 edgar_igl
        if (tmp == 0)
335 b41f7df0 edgar_igl
                flags |= Z_FLAG;
336 b41f7df0 edgar_igl
        else if (tmp >> 63)
337 b41f7df0 edgar_igl
                flags |= N_FLAG;
338 b41f7df0 edgar_igl
        if (mof)
339 b41f7df0 edgar_igl
                flags |= V_FLAG;
340 b41f7df0 edgar_igl
341 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
342 b41f7df0 edgar_igl
}
343 b41f7df0 edgar_igl
344 6231868b edgar_igl
uint32_t helper_evaluate_flags_mcp(uint32_t ccs,
345 6231868b edgar_igl
                                   uint32_t src, uint32_t dst, uint32_t res)
346 b41f7df0 edgar_igl
{
347 b41f7df0 edgar_igl
        uint32_t flags = 0;
348 b41f7df0 edgar_igl
349 6231868b edgar_igl
        src = src & 0x80000000;
350 6231868b edgar_igl
        dst = dst & 0x80000000;
351 b41f7df0 edgar_igl
352 b41f7df0 edgar_igl
        if ((res & 0x80000000L) != 0L)
353 b41f7df0 edgar_igl
        {
354 b41f7df0 edgar_igl
                flags |= N_FLAG;
355 a8cf66bb edgar_igl
                if (!src && !dst)
356 b41f7df0 edgar_igl
                        flags |= V_FLAG;
357 a8cf66bb edgar_igl
                else if (src & dst)
358 b41f7df0 edgar_igl
                        flags |= R_FLAG;
359 b41f7df0 edgar_igl
        }
360 b41f7df0 edgar_igl
        else
361 b41f7df0 edgar_igl
        {
362 b41f7df0 edgar_igl
                if (res == 0L)
363 b41f7df0 edgar_igl
                        flags |= Z_FLAG;
364 a8cf66bb edgar_igl
                if (src & dst) 
365 b41f7df0 edgar_igl
                        flags |= V_FLAG;
366 a8cf66bb edgar_igl
                if (dst | src) 
367 b41f7df0 edgar_igl
                        flags |= R_FLAG;
368 b41f7df0 edgar_igl
        }
369 b41f7df0 edgar_igl
370 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
371 b41f7df0 edgar_igl
}
372 b41f7df0 edgar_igl
373 6231868b edgar_igl
uint32_t helper_evaluate_flags_alu_4(uint32_t ccs,
374 6231868b edgar_igl
                                     uint32_t src, uint32_t dst, uint32_t res)
375 b41f7df0 edgar_igl
{
376 b41f7df0 edgar_igl
        uint32_t flags = 0;
377 b41f7df0 edgar_igl
378 6231868b edgar_igl
        src = src & 0x80000000;
379 6231868b edgar_igl
        dst = dst & 0x80000000;
380 30abcfc7 edgar_igl
381 a8cf66bb edgar_igl
        if ((res & 0x80000000L) != 0L)
382 30abcfc7 edgar_igl
        {
383 a8cf66bb edgar_igl
                flags |= N_FLAG;
384 a8cf66bb edgar_igl
                if (!src && !dst)
385 a8cf66bb edgar_igl
                        flags |= V_FLAG;
386 a8cf66bb edgar_igl
                else if (src & dst)
387 a8cf66bb edgar_igl
                        flags |= C_FLAG;
388 a8cf66bb edgar_igl
        }
389 a8cf66bb edgar_igl
        else
390 a8cf66bb edgar_igl
        {
391 a8cf66bb edgar_igl
                if (res == 0L)
392 a8cf66bb edgar_igl
                        flags |= Z_FLAG;
393 a8cf66bb edgar_igl
                if (src & dst) 
394 a8cf66bb edgar_igl
                        flags |= V_FLAG;
395 a8cf66bb edgar_igl
                if (dst | src) 
396 a8cf66bb edgar_igl
                        flags |= C_FLAG;
397 30abcfc7 edgar_igl
        }
398 30abcfc7 edgar_igl
399 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
400 a8cf66bb edgar_igl
}
401 a8cf66bb edgar_igl
402 6231868b edgar_igl
uint32_t helper_evaluate_flags_sub_4(uint32_t ccs,
403 6231868b edgar_igl
                                     uint32_t src, uint32_t dst, uint32_t res)
404 a8cf66bb edgar_igl
{
405 a8cf66bb edgar_igl
        uint32_t flags = 0;
406 a8cf66bb edgar_igl
407 6231868b edgar_igl
        src = (~src) & 0x80000000;
408 6231868b edgar_igl
        dst = dst & 0x80000000;
409 b41f7df0 edgar_igl
410 b41f7df0 edgar_igl
        if ((res & 0x80000000L) != 0L)
411 b41f7df0 edgar_igl
        {
412 b41f7df0 edgar_igl
                flags |= N_FLAG;
413 a8cf66bb edgar_igl
                if (!src && !dst)
414 b41f7df0 edgar_igl
                        flags |= V_FLAG;
415 a8cf66bb edgar_igl
                else if (src & dst)
416 b41f7df0 edgar_igl
                        flags |= C_FLAG;
417 b41f7df0 edgar_igl
        }
418 b41f7df0 edgar_igl
        else
419 b41f7df0 edgar_igl
        {
420 b41f7df0 edgar_igl
                if (res == 0L)
421 b41f7df0 edgar_igl
                        flags |= Z_FLAG;
422 a8cf66bb edgar_igl
                if (src & dst) 
423 b41f7df0 edgar_igl
                        flags |= V_FLAG;
424 a8cf66bb edgar_igl
                if (dst | src) 
425 b41f7df0 edgar_igl
                        flags |= C_FLAG;
426 b41f7df0 edgar_igl
        }
427 b41f7df0 edgar_igl
428 a8cf66bb edgar_igl
        flags ^= C_FLAG;
429 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
430 b41f7df0 edgar_igl
}
431 b41f7df0 edgar_igl
432 6231868b edgar_igl
uint32_t helper_evaluate_flags_move_4(uint32_t ccs, uint32_t res)
433 b41f7df0 edgar_igl
{
434 b41f7df0 edgar_igl
        uint32_t flags = 0;
435 b41f7df0 edgar_igl
436 b41f7df0 edgar_igl
        if ((int32_t)res < 0)
437 b41f7df0 edgar_igl
                flags |= N_FLAG;
438 b41f7df0 edgar_igl
        else if (res == 0L)
439 b41f7df0 edgar_igl
                flags |= Z_FLAG;
440 b41f7df0 edgar_igl
441 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
442 b41f7df0 edgar_igl
}
443 6231868b edgar_igl
uint32_t helper_evaluate_flags_move_2(uint32_t ccs, uint32_t res)
444 b41f7df0 edgar_igl
{
445 b41f7df0 edgar_igl
        uint32_t flags = 0;
446 b41f7df0 edgar_igl
447 b41f7df0 edgar_igl
        if ((int16_t)res < 0L)
448 b41f7df0 edgar_igl
                flags |= N_FLAG;
449 b41f7df0 edgar_igl
        else if (res == 0)
450 b41f7df0 edgar_igl
                flags |= Z_FLAG;
451 b41f7df0 edgar_igl
452 6231868b edgar_igl
        return evaluate_flags_writeback(flags, ccs);
453 b41f7df0 edgar_igl
}
454 b41f7df0 edgar_igl
455 b41f7df0 edgar_igl
/* TODO: This is expensive. We could split things up and only evaluate part of
456 b41f7df0 edgar_igl
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
457 6231868b edgar_igl
void  helper_evaluate_flags(void)
458 b41f7df0 edgar_igl
{
459 6231868b edgar_igl
        uint32_t src, dst, res;
460 b41f7df0 edgar_igl
        uint32_t flags = 0;
461 b41f7df0 edgar_igl
462 b41f7df0 edgar_igl
        src = env->cc_src;
463 b41f7df0 edgar_igl
        dst = env->cc_dest;
464 b41f7df0 edgar_igl
        res = env->cc_result;
465 b41f7df0 edgar_igl
466 30abcfc7 edgar_igl
        if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
467 30abcfc7 edgar_igl
                src = ~src;
468 b41f7df0 edgar_igl
469 b41f7df0 edgar_igl
        /* Now, evaluate the flags. This stuff is based on
470 b41f7df0 edgar_igl
           Per Zander's CRISv10 simulator.  */
471 b41f7df0 edgar_igl
        switch (env->cc_size)
472 b41f7df0 edgar_igl
        {
473 b41f7df0 edgar_igl
                case 1:
474 b41f7df0 edgar_igl
                        if ((res & 0x80L) != 0L)
475 b41f7df0 edgar_igl
                        {
476 b41f7df0 edgar_igl
                                flags |= N_FLAG;
477 b41f7df0 edgar_igl
                                if (((src & 0x80L) == 0L)
478 b41f7df0 edgar_igl
                                    && ((dst & 0x80L) == 0L))
479 b41f7df0 edgar_igl
                                {
480 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
481 b41f7df0 edgar_igl
                                }
482 b41f7df0 edgar_igl
                                else if (((src & 0x80L) != 0L)
483 b41f7df0 edgar_igl
                                         && ((dst & 0x80L) != 0L))
484 b41f7df0 edgar_igl
                                {
485 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
486 b41f7df0 edgar_igl
                                }
487 b41f7df0 edgar_igl
                        }
488 b41f7df0 edgar_igl
                        else
489 b41f7df0 edgar_igl
                        {
490 b41f7df0 edgar_igl
                                if ((res & 0xFFL) == 0L)
491 b41f7df0 edgar_igl
                                {
492 b41f7df0 edgar_igl
                                        flags |= Z_FLAG;
493 b41f7df0 edgar_igl
                                }
494 b41f7df0 edgar_igl
                                if (((src & 0x80L) != 0L)
495 b41f7df0 edgar_igl
                                    && ((dst & 0x80L) != 0L))
496 b41f7df0 edgar_igl
                                {
497 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
498 b41f7df0 edgar_igl
                                }
499 b41f7df0 edgar_igl
                                if ((dst & 0x80L) != 0L
500 b41f7df0 edgar_igl
                                    || (src & 0x80L) != 0L)
501 b41f7df0 edgar_igl
                                {
502 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
503 b41f7df0 edgar_igl
                                }
504 b41f7df0 edgar_igl
                        }
505 b41f7df0 edgar_igl
                        break;
506 b41f7df0 edgar_igl
                case 2:
507 b41f7df0 edgar_igl
                        if ((res & 0x8000L) != 0L)
508 b41f7df0 edgar_igl
                        {
509 b41f7df0 edgar_igl
                                flags |= N_FLAG;
510 b41f7df0 edgar_igl
                                if (((src & 0x8000L) == 0L)
511 b41f7df0 edgar_igl
                                    && ((dst & 0x8000L) == 0L))
512 b41f7df0 edgar_igl
                                {
513 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
514 b41f7df0 edgar_igl
                                }
515 b41f7df0 edgar_igl
                                else if (((src & 0x8000L) != 0L)
516 b41f7df0 edgar_igl
                                         && ((dst & 0x8000L) != 0L))
517 b41f7df0 edgar_igl
                                {
518 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
519 b41f7df0 edgar_igl
                                }
520 b41f7df0 edgar_igl
                        }
521 b41f7df0 edgar_igl
                        else
522 b41f7df0 edgar_igl
                        {
523 b41f7df0 edgar_igl
                                if ((res & 0xFFFFL) == 0L)
524 b41f7df0 edgar_igl
                                {
525 b41f7df0 edgar_igl
                                        flags |= Z_FLAG;
526 b41f7df0 edgar_igl
                                }
527 b41f7df0 edgar_igl
                                if (((src & 0x8000L) != 0L)
528 b41f7df0 edgar_igl
                                    && ((dst & 0x8000L) != 0L))
529 b41f7df0 edgar_igl
                                {
530 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
531 b41f7df0 edgar_igl
                                }
532 b41f7df0 edgar_igl
                                if ((dst & 0x8000L) != 0L
533 b41f7df0 edgar_igl
                                    || (src & 0x8000L) != 0L)
534 b41f7df0 edgar_igl
                                {
535 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
536 b41f7df0 edgar_igl
                                }
537 b41f7df0 edgar_igl
                        }
538 b41f7df0 edgar_igl
                        break;
539 b41f7df0 edgar_igl
                case 4:
540 b41f7df0 edgar_igl
                        if ((res & 0x80000000L) != 0L)
541 b41f7df0 edgar_igl
                        {
542 b41f7df0 edgar_igl
                                flags |= N_FLAG;
543 b41f7df0 edgar_igl
                                if (((src & 0x80000000L) == 0L)
544 b41f7df0 edgar_igl
                                    && ((dst & 0x80000000L) == 0L))
545 b41f7df0 edgar_igl
                                {
546 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
547 b41f7df0 edgar_igl
                                }
548 b41f7df0 edgar_igl
                                else if (((src & 0x80000000L) != 0L) &&
549 b41f7df0 edgar_igl
                                         ((dst & 0x80000000L) != 0L))
550 b41f7df0 edgar_igl
                                {
551 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
552 b41f7df0 edgar_igl
                                }
553 b41f7df0 edgar_igl
                        }
554 b41f7df0 edgar_igl
                        else
555 b41f7df0 edgar_igl
                        {
556 b41f7df0 edgar_igl
                                if (res == 0L)
557 b41f7df0 edgar_igl
                                        flags |= Z_FLAG;
558 b41f7df0 edgar_igl
                                if (((src & 0x80000000L) != 0L)
559 b41f7df0 edgar_igl
                                    && ((dst & 0x80000000L) != 0L))
560 b41f7df0 edgar_igl
                                        flags |= V_FLAG;
561 b41f7df0 edgar_igl
                                if ((dst & 0x80000000L) != 0L
562 b41f7df0 edgar_igl
                                    || (src & 0x80000000L) != 0L)
563 b41f7df0 edgar_igl
                                        flags |= C_FLAG;
564 b41f7df0 edgar_igl
                        }
565 b41f7df0 edgar_igl
                        break;
566 b41f7df0 edgar_igl
                default:
567 b41f7df0 edgar_igl
                        break;
568 b41f7df0 edgar_igl
        }
569 b41f7df0 edgar_igl
570 6231868b edgar_igl
        if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
571 b41f7df0 edgar_igl
                flags ^= C_FLAG;
572 6231868b edgar_igl
573 6231868b edgar_igl
        env->pregs[PR_CCS] = evaluate_flags_writeback(flags, env->pregs[PR_CCS]);
574 b41f7df0 edgar_igl
}
575 30abcfc7 edgar_igl
576 30abcfc7 edgar_igl
void helper_top_evaluate_flags(void)
577 30abcfc7 edgar_igl
{
578 30abcfc7 edgar_igl
        switch (env->cc_op)
579 30abcfc7 edgar_igl
        {
580 30abcfc7 edgar_igl
                case CC_OP_MCP:
581 6231868b edgar_igl
                        env->pregs[PR_CCS] = helper_evaluate_flags_mcp(
582 6231868b edgar_igl
                                        env->pregs[PR_CCS], env->cc_src,
583 6231868b edgar_igl
                                        env->cc_dest, env->cc_result);
584 30abcfc7 edgar_igl
                        break;
585 30abcfc7 edgar_igl
                case CC_OP_MULS:
586 6231868b edgar_igl
                        env->pregs[PR_CCS] = helper_evaluate_flags_muls(
587 6231868b edgar_igl
                                        env->pregs[PR_CCS], env->cc_result,
588 6231868b edgar_igl
                                        env->pregs[PR_MOF]);
589 30abcfc7 edgar_igl
                        break;
590 30abcfc7 edgar_igl
                case CC_OP_MULU:
591 6231868b edgar_igl
                        env->pregs[PR_CCS] = helper_evaluate_flags_mulu(
592 6231868b edgar_igl
                                        env->pregs[PR_CCS], env->cc_result,
593 6231868b edgar_igl
                                        env->pregs[PR_MOF]);
594 30abcfc7 edgar_igl
                        break;
595 30abcfc7 edgar_igl
                case CC_OP_MOVE:
596 30abcfc7 edgar_igl
                case CC_OP_AND:
597 30abcfc7 edgar_igl
                case CC_OP_OR:
598 30abcfc7 edgar_igl
                case CC_OP_XOR:
599 30abcfc7 edgar_igl
                case CC_OP_ASR:
600 30abcfc7 edgar_igl
                case CC_OP_LSR:
601 30abcfc7 edgar_igl
                case CC_OP_LSL:
602 6231868b edgar_igl
                switch (env->cc_size)
603 6231868b edgar_igl
                {
604 6231868b edgar_igl
                        case 4:
605 6231868b edgar_igl
                                env->pregs[PR_CCS] =
606 6231868b edgar_igl
                                        helper_evaluate_flags_move_4(
607 6231868b edgar_igl
                                                        env->pregs[PR_CCS],
608 6231868b edgar_igl
                                                        env->cc_result);
609 6231868b edgar_igl
                                break;
610 6231868b edgar_igl
                        case 2:
611 6231868b edgar_igl
                                env->pregs[PR_CCS] =
612 6231868b edgar_igl
                                        helper_evaluate_flags_move_2(
613 6231868b edgar_igl
                                                        env->pregs[PR_CCS],
614 6231868b edgar_igl
                                                        env->cc_result);
615 6231868b edgar_igl
                                break;
616 6231868b edgar_igl
                        default:
617 6231868b edgar_igl
                                helper_evaluate_flags();
618 6231868b edgar_igl
                                break;
619 6231868b edgar_igl
                }
620 6231868b edgar_igl
                break;
621 30abcfc7 edgar_igl
                case CC_OP_FLAGS:
622 30abcfc7 edgar_igl
                        /* live.  */
623 30abcfc7 edgar_igl
                        break;
624 a8cf66bb edgar_igl
                case CC_OP_SUB:
625 a8cf66bb edgar_igl
                case CC_OP_CMP:
626 a8cf66bb edgar_igl
                        if (env->cc_size == 4)
627 6231868b edgar_igl
                                env->pregs[PR_CCS] =
628 6231868b edgar_igl
                                        helper_evaluate_flags_sub_4(
629 6231868b edgar_igl
                                                env->pregs[PR_CCS],
630 6231868b edgar_igl
                                                env->cc_src, env->cc_dest,
631 6231868b edgar_igl
                                                env->cc_result);
632 a8cf66bb edgar_igl
                        else
633 a8cf66bb edgar_igl
                                helper_evaluate_flags();
634 a8cf66bb edgar_igl
                        break;
635 30abcfc7 edgar_igl
                default:
636 30abcfc7 edgar_igl
                {
637 30abcfc7 edgar_igl
                        switch (env->cc_size)
638 30abcfc7 edgar_igl
                        {
639 6231868b edgar_igl
                        case 4:
640 6231868b edgar_igl
                                env->pregs[PR_CCS] =
641 6231868b edgar_igl
                                        helper_evaluate_flags_alu_4(
642 6231868b edgar_igl
                                                env->pregs[PR_CCS],
643 6231868b edgar_igl
                                                env->cc_src, env->cc_dest,
644 6231868b edgar_igl
                                                env->cc_result);
645 6231868b edgar_igl
                                break;
646 6231868b edgar_igl
                        default:
647 6231868b edgar_igl
                                helper_evaluate_flags();
648 6231868b edgar_igl
                                break;
649 30abcfc7 edgar_igl
                        }
650 30abcfc7 edgar_igl
                }
651 30abcfc7 edgar_igl
                break;
652 30abcfc7 edgar_igl
        }
653 30abcfc7 edgar_igl
}