Revision d78f3995 hw/eepro100.c
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/* Common declarations for all PCI devices. */ |
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#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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#define PCI_COMMAND 0x04 /* 16 bits */ |
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#define PCI_STATUS 0x06 /* 16 bits */ |
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#define PCI_REVISION_ID 0x08 /* 8 bits */ |
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#define PCI_CLASS_CODE 0x0b /* 8 bits */ |
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#define PCI_SUBCLASS_CODE 0x0a /* 8 bits */ |
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */ |
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */ |
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
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#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
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#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
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#define PCI_CONFIG_8(offset, value) \ |
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(pci_conf[offset] = (value)) |
| ... | ... | |
| 199 | 188 |
ru_ready = 4 |
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} ru_state_t; |
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#if defined(__BIG_ENDIAN_BITFIELD) |
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#define X(a,b) b,a |
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#else |
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#define X(a,b) a,b |
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#endif |
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typedef struct {
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#if 1 |
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uint8_t cmd; |
| ... | ... | |
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//~ return !eepro100_buffer_full(s); |
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} |
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#define MIN_BUF_SIZE 60 |
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static void nic_receive(void *opaque, const uint8_t * buf, int size) |
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{
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/* TODO: |
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