root / target-mips / mips-defs.h @ d796321b
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1 | 6af0bf9c | bellard | #if !defined (__QEMU_MIPS_DEFS_H__)
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2 | 6af0bf9c | bellard | #define __QEMU_MIPS_DEFS_H__
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3 | 6af0bf9c | bellard | |
4 | 6af0bf9c | bellard | /* If we want to use 64 bits host regs... */
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5 | 6af0bf9c | bellard | //#define USE_64BITS_REGS
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6 | 6af0bf9c | bellard | /* If we want to use host float regs... */
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7 | 6af0bf9c | bellard | //#define USE_HOST_FLOAT_REGS
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8 | 6af0bf9c | bellard | |
9 | c5d6edc3 | bellard | #define MIPS_R4Kc 0x00018000 |
10 | c5d6edc3 | bellard | #define MIPS_R4Kp 0x00018300 |
11 | 6af0bf9c | bellard | |
12 | 6af0bf9c | bellard | /* Emulate MIPS R4Kc for now */
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13 | 6af0bf9c | bellard | #define MIPS_CPU MIPS_R4Kc
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14 | 6af0bf9c | bellard | |
15 | 6af0bf9c | bellard | #if (MIPS_CPU == MIPS_R4Kc)
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16 | 6af0bf9c | bellard | /* 32 bits target */
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17 | 6af0bf9c | bellard | #define TARGET_LONG_BITS 32 |
18 | 6af0bf9c | bellard | /* real pages are variable size... */
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19 | 6af0bf9c | bellard | #define TARGET_PAGE_BITS 12 |
20 | c5d6edc3 | bellard | /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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21 | 6af0bf9c | bellard | #define MIPS_USES_R4K_EXT
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22 | 6af0bf9c | bellard | /* Uses MIPS R4Kc TLB model */
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23 | 6af0bf9c | bellard | #define MIPS_USES_R4K_TLB
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24 | 6af0bf9c | bellard | #define MIPS_TLB_NB 16 |
25 | 6ea83fed | bellard | /* basic FPU register support */
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26 | 6ea83fed | bellard | #define MIPS_USES_FPU 1 |
27 | 6ea83fed | bellard | /* Define a implementation number of 1.
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28 | 6ea83fed | bellard | * Define a major version 1, minor version 0.
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29 | 6ea83fed | bellard | */
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30 | 6ea83fed | bellard | #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) |
31 | c5d6edc3 | bellard | /* Have config1, uses TLB */
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32 | c5d6edc3 | bellard | #define MIPS_CONFIG0_1 \
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33 | c5d6edc3 | bellard | ((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) | \ |
34 | c5d6edc3 | bellard | (1 << CP0C0_MT) | (2 << CP0C0_K0)) |
35 | c5d6edc3 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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36 | c5d6edc3 | bellard | #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE)) |
37 | c5d6edc3 | bellard | #else
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38 | c5d6edc3 | bellard | #define MIPS_CONFIG0 MIPS_CONFIG0_1
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39 | c5d6edc3 | bellard | #endif
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40 | 6af0bf9c | bellard | /* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache,
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41 | 6af0bf9c | bellard | * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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42 | 6af0bf9c | bellard | * no performance counters, watch registers present, no code compression,
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43 | 6ea83fed | bellard | * EJTAG present, FPU enable bit depending on MIPS_USES_FPU
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44 | 6af0bf9c | bellard | */
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45 | 6af0bf9c | bellard | #define MIPS_CONFIG1 \
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46 | 6af0bf9c | bellard | ((15 << CP0C1_MMU) | \
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47 | 6af0bf9c | bellard | (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \ |
48 | 6af0bf9c | bellard | (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \ |
49 | 6af0bf9c | bellard | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \ |
50 | 6ea83fed | bellard | (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP))
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51 | c5d6edc3 | bellard | #elif (MIPS_CPU == MIPS_R4Kp)
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52 | 6af0bf9c | bellard | /* 32 bits target */
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53 | 6af0bf9c | bellard | #define TARGET_LONG_BITS 32 |
54 | 6af0bf9c | bellard | /* real pages are variable size... */
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55 | 6af0bf9c | bellard | #define TARGET_PAGE_BITS 12 |
56 | c5d6edc3 | bellard | /* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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57 | 6af0bf9c | bellard | #define MIPS_USES_R4K_EXT
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58 | 6af0bf9c | bellard | /* Uses MIPS R4Km FPM MMU model */
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59 | 6af0bf9c | bellard | #define MIPS_USES_R4K_FPM
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60 | 6af0bf9c | bellard | #else
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61 | 6af0bf9c | bellard | #error "MIPS CPU not defined" |
62 | 6af0bf9c | bellard | /* Remainder for other flags */
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63 | 6af0bf9c | bellard | //#define TARGET_MIPS64
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64 | 6ea83fed | bellard | //#define MIPS_USES_FPU
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65 | 6af0bf9c | bellard | #endif
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66 | 6af0bf9c | bellard | |
67 | 6af0bf9c | bellard | #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |