root / hw / dma.c @ d7d02e3c
History | View | Annotate | Download (9.7 kB)
1 |
/*
|
---|---|
2 |
* QEMU DMA emulation
|
3 |
*
|
4 |
* Copyright (c) 2003 Vassili Karpov (malc)
|
5 |
*
|
6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 |
* of this software and associated documentation files (the "Software"), to deal
|
8 |
* in the Software without restriction, including without limitation the rights
|
9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 |
* copies of the Software, and to permit persons to whom the Software is
|
11 |
* furnished to do so, subject to the following conditions:
|
12 |
*
|
13 |
* The above copyright notice and this permission notice shall be included in
|
14 |
* all copies or substantial portions of the Software.
|
15 |
*
|
16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 |
* THE SOFTWARE.
|
23 |
*/
|
24 |
#include "vl.h" |
25 |
|
26 |
//#define DEBUG_DMA
|
27 |
|
28 |
#define log(...) fprintf (stderr, "dma: " __VA_ARGS__) |
29 |
#ifdef DEBUG_DMA
|
30 |
#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__) |
31 |
#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__) |
32 |
#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__) |
33 |
#else
|
34 |
#define lwarn(...)
|
35 |
#define linfo(...)
|
36 |
#define ldebug(...)
|
37 |
#endif
|
38 |
|
39 |
#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0]))) |
40 |
|
41 |
struct dma_regs {
|
42 |
int now[2]; |
43 |
uint16_t base[2];
|
44 |
uint8_t mode; |
45 |
uint8_t page; |
46 |
uint8_t dack; |
47 |
uint8_t eop; |
48 |
DMA_transfer_handler transfer_handler; |
49 |
void *opaque;
|
50 |
}; |
51 |
|
52 |
#define ADDR 0 |
53 |
#define COUNT 1 |
54 |
|
55 |
static struct dma_cont { |
56 |
uint8_t status; |
57 |
uint8_t command; |
58 |
uint8_t mask; |
59 |
uint8_t flip_flop; |
60 |
int dshift;
|
61 |
struct dma_regs regs[4]; |
62 |
} dma_controllers[2];
|
63 |
|
64 |
enum {
|
65 |
CMD_MEMORY_TO_MEMORY = 0x01,
|
66 |
CMD_FIXED_ADDRESS = 0x02,
|
67 |
CMD_BLOCK_CONTROLLER = 0x04,
|
68 |
CMD_COMPRESSED_TIME = 0x08,
|
69 |
CMD_CYCLIC_PRIORITY = 0x10,
|
70 |
CMD_EXTENDED_WRITE = 0x20,
|
71 |
CMD_LOW_DREQ = 0x40,
|
72 |
CMD_LOW_DACK = 0x80,
|
73 |
CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS |
74 |
| CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE |
75 |
| CMD_LOW_DREQ | CMD_LOW_DACK |
76 |
|
77 |
}; |
78 |
|
79 |
static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0}; |
80 |
|
81 |
static void write_page (void *opaque, uint32_t nport, uint32_t data) |
82 |
{ |
83 |
struct dma_cont *d = opaque;
|
84 |
int ichan;
|
85 |
|
86 |
ichan = channels[nport & 7];
|
87 |
|
88 |
if (-1 == ichan) { |
89 |
log ("invalid channel %#x %#x\n", nport, data);
|
90 |
return;
|
91 |
} |
92 |
d->regs[ichan].page = data; |
93 |
} |
94 |
|
95 |
static uint32_t read_page (void *opaque, uint32_t nport) |
96 |
{ |
97 |
struct dma_cont *d = opaque;
|
98 |
int ichan;
|
99 |
|
100 |
ichan = channels[nport & 7];
|
101 |
|
102 |
if (-1 == ichan) { |
103 |
log ("invalid channel read %#x\n", nport);
|
104 |
return 0; |
105 |
} |
106 |
return d->regs[ichan].page;
|
107 |
} |
108 |
|
109 |
static inline void init_chan (struct dma_cont *d, int ichan) |
110 |
{ |
111 |
struct dma_regs *r;
|
112 |
|
113 |
r = d->regs + ichan; |
114 |
r->now[ADDR] = r->base[0] << d->dshift;
|
115 |
r->now[COUNT] = 0;
|
116 |
} |
117 |
|
118 |
static inline int getff (struct dma_cont *d) |
119 |
{ |
120 |
int ff;
|
121 |
|
122 |
ff = d->flip_flop; |
123 |
d->flip_flop = !ff; |
124 |
return ff;
|
125 |
} |
126 |
|
127 |
static uint32_t read_chan (void *opaque, uint32_t nport) |
128 |
{ |
129 |
struct dma_cont *d = opaque;
|
130 |
int ichan, nreg, iport, ff, val;
|
131 |
struct dma_regs *r;
|
132 |
|
133 |
iport = (nport >> d->dshift) & 0x0f;
|
134 |
ichan = iport >> 1;
|
135 |
nreg = iport & 1;
|
136 |
r = d->regs + ichan; |
137 |
|
138 |
ff = getff (d); |
139 |
if (nreg)
|
140 |
val = (r->base[COUNT] << d->dshift) - r->now[COUNT]; |
141 |
else
|
142 |
val = r->now[ADDR] + r->now[COUNT]; |
143 |
|
144 |
return (val >> (d->dshift + (ff << 3))) & 0xff; |
145 |
} |
146 |
|
147 |
static void write_chan (void *opaque, uint32_t nport, uint32_t data) |
148 |
{ |
149 |
struct dma_cont *d = opaque;
|
150 |
int iport, ichan, nreg;
|
151 |
struct dma_regs *r;
|
152 |
|
153 |
iport = (nport >> d->dshift) & 0x0f;
|
154 |
ichan = iport >> 1;
|
155 |
nreg = iport & 1;
|
156 |
r = d->regs + ichan; |
157 |
if (getff (d)) {
|
158 |
r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
159 |
init_chan (d, ichan); |
160 |
} else {
|
161 |
r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
162 |
} |
163 |
} |
164 |
|
165 |
static void write_cont (void *opaque, uint32_t nport, uint32_t data) |
166 |
{ |
167 |
struct dma_cont *d = opaque;
|
168 |
int iport, ichan;
|
169 |
|
170 |
iport = (nport >> d->dshift) & 0x0f;
|
171 |
switch (iport) {
|
172 |
case 8: /* command */ |
173 |
if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { |
174 |
log ("command %#x not supported\n", data);
|
175 |
return;
|
176 |
} |
177 |
d->command = data; |
178 |
break;
|
179 |
|
180 |
case 9: |
181 |
ichan = data & 3;
|
182 |
if (data & 4) { |
183 |
d->status |= 1 << (ichan + 4); |
184 |
} |
185 |
else {
|
186 |
d->status &= ~(1 << (ichan + 4)); |
187 |
} |
188 |
d->status &= ~(1 << ichan);
|
189 |
break;
|
190 |
|
191 |
case 0xa: /* single mask */ |
192 |
if (data & 4) |
193 |
d->mask |= 1 << (data & 3); |
194 |
else
|
195 |
d->mask &= ~(1 << (data & 3)); |
196 |
break;
|
197 |
|
198 |
case 0xb: /* mode */ |
199 |
{ |
200 |
ichan = data & 3;
|
201 |
#ifdef DEBUG_DMA
|
202 |
int op;
|
203 |
int ai;
|
204 |
int dir;
|
205 |
int opmode;
|
206 |
|
207 |
op = (data >> 2) & 3; |
208 |
ai = (data >> 4) & 1; |
209 |
dir = (data >> 5) & 1; |
210 |
opmode = (data >> 6) & 3; |
211 |
|
212 |
linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
|
213 |
ichan, op, ai, dir, opmode); |
214 |
#endif
|
215 |
|
216 |
d->regs[ichan].mode = data; |
217 |
break;
|
218 |
} |
219 |
|
220 |
case 0xc: /* clear flip flop */ |
221 |
d->flip_flop = 0;
|
222 |
break;
|
223 |
|
224 |
case 0xd: /* reset */ |
225 |
d->flip_flop = 0;
|
226 |
d->mask = ~0;
|
227 |
d->status = 0;
|
228 |
d->command = 0;
|
229 |
break;
|
230 |
|
231 |
case 0xe: /* clear mask for all channels */ |
232 |
d->mask = 0;
|
233 |
break;
|
234 |
|
235 |
case 0xf: /* write mask for all channels */ |
236 |
d->mask = data; |
237 |
break;
|
238 |
|
239 |
default:
|
240 |
log ("dma: unknown iport %#x\n", iport);
|
241 |
break;
|
242 |
} |
243 |
|
244 |
#ifdef DEBUG_DMA
|
245 |
if (0xc != iport) { |
246 |
linfo ("nport %#06x, ichan % 2d, val %#06x\n",
|
247 |
nport, ichan, data); |
248 |
} |
249 |
#endif
|
250 |
} |
251 |
|
252 |
static uint32_t read_cont (void *opaque, uint32_t nport) |
253 |
{ |
254 |
struct dma_cont *d = opaque;
|
255 |
int iport, val;
|
256 |
|
257 |
iport = (nport >> d->dshift) & 0x0f;
|
258 |
switch (iport) {
|
259 |
case 0x08: /* status */ |
260 |
val = d->status; |
261 |
d->status &= 0xf0;
|
262 |
break;
|
263 |
case 0x0f: /* mask */ |
264 |
val = d->mask; |
265 |
break;
|
266 |
default:
|
267 |
val = 0;
|
268 |
break;
|
269 |
} |
270 |
return val;
|
271 |
} |
272 |
|
273 |
int DMA_get_channel_mode (int nchan) |
274 |
{ |
275 |
return dma_controllers[nchan > 3].regs[nchan & 3].mode; |
276 |
} |
277 |
|
278 |
void DMA_hold_DREQ (int nchan) |
279 |
{ |
280 |
int ncont, ichan;
|
281 |
|
282 |
ncont = nchan > 3;
|
283 |
ichan = nchan & 3;
|
284 |
linfo ("held cont=%d chan=%d\n", ncont, ichan);
|
285 |
dma_controllers[ncont].status |= 1 << (ichan + 4); |
286 |
} |
287 |
|
288 |
void DMA_release_DREQ (int nchan) |
289 |
{ |
290 |
int ncont, ichan;
|
291 |
|
292 |
ncont = nchan > 3;
|
293 |
ichan = nchan & 3;
|
294 |
linfo ("released cont=%d chan=%d\n", ncont, ichan);
|
295 |
dma_controllers[ncont].status &= ~(1 << (ichan + 4)); |
296 |
} |
297 |
|
298 |
static void channel_run (int ncont, int ichan) |
299 |
{ |
300 |
struct dma_regs *r;
|
301 |
int n;
|
302 |
target_ulong addr; |
303 |
/* int ai, dir; */
|
304 |
|
305 |
r = dma_controllers[ncont].regs + ichan; |
306 |
/* ai = r->mode & 16; */
|
307 |
/* dir = r->mode & 32 ? -1 : 1; */
|
308 |
|
309 |
addr = (r->page << 16) | r->now[ADDR];
|
310 |
n = r->transfer_handler (r->opaque, addr, |
311 |
(r->base[COUNT] << ncont) + (1 << ncont));
|
312 |
r->now[COUNT] = n; |
313 |
|
314 |
ldebug ("dma_pos %d size %d\n",
|
315 |
n, (r->base[1] << ncont) + (1 << ncont)); |
316 |
} |
317 |
|
318 |
void DMA_run (void) |
319 |
{ |
320 |
struct dma_cont *d;
|
321 |
int icont, ichan;
|
322 |
|
323 |
d = dma_controllers; |
324 |
|
325 |
for (icont = 0; icont < 2; icont++, d++) { |
326 |
for (ichan = 0; ichan < 4; ichan++) { |
327 |
int mask;
|
328 |
|
329 |
mask = 1 << ichan;
|
330 |
|
331 |
if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) |
332 |
channel_run (icont, ichan); |
333 |
} |
334 |
} |
335 |
} |
336 |
|
337 |
void DMA_register_channel (int nchan, |
338 |
DMA_transfer_handler transfer_handler, |
339 |
void *opaque)
|
340 |
{ |
341 |
struct dma_regs *r;
|
342 |
int ichan, ncont;
|
343 |
|
344 |
ncont = nchan > 3;
|
345 |
ichan = nchan & 3;
|
346 |
|
347 |
r = dma_controllers[ncont].regs + ichan; |
348 |
r->transfer_handler = transfer_handler; |
349 |
r->opaque = opaque; |
350 |
} |
351 |
|
352 |
/* request the emulator to transfer a new DMA memory block ASAP */
|
353 |
void DMA_schedule(int nchan) |
354 |
{ |
355 |
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT); |
356 |
} |
357 |
|
358 |
static void dma_reset(void *opaque) |
359 |
{ |
360 |
struct dma_cont *d = opaque;
|
361 |
write_cont (d, (0x0d << d->dshift), 0); |
362 |
} |
363 |
|
364 |
/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
|
365 |
static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base) |
366 |
{ |
367 |
const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; |
368 |
int i;
|
369 |
|
370 |
d->dshift = dshift; |
371 |
for (i = 0; i < 8; i++) { |
372 |
register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); |
373 |
register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); |
374 |
} |
375 |
for (i = 0; i < LENOFA (page_port_list); i++) { |
376 |
register_ioport_write (page_base + page_port_list[i], 1, 1, |
377 |
write_page, d); |
378 |
register_ioport_read (page_base + page_port_list[i], 1, 1, |
379 |
read_page, d); |
380 |
} |
381 |
for (i = 0; i < 8; i++) { |
382 |
register_ioport_write (base + ((i + 8) << dshift), 1, 1, |
383 |
write_cont, d); |
384 |
register_ioport_read (base + ((i + 8) << dshift), 1, 1, |
385 |
read_cont, d); |
386 |
} |
387 |
qemu_register_reset(dma_reset, d); |
388 |
dma_reset(d); |
389 |
} |
390 |
|
391 |
void DMA_init (void) |
392 |
{ |
393 |
dma_init2(&dma_controllers[0], 0x00, 0, 0x80); |
394 |
dma_init2(&dma_controllers[1], 0xc0, 1, 0x88); |
395 |
} |