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1 | 7a3f1944 | bellard | /*
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2 | 7a3f1944 | bellard | SPARC translation
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3 | 7a3f1944 | bellard | |
4 | 7a3f1944 | bellard | Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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5 | 3475187d | bellard | Copyright (C) 2003-2005 Fabrice Bellard
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6 | 7a3f1944 | bellard | |
7 | 7a3f1944 | bellard | This library is free software; you can redistribute it and/or
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8 | 7a3f1944 | bellard | modify it under the terms of the GNU Lesser General Public
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9 | 7a3f1944 | bellard | License as published by the Free Software Foundation; either
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10 | 7a3f1944 | bellard | version 2 of the License, or (at your option) any later version.
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11 | 7a3f1944 | bellard | |
12 | 7a3f1944 | bellard | This library is distributed in the hope that it will be useful,
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13 | 7a3f1944 | bellard | but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 7a3f1944 | bellard | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 7a3f1944 | bellard | Lesser General Public License for more details.
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16 | 7a3f1944 | bellard | |
17 | 7a3f1944 | bellard | You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 7a3f1944 | bellard | */
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20 | 7a3f1944 | bellard | |
21 | 7a3f1944 | bellard | #include <stdarg.h> |
22 | 7a3f1944 | bellard | #include <stdlib.h> |
23 | 7a3f1944 | bellard | #include <stdio.h> |
24 | 7a3f1944 | bellard | #include <string.h> |
25 | 7a3f1944 | bellard | #include <inttypes.h> |
26 | 7a3f1944 | bellard | |
27 | 7a3f1944 | bellard | #include "cpu.h" |
28 | 7a3f1944 | bellard | #include "exec-all.h" |
29 | 7a3f1944 | bellard | #include "disas.h" |
30 | 1a2fb1c0 | blueswir1 | #include "helper.h" |
31 | 57fec1fe | bellard | #include "tcg-op.h" |
32 | 7a3f1944 | bellard | |
33 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
34 | a7812ae4 | pbrook | #include "helper.h" |
35 | a7812ae4 | pbrook | |
36 | 7a3f1944 | bellard | #define DEBUG_DISAS
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37 | 7a3f1944 | bellard | |
38 | 72cbca10 | bellard | #define DYNAMIC_PC 1 /* dynamic pc value */ |
39 | 72cbca10 | bellard | #define JUMP_PC 2 /* dynamic pc value which takes only two values |
40 | 72cbca10 | bellard | according to jump_pc[T2] */
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41 | 72cbca10 | bellard | |
42 | 1a2fb1c0 | blueswir1 | /* global register indexes */
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43 | a7812ae4 | pbrook | static TCGv_ptr cpu_env, cpu_regwptr;
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44 | 25517f99 | Paul Brook | static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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45 | 25517f99 | Paul Brook | static TCGv_i32 cpu_cc_op;
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46 | a7812ae4 | pbrook | static TCGv_i32 cpu_psr;
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47 | a7812ae4 | pbrook | static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; |
48 | 255e1fcb | blueswir1 | static TCGv cpu_y;
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49 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
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50 | 255e1fcb | blueswir1 | static TCGv cpu_tbr;
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51 | 255e1fcb | blueswir1 | #endif
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52 | 6ae20372 | blueswir1 | static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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53 | dc99a3f2 | blueswir1 | #ifdef TARGET_SPARC64
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54 | a7812ae4 | pbrook | static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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55 | a7812ae4 | pbrook | static TCGv cpu_gsr;
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56 | 255e1fcb | blueswir1 | static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
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57 | a7812ae4 | pbrook | static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
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58 | a7812ae4 | pbrook | static TCGv_i32 cpu_softint;
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59 | 255e1fcb | blueswir1 | #else
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60 | 255e1fcb | blueswir1 | static TCGv cpu_wim;
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61 | dc99a3f2 | blueswir1 | #endif
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62 | 1a2fb1c0 | blueswir1 | /* local register indexes (only used inside old micro ops) */
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63 | a7812ae4 | pbrook | static TCGv cpu_tmp0;
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64 | a7812ae4 | pbrook | static TCGv_i32 cpu_tmp32;
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65 | a7812ae4 | pbrook | static TCGv_i64 cpu_tmp64;
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66 | 714547bb | blueswir1 | /* Floating point registers */
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67 | a7812ae4 | pbrook | static TCGv_i32 cpu_fpr[TARGET_FPREGS];
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68 | 1a2fb1c0 | blueswir1 | |
69 | 1a7ff922 | Paolo Bonzini | static target_ulong gen_opc_npc[OPC_BUF_SIZE];
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70 | 1a7ff922 | Paolo Bonzini | static target_ulong gen_opc_jump_pc[2]; |
71 | 1a7ff922 | Paolo Bonzini | |
72 | 2e70f6ef | pbrook | #include "gen-icount.h" |
73 | 2e70f6ef | pbrook | |
74 | 7a3f1944 | bellard | typedef struct DisasContext { |
75 | 0f8a249a | blueswir1 | target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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76 | 0f8a249a | blueswir1 | target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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77 | 72cbca10 | bellard | target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */ |
78 | cf495bcf | bellard | int is_br;
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79 | e8af50a3 | bellard | int mem_idx;
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80 | a80dde08 | bellard | int fpu_enabled;
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81 | 2cade6a3 | blueswir1 | int address_mask_32bit;
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82 | 8393617c | Blue Swirl | uint32_t cc_op; /* current CC operation */
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83 | cf495bcf | bellard | struct TranslationBlock *tb;
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84 | 5578ceab | blueswir1 | sparc_def_t *def; |
85 | 7a3f1944 | bellard | } DisasContext; |
86 | 7a3f1944 | bellard | |
87 | 3475187d | bellard | // This function uses non-native bit order
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88 | dc1a6971 | Blue Swirl | #define GET_FIELD(X, FROM, TO) \
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89 | dc1a6971 | Blue Swirl | ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1)) |
90 | 7a3f1944 | bellard | |
91 | 3475187d | bellard | // This function uses the order in the manuals, i.e. bit 0 is 2^0
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92 | dc1a6971 | Blue Swirl | #define GET_FIELD_SP(X, FROM, TO) \
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93 | 3475187d | bellard | GET_FIELD(X, 31 - (TO), 31 - (FROM)) |
94 | 3475187d | bellard | |
95 | 3475187d | bellard | #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1) |
96 | 46d38ba8 | blueswir1 | #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1)) |
97 | 3475187d | bellard | |
98 | 3475187d | bellard | #ifdef TARGET_SPARC64
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99 | 0387d928 | blueswir1 | #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e)) |
100 | 1f587329 | blueswir1 | #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c)) |
101 | 3475187d | bellard | #else
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102 | c185970a | blueswir1 | #define DFPREG(r) (r & 0x1e) |
103 | 1f587329 | blueswir1 | #define QFPREG(r) (r & 0x1c) |
104 | 3475187d | bellard | #endif
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105 | 3475187d | bellard | |
106 | b158a785 | blueswir1 | #define UA2005_HTRAP_MASK 0xff |
107 | b158a785 | blueswir1 | #define V8_TRAP_MASK 0x7f |
108 | b158a785 | blueswir1 | |
109 | 3475187d | bellard | static int sign_extend(int x, int len) |
110 | 3475187d | bellard | { |
111 | 3475187d | bellard | len = 32 - len;
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112 | 3475187d | bellard | return (x << len) >> len;
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113 | 3475187d | bellard | } |
114 | 3475187d | bellard | |
115 | 7a3f1944 | bellard | #define IS_IMM (insn & (1<<13)) |
116 | 7a3f1944 | bellard | |
117 | ff07ec83 | blueswir1 | /* floating point registers moves */
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118 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT0(unsigned int src) |
119 | ff07ec83 | blueswir1 | { |
120 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) + |
121 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
122 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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123 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
124 | ff07ec83 | blueswir1 | } |
125 | ff07ec83 | blueswir1 | |
126 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_DT1(unsigned int src) |
127 | ff07ec83 | blueswir1 | { |
128 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) + |
129 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
130 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
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131 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
132 | ff07ec83 | blueswir1 | } |
133 | ff07ec83 | blueswir1 | |
134 | ff07ec83 | blueswir1 | static void gen_op_store_DT0_fpr(unsigned int dst) |
135 | ff07ec83 | blueswir1 | { |
136 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) + |
137 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.upper)); |
138 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
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139 | 77f193da | blueswir1 | offsetof(CPU_DoubleU, l.lower)); |
140 | ff07ec83 | blueswir1 | } |
141 | ff07ec83 | blueswir1 | |
142 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT0(unsigned int src) |
143 | ff07ec83 | blueswir1 | { |
144 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + |
145 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
146 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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147 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
148 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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149 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
150 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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151 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
152 | ff07ec83 | blueswir1 | } |
153 | ff07ec83 | blueswir1 | |
154 | ff07ec83 | blueswir1 | static void gen_op_load_fpr_QT1(unsigned int src) |
155 | ff07ec83 | blueswir1 | { |
156 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + |
157 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
158 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
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159 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
160 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
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161 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
162 | 714547bb | blueswir1 | tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
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163 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
164 | ff07ec83 | blueswir1 | } |
165 | ff07ec83 | blueswir1 | |
166 | ff07ec83 | blueswir1 | static void gen_op_store_QT0_fpr(unsigned int dst) |
167 | ff07ec83 | blueswir1 | { |
168 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + |
169 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upmost)); |
170 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
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171 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.upper)); |
172 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
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173 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lower)); |
174 | 714547bb | blueswir1 | tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
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175 | 77f193da | blueswir1 | offsetof(CPU_QuadU, l.lowest)); |
176 | ff07ec83 | blueswir1 | } |
177 | 1f587329 | blueswir1 | |
178 | 81ad8ba2 | blueswir1 | /* moves */
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179 | 81ad8ba2 | blueswir1 | #ifdef CONFIG_USER_ONLY
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180 | 3475187d | bellard | #define supervisor(dc) 0 |
181 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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182 | e9ebed4d | blueswir1 | #define hypervisor(dc) 0 |
183 | 81ad8ba2 | blueswir1 | #endif
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184 | 3475187d | bellard | #else
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185 | 6f27aba6 | blueswir1 | #define supervisor(dc) (dc->mem_idx >= 1) |
186 | 81ad8ba2 | blueswir1 | #ifdef TARGET_SPARC64
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187 | 81ad8ba2 | blueswir1 | #define hypervisor(dc) (dc->mem_idx == 2) |
188 | 6f27aba6 | blueswir1 | #else
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189 | 3475187d | bellard | #endif
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190 | 81ad8ba2 | blueswir1 | #endif
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191 | 81ad8ba2 | blueswir1 | |
192 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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193 | 2cade6a3 | blueswir1 | #ifndef TARGET_ABI32
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194 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) ((dc)->address_mask_32bit)
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195 | 1a2fb1c0 | blueswir1 | #else
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196 | 2cade6a3 | blueswir1 | #define AM_CHECK(dc) (1) |
197 | 2cade6a3 | blueswir1 | #endif
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198 | 1a2fb1c0 | blueswir1 | #endif
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199 | 3391c818 | blueswir1 | |
200 | 2cade6a3 | blueswir1 | static inline void gen_address_mask(DisasContext *dc, TCGv addr) |
201 | 2cade6a3 | blueswir1 | { |
202 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
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203 | 2cade6a3 | blueswir1 | if (AM_CHECK(dc))
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204 | 2cade6a3 | blueswir1 | tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
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205 | 2cade6a3 | blueswir1 | #endif
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206 | 2cade6a3 | blueswir1 | } |
207 | 2cade6a3 | blueswir1 | |
208 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_reg_TN(int reg, TCGv tn) |
209 | 81ad8ba2 | blueswir1 | { |
210 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
211 | 1a2fb1c0 | blueswir1 | tcg_gen_movi_tl(tn, 0);
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212 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
213 | f5069b26 | blueswir1 | tcg_gen_mov_tl(tn, cpu_gregs[reg]); |
214 | 1a2fb1c0 | blueswir1 | else {
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215 | 1a2fb1c0 | blueswir1 | tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
216 | 81ad8ba2 | blueswir1 | } |
217 | 81ad8ba2 | blueswir1 | } |
218 | 81ad8ba2 | blueswir1 | |
219 | 1a2fb1c0 | blueswir1 | static inline void gen_movl_TN_reg(int reg, TCGv tn) |
220 | 81ad8ba2 | blueswir1 | { |
221 | 1a2fb1c0 | blueswir1 | if (reg == 0) |
222 | 1a2fb1c0 | blueswir1 | return;
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223 | 1a2fb1c0 | blueswir1 | else if (reg < 8) |
224 | f5069b26 | blueswir1 | tcg_gen_mov_tl(cpu_gregs[reg], tn); |
225 | 1a2fb1c0 | blueswir1 | else {
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226 | 1a2fb1c0 | blueswir1 | tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong)); |
227 | 81ad8ba2 | blueswir1 | } |
228 | 81ad8ba2 | blueswir1 | } |
229 | 81ad8ba2 | blueswir1 | |
230 | 5fafdf24 | ths | static inline void gen_goto_tb(DisasContext *s, int tb_num, |
231 | 6e256c93 | bellard | target_ulong pc, target_ulong npc) |
232 | 6e256c93 | bellard | { |
233 | 6e256c93 | bellard | TranslationBlock *tb; |
234 | 6e256c93 | bellard | |
235 | 6e256c93 | bellard | tb = s->tb; |
236 | 6e256c93 | bellard | if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
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237 | 6e256c93 | bellard | (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) { |
238 | 6e256c93 | bellard | /* jump to same page: we can use a direct jump */
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239 | 57fec1fe | bellard | tcg_gen_goto_tb(tb_num); |
240 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
241 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
242 | 57fec1fe | bellard | tcg_gen_exit_tb((long)tb + tb_num);
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243 | 6e256c93 | bellard | } else {
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244 | 6e256c93 | bellard | /* jump to another page: currently not optimized */
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245 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, pc); |
246 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc); |
247 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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248 | 6e256c93 | bellard | } |
249 | 6e256c93 | bellard | } |
250 | 6e256c93 | bellard | |
251 | 19f329ad | blueswir1 | // XXX suboptimal
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252 | a7812ae4 | pbrook | static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) |
253 | 19f329ad | blueswir1 | { |
254 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
255 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); |
256 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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257 | 19f329ad | blueswir1 | } |
258 | 19f329ad | blueswir1 | |
259 | a7812ae4 | pbrook | static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) |
260 | 19f329ad | blueswir1 | { |
261 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
262 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); |
263 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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264 | 19f329ad | blueswir1 | } |
265 | 19f329ad | blueswir1 | |
266 | a7812ae4 | pbrook | static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) |
267 | 19f329ad | blueswir1 | { |
268 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
269 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); |
270 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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271 | 19f329ad | blueswir1 | } |
272 | 19f329ad | blueswir1 | |
273 | a7812ae4 | pbrook | static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) |
274 | 19f329ad | blueswir1 | { |
275 | 8911f501 | blueswir1 | tcg_gen_extu_i32_tl(reg, src); |
276 | 4b8b8b76 | blueswir1 | tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); |
277 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
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278 | 19f329ad | blueswir1 | } |
279 | 19f329ad | blueswir1 | |
280 | dc99a3f2 | blueswir1 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
281 | dc99a3f2 | blueswir1 | { |
282 | a7812ae4 | pbrook | TCGv r_temp; |
283 | a7812ae4 | pbrook | TCGv_i32 r_const; |
284 | dc99a3f2 | blueswir1 | int l1;
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285 | dc99a3f2 | blueswir1 | |
286 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
287 | dc99a3f2 | blueswir1 | |
288 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
289 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
290 | 2576d836 | blueswir1 | tcg_gen_not_tl(r_temp, r_temp); |
291 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
292 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
293 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
294 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
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295 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
296 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
297 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
298 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
299 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
300 | dc99a3f2 | blueswir1 | } |
301 | dc99a3f2 | blueswir1 | |
302 | dc99a3f2 | blueswir1 | static inline void gen_tag_tv(TCGv src1, TCGv src2) |
303 | dc99a3f2 | blueswir1 | { |
304 | dc99a3f2 | blueswir1 | int l1;
|
305 | a7812ae4 | pbrook | TCGv_i32 r_const; |
306 | dc99a3f2 | blueswir1 | |
307 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
308 | 0425bee5 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, src1, src2); |
309 | 0425bee5 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
|
310 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
|
311 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
312 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
313 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
314 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
315 | dc99a3f2 | blueswir1 | } |
316 | dc99a3f2 | blueswir1 | |
317 | 41d72852 | Blue Swirl | static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2) |
318 | 41d72852 | Blue Swirl | { |
319 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
320 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
321 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2); |
322 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
323 | 41d72852 | Blue Swirl | } |
324 | 41d72852 | Blue Swirl | |
325 | 4af984a7 | blueswir1 | static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2) |
326 | dc99a3f2 | blueswir1 | { |
327 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
328 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
329 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
330 | bdf9f35d | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
331 | 41d72852 | Blue Swirl | } |
332 | 41d72852 | Blue Swirl | |
333 | 41d72852 | Blue Swirl | static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2) |
334 | dc99a3f2 | blueswir1 | { |
335 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
336 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
337 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
338 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
339 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
340 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
341 | 41d72852 | Blue Swirl | } |
342 | 41d72852 | Blue Swirl | |
343 | 41d72852 | Blue Swirl | static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2) |
344 | 41d72852 | Blue Swirl | { |
345 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
346 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
347 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
348 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
349 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
350 | 789c91ef | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
351 | dc99a3f2 | blueswir1 | } |
352 | dc99a3f2 | blueswir1 | |
353 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2) |
354 | dc99a3f2 | blueswir1 | { |
355 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
356 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
357 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
358 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
359 | dc99a3f2 | blueswir1 | } |
360 | dc99a3f2 | blueswir1 | |
361 | 4af984a7 | blueswir1 | static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2) |
362 | dc99a3f2 | blueswir1 | { |
363 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
364 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
365 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
366 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
367 | 5c6a0628 | blueswir1 | gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
368 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
369 | dc99a3f2 | blueswir1 | } |
370 | dc99a3f2 | blueswir1 | |
371 | dc99a3f2 | blueswir1 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
372 | dc99a3f2 | blueswir1 | { |
373 | a7812ae4 | pbrook | TCGv r_temp; |
374 | a7812ae4 | pbrook | TCGv_i32 r_const; |
375 | dc99a3f2 | blueswir1 | int l1;
|
376 | dc99a3f2 | blueswir1 | |
377 | dc99a3f2 | blueswir1 | l1 = gen_new_label(); |
378 | dc99a3f2 | blueswir1 | |
379 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
380 | dc99a3f2 | blueswir1 | tcg_gen_xor_tl(r_temp, src1, src2); |
381 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, src1, dst); |
382 | 0425bee5 | blueswir1 | tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); |
383 | dd5e6304 | blueswir1 | tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); |
384 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
|
385 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_TOVF); |
386 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
387 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
388 | dc99a3f2 | blueswir1 | gen_set_label(l1); |
389 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
390 | dc99a3f2 | blueswir1 | } |
391 | dc99a3f2 | blueswir1 | |
392 | d4b0d468 | Blue Swirl | static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc) |
393 | 41d72852 | Blue Swirl | { |
394 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
395 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
396 | 719f66a7 | Blue Swirl | if (src2 == 0) { |
397 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, src1); |
398 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
399 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
400 | 719f66a7 | Blue Swirl | } else {
|
401 | 719f66a7 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2); |
402 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
403 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
404 | 719f66a7 | Blue Swirl | } |
405 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
406 | 41d72852 | Blue Swirl | } |
407 | 41d72852 | Blue Swirl | |
408 | 41d72852 | Blue Swirl | static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) |
409 | dc99a3f2 | blueswir1 | { |
410 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
411 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
412 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
413 | d4b0d468 | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
414 | 41d72852 | Blue Swirl | } |
415 | 41d72852 | Blue Swirl | |
416 | 41d72852 | Blue Swirl | static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) |
417 | 41d72852 | Blue Swirl | { |
418 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
419 | 41d72852 | Blue Swirl | tcg_gen_movi_tl(cpu_cc_src2, src2); |
420 | dc99a3f2 | blueswir1 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
421 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
422 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); |
423 | 2ca1d92b | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
424 | 41d72852 | Blue Swirl | } |
425 | 41d72852 | Blue Swirl | |
426 | 41d72852 | Blue Swirl | static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) |
427 | 41d72852 | Blue Swirl | { |
428 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src, src1); |
429 | 41d72852 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_src2, src2); |
430 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
431 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); |
432 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); |
433 | 2ca1d92b | Blue Swirl | tcg_gen_mov_tl(dst, cpu_cc_dst); |
434 | dc99a3f2 | blueswir1 | } |
435 | dc99a3f2 | blueswir1 | |
436 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) |
437 | dc99a3f2 | blueswir1 | { |
438 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
439 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
440 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
441 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
442 | dc99a3f2 | blueswir1 | } |
443 | dc99a3f2 | blueswir1 | |
444 | 4af984a7 | blueswir1 | static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2) |
445 | dc99a3f2 | blueswir1 | { |
446 | 4af984a7 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
447 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
448 | 6f551262 | blueswir1 | gen_tag_tv(cpu_cc_src, cpu_cc_src2); |
449 | 5c6a0628 | blueswir1 | tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
450 | 5c6a0628 | blueswir1 | gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
451 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
452 | dc99a3f2 | blueswir1 | } |
453 | dc99a3f2 | blueswir1 | |
454 | 4af984a7 | blueswir1 | static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) |
455 | d9bdab86 | blueswir1 | { |
456 | 105a1f04 | blueswir1 | TCGv r_temp; |
457 | 6f551262 | blueswir1 | int l1;
|
458 | d9bdab86 | blueswir1 | |
459 | d9bdab86 | blueswir1 | l1 = gen_new_label(); |
460 | a7812ae4 | pbrook | r_temp = tcg_temp_new(); |
461 | d9bdab86 | blueswir1 | |
462 | d9bdab86 | blueswir1 | /* old op:
|
463 | d9bdab86 | blueswir1 | if (!(env->y & 1))
|
464 | d9bdab86 | blueswir1 | T1 = 0;
|
465 | d9bdab86 | blueswir1 | */
|
466 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
|
467 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
|
468 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
|
469 | 105a1f04 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
|
470 | d9bdab86 | blueswir1 | tcg_gen_movi_tl(cpu_cc_src2, 0);
|
471 | 6f551262 | blueswir1 | gen_set_label(l1); |
472 | d9bdab86 | blueswir1 | |
473 | d9bdab86 | blueswir1 | // b2 = T0 & 1;
|
474 | d9bdab86 | blueswir1 | // env->y = (b2 << 31) | (env->y >> 1);
|
475 | 105a1f04 | blueswir1 | tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
|
476 | 105a1f04 | blueswir1 | tcg_gen_shli_tl(r_temp, r_temp, 31);
|
477 | 255e1fcb | blueswir1 | tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
|
478 | 72ccba79 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
|
479 | 5068cbd9 | blueswir1 | tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp); |
480 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
481 | d9bdab86 | blueswir1 | |
482 | d9bdab86 | blueswir1 | // b1 = N ^ V;
|
483 | d9bdab86 | blueswir1 | gen_mov_reg_N(cpu_tmp0, cpu_psr); |
484 | d9bdab86 | blueswir1 | gen_mov_reg_V(r_temp, cpu_psr); |
485 | d9bdab86 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp); |
486 | 2ea815ca | blueswir1 | tcg_temp_free(r_temp); |
487 | d9bdab86 | blueswir1 | |
488 | d9bdab86 | blueswir1 | // T0 = (b1 << 31) | (T0 >> 1);
|
489 | d9bdab86 | blueswir1 | // src1 = T0;
|
490 | d9bdab86 | blueswir1 | tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
|
491 | 6f551262 | blueswir1 | tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
|
492 | d9bdab86 | blueswir1 | tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); |
493 | d9bdab86 | blueswir1 | |
494 | 5c6a0628 | blueswir1 | tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); |
495 | d9bdab86 | blueswir1 | |
496 | 5c6a0628 | blueswir1 | tcg_gen_mov_tl(dst, cpu_cc_dst); |
497 | d9bdab86 | blueswir1 | } |
498 | d9bdab86 | blueswir1 | |
499 | 4af984a7 | blueswir1 | static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) |
500 | 8879d139 | blueswir1 | { |
501 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
502 | 8879d139 | blueswir1 | |
503 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
504 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
505 | 8879d139 | blueswir1 | |
506 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp, src2); |
507 | 527067d8 | blueswir1 | tcg_gen_extu_tl_i64(r_temp2, src1); |
508 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
509 | 8879d139 | blueswir1 | |
510 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
511 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
512 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
513 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
514 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
515 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
516 | 8879d139 | blueswir1 | #else
|
517 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
518 | 8879d139 | blueswir1 | #endif
|
519 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
520 | 8879d139 | blueswir1 | } |
521 | 8879d139 | blueswir1 | |
522 | 4af984a7 | blueswir1 | static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) |
523 | 8879d139 | blueswir1 | { |
524 | a7812ae4 | pbrook | TCGv_i64 r_temp, r_temp2; |
525 | 8879d139 | blueswir1 | |
526 | a7812ae4 | pbrook | r_temp = tcg_temp_new_i64(); |
527 | a7812ae4 | pbrook | r_temp2 = tcg_temp_new_i64(); |
528 | 8879d139 | blueswir1 | |
529 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp, src2); |
530 | 527067d8 | blueswir1 | tcg_gen_ext_tl_i64(r_temp2, src1); |
531 | 8879d139 | blueswir1 | tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); |
532 | 8879d139 | blueswir1 | |
533 | 8879d139 | blueswir1 | tcg_gen_shri_i64(r_temp, r_temp2, 32);
|
534 | 105a1f04 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); |
535 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp); |
536 | 255e1fcb | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
537 | 8879d139 | blueswir1 | #ifdef TARGET_SPARC64
|
538 | 4af984a7 | blueswir1 | tcg_gen_mov_i64(dst, r_temp2); |
539 | 8879d139 | blueswir1 | #else
|
540 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, r_temp2); |
541 | 8879d139 | blueswir1 | #endif
|
542 | a7812ae4 | pbrook | tcg_temp_free_i64(r_temp2); |
543 | 8879d139 | blueswir1 | } |
544 | 8879d139 | blueswir1 | |
545 | 1a7b60e7 | blueswir1 | #ifdef TARGET_SPARC64
|
546 | 8911f501 | blueswir1 | static inline void gen_trap_ifdivzero_tl(TCGv divisor) |
547 | 1a7b60e7 | blueswir1 | { |
548 | a7812ae4 | pbrook | TCGv_i32 r_const; |
549 | 1a7b60e7 | blueswir1 | int l1;
|
550 | 1a7b60e7 | blueswir1 | |
551 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
552 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
|
553 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_DIV_ZERO); |
554 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
555 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
556 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
557 | 1a7b60e7 | blueswir1 | } |
558 | 1a7b60e7 | blueswir1 | |
559 | 4af984a7 | blueswir1 | static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) |
560 | 1a7b60e7 | blueswir1 | { |
561 | 1a7b60e7 | blueswir1 | int l1, l2;
|
562 | 1a7b60e7 | blueswir1 | |
563 | 1a7b60e7 | blueswir1 | l1 = gen_new_label(); |
564 | 1a7b60e7 | blueswir1 | l2 = gen_new_label(); |
565 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, src1); |
566 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, src2); |
567 | 5c6a0628 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
568 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); |
569 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
|
570 | 4af984a7 | blueswir1 | tcg_gen_movi_i64(dst, INT64_MIN); |
571 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
572 | 1a7b60e7 | blueswir1 | gen_set_label(l1); |
573 | 6f551262 | blueswir1 | tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); |
574 | 1a7b60e7 | blueswir1 | gen_set_label(l2); |
575 | 1a7b60e7 | blueswir1 | } |
576 | 1a7b60e7 | blueswir1 | #endif
|
577 | 1a7b60e7 | blueswir1 | |
578 | 19f329ad | blueswir1 | // 1
|
579 | 19f329ad | blueswir1 | static inline void gen_op_eval_ba(TCGv dst) |
580 | 19f329ad | blueswir1 | { |
581 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 1);
|
582 | 19f329ad | blueswir1 | } |
583 | 19f329ad | blueswir1 | |
584 | 19f329ad | blueswir1 | // Z
|
585 | a7812ae4 | pbrook | static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) |
586 | 19f329ad | blueswir1 | { |
587 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
588 | 19f329ad | blueswir1 | } |
589 | 19f329ad | blueswir1 | |
590 | 19f329ad | blueswir1 | // Z | (N ^ V)
|
591 | a7812ae4 | pbrook | static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) |
592 | 19f329ad | blueswir1 | { |
593 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
594 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
595 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
596 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
597 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
598 | 19f329ad | blueswir1 | } |
599 | 19f329ad | blueswir1 | |
600 | 19f329ad | blueswir1 | // N ^ V
|
601 | a7812ae4 | pbrook | static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) |
602 | 19f329ad | blueswir1 | { |
603 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
604 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
605 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
606 | 19f329ad | blueswir1 | } |
607 | 19f329ad | blueswir1 | |
608 | 19f329ad | blueswir1 | // C | Z
|
609 | a7812ae4 | pbrook | static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) |
610 | 19f329ad | blueswir1 | { |
611 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
612 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
613 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
614 | 19f329ad | blueswir1 | } |
615 | 19f329ad | blueswir1 | |
616 | 19f329ad | blueswir1 | // C
|
617 | a7812ae4 | pbrook | static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) |
618 | 19f329ad | blueswir1 | { |
619 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
620 | 19f329ad | blueswir1 | } |
621 | 19f329ad | blueswir1 | |
622 | 19f329ad | blueswir1 | // V
|
623 | a7812ae4 | pbrook | static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) |
624 | 19f329ad | blueswir1 | { |
625 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
626 | 19f329ad | blueswir1 | } |
627 | 19f329ad | blueswir1 | |
628 | 19f329ad | blueswir1 | // 0
|
629 | 19f329ad | blueswir1 | static inline void gen_op_eval_bn(TCGv dst) |
630 | 19f329ad | blueswir1 | { |
631 | 19f329ad | blueswir1 | tcg_gen_movi_tl(dst, 0);
|
632 | 19f329ad | blueswir1 | } |
633 | 19f329ad | blueswir1 | |
634 | 19f329ad | blueswir1 | // N
|
635 | a7812ae4 | pbrook | static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) |
636 | 19f329ad | blueswir1 | { |
637 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
638 | 19f329ad | blueswir1 | } |
639 | 19f329ad | blueswir1 | |
640 | 19f329ad | blueswir1 | // !Z
|
641 | a7812ae4 | pbrook | static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) |
642 | 19f329ad | blueswir1 | { |
643 | 19f329ad | blueswir1 | gen_mov_reg_Z(dst, src); |
644 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
645 | 19f329ad | blueswir1 | } |
646 | 19f329ad | blueswir1 | |
647 | 19f329ad | blueswir1 | // !(Z | (N ^ V))
|
648 | a7812ae4 | pbrook | static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) |
649 | 19f329ad | blueswir1 | { |
650 | 0425bee5 | blueswir1 | gen_mov_reg_N(cpu_tmp0, src); |
651 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
652 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
653 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
654 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
655 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
656 | 19f329ad | blueswir1 | } |
657 | 19f329ad | blueswir1 | |
658 | 19f329ad | blueswir1 | // !(N ^ V)
|
659 | a7812ae4 | pbrook | static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) |
660 | 19f329ad | blueswir1 | { |
661 | 0425bee5 | blueswir1 | gen_mov_reg_V(cpu_tmp0, src); |
662 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
663 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
664 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
665 | 19f329ad | blueswir1 | } |
666 | 19f329ad | blueswir1 | |
667 | 19f329ad | blueswir1 | // !(C | Z)
|
668 | a7812ae4 | pbrook | static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) |
669 | 19f329ad | blueswir1 | { |
670 | 0425bee5 | blueswir1 | gen_mov_reg_Z(cpu_tmp0, src); |
671 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
672 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
673 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
674 | 19f329ad | blueswir1 | } |
675 | 19f329ad | blueswir1 | |
676 | 19f329ad | blueswir1 | // !C
|
677 | a7812ae4 | pbrook | static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) |
678 | 19f329ad | blueswir1 | { |
679 | 19f329ad | blueswir1 | gen_mov_reg_C(dst, src); |
680 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
681 | 19f329ad | blueswir1 | } |
682 | 19f329ad | blueswir1 | |
683 | 19f329ad | blueswir1 | // !N
|
684 | a7812ae4 | pbrook | static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) |
685 | 19f329ad | blueswir1 | { |
686 | 19f329ad | blueswir1 | gen_mov_reg_N(dst, src); |
687 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
688 | 19f329ad | blueswir1 | } |
689 | 19f329ad | blueswir1 | |
690 | 19f329ad | blueswir1 | // !V
|
691 | a7812ae4 | pbrook | static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) |
692 | 19f329ad | blueswir1 | { |
693 | 19f329ad | blueswir1 | gen_mov_reg_V(dst, src); |
694 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
695 | 19f329ad | blueswir1 | } |
696 | 19f329ad | blueswir1 | |
697 | 19f329ad | blueswir1 | /*
|
698 | 19f329ad | blueswir1 | FPSR bit field FCC1 | FCC0:
|
699 | 19f329ad | blueswir1 | 0 =
|
700 | 19f329ad | blueswir1 | 1 <
|
701 | 19f329ad | blueswir1 | 2 >
|
702 | 19f329ad | blueswir1 | 3 unordered
|
703 | 19f329ad | blueswir1 | */
|
704 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src, |
705 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
706 | 19f329ad | blueswir1 | { |
707 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset); |
708 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
709 | 19f329ad | blueswir1 | } |
710 | 19f329ad | blueswir1 | |
711 | 19f329ad | blueswir1 | static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src, |
712 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
713 | 19f329ad | blueswir1 | { |
714 | ba6a9d8c | blueswir1 | tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset); |
715 | 19f329ad | blueswir1 | tcg_gen_andi_tl(reg, reg, 0x1);
|
716 | 19f329ad | blueswir1 | } |
717 | 19f329ad | blueswir1 | |
718 | 19f329ad | blueswir1 | // !0: FCC0 | FCC1
|
719 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbne(TCGv dst, TCGv src, |
720 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
721 | 19f329ad | blueswir1 | { |
722 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
723 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
724 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
725 | 19f329ad | blueswir1 | } |
726 | 19f329ad | blueswir1 | |
727 | 19f329ad | blueswir1 | // 1 or 2: FCC0 ^ FCC1
|
728 | 19f329ad | blueswir1 | static inline void gen_op_eval_fblg(TCGv dst, TCGv src, |
729 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
730 | 19f329ad | blueswir1 | { |
731 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
732 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
733 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
734 | 19f329ad | blueswir1 | } |
735 | 19f329ad | blueswir1 | |
736 | 19f329ad | blueswir1 | // 1 or 3: FCC0
|
737 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbul(TCGv dst, TCGv src, |
738 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
739 | 19f329ad | blueswir1 | { |
740 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
741 | 19f329ad | blueswir1 | } |
742 | 19f329ad | blueswir1 | |
743 | 19f329ad | blueswir1 | // 1: FCC0 & !FCC1
|
744 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbl(TCGv dst, TCGv src, |
745 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
746 | 19f329ad | blueswir1 | { |
747 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
748 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
749 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
750 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
751 | 19f329ad | blueswir1 | } |
752 | 19f329ad | blueswir1 | |
753 | 19f329ad | blueswir1 | // 2 or 3: FCC1
|
754 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbug(TCGv dst, TCGv src, |
755 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
756 | 19f329ad | blueswir1 | { |
757 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
758 | 19f329ad | blueswir1 | } |
759 | 19f329ad | blueswir1 | |
760 | 19f329ad | blueswir1 | // 2: !FCC0 & FCC1
|
761 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbg(TCGv dst, TCGv src, |
762 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
763 | 19f329ad | blueswir1 | { |
764 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
765 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
766 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
767 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
768 | 19f329ad | blueswir1 | } |
769 | 19f329ad | blueswir1 | |
770 | 19f329ad | blueswir1 | // 3: FCC0 & FCC1
|
771 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbu(TCGv dst, TCGv src, |
772 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
773 | 19f329ad | blueswir1 | { |
774 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
775 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
776 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
777 | 19f329ad | blueswir1 | } |
778 | 19f329ad | blueswir1 | |
779 | 19f329ad | blueswir1 | // 0: !(FCC0 | FCC1)
|
780 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbe(TCGv dst, TCGv src, |
781 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
782 | 19f329ad | blueswir1 | { |
783 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
784 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
785 | 0425bee5 | blueswir1 | tcg_gen_or_tl(dst, dst, cpu_tmp0); |
786 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
787 | 19f329ad | blueswir1 | } |
788 | 19f329ad | blueswir1 | |
789 | 19f329ad | blueswir1 | // 0 or 3: !(FCC0 ^ FCC1)
|
790 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbue(TCGv dst, TCGv src, |
791 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
792 | 19f329ad | blueswir1 | { |
793 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
794 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
795 | 0425bee5 | blueswir1 | tcg_gen_xor_tl(dst, dst, cpu_tmp0); |
796 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
797 | 19f329ad | blueswir1 | } |
798 | 19f329ad | blueswir1 | |
799 | 19f329ad | blueswir1 | // 0 or 2: !FCC0
|
800 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbge(TCGv dst, TCGv src, |
801 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
802 | 19f329ad | blueswir1 | { |
803 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
804 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
805 | 19f329ad | blueswir1 | } |
806 | 19f329ad | blueswir1 | |
807 | 19f329ad | blueswir1 | // !1: !(FCC0 & !FCC1)
|
808 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbuge(TCGv dst, TCGv src, |
809 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
810 | 19f329ad | blueswir1 | { |
811 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
812 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
813 | 0425bee5 | blueswir1 | tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
|
814 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
815 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
816 | 19f329ad | blueswir1 | } |
817 | 19f329ad | blueswir1 | |
818 | 19f329ad | blueswir1 | // 0 or 1: !FCC1
|
819 | 19f329ad | blueswir1 | static inline void gen_op_eval_fble(TCGv dst, TCGv src, |
820 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
821 | 19f329ad | blueswir1 | { |
822 | 19f329ad | blueswir1 | gen_mov_reg_FCC1(dst, src, fcc_offset); |
823 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
824 | 19f329ad | blueswir1 | } |
825 | 19f329ad | blueswir1 | |
826 | 19f329ad | blueswir1 | // !2: !(!FCC0 & FCC1)
|
827 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbule(TCGv dst, TCGv src, |
828 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
829 | 19f329ad | blueswir1 | { |
830 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
831 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
832 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
833 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
834 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
835 | 19f329ad | blueswir1 | } |
836 | 19f329ad | blueswir1 | |
837 | 19f329ad | blueswir1 | // !3: !(FCC0 & FCC1)
|
838 | 19f329ad | blueswir1 | static inline void gen_op_eval_fbo(TCGv dst, TCGv src, |
839 | 19f329ad | blueswir1 | unsigned int fcc_offset) |
840 | 19f329ad | blueswir1 | { |
841 | 19f329ad | blueswir1 | gen_mov_reg_FCC0(dst, src, fcc_offset); |
842 | 0425bee5 | blueswir1 | gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset); |
843 | 0425bee5 | blueswir1 | tcg_gen_and_tl(dst, dst, cpu_tmp0); |
844 | 19f329ad | blueswir1 | tcg_gen_xori_tl(dst, dst, 0x1);
|
845 | 19f329ad | blueswir1 | } |
846 | 19f329ad | blueswir1 | |
847 | 46525e1f | blueswir1 | static inline void gen_branch2(DisasContext *dc, target_ulong pc1, |
848 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
849 | 83469015 | bellard | { |
850 | 83469015 | bellard | int l1;
|
851 | 83469015 | bellard | |
852 | 83469015 | bellard | l1 = gen_new_label(); |
853 | 83469015 | bellard | |
854 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
855 | 83469015 | bellard | |
856 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc1, pc1 + 4); |
857 | 83469015 | bellard | |
858 | 83469015 | bellard | gen_set_label(l1); |
859 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2, pc2 + 4); |
860 | 83469015 | bellard | } |
861 | 83469015 | bellard | |
862 | 46525e1f | blueswir1 | static inline void gen_branch_a(DisasContext *dc, target_ulong pc1, |
863 | 19f329ad | blueswir1 | target_ulong pc2, TCGv r_cond) |
864 | 83469015 | bellard | { |
865 | 83469015 | bellard | int l1;
|
866 | 83469015 | bellard | |
867 | 83469015 | bellard | l1 = gen_new_label(); |
868 | 83469015 | bellard | |
869 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
870 | 83469015 | bellard | |
871 | 6e256c93 | bellard | gen_goto_tb(dc, 0, pc2, pc1);
|
872 | 83469015 | bellard | |
873 | 83469015 | bellard | gen_set_label(l1); |
874 | 6e256c93 | bellard | gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8); |
875 | 83469015 | bellard | } |
876 | 83469015 | bellard | |
877 | 19f329ad | blueswir1 | static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, |
878 | 19f329ad | blueswir1 | TCGv r_cond) |
879 | 83469015 | bellard | { |
880 | 83469015 | bellard | int l1, l2;
|
881 | 83469015 | bellard | |
882 | 83469015 | bellard | l1 = gen_new_label(); |
883 | 83469015 | bellard | l2 = gen_new_label(); |
884 | 19f329ad | blueswir1 | |
885 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
886 | 83469015 | bellard | |
887 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc1); |
888 | 06b3e1b3 | blueswir1 | tcg_gen_br(l2); |
889 | 83469015 | bellard | |
890 | 83469015 | bellard | gen_set_label(l1); |
891 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, npc2); |
892 | 83469015 | bellard | gen_set_label(l2); |
893 | 83469015 | bellard | } |
894 | 83469015 | bellard | |
895 | 4af984a7 | blueswir1 | /* call this function before using the condition register as it may
|
896 | 4af984a7 | blueswir1 | have been set for a jump */
|
897 | 4af984a7 | blueswir1 | static inline void flush_cond(DisasContext *dc, TCGv cond) |
898 | 83469015 | bellard | { |
899 | 83469015 | bellard | if (dc->npc == JUMP_PC) {
|
900 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
901 | 83469015 | bellard | dc->npc = DYNAMIC_PC; |
902 | 83469015 | bellard | } |
903 | 83469015 | bellard | } |
904 | 83469015 | bellard | |
905 | 4af984a7 | blueswir1 | static inline void save_npc(DisasContext *dc, TCGv cond) |
906 | 72cbca10 | bellard | { |
907 | 72cbca10 | bellard | if (dc->npc == JUMP_PC) {
|
908 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
909 | 72cbca10 | bellard | dc->npc = DYNAMIC_PC; |
910 | 72cbca10 | bellard | } else if (dc->npc != DYNAMIC_PC) { |
911 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_npc, dc->npc); |
912 | 72cbca10 | bellard | } |
913 | 72cbca10 | bellard | } |
914 | 72cbca10 | bellard | |
915 | 4af984a7 | blueswir1 | static inline void save_state(DisasContext *dc, TCGv cond) |
916 | 72cbca10 | bellard | { |
917 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
918 | cfa90513 | Blue Swirl | /* flush pending conditional evaluations before exposing cpu state */
|
919 | cfa90513 | Blue Swirl | if (dc->cc_op != CC_OP_FLAGS) {
|
920 | cfa90513 | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
921 | cfa90513 | Blue Swirl | gen_helper_compute_psr(); |
922 | cfa90513 | Blue Swirl | } |
923 | 4af984a7 | blueswir1 | save_npc(dc, cond); |
924 | 72cbca10 | bellard | } |
925 | 72cbca10 | bellard | |
926 | 4af984a7 | blueswir1 | static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond) |
927 | 0bee699e | bellard | { |
928 | 0bee699e | bellard | if (dc->npc == JUMP_PC) {
|
929 | 4af984a7 | blueswir1 | gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond); |
930 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
931 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
932 | 0bee699e | bellard | } else if (dc->npc == DYNAMIC_PC) { |
933 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
934 | 0bee699e | bellard | dc->pc = DYNAMIC_PC; |
935 | 0bee699e | bellard | } else {
|
936 | 0bee699e | bellard | dc->pc = dc->npc; |
937 | 0bee699e | bellard | } |
938 | 0bee699e | bellard | } |
939 | 0bee699e | bellard | |
940 | 38bc628b | blueswir1 | static inline void gen_op_next_insn(void) |
941 | 38bc628b | blueswir1 | { |
942 | 48d5c82b | blueswir1 | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
943 | 48d5c82b | blueswir1 | tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
|
944 | 38bc628b | blueswir1 | } |
945 | 38bc628b | blueswir1 | |
946 | 8393617c | Blue Swirl | static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, |
947 | 8393617c | Blue Swirl | DisasContext *dc) |
948 | 19f329ad | blueswir1 | { |
949 | a7812ae4 | pbrook | TCGv_i32 r_src; |
950 | 3475187d | bellard | |
951 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
952 | 19f329ad | blueswir1 | if (cc)
|
953 | dc99a3f2 | blueswir1 | r_src = cpu_xcc; |
954 | 19f329ad | blueswir1 | else
|
955 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
956 | 3475187d | bellard | #else
|
957 | dc99a3f2 | blueswir1 | r_src = cpu_psr; |
958 | 3475187d | bellard | #endif
|
959 | 8393617c | Blue Swirl | switch (dc->cc_op) {
|
960 | 8393617c | Blue Swirl | case CC_OP_FLAGS:
|
961 | 8393617c | Blue Swirl | break;
|
962 | 8393617c | Blue Swirl | default:
|
963 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
964 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
965 | 8393617c | Blue Swirl | break;
|
966 | 8393617c | Blue Swirl | } |
967 | 19f329ad | blueswir1 | switch (cond) {
|
968 | 19f329ad | blueswir1 | case 0x0: |
969 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
970 | 19f329ad | blueswir1 | break;
|
971 | 19f329ad | blueswir1 | case 0x1: |
972 | 19f329ad | blueswir1 | gen_op_eval_be(r_dst, r_src); |
973 | 19f329ad | blueswir1 | break;
|
974 | 19f329ad | blueswir1 | case 0x2: |
975 | 19f329ad | blueswir1 | gen_op_eval_ble(r_dst, r_src); |
976 | 19f329ad | blueswir1 | break;
|
977 | 19f329ad | blueswir1 | case 0x3: |
978 | 19f329ad | blueswir1 | gen_op_eval_bl(r_dst, r_src); |
979 | 19f329ad | blueswir1 | break;
|
980 | 19f329ad | blueswir1 | case 0x4: |
981 | 19f329ad | blueswir1 | gen_op_eval_bleu(r_dst, r_src); |
982 | 19f329ad | blueswir1 | break;
|
983 | 19f329ad | blueswir1 | case 0x5: |
984 | 19f329ad | blueswir1 | gen_op_eval_bcs(r_dst, r_src); |
985 | 19f329ad | blueswir1 | break;
|
986 | 19f329ad | blueswir1 | case 0x6: |
987 | 19f329ad | blueswir1 | gen_op_eval_bneg(r_dst, r_src); |
988 | 19f329ad | blueswir1 | break;
|
989 | 19f329ad | blueswir1 | case 0x7: |
990 | 19f329ad | blueswir1 | gen_op_eval_bvs(r_dst, r_src); |
991 | 19f329ad | blueswir1 | break;
|
992 | 19f329ad | blueswir1 | case 0x8: |
993 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
994 | 19f329ad | blueswir1 | break;
|
995 | 19f329ad | blueswir1 | case 0x9: |
996 | 19f329ad | blueswir1 | gen_op_eval_bne(r_dst, r_src); |
997 | 19f329ad | blueswir1 | break;
|
998 | 19f329ad | blueswir1 | case 0xa: |
999 | 19f329ad | blueswir1 | gen_op_eval_bg(r_dst, r_src); |
1000 | 19f329ad | blueswir1 | break;
|
1001 | 19f329ad | blueswir1 | case 0xb: |
1002 | 19f329ad | blueswir1 | gen_op_eval_bge(r_dst, r_src); |
1003 | 19f329ad | blueswir1 | break;
|
1004 | 19f329ad | blueswir1 | case 0xc: |
1005 | 19f329ad | blueswir1 | gen_op_eval_bgu(r_dst, r_src); |
1006 | 19f329ad | blueswir1 | break;
|
1007 | 19f329ad | blueswir1 | case 0xd: |
1008 | 19f329ad | blueswir1 | gen_op_eval_bcc(r_dst, r_src); |
1009 | 19f329ad | blueswir1 | break;
|
1010 | 19f329ad | blueswir1 | case 0xe: |
1011 | 19f329ad | blueswir1 | gen_op_eval_bpos(r_dst, r_src); |
1012 | 19f329ad | blueswir1 | break;
|
1013 | 19f329ad | blueswir1 | case 0xf: |
1014 | 19f329ad | blueswir1 | gen_op_eval_bvc(r_dst, r_src); |
1015 | 19f329ad | blueswir1 | break;
|
1016 | 19f329ad | blueswir1 | } |
1017 | 19f329ad | blueswir1 | } |
1018 | 7a3f1944 | bellard | |
1019 | 19f329ad | blueswir1 | static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) |
1020 | e8af50a3 | bellard | { |
1021 | 19f329ad | blueswir1 | unsigned int offset; |
1022 | 19f329ad | blueswir1 | |
1023 | 19f329ad | blueswir1 | switch (cc) {
|
1024 | 19f329ad | blueswir1 | default:
|
1025 | 19f329ad | blueswir1 | case 0x0: |
1026 | 19f329ad | blueswir1 | offset = 0;
|
1027 | 19f329ad | blueswir1 | break;
|
1028 | 19f329ad | blueswir1 | case 0x1: |
1029 | 19f329ad | blueswir1 | offset = 32 - 10; |
1030 | 19f329ad | blueswir1 | break;
|
1031 | 19f329ad | blueswir1 | case 0x2: |
1032 | 19f329ad | blueswir1 | offset = 34 - 10; |
1033 | 19f329ad | blueswir1 | break;
|
1034 | 19f329ad | blueswir1 | case 0x3: |
1035 | 19f329ad | blueswir1 | offset = 36 - 10; |
1036 | 19f329ad | blueswir1 | break;
|
1037 | 19f329ad | blueswir1 | } |
1038 | 19f329ad | blueswir1 | |
1039 | 19f329ad | blueswir1 | switch (cond) {
|
1040 | 19f329ad | blueswir1 | case 0x0: |
1041 | 19f329ad | blueswir1 | gen_op_eval_bn(r_dst); |
1042 | 19f329ad | blueswir1 | break;
|
1043 | 19f329ad | blueswir1 | case 0x1: |
1044 | 87e92502 | blueswir1 | gen_op_eval_fbne(r_dst, cpu_fsr, offset); |
1045 | 19f329ad | blueswir1 | break;
|
1046 | 19f329ad | blueswir1 | case 0x2: |
1047 | 87e92502 | blueswir1 | gen_op_eval_fblg(r_dst, cpu_fsr, offset); |
1048 | 19f329ad | blueswir1 | break;
|
1049 | 19f329ad | blueswir1 | case 0x3: |
1050 | 87e92502 | blueswir1 | gen_op_eval_fbul(r_dst, cpu_fsr, offset); |
1051 | 19f329ad | blueswir1 | break;
|
1052 | 19f329ad | blueswir1 | case 0x4: |
1053 | 87e92502 | blueswir1 | gen_op_eval_fbl(r_dst, cpu_fsr, offset); |
1054 | 19f329ad | blueswir1 | break;
|
1055 | 19f329ad | blueswir1 | case 0x5: |
1056 | 87e92502 | blueswir1 | gen_op_eval_fbug(r_dst, cpu_fsr, offset); |
1057 | 19f329ad | blueswir1 | break;
|
1058 | 19f329ad | blueswir1 | case 0x6: |
1059 | 87e92502 | blueswir1 | gen_op_eval_fbg(r_dst, cpu_fsr, offset); |
1060 | 19f329ad | blueswir1 | break;
|
1061 | 19f329ad | blueswir1 | case 0x7: |
1062 | 87e92502 | blueswir1 | gen_op_eval_fbu(r_dst, cpu_fsr, offset); |
1063 | 19f329ad | blueswir1 | break;
|
1064 | 19f329ad | blueswir1 | case 0x8: |
1065 | 19f329ad | blueswir1 | gen_op_eval_ba(r_dst); |
1066 | 19f329ad | blueswir1 | break;
|
1067 | 19f329ad | blueswir1 | case 0x9: |
1068 | 87e92502 | blueswir1 | gen_op_eval_fbe(r_dst, cpu_fsr, offset); |
1069 | 19f329ad | blueswir1 | break;
|
1070 | 19f329ad | blueswir1 | case 0xa: |
1071 | 87e92502 | blueswir1 | gen_op_eval_fbue(r_dst, cpu_fsr, offset); |
1072 | 19f329ad | blueswir1 | break;
|
1073 | 19f329ad | blueswir1 | case 0xb: |
1074 | 87e92502 | blueswir1 | gen_op_eval_fbge(r_dst, cpu_fsr, offset); |
1075 | 19f329ad | blueswir1 | break;
|
1076 | 19f329ad | blueswir1 | case 0xc: |
1077 | 87e92502 | blueswir1 | gen_op_eval_fbuge(r_dst, cpu_fsr, offset); |
1078 | 19f329ad | blueswir1 | break;
|
1079 | 19f329ad | blueswir1 | case 0xd: |
1080 | 87e92502 | blueswir1 | gen_op_eval_fble(r_dst, cpu_fsr, offset); |
1081 | 19f329ad | blueswir1 | break;
|
1082 | 19f329ad | blueswir1 | case 0xe: |
1083 | 87e92502 | blueswir1 | gen_op_eval_fbule(r_dst, cpu_fsr, offset); |
1084 | 19f329ad | blueswir1 | break;
|
1085 | 19f329ad | blueswir1 | case 0xf: |
1086 | 87e92502 | blueswir1 | gen_op_eval_fbo(r_dst, cpu_fsr, offset); |
1087 | 19f329ad | blueswir1 | break;
|
1088 | 19f329ad | blueswir1 | } |
1089 | e8af50a3 | bellard | } |
1090 | 00f219bf | blueswir1 | |
1091 | 19f329ad | blueswir1 | #ifdef TARGET_SPARC64
|
1092 | 00f219bf | blueswir1 | // Inverted logic
|
1093 | 00f219bf | blueswir1 | static const int gen_tcg_cond_reg[8] = { |
1094 | 00f219bf | blueswir1 | -1,
|
1095 | 00f219bf | blueswir1 | TCG_COND_NE, |
1096 | 00f219bf | blueswir1 | TCG_COND_GT, |
1097 | 00f219bf | blueswir1 | TCG_COND_GE, |
1098 | 00f219bf | blueswir1 | -1,
|
1099 | 00f219bf | blueswir1 | TCG_COND_EQ, |
1100 | 00f219bf | blueswir1 | TCG_COND_LE, |
1101 | 00f219bf | blueswir1 | TCG_COND_LT, |
1102 | 00f219bf | blueswir1 | }; |
1103 | 19f329ad | blueswir1 | |
1104 | 4af984a7 | blueswir1 | static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) |
1105 | 19f329ad | blueswir1 | { |
1106 | 19f329ad | blueswir1 | int l1;
|
1107 | 19f329ad | blueswir1 | |
1108 | 19f329ad | blueswir1 | l1 = gen_new_label(); |
1109 | 0425bee5 | blueswir1 | tcg_gen_movi_tl(r_dst, 0);
|
1110 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
|
1111 | 19f329ad | blueswir1 | tcg_gen_movi_tl(r_dst, 1);
|
1112 | 19f329ad | blueswir1 | gen_set_label(l1); |
1113 | 19f329ad | blueswir1 | } |
1114 | 3475187d | bellard | #endif
|
1115 | cf495bcf | bellard | |
1116 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1117 | 4af984a7 | blueswir1 | static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1118 | 4af984a7 | blueswir1 | TCGv r_cond) |
1119 | 7a3f1944 | bellard | { |
1120 | cf495bcf | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1121 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1122 | 5fafdf24 | ths | |
1123 | cf495bcf | bellard | if (cond == 0x0) { |
1124 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1125 | 0f8a249a | blueswir1 | if (a) {
|
1126 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1127 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1128 | 0f8a249a | blueswir1 | } else {
|
1129 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1130 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1131 | 0f8a249a | blueswir1 | } |
1132 | cf495bcf | bellard | } else if (cond == 0x8) { |
1133 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1134 | 0f8a249a | blueswir1 | if (a) {
|
1135 | 0f8a249a | blueswir1 | dc->pc = target; |
1136 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1137 | 0f8a249a | blueswir1 | } else {
|
1138 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1139 | 0f8a249a | blueswir1 | dc->npc = target; |
1140 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1141 | 0f8a249a | blueswir1 | } |
1142 | cf495bcf | bellard | } else {
|
1143 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1144 | 8393617c | Blue Swirl | gen_cond(r_cond, cc, cond, dc); |
1145 | 0f8a249a | blueswir1 | if (a) {
|
1146 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1147 | cf495bcf | bellard | dc->is_br = 1;
|
1148 | 0f8a249a | blueswir1 | } else {
|
1149 | cf495bcf | bellard | dc->pc = dc->npc; |
1150 | 72cbca10 | bellard | dc->jump_pc[0] = target;
|
1151 | 72cbca10 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1152 | 72cbca10 | bellard | dc->npc = JUMP_PC; |
1153 | 0f8a249a | blueswir1 | } |
1154 | cf495bcf | bellard | } |
1155 | 7a3f1944 | bellard | } |
1156 | 7a3f1944 | bellard | |
1157 | 0bee699e | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1158 | 4af984a7 | blueswir1 | static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc, |
1159 | 4af984a7 | blueswir1 | TCGv r_cond) |
1160 | e8af50a3 | bellard | { |
1161 | e8af50a3 | bellard | unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); |
1162 | af7bf89b | bellard | target_ulong target = dc->pc + offset; |
1163 | af7bf89b | bellard | |
1164 | e8af50a3 | bellard | if (cond == 0x0) { |
1165 | 0f8a249a | blueswir1 | /* unconditional not taken */
|
1166 | 0f8a249a | blueswir1 | if (a) {
|
1167 | 0f8a249a | blueswir1 | dc->pc = dc->npc + 4;
|
1168 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1169 | 0f8a249a | blueswir1 | } else {
|
1170 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1171 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1172 | 0f8a249a | blueswir1 | } |
1173 | e8af50a3 | bellard | } else if (cond == 0x8) { |
1174 | 0f8a249a | blueswir1 | /* unconditional taken */
|
1175 | 0f8a249a | blueswir1 | if (a) {
|
1176 | 0f8a249a | blueswir1 | dc->pc = target; |
1177 | 0f8a249a | blueswir1 | dc->npc = dc->pc + 4;
|
1178 | 0f8a249a | blueswir1 | } else {
|
1179 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1180 | 0f8a249a | blueswir1 | dc->npc = target; |
1181 | c27e2752 | Blue Swirl | tcg_gen_mov_tl(cpu_pc, cpu_npc); |
1182 | 0f8a249a | blueswir1 | } |
1183 | e8af50a3 | bellard | } else {
|
1184 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1185 | 4af984a7 | blueswir1 | gen_fcond(r_cond, cc, cond); |
1186 | 0f8a249a | blueswir1 | if (a) {
|
1187 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1188 | e8af50a3 | bellard | dc->is_br = 1;
|
1189 | 0f8a249a | blueswir1 | } else {
|
1190 | e8af50a3 | bellard | dc->pc = dc->npc; |
1191 | e8af50a3 | bellard | dc->jump_pc[0] = target;
|
1192 | e8af50a3 | bellard | dc->jump_pc[1] = dc->npc + 4; |
1193 | e8af50a3 | bellard | dc->npc = JUMP_PC; |
1194 | 0f8a249a | blueswir1 | } |
1195 | e8af50a3 | bellard | } |
1196 | e8af50a3 | bellard | } |
1197 | e8af50a3 | bellard | |
1198 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1199 | 3475187d | bellard | /* XXX: potentially incorrect if dynamic npc */
|
1200 | 4af984a7 | blueswir1 | static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, |
1201 | 4af984a7 | blueswir1 | TCGv r_cond, TCGv r_reg) |
1202 | 7a3f1944 | bellard | { |
1203 | 3475187d | bellard | unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); |
1204 | 3475187d | bellard | target_ulong target = dc->pc + offset; |
1205 | 3475187d | bellard | |
1206 | 4af984a7 | blueswir1 | flush_cond(dc, r_cond); |
1207 | 4af984a7 | blueswir1 | gen_cond_reg(r_cond, cond, r_reg); |
1208 | 3475187d | bellard | if (a) {
|
1209 | 4af984a7 | blueswir1 | gen_branch_a(dc, target, dc->npc, r_cond); |
1210 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
1211 | 3475187d | bellard | } else {
|
1212 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
1213 | 0f8a249a | blueswir1 | dc->jump_pc[0] = target;
|
1214 | 0f8a249a | blueswir1 | dc->jump_pc[1] = dc->npc + 4; |
1215 | 0f8a249a | blueswir1 | dc->npc = JUMP_PC; |
1216 | 3475187d | bellard | } |
1217 | 7a3f1944 | bellard | } |
1218 | 7a3f1944 | bellard | |
1219 | a7812ae4 | pbrook | static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1220 | 7e8c2b6c | blueswir1 | { |
1221 | 714547bb | blueswir1 | switch (fccno) {
|
1222 | 714547bb | blueswir1 | case 0: |
1223 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1224 | 714547bb | blueswir1 | break;
|
1225 | 714547bb | blueswir1 | case 1: |
1226 | a7812ae4 | pbrook | gen_helper_fcmps_fcc1(r_rs1, r_rs2); |
1227 | 714547bb | blueswir1 | break;
|
1228 | 714547bb | blueswir1 | case 2: |
1229 | a7812ae4 | pbrook | gen_helper_fcmps_fcc2(r_rs1, r_rs2); |
1230 | 714547bb | blueswir1 | break;
|
1231 | 714547bb | blueswir1 | case 3: |
1232 | a7812ae4 | pbrook | gen_helper_fcmps_fcc3(r_rs1, r_rs2); |
1233 | 714547bb | blueswir1 | break;
|
1234 | 714547bb | blueswir1 | } |
1235 | 7e8c2b6c | blueswir1 | } |
1236 | 7e8c2b6c | blueswir1 | |
1237 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1238 | 7e8c2b6c | blueswir1 | { |
1239 | a7812ae4 | pbrook | switch (fccno) {
|
1240 | a7812ae4 | pbrook | case 0: |
1241 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1242 | a7812ae4 | pbrook | break;
|
1243 | a7812ae4 | pbrook | case 1: |
1244 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc1(); |
1245 | a7812ae4 | pbrook | break;
|
1246 | a7812ae4 | pbrook | case 2: |
1247 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc2(); |
1248 | a7812ae4 | pbrook | break;
|
1249 | a7812ae4 | pbrook | case 3: |
1250 | a7812ae4 | pbrook | gen_helper_fcmpd_fcc3(); |
1251 | a7812ae4 | pbrook | break;
|
1252 | a7812ae4 | pbrook | } |
1253 | 7e8c2b6c | blueswir1 | } |
1254 | 7e8c2b6c | blueswir1 | |
1255 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1256 | 7e8c2b6c | blueswir1 | { |
1257 | a7812ae4 | pbrook | switch (fccno) {
|
1258 | a7812ae4 | pbrook | case 0: |
1259 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1260 | a7812ae4 | pbrook | break;
|
1261 | a7812ae4 | pbrook | case 1: |
1262 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc1(); |
1263 | a7812ae4 | pbrook | break;
|
1264 | a7812ae4 | pbrook | case 2: |
1265 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc2(); |
1266 | a7812ae4 | pbrook | break;
|
1267 | a7812ae4 | pbrook | case 3: |
1268 | a7812ae4 | pbrook | gen_helper_fcmpq_fcc3(); |
1269 | a7812ae4 | pbrook | break;
|
1270 | a7812ae4 | pbrook | } |
1271 | 7e8c2b6c | blueswir1 | } |
1272 | 7e8c2b6c | blueswir1 | |
1273 | a7812ae4 | pbrook | static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) |
1274 | 7e8c2b6c | blueswir1 | { |
1275 | 714547bb | blueswir1 | switch (fccno) {
|
1276 | 714547bb | blueswir1 | case 0: |
1277 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1278 | 714547bb | blueswir1 | break;
|
1279 | 714547bb | blueswir1 | case 1: |
1280 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc1(r_rs1, r_rs2); |
1281 | 714547bb | blueswir1 | break;
|
1282 | 714547bb | blueswir1 | case 2: |
1283 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc2(r_rs1, r_rs2); |
1284 | 714547bb | blueswir1 | break;
|
1285 | 714547bb | blueswir1 | case 3: |
1286 | a7812ae4 | pbrook | gen_helper_fcmpes_fcc3(r_rs1, r_rs2); |
1287 | 714547bb | blueswir1 | break;
|
1288 | 714547bb | blueswir1 | } |
1289 | 7e8c2b6c | blueswir1 | } |
1290 | 7e8c2b6c | blueswir1 | |
1291 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1292 | 7e8c2b6c | blueswir1 | { |
1293 | a7812ae4 | pbrook | switch (fccno) {
|
1294 | a7812ae4 | pbrook | case 0: |
1295 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1296 | a7812ae4 | pbrook | break;
|
1297 | a7812ae4 | pbrook | case 1: |
1298 | a7812ae4 | pbrook | gen_helper_fcmped_fcc1(); |
1299 | a7812ae4 | pbrook | break;
|
1300 | a7812ae4 | pbrook | case 2: |
1301 | a7812ae4 | pbrook | gen_helper_fcmped_fcc2(); |
1302 | a7812ae4 | pbrook | break;
|
1303 | a7812ae4 | pbrook | case 3: |
1304 | a7812ae4 | pbrook | gen_helper_fcmped_fcc3(); |
1305 | a7812ae4 | pbrook | break;
|
1306 | a7812ae4 | pbrook | } |
1307 | 7e8c2b6c | blueswir1 | } |
1308 | 7e8c2b6c | blueswir1 | |
1309 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1310 | 7e8c2b6c | blueswir1 | { |
1311 | a7812ae4 | pbrook | switch (fccno) {
|
1312 | a7812ae4 | pbrook | case 0: |
1313 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1314 | a7812ae4 | pbrook | break;
|
1315 | a7812ae4 | pbrook | case 1: |
1316 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc1(); |
1317 | a7812ae4 | pbrook | break;
|
1318 | a7812ae4 | pbrook | case 2: |
1319 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc2(); |
1320 | a7812ae4 | pbrook | break;
|
1321 | a7812ae4 | pbrook | case 3: |
1322 | a7812ae4 | pbrook | gen_helper_fcmpeq_fcc3(); |
1323 | a7812ae4 | pbrook | break;
|
1324 | a7812ae4 | pbrook | } |
1325 | 7e8c2b6c | blueswir1 | } |
1326 | 7e8c2b6c | blueswir1 | |
1327 | 7e8c2b6c | blueswir1 | #else
|
1328 | 7e8c2b6c | blueswir1 | |
1329 | 714547bb | blueswir1 | static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) |
1330 | 7e8c2b6c | blueswir1 | { |
1331 | a7812ae4 | pbrook | gen_helper_fcmps(r_rs1, r_rs2); |
1332 | 7e8c2b6c | blueswir1 | } |
1333 | 7e8c2b6c | blueswir1 | |
1334 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpd(int fccno) |
1335 | 7e8c2b6c | blueswir1 | { |
1336 | a7812ae4 | pbrook | gen_helper_fcmpd(); |
1337 | 7e8c2b6c | blueswir1 | } |
1338 | 7e8c2b6c | blueswir1 | |
1339 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpq(int fccno) |
1340 | 7e8c2b6c | blueswir1 | { |
1341 | a7812ae4 | pbrook | gen_helper_fcmpq(); |
1342 | 7e8c2b6c | blueswir1 | } |
1343 | 7e8c2b6c | blueswir1 | |
1344 | 714547bb | blueswir1 | static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) |
1345 | 7e8c2b6c | blueswir1 | { |
1346 | a7812ae4 | pbrook | gen_helper_fcmpes(r_rs1, r_rs2); |
1347 | 7e8c2b6c | blueswir1 | } |
1348 | 7e8c2b6c | blueswir1 | |
1349 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmped(int fccno) |
1350 | 7e8c2b6c | blueswir1 | { |
1351 | a7812ae4 | pbrook | gen_helper_fcmped(); |
1352 | 7e8c2b6c | blueswir1 | } |
1353 | 7e8c2b6c | blueswir1 | |
1354 | 7e8c2b6c | blueswir1 | static inline void gen_op_fcmpeq(int fccno) |
1355 | 7e8c2b6c | blueswir1 | { |
1356 | a7812ae4 | pbrook | gen_helper_fcmpeq(); |
1357 | 7e8c2b6c | blueswir1 | } |
1358 | 7e8c2b6c | blueswir1 | #endif
|
1359 | 7e8c2b6c | blueswir1 | |
1360 | 134d77a1 | blueswir1 | static inline void gen_op_fpexception_im(int fsr_flags) |
1361 | 134d77a1 | blueswir1 | { |
1362 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1363 | 2ea815ca | blueswir1 | |
1364 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); |
1365 | 87e92502 | blueswir1 | tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); |
1366 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_FP_EXCP); |
1367 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1368 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1369 | 134d77a1 | blueswir1 | } |
1370 | 134d77a1 | blueswir1 | |
1371 | 4af984a7 | blueswir1 | static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) |
1372 | a80dde08 | bellard | { |
1373 | a80dde08 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1374 | a80dde08 | bellard | if (!dc->fpu_enabled) {
|
1375 | a7812ae4 | pbrook | TCGv_i32 r_const; |
1376 | 2ea815ca | blueswir1 | |
1377 | 4af984a7 | blueswir1 | save_state(dc, r_cond); |
1378 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NFPU_INSN); |
1379 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
1380 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
1381 | a80dde08 | bellard | dc->is_br = 1;
|
1382 | a80dde08 | bellard | return 1; |
1383 | a80dde08 | bellard | } |
1384 | a80dde08 | bellard | #endif
|
1385 | a80dde08 | bellard | return 0; |
1386 | a80dde08 | bellard | } |
1387 | a80dde08 | bellard | |
1388 | 7e8c2b6c | blueswir1 | static inline void gen_op_clear_ieee_excp_and_FTT(void) |
1389 | 7e8c2b6c | blueswir1 | { |
1390 | 47ad35f1 | blueswir1 | tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); |
1391 | 7e8c2b6c | blueswir1 | } |
1392 | 7e8c2b6c | blueswir1 | |
1393 | 7e8c2b6c | blueswir1 | static inline void gen_clear_float_exceptions(void) |
1394 | 7e8c2b6c | blueswir1 | { |
1395 | a7812ae4 | pbrook | gen_helper_clear_float_exceptions(); |
1396 | 7e8c2b6c | blueswir1 | } |
1397 | 7e8c2b6c | blueswir1 | |
1398 | 1a2fb1c0 | blueswir1 | /* asi moves */
|
1399 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
1400 | a7812ae4 | pbrook | static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr) |
1401 | 1a2fb1c0 | blueswir1 | { |
1402 | 95f9397c | blueswir1 | int asi;
|
1403 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1404 | 1a2fb1c0 | blueswir1 | |
1405 | 1a2fb1c0 | blueswir1 | if (IS_IMM) {
|
1406 | a7812ae4 | pbrook | r_asi = tcg_temp_new_i32(); |
1407 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(r_asi, cpu_asi); |
1408 | 1a2fb1c0 | blueswir1 | } else {
|
1409 | 1a2fb1c0 | blueswir1 | asi = GET_FIELD(insn, 19, 26); |
1410 | 0425bee5 | blueswir1 | r_asi = tcg_const_i32(asi); |
1411 | 1a2fb1c0 | blueswir1 | } |
1412 | 0425bee5 | blueswir1 | return r_asi;
|
1413 | 0425bee5 | blueswir1 | } |
1414 | 0425bee5 | blueswir1 | |
1415 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1416 | 77f193da | blueswir1 | int sign)
|
1417 | 0425bee5 | blueswir1 | { |
1418 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1419 | 0425bee5 | blueswir1 | |
1420 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1421 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1422 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1423 | a7812ae4 | pbrook | gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign); |
1424 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1425 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1426 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1427 | 1a2fb1c0 | blueswir1 | } |
1428 | 1a2fb1c0 | blueswir1 | |
1429 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1430 | 1a2fb1c0 | blueswir1 | { |
1431 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1432 | 1a2fb1c0 | blueswir1 | |
1433 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1434 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1435 | a7812ae4 | pbrook | gen_helper_st_asi(addr, src, r_asi, r_size); |
1436 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1437 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1438 | 1a2fb1c0 | blueswir1 | } |
1439 | 1a2fb1c0 | blueswir1 | |
1440 | 4af984a7 | blueswir1 | static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) |
1441 | 1a2fb1c0 | blueswir1 | { |
1442 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1443 | 1a2fb1c0 | blueswir1 | |
1444 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1445 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1446 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1447 | a7812ae4 | pbrook | gen_helper_ldf_asi(addr, r_asi, r_size, r_rd); |
1448 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1449 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1450 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1451 | 1a2fb1c0 | blueswir1 | } |
1452 | 1a2fb1c0 | blueswir1 | |
1453 | 4af984a7 | blueswir1 | static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) |
1454 | 1a2fb1c0 | blueswir1 | { |
1455 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_rd; |
1456 | 1a2fb1c0 | blueswir1 | |
1457 | 31741a27 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1458 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1459 | 2ea815ca | blueswir1 | r_rd = tcg_const_i32(rd); |
1460 | a7812ae4 | pbrook | gen_helper_stf_asi(addr, r_asi, r_size, r_rd); |
1461 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1462 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1463 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1464 | 1a2fb1c0 | blueswir1 | } |
1465 | 1a2fb1c0 | blueswir1 | |
1466 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1467 | 1a2fb1c0 | blueswir1 | { |
1468 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1469 | 1a2fb1c0 | blueswir1 | |
1470 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1471 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1472 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1473 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1474 | a7812ae4 | pbrook | tcg_temp_free_i32(r_sign); |
1475 | a7812ae4 | pbrook | gen_helper_st_asi(addr, dst, r_asi, r_size); |
1476 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1477 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1478 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1479 | 1a2fb1c0 | blueswir1 | } |
1480 | 1a2fb1c0 | blueswir1 | |
1481 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1482 | 1a2fb1c0 | blueswir1 | { |
1483 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_rd; |
1484 | 1a2fb1c0 | blueswir1 | |
1485 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1486 | db166940 | blueswir1 | r_rd = tcg_const_i32(rd); |
1487 | a7812ae4 | pbrook | gen_helper_ldda_asi(addr, r_asi, r_rd); |
1488 | a7812ae4 | pbrook | tcg_temp_free_i32(r_rd); |
1489 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1490 | 0425bee5 | blueswir1 | } |
1491 | 0425bee5 | blueswir1 | |
1492 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1493 | 0425bee5 | blueswir1 | { |
1494 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1495 | a7ec4229 | blueswir1 | |
1496 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1497 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1498 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1499 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1500 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1501 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1502 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1503 | 1a2fb1c0 | blueswir1 | } |
1504 | 1a2fb1c0 | blueswir1 | |
1505 | 77f193da | blueswir1 | static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1506 | 77f193da | blueswir1 | int rd)
|
1507 | 1a2fb1c0 | blueswir1 | { |
1508 | a7812ae4 | pbrook | TCGv r_val1; |
1509 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1510 | 1a2fb1c0 | blueswir1 | |
1511 | a7812ae4 | pbrook | r_val1 = tcg_temp_new(); |
1512 | 1a2fb1c0 | blueswir1 | gen_movl_reg_TN(rd, r_val1); |
1513 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1514 | a7812ae4 | pbrook | gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi); |
1515 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1516 | 2ea815ca | blueswir1 | tcg_temp_free(r_val1); |
1517 | 1a2fb1c0 | blueswir1 | } |
1518 | 1a2fb1c0 | blueswir1 | |
1519 | 77f193da | blueswir1 | static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, |
1520 | 77f193da | blueswir1 | int rd)
|
1521 | 1a2fb1c0 | blueswir1 | { |
1522 | a7812ae4 | pbrook | TCGv_i32 r_asi; |
1523 | 1a2fb1c0 | blueswir1 | |
1524 | 8911f501 | blueswir1 | gen_movl_reg_TN(rd, cpu_tmp64); |
1525 | 4af984a7 | blueswir1 | r_asi = gen_get_asi(insn, addr); |
1526 | a7812ae4 | pbrook | gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi); |
1527 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1528 | 1a2fb1c0 | blueswir1 | } |
1529 | 1a2fb1c0 | blueswir1 | |
1530 | 1a2fb1c0 | blueswir1 | #elif !defined(CONFIG_USER_ONLY)
|
1531 | 1a2fb1c0 | blueswir1 | |
1532 | 77f193da | blueswir1 | static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, |
1533 | 77f193da | blueswir1 | int sign)
|
1534 | 1a2fb1c0 | blueswir1 | { |
1535 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1536 | 1a2fb1c0 | blueswir1 | |
1537 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1538 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1539 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(sign); |
1540 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1541 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1542 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1543 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1544 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1545 | 1a2fb1c0 | blueswir1 | } |
1546 | 1a2fb1c0 | blueswir1 | |
1547 | 4af984a7 | blueswir1 | static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) |
1548 | 1a2fb1c0 | blueswir1 | { |
1549 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1550 | 1a2fb1c0 | blueswir1 | |
1551 | 4af984a7 | blueswir1 | tcg_gen_extu_tl_i64(cpu_tmp64, src); |
1552 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1553 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(size); |
1554 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1555 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1556 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1557 | 1a2fb1c0 | blueswir1 | } |
1558 | 1a2fb1c0 | blueswir1 | |
1559 | 4af984a7 | blueswir1 | static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) |
1560 | 1a2fb1c0 | blueswir1 | { |
1561 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1562 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1563 | 1a2fb1c0 | blueswir1 | |
1564 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1565 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(4);
|
1566 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1567 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1568 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1569 | a7812ae4 | pbrook | r_val = tcg_temp_new_i64(); |
1570 | a7812ae4 | pbrook | tcg_gen_extu_tl_i64(r_val, dst); |
1571 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1572 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1573 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1574 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1575 | 8d96d209 | blueswir1 | tcg_gen_trunc_i64_tl(dst, cpu_tmp64); |
1576 | 1a2fb1c0 | blueswir1 | } |
1577 | 1a2fb1c0 | blueswir1 | |
1578 | db166940 | blueswir1 | static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1579 | 1a2fb1c0 | blueswir1 | { |
1580 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size, r_sign; |
1581 | 1a2fb1c0 | blueswir1 | |
1582 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1583 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1584 | 2ea815ca | blueswir1 | r_sign = tcg_const_i32(0);
|
1585 | a7812ae4 | pbrook | gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); |
1586 | 2ea815ca | blueswir1 | tcg_temp_free(r_sign); |
1587 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1588 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1589 | db166940 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
1590 | db166940 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
1591 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
1592 | 4af984a7 | blueswir1 | tcg_gen_trunc_i64_tl(hi, cpu_tmp64); |
1593 | db166940 | blueswir1 | gen_movl_TN_reg(rd, hi); |
1594 | 0425bee5 | blueswir1 | } |
1595 | 0425bee5 | blueswir1 | |
1596 | 4af984a7 | blueswir1 | static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) |
1597 | 0425bee5 | blueswir1 | { |
1598 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1599 | a7ec4229 | blueswir1 | |
1600 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
1601 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); |
1602 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1603 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(8);
|
1604 | a7812ae4 | pbrook | gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); |
1605 | 2ea815ca | blueswir1 | tcg_temp_free(r_size); |
1606 | 2ea815ca | blueswir1 | tcg_temp_free(r_asi); |
1607 | 1a2fb1c0 | blueswir1 | } |
1608 | 1a2fb1c0 | blueswir1 | #endif
|
1609 | 1a2fb1c0 | blueswir1 | |
1610 | 1a2fb1c0 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
1611 | 4af984a7 | blueswir1 | static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) |
1612 | 1a2fb1c0 | blueswir1 | { |
1613 | a7812ae4 | pbrook | TCGv_i64 r_val; |
1614 | a7812ae4 | pbrook | TCGv_i32 r_asi, r_size; |
1615 | 1a2fb1c0 | blueswir1 | |
1616 | 4af984a7 | blueswir1 | gen_ld_asi(dst, addr, insn, 1, 0); |
1617 | 1a2fb1c0 | blueswir1 | |
1618 | 2ea815ca | blueswir1 | r_val = tcg_const_i64(0xffULL);
|
1619 | 2ea815ca | blueswir1 | r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); |
1620 | 2ea815ca | blueswir1 | r_size = tcg_const_i32(1);
|
1621 | a7812ae4 | pbrook | gen_helper_st_asi(addr, r_val, r_asi, r_size); |
1622 | a7812ae4 | pbrook | tcg_temp_free_i32(r_size); |
1623 | a7812ae4 | pbrook | tcg_temp_free_i32(r_asi); |
1624 | a7812ae4 | pbrook | tcg_temp_free_i64(r_val); |
1625 | 1a2fb1c0 | blueswir1 | } |
1626 | 1a2fb1c0 | blueswir1 | #endif
|
1627 | 1a2fb1c0 | blueswir1 | |
1628 | 9322a4bf | blueswir1 | static inline TCGv get_src1(unsigned int insn, TCGv def) |
1629 | 9322a4bf | blueswir1 | { |
1630 | 9322a4bf | blueswir1 | TCGv r_rs1 = def; |
1631 | 9322a4bf | blueswir1 | unsigned int rs1; |
1632 | 9322a4bf | blueswir1 | |
1633 | 9322a4bf | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1634 | 9322a4bf | blueswir1 | if (rs1 == 0) |
1635 | 5c6a0628 | blueswir1 | r_rs1 = tcg_const_tl(0); // XXX how to free? |
1636 | 9322a4bf | blueswir1 | else if (rs1 < 8) |
1637 | 5c6a0628 | blueswir1 | r_rs1 = cpu_gregs[rs1]; |
1638 | 9322a4bf | blueswir1 | else
|
1639 | 9322a4bf | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong)); |
1640 | 9322a4bf | blueswir1 | return r_rs1;
|
1641 | 9322a4bf | blueswir1 | } |
1642 | 9322a4bf | blueswir1 | |
1643 | a49d9390 | blueswir1 | static inline TCGv get_src2(unsigned int insn, TCGv def) |
1644 | a49d9390 | blueswir1 | { |
1645 | a49d9390 | blueswir1 | TCGv r_rs2 = def; |
1646 | a49d9390 | blueswir1 | |
1647 | a49d9390 | blueswir1 | if (IS_IMM) { /* immediate */ |
1648 | 67526b20 | Blue Swirl | target_long simm; |
1649 | 67526b20 | Blue Swirl | |
1650 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
1651 | 67526b20 | Blue Swirl | r_rs2 = tcg_const_tl(simm); // XXX how to free?
|
1652 | a49d9390 | blueswir1 | } else { /* register */ |
1653 | 67526b20 | Blue Swirl | unsigned int rs2; |
1654 | 67526b20 | Blue Swirl | |
1655 | a49d9390 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
1656 | a49d9390 | blueswir1 | if (rs2 == 0) |
1657 | 2ea815ca | blueswir1 | r_rs2 = tcg_const_tl(0); // XXX how to free? |
1658 | a49d9390 | blueswir1 | else if (rs2 < 8) |
1659 | a49d9390 | blueswir1 | r_rs2 = cpu_gregs[rs2]; |
1660 | a49d9390 | blueswir1 | else
|
1661 | a49d9390 | blueswir1 | tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong)); |
1662 | a49d9390 | blueswir1 | } |
1663 | a49d9390 | blueswir1 | return r_rs2;
|
1664 | a49d9390 | blueswir1 | } |
1665 | a49d9390 | blueswir1 | |
1666 | 8194f35a | Igor Kovalenko | #ifdef TARGET_SPARC64
|
1667 | 8194f35a | Igor Kovalenko | static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env) |
1668 | 8194f35a | Igor Kovalenko | { |
1669 | b551ec04 | Jay Foad | TCGv_i32 r_tl = tcg_temp_new_i32(); |
1670 | 8194f35a | Igor Kovalenko | |
1671 | 8194f35a | Igor Kovalenko | /* load env->tl into r_tl */
|
1672 | b551ec04 | Jay Foad | tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl)); |
1673 | 8194f35a | Igor Kovalenko | |
1674 | 8194f35a | Igor Kovalenko | /* tl = [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */
|
1675 | b551ec04 | Jay Foad | tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); |
1676 | 8194f35a | Igor Kovalenko | |
1677 | 8194f35a | Igor Kovalenko | /* calculate offset to current trap state from env->ts, reuse r_tl */
|
1678 | b551ec04 | Jay Foad | tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state));
|
1679 | 8194f35a | Igor Kovalenko | tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUState, ts)); |
1680 | 8194f35a | Igor Kovalenko | |
1681 | 8194f35a | Igor Kovalenko | /* tsptr = env->ts[env->tl & MAXTL_MASK] */
|
1682 | b551ec04 | Jay Foad | { |
1683 | b551ec04 | Jay Foad | TCGv_ptr r_tl_tmp = tcg_temp_new_ptr(); |
1684 | b551ec04 | Jay Foad | tcg_gen_ext_i32_ptr(r_tl_tmp, r_tl); |
1685 | b551ec04 | Jay Foad | tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); |
1686 | bc57c114 | Stefan Weil | tcg_temp_free_ptr(r_tl_tmp); |
1687 | b551ec04 | Jay Foad | } |
1688 | 8194f35a | Igor Kovalenko | |
1689 | b551ec04 | Jay Foad | tcg_temp_free_i32(r_tl); |
1690 | 8194f35a | Igor Kovalenko | } |
1691 | 8194f35a | Igor Kovalenko | #endif
|
1692 | 8194f35a | Igor Kovalenko | |
1693 | 64a88d5d | blueswir1 | #define CHECK_IU_FEATURE(dc, FEATURE) \
|
1694 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1695 | 64a88d5d | blueswir1 | goto illegal_insn;
|
1696 | 64a88d5d | blueswir1 | #define CHECK_FPU_FEATURE(dc, FEATURE) \
|
1697 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ |
1698 | 64a88d5d | blueswir1 | goto nfpu_insn;
|
1699 | 64a88d5d | blueswir1 | |
1700 | 0bee699e | bellard | /* before an instruction, dc->pc must be static */
|
1701 | cf495bcf | bellard | static void disas_sparc_insn(DisasContext * dc) |
1702 | cf495bcf | bellard | { |
1703 | cf495bcf | bellard | unsigned int insn, opc, rs1, rs2, rd; |
1704 | 67526b20 | Blue Swirl | target_long simm; |
1705 | 7a3f1944 | bellard | |
1706 | 8fec2b8c | aliguori | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
1707 | a8c768c0 | blueswir1 | tcg_gen_debug_insn_start(dc->pc); |
1708 | 0fa85d43 | bellard | insn = ldl_code(dc->pc); |
1709 | cf495bcf | bellard | opc = GET_FIELD(insn, 0, 1); |
1710 | 7a3f1944 | bellard | |
1711 | cf495bcf | bellard | rd = GET_FIELD(insn, 2, 6); |
1712 | 6ae20372 | blueswir1 | |
1713 | a7812ae4 | pbrook | cpu_src1 = tcg_temp_new(); // const
|
1714 | a7812ae4 | pbrook | cpu_src2 = tcg_temp_new(); // const
|
1715 | 6ae20372 | blueswir1 | |
1716 | cf495bcf | bellard | switch (opc) {
|
1717 | 0f8a249a | blueswir1 | case 0: /* branches/sethi */ |
1718 | 0f8a249a | blueswir1 | { |
1719 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 9); |
1720 | 0f8a249a | blueswir1 | int32_t target; |
1721 | 0f8a249a | blueswir1 | switch (xop) {
|
1722 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1723 | 0f8a249a | blueswir1 | case 0x1: /* V9 BPcc */ |
1724 | 0f8a249a | blueswir1 | { |
1725 | 0f8a249a | blueswir1 | int cc;
|
1726 | 0f8a249a | blueswir1 | |
1727 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1728 | 0f8a249a | blueswir1 | target = sign_extend(target, 18);
|
1729 | 0f8a249a | blueswir1 | target <<= 2;
|
1730 | 0f8a249a | blueswir1 | cc = GET_FIELD_SP(insn, 20, 21); |
1731 | 0f8a249a | blueswir1 | if (cc == 0) |
1732 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1733 | 0f8a249a | blueswir1 | else if (cc == 2) |
1734 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 1, cpu_cond);
|
1735 | 0f8a249a | blueswir1 | else
|
1736 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1737 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1738 | 0f8a249a | blueswir1 | } |
1739 | 0f8a249a | blueswir1 | case 0x3: /* V9 BPr */ |
1740 | 0f8a249a | blueswir1 | { |
1741 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 13) | |
1742 | 13846e70 | bellard | (GET_FIELD_SP(insn, 20, 21) << 14); |
1743 | 0f8a249a | blueswir1 | target = sign_extend(target, 16);
|
1744 | 0f8a249a | blueswir1 | target <<= 2;
|
1745 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1746 | 6ae20372 | blueswir1 | do_branch_reg(dc, target, insn, cpu_cond, cpu_src1); |
1747 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1748 | 0f8a249a | blueswir1 | } |
1749 | 0f8a249a | blueswir1 | case 0x5: /* V9 FBPcc */ |
1750 | 0f8a249a | blueswir1 | { |
1751 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 20, 21); |
1752 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1753 | a80dde08 | bellard | goto jmp_insn;
|
1754 | 0f8a249a | blueswir1 | target = GET_FIELD_SP(insn, 0, 18); |
1755 | 0f8a249a | blueswir1 | target = sign_extend(target, 19);
|
1756 | 0f8a249a | blueswir1 | target <<= 2;
|
1757 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, cc, cpu_cond); |
1758 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1759 | 0f8a249a | blueswir1 | } |
1760 | a4d17f19 | blueswir1 | #else
|
1761 | 0f8a249a | blueswir1 | case 0x7: /* CBN+x */ |
1762 | 0f8a249a | blueswir1 | { |
1763 | 0f8a249a | blueswir1 | goto ncp_insn;
|
1764 | 0f8a249a | blueswir1 | } |
1765 | 0f8a249a | blueswir1 | #endif
|
1766 | 0f8a249a | blueswir1 | case 0x2: /* BN+x */ |
1767 | 0f8a249a | blueswir1 | { |
1768 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1769 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1770 | 0f8a249a | blueswir1 | target <<= 2;
|
1771 | 6ae20372 | blueswir1 | do_branch(dc, target, insn, 0, cpu_cond);
|
1772 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1773 | 0f8a249a | blueswir1 | } |
1774 | 0f8a249a | blueswir1 | case 0x6: /* FBN+x */ |
1775 | 0f8a249a | blueswir1 | { |
1776 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1777 | a80dde08 | bellard | goto jmp_insn;
|
1778 | 0f8a249a | blueswir1 | target = GET_FIELD(insn, 10, 31); |
1779 | 0f8a249a | blueswir1 | target = sign_extend(target, 22);
|
1780 | 0f8a249a | blueswir1 | target <<= 2;
|
1781 | 6ae20372 | blueswir1 | do_fbranch(dc, target, insn, 0, cpu_cond);
|
1782 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1783 | 0f8a249a | blueswir1 | } |
1784 | 0f8a249a | blueswir1 | case 0x4: /* SETHI */ |
1785 | 0f8a249a | blueswir1 | if (rd) { // nop |
1786 | 0f8a249a | blueswir1 | uint32_t value = GET_FIELD(insn, 10, 31); |
1787 | 2ea815ca | blueswir1 | TCGv r_const; |
1788 | 2ea815ca | blueswir1 | |
1789 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(value << 10);
|
1790 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1791 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1792 | 0f8a249a | blueswir1 | } |
1793 | 0f8a249a | blueswir1 | break;
|
1794 | 0f8a249a | blueswir1 | case 0x0: /* UNIMPL */ |
1795 | 0f8a249a | blueswir1 | default:
|
1796 | 3475187d | bellard | goto illegal_insn;
|
1797 | 0f8a249a | blueswir1 | } |
1798 | 0f8a249a | blueswir1 | break;
|
1799 | 0f8a249a | blueswir1 | } |
1800 | 0f8a249a | blueswir1 | break;
|
1801 | dc1a6971 | Blue Swirl | case 1: /*CALL*/ |
1802 | dc1a6971 | Blue Swirl | { |
1803 | 0f8a249a | blueswir1 | target_long target = GET_FIELDs(insn, 2, 31) << 2; |
1804 | 2ea815ca | blueswir1 | TCGv r_const; |
1805 | cf495bcf | bellard | |
1806 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
1807 | 2ea815ca | blueswir1 | gen_movl_TN_reg(15, r_const);
|
1808 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1809 | 0f8a249a | blueswir1 | target += dc->pc; |
1810 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
1811 | 0f8a249a | blueswir1 | dc->npc = target; |
1812 | 0f8a249a | blueswir1 | } |
1813 | 0f8a249a | blueswir1 | goto jmp_insn;
|
1814 | 0f8a249a | blueswir1 | case 2: /* FPU & Logical Operations */ |
1815 | 0f8a249a | blueswir1 | { |
1816 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
1817 | 0f8a249a | blueswir1 | if (xop == 0x3a) { /* generate trap */ |
1818 | cf495bcf | bellard | int cond;
|
1819 | 3475187d | bellard | |
1820 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
1821 | 0f8a249a | blueswir1 | if (IS_IMM) {
|
1822 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 25, 31); |
1823 | 6ae20372 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2); |
1824 | cf495bcf | bellard | } else {
|
1825 | cf495bcf | bellard | rs2 = GET_FIELD(insn, 27, 31); |
1826 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
1827 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
1828 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
1829 | 6f551262 | blueswir1 | } else
|
1830 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
1831 | cf495bcf | bellard | } |
1832 | cf495bcf | bellard | cond = GET_FIELD(insn, 3, 6); |
1833 | cf495bcf | bellard | if (cond == 0x8) { |
1834 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1835 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
1836 | b158a785 | blueswir1 | supervisor(dc)) |
1837 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
1838 | b158a785 | blueswir1 | else
|
1839 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
1840 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
1841 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
1842 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
1843 | af7bf89b | bellard | } else if (cond != 0) { |
1844 | a7812ae4 | pbrook | TCGv r_cond = tcg_temp_new(); |
1845 | b158a785 | blueswir1 | int l1;
|
1846 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1847 | 0f8a249a | blueswir1 | /* V9 icc/xcc */
|
1848 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
1849 | 748b9d8e | blueswir1 | |
1850 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1851 | 0f8a249a | blueswir1 | if (cc == 0) |
1852 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
1853 | 0f8a249a | blueswir1 | else if (cc == 2) |
1854 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
1855 | 0f8a249a | blueswir1 | else
|
1856 | 0f8a249a | blueswir1 | goto illegal_insn;
|
1857 | 3475187d | bellard | #else
|
1858 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
1859 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
1860 | 3475187d | bellard | #endif
|
1861 | b158a785 | blueswir1 | l1 = gen_new_label(); |
1862 | b158a785 | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
1863 | b158a785 | blueswir1 | |
1864 | b158a785 | blueswir1 | if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
1865 | b158a785 | blueswir1 | supervisor(dc)) |
1866 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK); |
1867 | b158a785 | blueswir1 | else
|
1868 | b158a785 | blueswir1 | tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); |
1869 | b158a785 | blueswir1 | tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); |
1870 | a7812ae4 | pbrook | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); |
1871 | a7812ae4 | pbrook | gen_helper_raise_exception(cpu_tmp32); |
1872 | b158a785 | blueswir1 | |
1873 | b158a785 | blueswir1 | gen_set_label(l1); |
1874 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
1875 | cf495bcf | bellard | } |
1876 | a80dde08 | bellard | gen_op_next_insn(); |
1877 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1878 | a80dde08 | bellard | dc->is_br = 1;
|
1879 | a80dde08 | bellard | goto jmp_insn;
|
1880 | cf495bcf | bellard | } else if (xop == 0x28) { |
1881 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
1882 | cf495bcf | bellard | switch(rs1) {
|
1883 | cf495bcf | bellard | case 0: /* rdy */ |
1884 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
1885 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0e: /* undefined in the SPARCv8 |
1886 | 65fe7b09 | blueswir1 | manual, rdy on the microSPARC
|
1887 | 65fe7b09 | blueswir1 | II */
|
1888 | 65fe7b09 | blueswir1 | case 0x0f: /* stbar in the SPARCv8 manual, |
1889 | 65fe7b09 | blueswir1 | rdy on the microSPARC II */
|
1890 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent in the |
1891 | 65fe7b09 | blueswir1 | SPARCv8 manual, rdy on the
|
1892 | 65fe7b09 | blueswir1 | microSPARC II */
|
1893 | 65fe7b09 | blueswir1 | #endif
|
1894 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_y); |
1895 | cf495bcf | bellard | break;
|
1896 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
1897 | 0f8a249a | blueswir1 | case 0x2: /* V9 rdccr */ |
1898 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1899 | a7812ae4 | pbrook | gen_helper_rdccr(cpu_dst); |
1900 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1901 | 3475187d | bellard | break;
|
1902 | 0f8a249a | blueswir1 | case 0x3: /* V9 rdasi */ |
1903 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_asi); |
1904 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1905 | 3475187d | bellard | break;
|
1906 | 0f8a249a | blueswir1 | case 0x4: /* V9 rdtick */ |
1907 | ccd4a219 | blueswir1 | { |
1908 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
1909 | ccd4a219 | blueswir1 | |
1910 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
1911 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
1912 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
1913 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
1914 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
1915 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1916 | ccd4a219 | blueswir1 | } |
1917 | 3475187d | bellard | break;
|
1918 | 0f8a249a | blueswir1 | case 0x5: /* V9 rdpc */ |
1919 | 2ea815ca | blueswir1 | { |
1920 | 2ea815ca | blueswir1 | TCGv r_const; |
1921 | 2ea815ca | blueswir1 | |
1922 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(dc->pc); |
1923 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
1924 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
1925 | 2ea815ca | blueswir1 | } |
1926 | 0f8a249a | blueswir1 | break;
|
1927 | 0f8a249a | blueswir1 | case 0x6: /* V9 rdfprs */ |
1928 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); |
1929 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1930 | 3475187d | bellard | break;
|
1931 | 65fe7b09 | blueswir1 | case 0xf: /* V9 membar */ |
1932 | 65fe7b09 | blueswir1 | break; /* no effect */ |
1933 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
1934 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
1935 | 725cb90b | bellard | goto jmp_insn;
|
1936 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_gsr); |
1937 | 725cb90b | bellard | break;
|
1938 | 9d926598 | blueswir1 | case 0x16: /* Softint */ |
1939 | 9d926598 | blueswir1 | tcg_gen_ext_i32_tl(cpu_dst, cpu_softint); |
1940 | 9d926598 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1941 | 9d926598 | blueswir1 | break;
|
1942 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
1943 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tick_cmpr); |
1944 | 83469015 | bellard | break;
|
1945 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
1946 | ccd4a219 | blueswir1 | { |
1947 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
1948 | ccd4a219 | blueswir1 | |
1949 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
1950 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
1951 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
1952 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_dst, r_tickptr); |
1953 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
1954 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
1955 | ccd4a219 | blueswir1 | } |
1956 | 83469015 | bellard | break;
|
1957 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
1958 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_stick_cmpr); |
1959 | 83469015 | bellard | break;
|
1960 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
1961 | 0f8a249a | blueswir1 | case 0x11: /* Performance Instrumentation Counter */ |
1962 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
1963 | 0f8a249a | blueswir1 | case 0x14: /* Softint set, WO */ |
1964 | 0f8a249a | blueswir1 | case 0x15: /* Softint clear, WO */ |
1965 | 3475187d | bellard | #endif
|
1966 | 3475187d | bellard | default:
|
1967 | cf495bcf | bellard | goto illegal_insn;
|
1968 | cf495bcf | bellard | } |
1969 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1970 | e9ebed4d | blueswir1 | } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ |
1971 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
1972 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
1973 | 0f8a249a | blueswir1 | goto priv_insn;
|
1974 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
1975 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
1976 | a7812ae4 | pbrook | gen_helper_rdpsr(cpu_dst); |
1977 | e9ebed4d | blueswir1 | #else
|
1978 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
1979 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
1980 | e9ebed4d | blueswir1 | goto priv_insn;
|
1981 | e9ebed4d | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
1982 | e9ebed4d | blueswir1 | switch (rs1) {
|
1983 | e9ebed4d | blueswir1 | case 0: // hpstate |
1984 | e9ebed4d | blueswir1 | // gen_op_rdhpstate();
|
1985 | e9ebed4d | blueswir1 | break;
|
1986 | e9ebed4d | blueswir1 | case 1: // htstate |
1987 | e9ebed4d | blueswir1 | // gen_op_rdhtstate();
|
1988 | e9ebed4d | blueswir1 | break;
|
1989 | e9ebed4d | blueswir1 | case 3: // hintp |
1990 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hintp); |
1991 | e9ebed4d | blueswir1 | break;
|
1992 | e9ebed4d | blueswir1 | case 5: // htba |
1993 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_htba); |
1994 | e9ebed4d | blueswir1 | break;
|
1995 | e9ebed4d | blueswir1 | case 6: // hver |
1996 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hver); |
1997 | e9ebed4d | blueswir1 | break;
|
1998 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
1999 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); |
2000 | e9ebed4d | blueswir1 | break;
|
2001 | e9ebed4d | blueswir1 | default:
|
2002 | e9ebed4d | blueswir1 | goto illegal_insn;
|
2003 | e9ebed4d | blueswir1 | } |
2004 | e9ebed4d | blueswir1 | #endif
|
2005 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2006 | e8af50a3 | bellard | break;
|
2007 | 3475187d | bellard | } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ |
2008 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2009 | 0f8a249a | blueswir1 | goto priv_insn;
|
2010 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2011 | 3475187d | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2012 | 0f8a249a | blueswir1 | switch (rs1) {
|
2013 | 0f8a249a | blueswir1 | case 0: // tpc |
2014 | 375ee38b | blueswir1 | { |
2015 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2016 | 375ee38b | blueswir1 | |
2017 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2018 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2019 | a7812ae4 | pbrook | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2020 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
2021 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2022 | 375ee38b | blueswir1 | } |
2023 | 0f8a249a | blueswir1 | break;
|
2024 | 0f8a249a | blueswir1 | case 1: // tnpc |
2025 | 375ee38b | blueswir1 | { |
2026 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2027 | 375ee38b | blueswir1 | |
2028 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2029 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2030 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2031 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
2032 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2033 | 375ee38b | blueswir1 | } |
2034 | 0f8a249a | blueswir1 | break;
|
2035 | 0f8a249a | blueswir1 | case 2: // tstate |
2036 | 375ee38b | blueswir1 | { |
2037 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2038 | 375ee38b | blueswir1 | |
2039 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2040 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2041 | ece43b8d | blueswir1 | tcg_gen_ld_tl(cpu_tmp0, r_tsptr, |
2042 | 375ee38b | blueswir1 | offsetof(trap_state, tstate)); |
2043 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2044 | 375ee38b | blueswir1 | } |
2045 | 0f8a249a | blueswir1 | break;
|
2046 | 0f8a249a | blueswir1 | case 3: // tt |
2047 | 375ee38b | blueswir1 | { |
2048 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
2049 | 375ee38b | blueswir1 | |
2050 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
2051 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
2052 | a7812ae4 | pbrook | tcg_gen_ld_i32(cpu_tmp32, r_tsptr, |
2053 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
2054 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
2055 | a7812ae4 | pbrook | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2056 | 375ee38b | blueswir1 | } |
2057 | 0f8a249a | blueswir1 | break;
|
2058 | 0f8a249a | blueswir1 | case 4: // tick |
2059 | ccd4a219 | blueswir1 | { |
2060 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
2061 | ccd4a219 | blueswir1 | |
2062 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
2063 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
2064 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
2065 | a7812ae4 | pbrook | gen_helper_tick_get_count(cpu_tmp0, r_tickptr); |
2066 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2067 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
2068 | ccd4a219 | blueswir1 | } |
2069 | 0f8a249a | blueswir1 | break;
|
2070 | 0f8a249a | blueswir1 | case 5: // tba |
2071 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); |
2072 | 0f8a249a | blueswir1 | break;
|
2073 | 0f8a249a | blueswir1 | case 6: // pstate |
2074 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2075 | 77f193da | blueswir1 | offsetof(CPUSPARCState, pstate)); |
2076 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2077 | 0f8a249a | blueswir1 | break;
|
2078 | 0f8a249a | blueswir1 | case 7: // tl |
2079 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2080 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
2081 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2082 | 0f8a249a | blueswir1 | break;
|
2083 | 0f8a249a | blueswir1 | case 8: // pil |
2084 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2085 | 77f193da | blueswir1 | offsetof(CPUSPARCState, psrpil)); |
2086 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2087 | 0f8a249a | blueswir1 | break;
|
2088 | 0f8a249a | blueswir1 | case 9: // cwp |
2089 | a7812ae4 | pbrook | gen_helper_rdcwp(cpu_tmp0); |
2090 | 0f8a249a | blueswir1 | break;
|
2091 | 0f8a249a | blueswir1 | case 10: // cansave |
2092 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2093 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cansave)); |
2094 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2095 | 0f8a249a | blueswir1 | break;
|
2096 | 0f8a249a | blueswir1 | case 11: // canrestore |
2097 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2098 | 77f193da | blueswir1 | offsetof(CPUSPARCState, canrestore)); |
2099 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2100 | 0f8a249a | blueswir1 | break;
|
2101 | 0f8a249a | blueswir1 | case 12: // cleanwin |
2102 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2103 | 77f193da | blueswir1 | offsetof(CPUSPARCState, cleanwin)); |
2104 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2105 | 0f8a249a | blueswir1 | break;
|
2106 | 0f8a249a | blueswir1 | case 13: // otherwin |
2107 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2108 | 77f193da | blueswir1 | offsetof(CPUSPARCState, otherwin)); |
2109 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2110 | 0f8a249a | blueswir1 | break;
|
2111 | 0f8a249a | blueswir1 | case 14: // wstate |
2112 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2113 | 77f193da | blueswir1 | offsetof(CPUSPARCState, wstate)); |
2114 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2115 | 0f8a249a | blueswir1 | break;
|
2116 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
2117 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
2118 | 77f193da | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, |
2119 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
2120 | ece43b8d | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); |
2121 | e9ebed4d | blueswir1 | break;
|
2122 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
2123 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
2124 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
2125 | e9ebed4d | blueswir1 | goto priv_insn;
|
2126 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); |
2127 | e9ebed4d | blueswir1 | break;
|
2128 | 0f8a249a | blueswir1 | case 31: // ver |
2129 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tmp0, cpu_ver); |
2130 | 0f8a249a | blueswir1 | break;
|
2131 | 0f8a249a | blueswir1 | case 15: // fq |
2132 | 0f8a249a | blueswir1 | default:
|
2133 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2134 | 0f8a249a | blueswir1 | } |
2135 | 3475187d | bellard | #else
|
2136 | 255e1fcb | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); |
2137 | 3475187d | bellard | #endif
|
2138 | ece43b8d | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
2139 | e8af50a3 | bellard | break;
|
2140 | 3475187d | bellard | } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ |
2141 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2142 | c5f2f668 | blueswir1 | save_state(dc, cpu_cond); |
2143 | a7812ae4 | pbrook | gen_helper_flushw(); |
2144 | 3475187d | bellard | #else
|
2145 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
2146 | 0f8a249a | blueswir1 | goto priv_insn;
|
2147 | 255e1fcb | blueswir1 | gen_movl_TN_reg(rd, cpu_tbr); |
2148 | 3475187d | bellard | #endif
|
2149 | e8af50a3 | bellard | break;
|
2150 | e8af50a3 | bellard | #endif
|
2151 | 0f8a249a | blueswir1 | } else if (xop == 0x34) { /* FPU Operations */ |
2152 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2153 | a80dde08 | bellard | goto jmp_insn;
|
2154 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2155 | e8af50a3 | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2156 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2157 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2158 | 0f8a249a | blueswir1 | switch (xop) {
|
2159 | dc1a6971 | Blue Swirl | case 0x1: /* fmovs */ |
2160 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2161 | dc1a6971 | Blue Swirl | break;
|
2162 | dc1a6971 | Blue Swirl | case 0x5: /* fnegs */ |
2163 | dc1a6971 | Blue Swirl | gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); |
2164 | dc1a6971 | Blue Swirl | break;
|
2165 | dc1a6971 | Blue Swirl | case 0x9: /* fabss */ |
2166 | dc1a6971 | Blue Swirl | gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); |
2167 | dc1a6971 | Blue Swirl | break;
|
2168 | dc1a6971 | Blue Swirl | case 0x29: /* fsqrts */ |
2169 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2170 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2171 | dc1a6971 | Blue Swirl | gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); |
2172 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2173 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2174 | dc1a6971 | Blue Swirl | break;
|
2175 | dc1a6971 | Blue Swirl | case 0x2a: /* fsqrtd */ |
2176 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSQRT); |
2177 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2178 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2179 | dc1a6971 | Blue Swirl | gen_helper_fsqrtd(); |
2180 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2181 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2182 | dc1a6971 | Blue Swirl | break;
|
2183 | dc1a6971 | Blue Swirl | case 0x2b: /* fsqrtq */ |
2184 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2185 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2186 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2187 | dc1a6971 | Blue Swirl | gen_helper_fsqrtq(); |
2188 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2189 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2190 | dc1a6971 | Blue Swirl | break;
|
2191 | dc1a6971 | Blue Swirl | case 0x41: /* fadds */ |
2192 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2193 | dc1a6971 | Blue Swirl | gen_helper_fadds(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2194 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2195 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2196 | dc1a6971 | Blue Swirl | break;
|
2197 | dc1a6971 | Blue Swirl | case 0x42: /* faddd */ |
2198 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2199 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2200 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2201 | dc1a6971 | Blue Swirl | gen_helper_faddd(); |
2202 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2203 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2204 | dc1a6971 | Blue Swirl | break;
|
2205 | dc1a6971 | Blue Swirl | case 0x43: /* faddq */ |
2206 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2207 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2208 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2209 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2210 | dc1a6971 | Blue Swirl | gen_helper_faddq(); |
2211 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2212 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2213 | dc1a6971 | Blue Swirl | break;
|
2214 | dc1a6971 | Blue Swirl | case 0x45: /* fsubs */ |
2215 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2216 | dc1a6971 | Blue Swirl | gen_helper_fsubs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2217 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2218 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2219 | dc1a6971 | Blue Swirl | break;
|
2220 | dc1a6971 | Blue Swirl | case 0x46: /* fsubd */ |
2221 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2222 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2223 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2224 | dc1a6971 | Blue Swirl | gen_helper_fsubd(); |
2225 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2226 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2227 | dc1a6971 | Blue Swirl | break;
|
2228 | dc1a6971 | Blue Swirl | case 0x47: /* fsubq */ |
2229 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2230 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2231 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2232 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2233 | dc1a6971 | Blue Swirl | gen_helper_fsubq(); |
2234 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2235 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2236 | dc1a6971 | Blue Swirl | break;
|
2237 | dc1a6971 | Blue Swirl | case 0x49: /* fmuls */ |
2238 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2239 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2240 | dc1a6971 | Blue Swirl | gen_helper_fmuls(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2241 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2242 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2243 | dc1a6971 | Blue Swirl | break;
|
2244 | dc1a6971 | Blue Swirl | case 0x4a: /* fmuld */ |
2245 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2246 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2247 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2248 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2249 | dc1a6971 | Blue Swirl | gen_helper_fmuld(); |
2250 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2251 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2252 | dc1a6971 | Blue Swirl | break;
|
2253 | dc1a6971 | Blue Swirl | case 0x4b: /* fmulq */ |
2254 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2255 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FMUL); |
2256 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2257 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2258 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2259 | dc1a6971 | Blue Swirl | gen_helper_fmulq(); |
2260 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2261 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2262 | dc1a6971 | Blue Swirl | break;
|
2263 | dc1a6971 | Blue Swirl | case 0x4d: /* fdivs */ |
2264 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2265 | dc1a6971 | Blue Swirl | gen_helper_fdivs(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
2266 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2267 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2268 | dc1a6971 | Blue Swirl | break;
|
2269 | dc1a6971 | Blue Swirl | case 0x4e: /* fdivd */ |
2270 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2271 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2272 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2273 | dc1a6971 | Blue Swirl | gen_helper_fdivd(); |
2274 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2275 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2276 | dc1a6971 | Blue Swirl | break;
|
2277 | dc1a6971 | Blue Swirl | case 0x4f: /* fdivq */ |
2278 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2279 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2280 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2281 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2282 | dc1a6971 | Blue Swirl | gen_helper_fdivq(); |
2283 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2284 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2285 | dc1a6971 | Blue Swirl | break;
|
2286 | dc1a6971 | Blue Swirl | case 0x69: /* fsmuld */ |
2287 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FSMULD); |
2288 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2289 | dc1a6971 | Blue Swirl | gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); |
2290 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2291 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2292 | dc1a6971 | Blue Swirl | break;
|
2293 | dc1a6971 | Blue Swirl | case 0x6e: /* fdmulq */ |
2294 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2295 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2296 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2297 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2298 | dc1a6971 | Blue Swirl | gen_helper_fdmulq(); |
2299 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2300 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2301 | dc1a6971 | Blue Swirl | break;
|
2302 | dc1a6971 | Blue Swirl | case 0xc4: /* fitos */ |
2303 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2304 | dc1a6971 | Blue Swirl | gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); |
2305 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2306 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2307 | dc1a6971 | Blue Swirl | break;
|
2308 | dc1a6971 | Blue Swirl | case 0xc6: /* fdtos */ |
2309 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2310 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2311 | dc1a6971 | Blue Swirl | gen_helper_fdtos(cpu_tmp32); |
2312 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2313 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2314 | dc1a6971 | Blue Swirl | break;
|
2315 | dc1a6971 | Blue Swirl | case 0xc7: /* fqtos */ |
2316 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2317 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2318 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2319 | dc1a6971 | Blue Swirl | gen_helper_fqtos(cpu_tmp32); |
2320 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2321 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2322 | dc1a6971 | Blue Swirl | break;
|
2323 | dc1a6971 | Blue Swirl | case 0xc8: /* fitod */ |
2324 | dc1a6971 | Blue Swirl | gen_helper_fitod(cpu_fpr[rs2]); |
2325 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2326 | dc1a6971 | Blue Swirl | break;
|
2327 | dc1a6971 | Blue Swirl | case 0xc9: /* fstod */ |
2328 | dc1a6971 | Blue Swirl | gen_helper_fstod(cpu_fpr[rs2]); |
2329 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2330 | dc1a6971 | Blue Swirl | break;
|
2331 | dc1a6971 | Blue Swirl | case 0xcb: /* fqtod */ |
2332 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2333 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2334 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2335 | dc1a6971 | Blue Swirl | gen_helper_fqtod(); |
2336 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2337 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2338 | dc1a6971 | Blue Swirl | break;
|
2339 | dc1a6971 | Blue Swirl | case 0xcc: /* fitoq */ |
2340 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2341 | dc1a6971 | Blue Swirl | gen_helper_fitoq(cpu_fpr[rs2]); |
2342 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2343 | dc1a6971 | Blue Swirl | break;
|
2344 | dc1a6971 | Blue Swirl | case 0xcd: /* fstoq */ |
2345 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2346 | dc1a6971 | Blue Swirl | gen_helper_fstoq(cpu_fpr[rs2]); |
2347 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2348 | dc1a6971 | Blue Swirl | break;
|
2349 | dc1a6971 | Blue Swirl | case 0xce: /* fdtoq */ |
2350 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2351 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2352 | dc1a6971 | Blue Swirl | gen_helper_fdtoq(); |
2353 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2354 | dc1a6971 | Blue Swirl | break;
|
2355 | dc1a6971 | Blue Swirl | case 0xd1: /* fstoi */ |
2356 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2357 | dc1a6971 | Blue Swirl | gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); |
2358 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2359 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2360 | dc1a6971 | Blue Swirl | break;
|
2361 | dc1a6971 | Blue Swirl | case 0xd2: /* fdtoi */ |
2362 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2363 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2364 | dc1a6971 | Blue Swirl | gen_helper_fdtoi(cpu_tmp32); |
2365 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2366 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2367 | dc1a6971 | Blue Swirl | break;
|
2368 | dc1a6971 | Blue Swirl | case 0xd3: /* fqtoi */ |
2369 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2370 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2371 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2372 | dc1a6971 | Blue Swirl | gen_helper_fqtoi(cpu_tmp32); |
2373 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2374 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2375 | dc1a6971 | Blue Swirl | break;
|
2376 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2377 | dc1a6971 | Blue Swirl | case 0x2: /* V9 fmovd */ |
2378 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2379 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
2380 | dc1a6971 | Blue Swirl | cpu_fpr[DFPREG(rs2) + 1]);
|
2381 | dc1a6971 | Blue Swirl | break;
|
2382 | dc1a6971 | Blue Swirl | case 0x3: /* V9 fmovq */ |
2383 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2384 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2385 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
|
2386 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 1]);
|
2387 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
|
2388 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 2]);
|
2389 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
|
2390 | dc1a6971 | Blue Swirl | cpu_fpr[QFPREG(rs2) + 3]);
|
2391 | dc1a6971 | Blue Swirl | break;
|
2392 | dc1a6971 | Blue Swirl | case 0x6: /* V9 fnegd */ |
2393 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2394 | dc1a6971 | Blue Swirl | gen_helper_fnegd(); |
2395 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2396 | dc1a6971 | Blue Swirl | break;
|
2397 | dc1a6971 | Blue Swirl | case 0x7: /* V9 fnegq */ |
2398 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2399 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2400 | dc1a6971 | Blue Swirl | gen_helper_fnegq(); |
2401 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2402 | dc1a6971 | Blue Swirl | break;
|
2403 | dc1a6971 | Blue Swirl | case 0xa: /* V9 fabsd */ |
2404 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2405 | dc1a6971 | Blue Swirl | gen_helper_fabsd(); |
2406 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2407 | dc1a6971 | Blue Swirl | break;
|
2408 | dc1a6971 | Blue Swirl | case 0xb: /* V9 fabsq */ |
2409 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2410 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2411 | dc1a6971 | Blue Swirl | gen_helper_fabsq(); |
2412 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2413 | dc1a6971 | Blue Swirl | break;
|
2414 | dc1a6971 | Blue Swirl | case 0x81: /* V9 fstox */ |
2415 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2416 | dc1a6971 | Blue Swirl | gen_helper_fstox(cpu_fpr[rs2]); |
2417 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2418 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2419 | dc1a6971 | Blue Swirl | break;
|
2420 | dc1a6971 | Blue Swirl | case 0x82: /* V9 fdtox */ |
2421 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2422 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2423 | dc1a6971 | Blue Swirl | gen_helper_fdtox(); |
2424 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2425 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2426 | dc1a6971 | Blue Swirl | break;
|
2427 | dc1a6971 | Blue Swirl | case 0x83: /* V9 fqtox */ |
2428 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2429 | dc1a6971 | Blue Swirl | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2430 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2431 | dc1a6971 | Blue Swirl | gen_helper_fqtox(); |
2432 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2433 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2434 | dc1a6971 | Blue Swirl | break;
|
2435 | dc1a6971 | Blue Swirl | case 0x84: /* V9 fxtos */ |
2436 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2437 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2438 | dc1a6971 | Blue Swirl | gen_helper_fxtos(cpu_tmp32); |
2439 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2440 | dc1a6971 | Blue Swirl | tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); |
2441 | dc1a6971 | Blue Swirl | break;
|
2442 | dc1a6971 | Blue Swirl | case 0x88: /* V9 fxtod */ |
2443 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2444 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2445 | dc1a6971 | Blue Swirl | gen_helper_fxtod(); |
2446 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2447 | dc1a6971 | Blue Swirl | gen_op_store_DT0_fpr(DFPREG(rd)); |
2448 | dc1a6971 | Blue Swirl | break;
|
2449 | dc1a6971 | Blue Swirl | case 0x8c: /* V9 fxtoq */ |
2450 | dc1a6971 | Blue Swirl | CHECK_FPU_FEATURE(dc, FLOAT128); |
2451 | dc1a6971 | Blue Swirl | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2452 | dc1a6971 | Blue Swirl | gen_clear_float_exceptions(); |
2453 | dc1a6971 | Blue Swirl | gen_helper_fxtoq(); |
2454 | dc1a6971 | Blue Swirl | gen_helper_check_ieee_exceptions(); |
2455 | dc1a6971 | Blue Swirl | gen_op_store_QT0_fpr(QFPREG(rd)); |
2456 | dc1a6971 | Blue Swirl | break;
|
2457 | 1f587329 | blueswir1 | #endif
|
2458 | dc1a6971 | Blue Swirl | default:
|
2459 | dc1a6971 | Blue Swirl | goto illegal_insn;
|
2460 | 0f8a249a | blueswir1 | } |
2461 | 0f8a249a | blueswir1 | } else if (xop == 0x35) { /* FPU Operations */ |
2462 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2463 | 0f8a249a | blueswir1 | int cond;
|
2464 | 3475187d | bellard | #endif
|
2465 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
2466 | a80dde08 | bellard | goto jmp_insn;
|
2467 | 0f8a249a | blueswir1 | gen_op_clear_ieee_excp_and_FTT(); |
2468 | cf495bcf | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2469 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2470 | 0f8a249a | blueswir1 | xop = GET_FIELD(insn, 18, 26); |
2471 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2472 | 0f8a249a | blueswir1 | if ((xop & 0x11f) == 0x005) { // V9 fmovsr |
2473 | dcf24905 | blueswir1 | int l1;
|
2474 | dcf24905 | blueswir1 | |
2475 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2476 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2477 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2478 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2479 | cb63669a | pbrook | 0, l1);
|
2480 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
2481 | dcf24905 | blueswir1 | gen_set_label(l1); |
2482 | 0f8a249a | blueswir1 | break;
|
2483 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr |
2484 | dcf24905 | blueswir1 | int l1;
|
2485 | dcf24905 | blueswir1 | |
2486 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2487 | 0f8a249a | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2488 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2489 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2490 | cb63669a | pbrook | 0, l1);
|
2491 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
2492 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]); |
2493 | dcf24905 | blueswir1 | gen_set_label(l1); |
2494 | 0f8a249a | blueswir1 | break;
|
2495 | 0f8a249a | blueswir1 | } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr |
2496 | dcf24905 | blueswir1 | int l1;
|
2497 | dcf24905 | blueswir1 | |
2498 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2499 | dcf24905 | blueswir1 | l1 = gen_new_label(); |
2500 | 1f587329 | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); |
2501 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2502 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1, |
2503 | cb63669a | pbrook | 0, l1);
|
2504 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]); |
2505 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]); |
2506 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]); |
2507 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]); |
2508 | dcf24905 | blueswir1 | gen_set_label(l1); |
2509 | 1f587329 | blueswir1 | break;
|
2510 | 0f8a249a | blueswir1 | } |
2511 | 0f8a249a | blueswir1 | #endif
|
2512 | 0f8a249a | blueswir1 | switch (xop) {
|
2513 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
2514 | 714547bb | blueswir1 | #define FMOVSCC(fcc) \
|
2515 | 19f329ad | blueswir1 | { \ |
2516 | 0425bee5 | blueswir1 | TCGv r_cond; \ |
2517 | 19f329ad | blueswir1 | int l1; \
|
2518 | 19f329ad | blueswir1 | \ |
2519 | 19f329ad | blueswir1 | l1 = gen_new_label(); \ |
2520 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2521 | 19f329ad | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2522 | 19f329ad | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2523 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2524 | cb63669a | pbrook | 0, l1); \
|
2525 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2526 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2527 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2528 | 714547bb | blueswir1 | } |
2529 | 714547bb | blueswir1 | #define FMOVDCC(fcc) \
|
2530 | 714547bb | blueswir1 | { \ |
2531 | 714547bb | blueswir1 | TCGv r_cond; \ |
2532 | 714547bb | blueswir1 | int l1; \
|
2533 | 714547bb | blueswir1 | \ |
2534 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2535 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2536 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2537 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2538 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2539 | 714547bb | blueswir1 | 0, l1); \
|
2540 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2541 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2542 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2543 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2544 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2545 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2546 | 714547bb | blueswir1 | } |
2547 | 714547bb | blueswir1 | #define FMOVQCC(fcc) \
|
2548 | 714547bb | blueswir1 | { \ |
2549 | 714547bb | blueswir1 | TCGv r_cond; \ |
2550 | 714547bb | blueswir1 | int l1; \
|
2551 | 714547bb | blueswir1 | \ |
2552 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2553 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2554 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2555 | 714547bb | blueswir1 | gen_fcond(r_cond, fcc, cond); \ |
2556 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2557 | 714547bb | blueswir1 | 0, l1); \
|
2558 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2559 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2560 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2561 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2562 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2563 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2564 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2565 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2566 | 19f329ad | blueswir1 | gen_set_label(l1); \ |
2567 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); \ |
2568 | 19f329ad | blueswir1 | } |
2569 | 0f8a249a | blueswir1 | case 0x001: /* V9 fmovscc %fcc0 */ |
2570 | 714547bb | blueswir1 | FMOVSCC(0);
|
2571 | 0f8a249a | blueswir1 | break;
|
2572 | 0f8a249a | blueswir1 | case 0x002: /* V9 fmovdcc %fcc0 */ |
2573 | 714547bb | blueswir1 | FMOVDCC(0);
|
2574 | 0f8a249a | blueswir1 | break;
|
2575 | 0f8a249a | blueswir1 | case 0x003: /* V9 fmovqcc %fcc0 */ |
2576 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2577 | 714547bb | blueswir1 | FMOVQCC(0);
|
2578 | 1f587329 | blueswir1 | break;
|
2579 | 0f8a249a | blueswir1 | case 0x041: /* V9 fmovscc %fcc1 */ |
2580 | 714547bb | blueswir1 | FMOVSCC(1);
|
2581 | 0f8a249a | blueswir1 | break;
|
2582 | 0f8a249a | blueswir1 | case 0x042: /* V9 fmovdcc %fcc1 */ |
2583 | 714547bb | blueswir1 | FMOVDCC(1);
|
2584 | 0f8a249a | blueswir1 | break;
|
2585 | 0f8a249a | blueswir1 | case 0x043: /* V9 fmovqcc %fcc1 */ |
2586 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2587 | 714547bb | blueswir1 | FMOVQCC(1);
|
2588 | 1f587329 | blueswir1 | break;
|
2589 | 0f8a249a | blueswir1 | case 0x081: /* V9 fmovscc %fcc2 */ |
2590 | 714547bb | blueswir1 | FMOVSCC(2);
|
2591 | 0f8a249a | blueswir1 | break;
|
2592 | 0f8a249a | blueswir1 | case 0x082: /* V9 fmovdcc %fcc2 */ |
2593 | 714547bb | blueswir1 | FMOVDCC(2);
|
2594 | 0f8a249a | blueswir1 | break;
|
2595 | 0f8a249a | blueswir1 | case 0x083: /* V9 fmovqcc %fcc2 */ |
2596 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2597 | 714547bb | blueswir1 | FMOVQCC(2);
|
2598 | 1f587329 | blueswir1 | break;
|
2599 | 0f8a249a | blueswir1 | case 0x0c1: /* V9 fmovscc %fcc3 */ |
2600 | 714547bb | blueswir1 | FMOVSCC(3);
|
2601 | 0f8a249a | blueswir1 | break;
|
2602 | 0f8a249a | blueswir1 | case 0x0c2: /* V9 fmovdcc %fcc3 */ |
2603 | 714547bb | blueswir1 | FMOVDCC(3);
|
2604 | 0f8a249a | blueswir1 | break;
|
2605 | 0f8a249a | blueswir1 | case 0x0c3: /* V9 fmovqcc %fcc3 */ |
2606 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2607 | 714547bb | blueswir1 | FMOVQCC(3);
|
2608 | 1f587329 | blueswir1 | break;
|
2609 | 714547bb | blueswir1 | #undef FMOVSCC
|
2610 | 714547bb | blueswir1 | #undef FMOVDCC
|
2611 | 714547bb | blueswir1 | #undef FMOVQCC
|
2612 | 714547bb | blueswir1 | #define FMOVSCC(icc) \
|
2613 | 714547bb | blueswir1 | { \ |
2614 | 714547bb | blueswir1 | TCGv r_cond; \ |
2615 | 714547bb | blueswir1 | int l1; \
|
2616 | 714547bb | blueswir1 | \ |
2617 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2618 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2619 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2620 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2621 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2622 | 714547bb | blueswir1 | 0, l1); \
|
2623 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \ |
2624 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2625 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2626 | 714547bb | blueswir1 | } |
2627 | 714547bb | blueswir1 | #define FMOVDCC(icc) \
|
2628 | 714547bb | blueswir1 | { \ |
2629 | 714547bb | blueswir1 | TCGv r_cond; \ |
2630 | 714547bb | blueswir1 | int l1; \
|
2631 | 714547bb | blueswir1 | \ |
2632 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2633 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2634 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2635 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2636 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2637 | 714547bb | blueswir1 | 0, l1); \
|
2638 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \ |
2639 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2)]); \ |
2640 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
|
2641 | 714547bb | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]); \
|
2642 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2643 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2644 | 714547bb | blueswir1 | } |
2645 | 714547bb | blueswir1 | #define FMOVQCC(icc) \
|
2646 | 714547bb | blueswir1 | { \ |
2647 | 714547bb | blueswir1 | TCGv r_cond; \ |
2648 | 714547bb | blueswir1 | int l1; \
|
2649 | 714547bb | blueswir1 | \ |
2650 | 714547bb | blueswir1 | l1 = gen_new_label(); \ |
2651 | dc1a6971 | Blue Swirl | r_cond = tcg_temp_new(); \ |
2652 | 714547bb | blueswir1 | cond = GET_FIELD_SP(insn, 14, 17); \ |
2653 | 8393617c | Blue Swirl | gen_cond(r_cond, icc, cond, dc); \ |
2654 | 714547bb | blueswir1 | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ |
2655 | 714547bb | blueswir1 | 0, l1); \
|
2656 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \ |
2657 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2)]); \ |
2658 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
|
2659 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 1]); \
|
2660 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
|
2661 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 2]); \
|
2662 | 714547bb | blueswir1 | tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
|
2663 | 714547bb | blueswir1 | cpu_fpr[QFPREG(rs2) + 3]); \
|
2664 | 714547bb | blueswir1 | gen_set_label(l1); \ |
2665 | 714547bb | blueswir1 | tcg_temp_free(r_cond); \ |
2666 | 714547bb | blueswir1 | } |
2667 | 19f329ad | blueswir1 | |
2668 | 0f8a249a | blueswir1 | case 0x101: /* V9 fmovscc %icc */ |
2669 | 714547bb | blueswir1 | FMOVSCC(0);
|
2670 | 0f8a249a | blueswir1 | break;
|
2671 | 0f8a249a | blueswir1 | case 0x102: /* V9 fmovdcc %icc */ |
2672 | 714547bb | blueswir1 | FMOVDCC(0);
|
2673 | 0f8a249a | blueswir1 | case 0x103: /* V9 fmovqcc %icc */ |
2674 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2675 | 714547bb | blueswir1 | FMOVQCC(0);
|
2676 | 1f587329 | blueswir1 | break;
|
2677 | 0f8a249a | blueswir1 | case 0x181: /* V9 fmovscc %xcc */ |
2678 | 714547bb | blueswir1 | FMOVSCC(1);
|
2679 | 0f8a249a | blueswir1 | break;
|
2680 | 0f8a249a | blueswir1 | case 0x182: /* V9 fmovdcc %xcc */ |
2681 | 714547bb | blueswir1 | FMOVDCC(1);
|
2682 | 0f8a249a | blueswir1 | break;
|
2683 | 0f8a249a | blueswir1 | case 0x183: /* V9 fmovqcc %xcc */ |
2684 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2685 | 714547bb | blueswir1 | FMOVQCC(1);
|
2686 | 1f587329 | blueswir1 | break;
|
2687 | 714547bb | blueswir1 | #undef FMOVSCC
|
2688 | 714547bb | blueswir1 | #undef FMOVDCC
|
2689 | 714547bb | blueswir1 | #undef FMOVQCC
|
2690 | 1f587329 | blueswir1 | #endif
|
2691 | 1f587329 | blueswir1 | case 0x51: /* fcmps, V9 %fcc */ |
2692 | 714547bb | blueswir1 | gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2693 | 0f8a249a | blueswir1 | break;
|
2694 | 1f587329 | blueswir1 | case 0x52: /* fcmpd, V9 %fcc */ |
2695 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2696 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2697 | 7e8c2b6c | blueswir1 | gen_op_fcmpd(rd & 3);
|
2698 | 0f8a249a | blueswir1 | break;
|
2699 | 1f587329 | blueswir1 | case 0x53: /* fcmpq, V9 %fcc */ |
2700 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2701 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2702 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2703 | 7e8c2b6c | blueswir1 | gen_op_fcmpq(rd & 3);
|
2704 | 1f587329 | blueswir1 | break;
|
2705 | 0f8a249a | blueswir1 | case 0x55: /* fcmpes, V9 %fcc */ |
2706 | 714547bb | blueswir1 | gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
|
2707 | 0f8a249a | blueswir1 | break;
|
2708 | 0f8a249a | blueswir1 | case 0x56: /* fcmped, V9 %fcc */ |
2709 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
2710 | 0f8a249a | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
2711 | 7e8c2b6c | blueswir1 | gen_op_fcmped(rd & 3);
|
2712 | 0f8a249a | blueswir1 | break;
|
2713 | 1f587329 | blueswir1 | case 0x57: /* fcmpeq, V9 %fcc */ |
2714 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
2715 | 1f587329 | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rs1)); |
2716 | 1f587329 | blueswir1 | gen_op_load_fpr_QT1(QFPREG(rs2)); |
2717 | 7e8c2b6c | blueswir1 | gen_op_fcmpeq(rd & 3);
|
2718 | 1f587329 | blueswir1 | break;
|
2719 | 0f8a249a | blueswir1 | default:
|
2720 | 0f8a249a | blueswir1 | goto illegal_insn;
|
2721 | 0f8a249a | blueswir1 | } |
2722 | 0f8a249a | blueswir1 | } else if (xop == 0x2) { |
2723 | 0f8a249a | blueswir1 | // clr/mov shortcut
|
2724 | e80cfcfc | bellard | |
2725 | e80cfcfc | bellard | rs1 = GET_FIELD(insn, 13, 17); |
2726 | 0f8a249a | blueswir1 | if (rs1 == 0) { |
2727 | 1a2fb1c0 | blueswir1 | // or %g0, x, y -> mov T0, x; mov y, T0
|
2728 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2729 | 2ea815ca | blueswir1 | TCGv r_const; |
2730 | 2ea815ca | blueswir1 | |
2731 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2732 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
2733 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
2734 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
2735 | 0f8a249a | blueswir1 | } else { /* register */ |
2736 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2737 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_dst); |
2738 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2739 | 0f8a249a | blueswir1 | } |
2740 | 0f8a249a | blueswir1 | } else {
|
2741 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2742 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2743 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2744 | 67526b20 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
2745 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2746 | 0f8a249a | blueswir1 | } else { /* register */ |
2747 | 0f8a249a | blueswir1 | // or x, %g0, y -> mov T1, x; mov y, T1
|
2748 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
2749 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
2750 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2751 | 6ae20372 | blueswir1 | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2752 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2753 | 6f551262 | blueswir1 | } else
|
2754 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_src1); |
2755 | 0f8a249a | blueswir1 | } |
2756 | 0f8a249a | blueswir1 | } |
2757 | 83469015 | bellard | #ifdef TARGET_SPARC64
|
2758 | 0f8a249a | blueswir1 | } else if (xop == 0x25) { /* sll, V9 sllx */ |
2759 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2760 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2761 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2762 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2763 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2764 | 1a2fb1c0 | blueswir1 | } else {
|
2765 | 67526b20 | Blue Swirl | tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f);
|
2766 | 1a2fb1c0 | blueswir1 | } |
2767 | 0f8a249a | blueswir1 | } else { /* register */ |
2768 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2769 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2770 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2771 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2772 | 1a2fb1c0 | blueswir1 | } else {
|
2773 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2774 | 1a2fb1c0 | blueswir1 | } |
2775 | 01b1fa6d | blueswir1 | tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2776 | 83469015 | bellard | } |
2777 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2778 | 0f8a249a | blueswir1 | } else if (xop == 0x26) { /* srl, V9 srlx */ |
2779 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2780 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2781 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2782 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2783 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2784 | 1a2fb1c0 | blueswir1 | } else {
|
2785 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2786 | 67526b20 | Blue Swirl | tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2787 | 1a2fb1c0 | blueswir1 | } |
2788 | 0f8a249a | blueswir1 | } else { /* register */ |
2789 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2790 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2791 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2792 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2793 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2794 | 1a2fb1c0 | blueswir1 | } else {
|
2795 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2796 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2797 | 6ae20372 | blueswir1 | tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2798 | 1a2fb1c0 | blueswir1 | } |
2799 | 83469015 | bellard | } |
2800 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2801 | 0f8a249a | blueswir1 | } else if (xop == 0x27) { /* sra, V9 srax */ |
2802 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
2803 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
2804 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
2805 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2806 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f);
|
2807 | 1a2fb1c0 | blueswir1 | } else {
|
2808 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2809 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2810 | 67526b20 | Blue Swirl | tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f);
|
2811 | 1a2fb1c0 | blueswir1 | } |
2812 | 0f8a249a | blueswir1 | } else { /* register */ |
2813 | 83469015 | bellard | rs2 = GET_FIELD(insn, 27, 31); |
2814 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
2815 | 1a2fb1c0 | blueswir1 | if (insn & (1 << 12)) { |
2816 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
|
2817 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); |
2818 | 1a2fb1c0 | blueswir1 | } else {
|
2819 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
|
2820 | 6ae20372 | blueswir1 | tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
|
2821 | 527067d8 | blueswir1 | tcg_gen_ext32s_i64(cpu_dst, cpu_dst); |
2822 | 6ae20372 | blueswir1 | tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); |
2823 | 1a2fb1c0 | blueswir1 | } |
2824 | 83469015 | bellard | } |
2825 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
2826 | 83469015 | bellard | #endif
|
2827 | fcc72045 | blueswir1 | } else if (xop < 0x36) { |
2828 | cf495bcf | bellard | if (xop < 0x20) { |
2829 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
2830 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
2831 | cf495bcf | bellard | switch (xop & ~0x10) { |
2832 | b89e94af | Blue Swirl | case 0x0: /* add */ |
2833 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2834 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2835 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2836 | 41d72852 | Blue Swirl | gen_op_addi_cc(cpu_dst, cpu_src1, simm); |
2837 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
2838 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
2839 | 41d72852 | Blue Swirl | } else {
|
2840 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
2841 | 41d72852 | Blue Swirl | } |
2842 | 41d72852 | Blue Swirl | } else {
|
2843 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2844 | 41d72852 | Blue Swirl | gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); |
2845 | bdf9f35d | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
2846 | bdf9f35d | Blue Swirl | dc->cc_op = CC_OP_ADD; |
2847 | 41d72852 | Blue Swirl | } else {
|
2848 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
2849 | 41d72852 | Blue Swirl | } |
2850 | 41d72852 | Blue Swirl | } |
2851 | cf495bcf | bellard | break;
|
2852 | b89e94af | Blue Swirl | case 0x1: /* and */ |
2853 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2854 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2855 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, simm); |
2856 | 41d72852 | Blue Swirl | } else {
|
2857 | 41d72852 | Blue Swirl | tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); |
2858 | 41d72852 | Blue Swirl | } |
2859 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2860 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2861 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2862 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2863 | 41d72852 | Blue Swirl | } |
2864 | cf495bcf | bellard | break;
|
2865 | b89e94af | Blue Swirl | case 0x2: /* or */ |
2866 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2867 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2868 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, simm); |
2869 | 41d72852 | Blue Swirl | } else {
|
2870 | 41d72852 | Blue Swirl | tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); |
2871 | 41d72852 | Blue Swirl | } |
2872 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2873 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2874 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2875 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2876 | 8393617c | Blue Swirl | } |
2877 | 0f8a249a | blueswir1 | break;
|
2878 | b89e94af | Blue Swirl | case 0x3: /* xor */ |
2879 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2880 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2881 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, simm); |
2882 | 41d72852 | Blue Swirl | } else {
|
2883 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
2884 | 41d72852 | Blue Swirl | } |
2885 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2886 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2887 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2888 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2889 | 8393617c | Blue Swirl | } |
2890 | cf495bcf | bellard | break;
|
2891 | b89e94af | Blue Swirl | case 0x4: /* sub */ |
2892 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2893 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2894 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2895 | d4b0d468 | Blue Swirl | gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc); |
2896 | 41d72852 | Blue Swirl | } else {
|
2897 | 41d72852 | Blue Swirl | tcg_gen_subi_tl(cpu_dst, cpu_src1, simm); |
2898 | 41d72852 | Blue Swirl | } |
2899 | 41d72852 | Blue Swirl | } else {
|
2900 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
2901 | 41d72852 | Blue Swirl | gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); |
2902 | d4b0d468 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); |
2903 | d4b0d468 | Blue Swirl | dc->cc_op = CC_OP_SUB; |
2904 | 41d72852 | Blue Swirl | } else {
|
2905 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); |
2906 | 41d72852 | Blue Swirl | } |
2907 | 41d72852 | Blue Swirl | } |
2908 | cf495bcf | bellard | break;
|
2909 | b89e94af | Blue Swirl | case 0x5: /* andn */ |
2910 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2911 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2912 | 41d72852 | Blue Swirl | tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm); |
2913 | 41d72852 | Blue Swirl | } else {
|
2914 | 41d72852 | Blue Swirl | tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); |
2915 | 41d72852 | Blue Swirl | } |
2916 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2917 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2918 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2919 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2920 | 8393617c | Blue Swirl | } |
2921 | cf495bcf | bellard | break;
|
2922 | b89e94af | Blue Swirl | case 0x6: /* orn */ |
2923 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2924 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2925 | 41d72852 | Blue Swirl | tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm); |
2926 | 41d72852 | Blue Swirl | } else {
|
2927 | 41d72852 | Blue Swirl | tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); |
2928 | 41d72852 | Blue Swirl | } |
2929 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2930 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2931 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2932 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2933 | 8393617c | Blue Swirl | } |
2934 | cf495bcf | bellard | break;
|
2935 | b89e94af | Blue Swirl | case 0x7: /* xorn */ |
2936 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2937 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2938 | 41d72852 | Blue Swirl | tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm); |
2939 | 41d72852 | Blue Swirl | } else {
|
2940 | 41d72852 | Blue Swirl | tcg_gen_not_tl(cpu_tmp0, cpu_src2); |
2941 | 41d72852 | Blue Swirl | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2942 | 41d72852 | Blue Swirl | } |
2943 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2944 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2945 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2946 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2947 | 8393617c | Blue Swirl | } |
2948 | cf495bcf | bellard | break;
|
2949 | b89e94af | Blue Swirl | case 0x8: /* addx, V9 addc */ |
2950 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2951 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2952 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2953 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2954 | 41d72852 | Blue Swirl | gen_op_addxi_cc(cpu_dst, cpu_src1, simm); |
2955 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
2956 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
2957 | 8393617c | Blue Swirl | } else {
|
2958 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2959 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2960 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
2961 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2962 | 41d72852 | Blue Swirl | } |
2963 | 41d72852 | Blue Swirl | } else {
|
2964 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2965 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2966 | 41d72852 | Blue Swirl | gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2); |
2967 | 789c91ef | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX); |
2968 | 789c91ef | Blue Swirl | dc->cc_op = CC_OP_ADDX; |
2969 | 8393617c | Blue Swirl | } else {
|
2970 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
2971 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
2972 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
2973 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0); |
2974 | 41d72852 | Blue Swirl | } |
2975 | 38bc628b | blueswir1 | } |
2976 | cf495bcf | bellard | break;
|
2977 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
2978 | 0f8a249a | blueswir1 | case 0x9: /* V9 mulx */ |
2979 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
2980 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
2981 | 41d72852 | Blue Swirl | tcg_gen_muli_i64(cpu_dst, cpu_src1, simm); |
2982 | 41d72852 | Blue Swirl | } else {
|
2983 | 41d72852 | Blue Swirl | tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); |
2984 | 41d72852 | Blue Swirl | } |
2985 | ded3ab80 | pbrook | break;
|
2986 | ded3ab80 | pbrook | #endif
|
2987 | b89e94af | Blue Swirl | case 0xa: /* umul */ |
2988 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
2989 | 6ae20372 | blueswir1 | gen_op_umul(cpu_dst, cpu_src1, cpu_src2); |
2990 | 8393617c | Blue Swirl | if (xop & 0x10) { |
2991 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
2992 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
2993 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
2994 | 8393617c | Blue Swirl | } |
2995 | cf495bcf | bellard | break;
|
2996 | b89e94af | Blue Swirl | case 0xb: /* smul */ |
2997 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, MUL); |
2998 | 6ae20372 | blueswir1 | gen_op_smul(cpu_dst, cpu_src1, cpu_src2); |
2999 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3000 | 38482a77 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3001 | 38482a77 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); |
3002 | 38482a77 | Blue Swirl | dc->cc_op = CC_OP_LOGIC; |
3003 | 8393617c | Blue Swirl | } |
3004 | cf495bcf | bellard | break;
|
3005 | b89e94af | Blue Swirl | case 0xc: /* subx, V9 subc */ |
3006 | 41d72852 | Blue Swirl | if (IS_IMM) {
|
3007 | 41d72852 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
3008 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3009 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3010 | 41d72852 | Blue Swirl | gen_op_subxi_cc(cpu_dst, cpu_src1, simm); |
3011 | 2ca1d92b | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
3012 | 2ca1d92b | Blue Swirl | dc->cc_op = CC_OP_SUBX; |
3013 | 41d72852 | Blue Swirl | } else {
|
3014 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3015 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3016 | 41d72852 | Blue Swirl | tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, simm); |
3017 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3018 | 41d72852 | Blue Swirl | } |
3019 | 41d72852 | Blue Swirl | } else {
|
3020 | 41d72852 | Blue Swirl | if (xop & 0x10) { |
3021 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3022 | 41d72852 | Blue Swirl | gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); |
3023 | 2ca1d92b | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); |
3024 | 2ca1d92b | Blue Swirl | dc->cc_op = CC_OP_SUBX; |
3025 | 41d72852 | Blue Swirl | } else {
|
3026 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3027 | 41d72852 | Blue Swirl | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
3028 | 41d72852 | Blue Swirl | tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0); |
3029 | 41d72852 | Blue Swirl | tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3030 | 41d72852 | Blue Swirl | } |
3031 | 38bc628b | blueswir1 | } |
3032 | cf495bcf | bellard | break;
|
3033 | ded3ab80 | pbrook | #ifdef TARGET_SPARC64
|
3034 | 0f8a249a | blueswir1 | case 0xd: /* V9 udivx */ |
3035 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src, cpu_src1); |
3036 | 07bf2857 | blueswir1 | tcg_gen_mov_tl(cpu_cc_src2, cpu_src2); |
3037 | 07bf2857 | blueswir1 | gen_trap_ifdivzero_tl(cpu_cc_src2); |
3038 | 07bf2857 | blueswir1 | tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2); |
3039 | ded3ab80 | pbrook | break;
|
3040 | ded3ab80 | pbrook | #endif
|
3041 | b89e94af | Blue Swirl | case 0xe: /* udiv */ |
3042 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3043 | a7812ae4 | pbrook | gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); |
3044 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3045 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3046 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3047 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3048 | 8393617c | Blue Swirl | } |
3049 | cf495bcf | bellard | break;
|
3050 | b89e94af | Blue Swirl | case 0xf: /* sdiv */ |
3051 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, DIV); |
3052 | a7812ae4 | pbrook | gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); |
3053 | 8393617c | Blue Swirl | if (xop & 0x10) { |
3054 | 6c78ea32 | Blue Swirl | tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); |
3055 | 6c78ea32 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_DIV); |
3056 | 6c78ea32 | Blue Swirl | dc->cc_op = CC_OP_DIV; |
3057 | 8393617c | Blue Swirl | } |
3058 | cf495bcf | bellard | break;
|
3059 | cf495bcf | bellard | default:
|
3060 | cf495bcf | bellard | goto illegal_insn;
|
3061 | cf495bcf | bellard | } |
3062 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3063 | cf495bcf | bellard | } else {
|
3064 | 41d72852 | Blue Swirl | cpu_src1 = get_src1(insn, cpu_src1); |
3065 | 41d72852 | Blue Swirl | cpu_src2 = get_src2(insn, cpu_src2); |
3066 | cf495bcf | bellard | switch (xop) {
|
3067 | 0f8a249a | blueswir1 | case 0x20: /* taddcc */ |
3068 | 6ae20372 | blueswir1 | gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2); |
3069 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3070 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); |
3071 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADD; |
3072 | 0f8a249a | blueswir1 | break;
|
3073 | 0f8a249a | blueswir1 | case 0x21: /* tsubcc */ |
3074 | 6ae20372 | blueswir1 | gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2); |
3075 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3076 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); |
3077 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUB; |
3078 | 0f8a249a | blueswir1 | break;
|
3079 | 0f8a249a | blueswir1 | case 0x22: /* taddcctv */ |
3080 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3081 | 6ae20372 | blueswir1 | gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3082 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3083 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADDTV); |
3084 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TADDTV; |
3085 | 0f8a249a | blueswir1 | break;
|
3086 | 0f8a249a | blueswir1 | case 0x23: /* tsubcctv */ |
3087 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3088 | 6ae20372 | blueswir1 | gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2); |
3089 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3090 | 3b2d1e92 | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUBTV); |
3091 | 3b2d1e92 | Blue Swirl | dc->cc_op = CC_OP_TSUBTV; |
3092 | 0f8a249a | blueswir1 | break;
|
3093 | cf495bcf | bellard | case 0x24: /* mulscc */ |
3094 | 8393617c | Blue Swirl | gen_helper_compute_psr(); |
3095 | 6ae20372 | blueswir1 | gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); |
3096 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3097 | d084469c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); |
3098 | d084469c | Blue Swirl | dc->cc_op = CC_OP_ADD; |
3099 | cf495bcf | bellard | break;
|
3100 | 83469015 | bellard | #ifndef TARGET_SPARC64
|
3101 | 0f8a249a | blueswir1 | case 0x25: /* sll */ |
3102 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3103 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3104 | 67526b20 | Blue Swirl | tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3105 | e35298cd | blueswir1 | } else { /* register */ |
3106 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3107 | e35298cd | blueswir1 | tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3108 | e35298cd | blueswir1 | } |
3109 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3110 | cf495bcf | bellard | break;
|
3111 | 83469015 | bellard | case 0x26: /* srl */ |
3112 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3113 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3114 | 67526b20 | Blue Swirl | tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3115 | e35298cd | blueswir1 | } else { /* register */ |
3116 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3117 | e35298cd | blueswir1 | tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3118 | e35298cd | blueswir1 | } |
3119 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3120 | cf495bcf | bellard | break;
|
3121 | 83469015 | bellard | case 0x27: /* sra */ |
3122 | e35298cd | blueswir1 | if (IS_IMM) { /* immediate */ |
3123 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 20, 31); |
3124 | 67526b20 | Blue Swirl | tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f);
|
3125 | e35298cd | blueswir1 | } else { /* register */ |
3126 | e35298cd | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
|
3127 | e35298cd | blueswir1 | tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); |
3128 | e35298cd | blueswir1 | } |
3129 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3130 | cf495bcf | bellard | break;
|
3131 | 83469015 | bellard | #endif
|
3132 | cf495bcf | bellard | case 0x30: |
3133 | cf495bcf | bellard | { |
3134 | cf495bcf | bellard | switch(rd) {
|
3135 | 3475187d | bellard | case 0: /* wry */ |
3136 | 5068cbd9 | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3137 | 5068cbd9 | blueswir1 | tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
|
3138 | cf495bcf | bellard | break;
|
3139 | 65fe7b09 | blueswir1 | #ifndef TARGET_SPARC64
|
3140 | 65fe7b09 | blueswir1 | case 0x01 ... 0x0f: /* undefined in the |
3141 | 65fe7b09 | blueswir1 | SPARCv8 manual, nop
|
3142 | 65fe7b09 | blueswir1 | on the microSPARC
|
3143 | 65fe7b09 | blueswir1 | II */
|
3144 | 65fe7b09 | blueswir1 | case 0x10 ... 0x1f: /* implementation-dependent |
3145 | 65fe7b09 | blueswir1 | in the SPARCv8
|
3146 | 65fe7b09 | blueswir1 | manual, nop on the
|
3147 | 65fe7b09 | blueswir1 | microSPARC II */
|
3148 | 65fe7b09 | blueswir1 | break;
|
3149 | 65fe7b09 | blueswir1 | #else
|
3150 | 0f8a249a | blueswir1 | case 0x2: /* V9 wrccr */ |
3151 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3152 | a7812ae4 | pbrook | gen_helper_wrccr(cpu_dst); |
3153 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3154 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3155 | 0f8a249a | blueswir1 | break;
|
3156 | 0f8a249a | blueswir1 | case 0x3: /* V9 wrasi */ |
3157 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3158 | 01b5d4e5 | Igor V. Kovalenko | tcg_gen_andi_tl(cpu_dst, cpu_dst, 0xff);
|
3159 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst); |
3160 | 0f8a249a | blueswir1 | break;
|
3161 | 0f8a249a | blueswir1 | case 0x6: /* V9 wrfprs */ |
3162 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3163 | 255e1fcb | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst); |
3164 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3165 | 3299908c | blueswir1 | gen_op_next_insn(); |
3166 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3167 | 3299908c | blueswir1 | dc->is_br = 1;
|
3168 | 0f8a249a | blueswir1 | break;
|
3169 | 0f8a249a | blueswir1 | case 0xf: /* V9 sir, nop if user */ |
3170 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY)
|
3171 | 0f8a249a | blueswir1 | if (supervisor(dc))
|
3172 | 1a2fb1c0 | blueswir1 | ; // XXX
|
3173 | 3475187d | bellard | #endif
|
3174 | 0f8a249a | blueswir1 | break;
|
3175 | 0f8a249a | blueswir1 | case 0x13: /* Graphics Status */ |
3176 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3177 | 725cb90b | bellard | goto jmp_insn;
|
3178 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); |
3179 | 0f8a249a | blueswir1 | break;
|
3180 | 9d926598 | blueswir1 | case 0x14: /* Softint set */ |
3181 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3182 | 9d926598 | blueswir1 | goto illegal_insn;
|
3183 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3184 | a7812ae4 | pbrook | gen_helper_set_softint(cpu_tmp64); |
3185 | 9d926598 | blueswir1 | break;
|
3186 | 9d926598 | blueswir1 | case 0x15: /* Softint clear */ |
3187 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3188 | 9d926598 | blueswir1 | goto illegal_insn;
|
3189 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3190 | a7812ae4 | pbrook | gen_helper_clear_softint(cpu_tmp64); |
3191 | 9d926598 | blueswir1 | break;
|
3192 | 9d926598 | blueswir1 | case 0x16: /* Softint write */ |
3193 | 9d926598 | blueswir1 | if (!supervisor(dc))
|
3194 | 9d926598 | blueswir1 | goto illegal_insn;
|
3195 | 9d926598 | blueswir1 | tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); |
3196 | a7812ae4 | pbrook | gen_helper_write_softint(cpu_tmp64); |
3197 | 9d926598 | blueswir1 | break;
|
3198 | 0f8a249a | blueswir1 | case 0x17: /* Tick compare */ |
3199 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3200 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3201 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3202 | 83469015 | bellard | #endif
|
3203 | ccd4a219 | blueswir1 | { |
3204 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3205 | ccd4a219 | blueswir1 | |
3206 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, |
3207 | 6ae20372 | blueswir1 | cpu_src2); |
3208 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3209 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3210 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3211 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3212 | a7812ae4 | pbrook | cpu_tick_cmpr); |
3213 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3214 | ccd4a219 | blueswir1 | } |
3215 | 0f8a249a | blueswir1 | break;
|
3216 | 0f8a249a | blueswir1 | case 0x18: /* System tick */ |
3217 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3218 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3219 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3220 | 83469015 | bellard | #endif
|
3221 | ccd4a219 | blueswir1 | { |
3222 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3223 | ccd4a219 | blueswir1 | |
3224 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, |
3225 | 6ae20372 | blueswir1 | cpu_src2); |
3226 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3227 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3228 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3229 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3230 | a7812ae4 | pbrook | cpu_dst); |
3231 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3232 | ccd4a219 | blueswir1 | } |
3233 | 0f8a249a | blueswir1 | break;
|
3234 | 0f8a249a | blueswir1 | case 0x19: /* System tick compare */ |
3235 | 83469015 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3236 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3237 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3238 | 3475187d | bellard | #endif
|
3239 | ccd4a219 | blueswir1 | { |
3240 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3241 | ccd4a219 | blueswir1 | |
3242 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, |
3243 | 6ae20372 | blueswir1 | cpu_src2); |
3244 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3245 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3246 | ccd4a219 | blueswir1 | offsetof(CPUState, stick)); |
3247 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3248 | a7812ae4 | pbrook | cpu_stick_cmpr); |
3249 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3250 | ccd4a219 | blueswir1 | } |
3251 | 0f8a249a | blueswir1 | break;
|
3252 | 83469015 | bellard | |
3253 | 0f8a249a | blueswir1 | case 0x10: /* Performance Control */ |
3254 | 77f193da | blueswir1 | case 0x11: /* Performance Instrumentation |
3255 | 77f193da | blueswir1 | Counter */
|
3256 | 0f8a249a | blueswir1 | case 0x12: /* Dispatch Control */ |
3257 | 83469015 | bellard | #endif
|
3258 | 3475187d | bellard | default:
|
3259 | cf495bcf | bellard | goto illegal_insn;
|
3260 | cf495bcf | bellard | } |
3261 | cf495bcf | bellard | } |
3262 | cf495bcf | bellard | break;
|
3263 | e8af50a3 | bellard | #if !defined(CONFIG_USER_ONLY)
|
3264 | af7bf89b | bellard | case 0x31: /* wrpsr, V9 saved, restored */ |
3265 | e8af50a3 | bellard | { |
3266 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3267 | 0f8a249a | blueswir1 | goto priv_insn;
|
3268 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3269 | 0f8a249a | blueswir1 | switch (rd) {
|
3270 | 0f8a249a | blueswir1 | case 0: |
3271 | a7812ae4 | pbrook | gen_helper_saved(); |
3272 | 0f8a249a | blueswir1 | break;
|
3273 | 0f8a249a | blueswir1 | case 1: |
3274 | a7812ae4 | pbrook | gen_helper_restored(); |
3275 | 0f8a249a | blueswir1 | break;
|
3276 | e9ebed4d | blueswir1 | case 2: /* UA2005 allclean */ |
3277 | e9ebed4d | blueswir1 | case 3: /* UA2005 otherw */ |
3278 | e9ebed4d | blueswir1 | case 4: /* UA2005 normalw */ |
3279 | e9ebed4d | blueswir1 | case 5: /* UA2005 invalw */ |
3280 | e9ebed4d | blueswir1 | // XXX
|
3281 | 0f8a249a | blueswir1 | default:
|
3282 | 3475187d | bellard | goto illegal_insn;
|
3283 | 3475187d | bellard | } |
3284 | 3475187d | bellard | #else
|
3285 | 6ae20372 | blueswir1 | tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); |
3286 | a7812ae4 | pbrook | gen_helper_wrpsr(cpu_dst); |
3287 | 8393617c | Blue Swirl | tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); |
3288 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
3289 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3290 | 9e61bde5 | bellard | gen_op_next_insn(); |
3291 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3292 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
3293 | 3475187d | bellard | #endif
|
3294 | e8af50a3 | bellard | } |
3295 | e8af50a3 | bellard | break;
|
3296 | af7bf89b | bellard | case 0x32: /* wrwim, V9 wrpr */ |
3297 | e8af50a3 | bellard | { |
3298 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3299 | 0f8a249a | blueswir1 | goto priv_insn;
|
3300 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3301 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3302 | 0f8a249a | blueswir1 | switch (rd) {
|
3303 | 0f8a249a | blueswir1 | case 0: // tpc |
3304 | 375ee38b | blueswir1 | { |
3305 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3306 | 375ee38b | blueswir1 | |
3307 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3308 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3309 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3310 | 375ee38b | blueswir1 | offsetof(trap_state, tpc)); |
3311 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3312 | 375ee38b | blueswir1 | } |
3313 | 0f8a249a | blueswir1 | break;
|
3314 | 0f8a249a | blueswir1 | case 1: // tnpc |
3315 | 375ee38b | blueswir1 | { |
3316 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3317 | 375ee38b | blueswir1 | |
3318 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3319 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3320 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3321 | 375ee38b | blueswir1 | offsetof(trap_state, tnpc)); |
3322 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3323 | 375ee38b | blueswir1 | } |
3324 | 0f8a249a | blueswir1 | break;
|
3325 | 0f8a249a | blueswir1 | case 2: // tstate |
3326 | 375ee38b | blueswir1 | { |
3327 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3328 | 375ee38b | blueswir1 | |
3329 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3330 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3331 | ece43b8d | blueswir1 | tcg_gen_st_tl(cpu_tmp0, r_tsptr, |
3332 | 77f193da | blueswir1 | offsetof(trap_state, |
3333 | 77f193da | blueswir1 | tstate)); |
3334 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3335 | 375ee38b | blueswir1 | } |
3336 | 0f8a249a | blueswir1 | break;
|
3337 | 0f8a249a | blueswir1 | case 3: // tt |
3338 | 375ee38b | blueswir1 | { |
3339 | a7812ae4 | pbrook | TCGv_ptr r_tsptr; |
3340 | 375ee38b | blueswir1 | |
3341 | a7812ae4 | pbrook | r_tsptr = tcg_temp_new_ptr(); |
3342 | 8194f35a | Igor Kovalenko | gen_load_trap_state_at_tl(r_tsptr, cpu_env); |
3343 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3344 | 527067d8 | blueswir1 | tcg_gen_st_i32(cpu_tmp32, r_tsptr, |
3345 | 375ee38b | blueswir1 | offsetof(trap_state, tt)); |
3346 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tsptr); |
3347 | 375ee38b | blueswir1 | } |
3348 | 0f8a249a | blueswir1 | break;
|
3349 | 0f8a249a | blueswir1 | case 4: // tick |
3350 | ccd4a219 | blueswir1 | { |
3351 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3352 | ccd4a219 | blueswir1 | |
3353 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3354 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3355 | ccd4a219 | blueswir1 | offsetof(CPUState, tick)); |
3356 | a7812ae4 | pbrook | gen_helper_tick_set_count(r_tickptr, |
3357 | a7812ae4 | pbrook | cpu_tmp0); |
3358 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3359 | ccd4a219 | blueswir1 | } |
3360 | 0f8a249a | blueswir1 | break;
|
3361 | 0f8a249a | blueswir1 | case 5: // tba |
3362 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); |
3363 | 0f8a249a | blueswir1 | break;
|
3364 | 0f8a249a | blueswir1 | case 6: // pstate |
3365 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3366 | a7812ae4 | pbrook | gen_helper_wrpstate(cpu_tmp0); |
3367 | ded3ab80 | pbrook | gen_op_next_insn(); |
3368 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3369 | ded3ab80 | pbrook | dc->is_br = 1;
|
3370 | 0f8a249a | blueswir1 | break;
|
3371 | 0f8a249a | blueswir1 | case 7: // tl |
3372 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3373 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3374 | 77f193da | blueswir1 | offsetof(CPUSPARCState, tl)); |
3375 | 0f8a249a | blueswir1 | break;
|
3376 | 0f8a249a | blueswir1 | case 8: // pil |
3377 | 1fae7b70 | Igor V. Kovalenko | gen_helper_wrpil(cpu_tmp0); |
3378 | 0f8a249a | blueswir1 | break;
|
3379 | 0f8a249a | blueswir1 | case 9: // cwp |
3380 | a7812ae4 | pbrook | gen_helper_wrcwp(cpu_tmp0); |
3381 | 0f8a249a | blueswir1 | break;
|
3382 | 0f8a249a | blueswir1 | case 10: // cansave |
3383 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3384 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3385 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3386 | 77f193da | blueswir1 | cansave)); |
3387 | 0f8a249a | blueswir1 | break;
|
3388 | 0f8a249a | blueswir1 | case 11: // canrestore |
3389 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3390 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3391 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3392 | 77f193da | blueswir1 | canrestore)); |
3393 | 0f8a249a | blueswir1 | break;
|
3394 | 0f8a249a | blueswir1 | case 12: // cleanwin |
3395 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3396 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3397 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3398 | 77f193da | blueswir1 | cleanwin)); |
3399 | 0f8a249a | blueswir1 | break;
|
3400 | 0f8a249a | blueswir1 | case 13: // otherwin |
3401 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3402 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3403 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3404 | 77f193da | blueswir1 | otherwin)); |
3405 | 0f8a249a | blueswir1 | break;
|
3406 | 0f8a249a | blueswir1 | case 14: // wstate |
3407 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3408 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3409 | 77f193da | blueswir1 | offsetof(CPUSPARCState, |
3410 | 77f193da | blueswir1 | wstate)); |
3411 | 0f8a249a | blueswir1 | break;
|
3412 | e9ebed4d | blueswir1 | case 16: // UA2005 gl |
3413 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, GL); |
3414 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3415 | 77f193da | blueswir1 | tcg_gen_st_i32(cpu_tmp32, cpu_env, |
3416 | 77f193da | blueswir1 | offsetof(CPUSPARCState, gl)); |
3417 | e9ebed4d | blueswir1 | break;
|
3418 | e9ebed4d | blueswir1 | case 26: // UA2005 strand status |
3419 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3420 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3421 | e9ebed4d | blueswir1 | goto priv_insn;
|
3422 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); |
3423 | e9ebed4d | blueswir1 | break;
|
3424 | 0f8a249a | blueswir1 | default:
|
3425 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3426 | 0f8a249a | blueswir1 | } |
3427 | 3475187d | bellard | #else
|
3428 | ece43b8d | blueswir1 | tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); |
3429 | c93e7817 | blueswir1 | if (dc->def->nwindows != 32) |
3430 | c93e7817 | blueswir1 | tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32, |
3431 | c93e7817 | blueswir1 | (1 << dc->def->nwindows) - 1); |
3432 | 255e1fcb | blueswir1 | tcg_gen_mov_i32(cpu_wim, cpu_tmp32); |
3433 | 3475187d | bellard | #endif
|
3434 | e8af50a3 | bellard | } |
3435 | e8af50a3 | bellard | break;
|
3436 | e9ebed4d | blueswir1 | case 0x33: /* wrtbr, UA2005 wrhpr */ |
3437 | e8af50a3 | bellard | { |
3438 | e9ebed4d | blueswir1 | #ifndef TARGET_SPARC64
|
3439 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
3440 | 0f8a249a | blueswir1 | goto priv_insn;
|
3441 | 255e1fcb | blueswir1 | tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); |
3442 | e9ebed4d | blueswir1 | #else
|
3443 | fb79ceb9 | blueswir1 | CHECK_IU_FEATURE(dc, HYPV); |
3444 | e9ebed4d | blueswir1 | if (!hypervisor(dc))
|
3445 | e9ebed4d | blueswir1 | goto priv_insn;
|
3446 | ece43b8d | blueswir1 | tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); |
3447 | e9ebed4d | blueswir1 | switch (rd) {
|
3448 | e9ebed4d | blueswir1 | case 0: // hpstate |
3449 | e9ebed4d | blueswir1 | // XXX gen_op_wrhpstate();
|
3450 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
3451 | e9ebed4d | blueswir1 | gen_op_next_insn(); |
3452 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
3453 | e9ebed4d | blueswir1 | dc->is_br = 1;
|
3454 | e9ebed4d | blueswir1 | break;
|
3455 | e9ebed4d | blueswir1 | case 1: // htstate |
3456 | e9ebed4d | blueswir1 | // XXX gen_op_wrhtstate();
|
3457 | e9ebed4d | blueswir1 | break;
|
3458 | e9ebed4d | blueswir1 | case 3: // hintp |
3459 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); |
3460 | e9ebed4d | blueswir1 | break;
|
3461 | e9ebed4d | blueswir1 | case 5: // htba |
3462 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_htba, cpu_tmp0); |
3463 | e9ebed4d | blueswir1 | break;
|
3464 | e9ebed4d | blueswir1 | case 31: // hstick_cmpr |
3465 | ccd4a219 | blueswir1 | { |
3466 | a7812ae4 | pbrook | TCGv_ptr r_tickptr; |
3467 | ccd4a219 | blueswir1 | |
3468 | 255e1fcb | blueswir1 | tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); |
3469 | a7812ae4 | pbrook | r_tickptr = tcg_temp_new_ptr(); |
3470 | ccd4a219 | blueswir1 | tcg_gen_ld_ptr(r_tickptr, cpu_env, |
3471 | ccd4a219 | blueswir1 | offsetof(CPUState, hstick)); |
3472 | a7812ae4 | pbrook | gen_helper_tick_set_limit(r_tickptr, |
3473 | a7812ae4 | pbrook | cpu_hstick_cmpr); |
3474 | a7812ae4 | pbrook | tcg_temp_free_ptr(r_tickptr); |
3475 | ccd4a219 | blueswir1 | } |
3476 | e9ebed4d | blueswir1 | break;
|
3477 | e9ebed4d | blueswir1 | case 6: // hver readonly |
3478 | e9ebed4d | blueswir1 | default:
|
3479 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3480 | e9ebed4d | blueswir1 | } |
3481 | e9ebed4d | blueswir1 | #endif
|
3482 | e8af50a3 | bellard | } |
3483 | e8af50a3 | bellard | break;
|
3484 | e8af50a3 | bellard | #endif
|
3485 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3486 | 0f8a249a | blueswir1 | case 0x2c: /* V9 movcc */ |
3487 | 0f8a249a | blueswir1 | { |
3488 | 0f8a249a | blueswir1 | int cc = GET_FIELD_SP(insn, 11, 12); |
3489 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 14, 17); |
3490 | 748b9d8e | blueswir1 | TCGv r_cond; |
3491 | 00f219bf | blueswir1 | int l1;
|
3492 | 00f219bf | blueswir1 | |
3493 | a7812ae4 | pbrook | r_cond = tcg_temp_new(); |
3494 | 0f8a249a | blueswir1 | if (insn & (1 << 18)) { |
3495 | 0f8a249a | blueswir1 | if (cc == 0) |
3496 | 8393617c | Blue Swirl | gen_cond(r_cond, 0, cond, dc);
|
3497 | 0f8a249a | blueswir1 | else if (cc == 2) |
3498 | 8393617c | Blue Swirl | gen_cond(r_cond, 1, cond, dc);
|
3499 | 0f8a249a | blueswir1 | else
|
3500 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3501 | 0f8a249a | blueswir1 | } else {
|
3502 | 748b9d8e | blueswir1 | gen_fcond(r_cond, cc, cond); |
3503 | 0f8a249a | blueswir1 | } |
3504 | 00f219bf | blueswir1 | |
3505 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3506 | 00f219bf | blueswir1 | |
3507 | cb63669a | pbrook | tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
|
3508 | 00f219bf | blueswir1 | if (IS_IMM) { /* immediate */ |
3509 | 2ea815ca | blueswir1 | TCGv r_const; |
3510 | 2ea815ca | blueswir1 | |
3511 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 10); |
3512 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3513 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3514 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3515 | 00f219bf | blueswir1 | } else {
|
3516 | 00f219bf | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3517 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3518 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3519 | 00f219bf | blueswir1 | } |
3520 | 00f219bf | blueswir1 | gen_set_label(l1); |
3521 | 2ea815ca | blueswir1 | tcg_temp_free(r_cond); |
3522 | 0f8a249a | blueswir1 | break;
|
3523 | 0f8a249a | blueswir1 | } |
3524 | 0f8a249a | blueswir1 | case 0x2d: /* V9 sdivx */ |
3525 | 6ae20372 | blueswir1 | gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2); |
3526 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3527 | 0f8a249a | blueswir1 | break;
|
3528 | 0f8a249a | blueswir1 | case 0x2e: /* V9 popc */ |
3529 | 0f8a249a | blueswir1 | { |
3530 | a49d9390 | blueswir1 | cpu_src2 = get_src2(insn, cpu_src2); |
3531 | a7812ae4 | pbrook | gen_helper_popc(cpu_dst, cpu_src2); |
3532 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3533 | 0f8a249a | blueswir1 | } |
3534 | 0f8a249a | blueswir1 | case 0x2f: /* V9 movr */ |
3535 | 0f8a249a | blueswir1 | { |
3536 | 0f8a249a | blueswir1 | int cond = GET_FIELD_SP(insn, 10, 12); |
3537 | 00f219bf | blueswir1 | int l1;
|
3538 | 00f219bf | blueswir1 | |
3539 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3540 | 00f219bf | blueswir1 | |
3541 | 00f219bf | blueswir1 | l1 = gen_new_label(); |
3542 | 00f219bf | blueswir1 | |
3543 | cb63669a | pbrook | tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], |
3544 | cb63669a | pbrook | cpu_src1, 0, l1);
|
3545 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
3546 | 2ea815ca | blueswir1 | TCGv r_const; |
3547 | 2ea815ca | blueswir1 | |
3548 | 67526b20 | Blue Swirl | simm = GET_FIELD_SPs(insn, 0, 9); |
3549 | 67526b20 | Blue Swirl | r_const = tcg_const_tl(simm); |
3550 | 2ea815ca | blueswir1 | gen_movl_TN_reg(rd, r_const); |
3551 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
3552 | 00f219bf | blueswir1 | } else {
|
3553 | 0f8a249a | blueswir1 | rs2 = GET_FIELD_SP(insn, 0, 4); |
3554 | 9c6c6662 | blueswir1 | gen_movl_reg_TN(rs2, cpu_tmp0); |
3555 | 9c6c6662 | blueswir1 | gen_movl_TN_reg(rd, cpu_tmp0); |
3556 | 0f8a249a | blueswir1 | } |
3557 | 00f219bf | blueswir1 | gen_set_label(l1); |
3558 | 0f8a249a | blueswir1 | break;
|
3559 | 0f8a249a | blueswir1 | } |
3560 | 0f8a249a | blueswir1 | #endif
|
3561 | 0f8a249a | blueswir1 | default:
|
3562 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3563 | 0f8a249a | blueswir1 | } |
3564 | 0f8a249a | blueswir1 | } |
3565 | 3299908c | blueswir1 | } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ |
3566 | 3299908c | blueswir1 | #ifdef TARGET_SPARC64
|
3567 | 3299908c | blueswir1 | int opf = GET_FIELD_SP(insn, 5, 13); |
3568 | 3299908c | blueswir1 | rs1 = GET_FIELD(insn, 13, 17); |
3569 | 3299908c | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
3570 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
3571 | e9ebed4d | blueswir1 | goto jmp_insn;
|
3572 | 3299908c | blueswir1 | |
3573 | 3299908c | blueswir1 | switch (opf) {
|
3574 | e9ebed4d | blueswir1 | case 0x000: /* VIS I edge8cc */ |
3575 | e9ebed4d | blueswir1 | case 0x001: /* VIS II edge8n */ |
3576 | e9ebed4d | blueswir1 | case 0x002: /* VIS I edge8lcc */ |
3577 | e9ebed4d | blueswir1 | case 0x003: /* VIS II edge8ln */ |
3578 | e9ebed4d | blueswir1 | case 0x004: /* VIS I edge16cc */ |
3579 | e9ebed4d | blueswir1 | case 0x005: /* VIS II edge16n */ |
3580 | e9ebed4d | blueswir1 | case 0x006: /* VIS I edge16lcc */ |
3581 | e9ebed4d | blueswir1 | case 0x007: /* VIS II edge16ln */ |
3582 | e9ebed4d | blueswir1 | case 0x008: /* VIS I edge32cc */ |
3583 | e9ebed4d | blueswir1 | case 0x009: /* VIS II edge32n */ |
3584 | e9ebed4d | blueswir1 | case 0x00a: /* VIS I edge32lcc */ |
3585 | e9ebed4d | blueswir1 | case 0x00b: /* VIS II edge32ln */ |
3586 | e9ebed4d | blueswir1 | // XXX
|
3587 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3588 | e9ebed4d | blueswir1 | case 0x010: /* VIS I array8 */ |
3589 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3590 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3591 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3592 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3593 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3594 | e9ebed4d | blueswir1 | break;
|
3595 | e9ebed4d | blueswir1 | case 0x012: /* VIS I array16 */ |
3596 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3597 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3598 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3599 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3600 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
|
3601 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3602 | e9ebed4d | blueswir1 | break;
|
3603 | e9ebed4d | blueswir1 | case 0x014: /* VIS I array32 */ |
3604 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3605 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3606 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3607 | a7812ae4 | pbrook | gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); |
3608 | 6ae20372 | blueswir1 | tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
|
3609 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3610 | e9ebed4d | blueswir1 | break;
|
3611 | 3299908c | blueswir1 | case 0x018: /* VIS I alignaddr */ |
3612 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3613 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
3614 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
3615 | a7812ae4 | pbrook | gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); |
3616 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
3617 | 3299908c | blueswir1 | break;
|
3618 | e9ebed4d | blueswir1 | case 0x019: /* VIS II bmask */ |
3619 | 3299908c | blueswir1 | case 0x01a: /* VIS I alignaddrl */ |
3620 | 3299908c | blueswir1 | // XXX
|
3621 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3622 | e9ebed4d | blueswir1 | case 0x020: /* VIS I fcmple16 */ |
3623 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3624 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3625 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3626 | a7812ae4 | pbrook | gen_helper_fcmple16(); |
3627 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3628 | e9ebed4d | blueswir1 | break;
|
3629 | e9ebed4d | blueswir1 | case 0x022: /* VIS I fcmpne16 */ |
3630 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3631 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3632 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3633 | a7812ae4 | pbrook | gen_helper_fcmpne16(); |
3634 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3635 | 3299908c | blueswir1 | break;
|
3636 | e9ebed4d | blueswir1 | case 0x024: /* VIS I fcmple32 */ |
3637 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3638 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3639 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3640 | a7812ae4 | pbrook | gen_helper_fcmple32(); |
3641 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3642 | e9ebed4d | blueswir1 | break;
|
3643 | e9ebed4d | blueswir1 | case 0x026: /* VIS I fcmpne32 */ |
3644 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3645 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3646 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3647 | a7812ae4 | pbrook | gen_helper_fcmpne32(); |
3648 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3649 | e9ebed4d | blueswir1 | break;
|
3650 | e9ebed4d | blueswir1 | case 0x028: /* VIS I fcmpgt16 */ |
3651 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3652 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3653 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3654 | a7812ae4 | pbrook | gen_helper_fcmpgt16(); |
3655 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3656 | e9ebed4d | blueswir1 | break;
|
3657 | e9ebed4d | blueswir1 | case 0x02a: /* VIS I fcmpeq16 */ |
3658 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3659 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3660 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3661 | a7812ae4 | pbrook | gen_helper_fcmpeq16(); |
3662 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3663 | e9ebed4d | blueswir1 | break;
|
3664 | e9ebed4d | blueswir1 | case 0x02c: /* VIS I fcmpgt32 */ |
3665 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3666 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3667 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3668 | a7812ae4 | pbrook | gen_helper_fcmpgt32(); |
3669 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3670 | e9ebed4d | blueswir1 | break;
|
3671 | e9ebed4d | blueswir1 | case 0x02e: /* VIS I fcmpeq32 */ |
3672 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3673 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3674 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3675 | a7812ae4 | pbrook | gen_helper_fcmpeq32(); |
3676 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3677 | e9ebed4d | blueswir1 | break;
|
3678 | e9ebed4d | blueswir1 | case 0x031: /* VIS I fmul8x16 */ |
3679 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3680 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3681 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3682 | a7812ae4 | pbrook | gen_helper_fmul8x16(); |
3683 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3684 | e9ebed4d | blueswir1 | break;
|
3685 | e9ebed4d | blueswir1 | case 0x033: /* VIS I fmul8x16au */ |
3686 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3687 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3688 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3689 | a7812ae4 | pbrook | gen_helper_fmul8x16au(); |
3690 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3691 | e9ebed4d | blueswir1 | break;
|
3692 | e9ebed4d | blueswir1 | case 0x035: /* VIS I fmul8x16al */ |
3693 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3694 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3695 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3696 | a7812ae4 | pbrook | gen_helper_fmul8x16al(); |
3697 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3698 | e9ebed4d | blueswir1 | break;
|
3699 | e9ebed4d | blueswir1 | case 0x036: /* VIS I fmul8sux16 */ |
3700 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3701 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3702 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3703 | a7812ae4 | pbrook | gen_helper_fmul8sux16(); |
3704 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3705 | e9ebed4d | blueswir1 | break;
|
3706 | e9ebed4d | blueswir1 | case 0x037: /* VIS I fmul8ulx16 */ |
3707 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3708 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3709 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3710 | a7812ae4 | pbrook | gen_helper_fmul8ulx16(); |
3711 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3712 | e9ebed4d | blueswir1 | break;
|
3713 | e9ebed4d | blueswir1 | case 0x038: /* VIS I fmuld8sux16 */ |
3714 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3715 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3716 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3717 | a7812ae4 | pbrook | gen_helper_fmuld8sux16(); |
3718 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3719 | e9ebed4d | blueswir1 | break;
|
3720 | e9ebed4d | blueswir1 | case 0x039: /* VIS I fmuld8ulx16 */ |
3721 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3722 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3723 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3724 | a7812ae4 | pbrook | gen_helper_fmuld8ulx16(); |
3725 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3726 | e9ebed4d | blueswir1 | break;
|
3727 | e9ebed4d | blueswir1 | case 0x03a: /* VIS I fpack32 */ |
3728 | e9ebed4d | blueswir1 | case 0x03b: /* VIS I fpack16 */ |
3729 | e9ebed4d | blueswir1 | case 0x03d: /* VIS I fpackfix */ |
3730 | e9ebed4d | blueswir1 | case 0x03e: /* VIS I pdist */ |
3731 | e9ebed4d | blueswir1 | // XXX
|
3732 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3733 | 3299908c | blueswir1 | case 0x048: /* VIS I faligndata */ |
3734 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3735 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3736 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3737 | a7812ae4 | pbrook | gen_helper_faligndata(); |
3738 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3739 | 3299908c | blueswir1 | break;
|
3740 | e9ebed4d | blueswir1 | case 0x04b: /* VIS I fpmerge */ |
3741 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3742 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3743 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3744 | a7812ae4 | pbrook | gen_helper_fpmerge(); |
3745 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3746 | e9ebed4d | blueswir1 | break;
|
3747 | e9ebed4d | blueswir1 | case 0x04c: /* VIS II bshuffle */ |
3748 | e9ebed4d | blueswir1 | // XXX
|
3749 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3750 | e9ebed4d | blueswir1 | case 0x04d: /* VIS I fexpand */ |
3751 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3752 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3753 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3754 | a7812ae4 | pbrook | gen_helper_fexpand(); |
3755 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3756 | e9ebed4d | blueswir1 | break;
|
3757 | e9ebed4d | blueswir1 | case 0x050: /* VIS I fpadd16 */ |
3758 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3759 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3760 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3761 | a7812ae4 | pbrook | gen_helper_fpadd16(); |
3762 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3763 | e9ebed4d | blueswir1 | break;
|
3764 | e9ebed4d | blueswir1 | case 0x051: /* VIS I fpadd16s */ |
3765 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3766 | a7812ae4 | pbrook | gen_helper_fpadd16s(cpu_fpr[rd], |
3767 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3768 | e9ebed4d | blueswir1 | break;
|
3769 | e9ebed4d | blueswir1 | case 0x052: /* VIS I fpadd32 */ |
3770 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3771 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3772 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3773 | a7812ae4 | pbrook | gen_helper_fpadd32(); |
3774 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3775 | e9ebed4d | blueswir1 | break;
|
3776 | e9ebed4d | blueswir1 | case 0x053: /* VIS I fpadd32s */ |
3777 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3778 | a7812ae4 | pbrook | gen_helper_fpadd32s(cpu_fpr[rd], |
3779 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3780 | e9ebed4d | blueswir1 | break;
|
3781 | e9ebed4d | blueswir1 | case 0x054: /* VIS I fpsub16 */ |
3782 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3783 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3784 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3785 | a7812ae4 | pbrook | gen_helper_fpsub16(); |
3786 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3787 | e9ebed4d | blueswir1 | break;
|
3788 | e9ebed4d | blueswir1 | case 0x055: /* VIS I fpsub16s */ |
3789 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3790 | a7812ae4 | pbrook | gen_helper_fpsub16s(cpu_fpr[rd], |
3791 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3792 | e9ebed4d | blueswir1 | break;
|
3793 | e9ebed4d | blueswir1 | case 0x056: /* VIS I fpsub32 */ |
3794 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3795 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs1)); |
3796 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT1(DFPREG(rs2)); |
3797 | a7812ae4 | pbrook | gen_helper_fpsub32(); |
3798 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3799 | e9ebed4d | blueswir1 | break;
|
3800 | e9ebed4d | blueswir1 | case 0x057: /* VIS I fpsub32s */ |
3801 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3802 | a7812ae4 | pbrook | gen_helper_fpsub32s(cpu_fpr[rd], |
3803 | a7812ae4 | pbrook | cpu_fpr[rs1], cpu_fpr[rs2]); |
3804 | e9ebed4d | blueswir1 | break;
|
3805 | 3299908c | blueswir1 | case 0x060: /* VIS I fzero */ |
3806 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3807 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
|
3808 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0); |
3809 | 3299908c | blueswir1 | break;
|
3810 | 3299908c | blueswir1 | case 0x061: /* VIS I fzeros */ |
3811 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3812 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], 0);
|
3813 | 3299908c | blueswir1 | break;
|
3814 | e9ebed4d | blueswir1 | case 0x062: /* VIS I fnor */ |
3815 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3816 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3817 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3818 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3819 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3820 | e9ebed4d | blueswir1 | break;
|
3821 | e9ebed4d | blueswir1 | case 0x063: /* VIS I fnors */ |
3822 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3823 | 81b5b816 | blueswir1 | tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3824 | e9ebed4d | blueswir1 | break;
|
3825 | e9ebed4d | blueswir1 | case 0x064: /* VIS I fandnot2 */ |
3826 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3827 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3828 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3829 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3830 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3831 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3832 | e9ebed4d | blueswir1 | break;
|
3833 | e9ebed4d | blueswir1 | case 0x065: /* VIS I fandnot2s */ |
3834 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3835 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3836 | e9ebed4d | blueswir1 | break;
|
3837 | e9ebed4d | blueswir1 | case 0x066: /* VIS I fnot2 */ |
3838 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3839 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]); |
3840 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3841 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3842 | e9ebed4d | blueswir1 | break;
|
3843 | e9ebed4d | blueswir1 | case 0x067: /* VIS I fnot2s */ |
3844 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3845 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
3846 | e9ebed4d | blueswir1 | break;
|
3847 | e9ebed4d | blueswir1 | case 0x068: /* VIS I fandnot1 */ |
3848 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3849 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3850 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3851 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3852 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
3853 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3854 | e9ebed4d | blueswir1 | break;
|
3855 | e9ebed4d | blueswir1 | case 0x069: /* VIS I fandnot1s */ |
3856 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3857 | 81b5b816 | blueswir1 | tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
3858 | e9ebed4d | blueswir1 | break;
|
3859 | e9ebed4d | blueswir1 | case 0x06a: /* VIS I fnot1 */ |
3860 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3861 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3862 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
|
3863 | 2576d836 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3864 | e9ebed4d | blueswir1 | break;
|
3865 | e9ebed4d | blueswir1 | case 0x06b: /* VIS I fnot1s */ |
3866 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3867 | 2576d836 | blueswir1 | tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3868 | e9ebed4d | blueswir1 | break;
|
3869 | e9ebed4d | blueswir1 | case 0x06c: /* VIS I fxor */ |
3870 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3871 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3872 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3873 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
|
3874 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3875 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3876 | e9ebed4d | blueswir1 | break;
|
3877 | e9ebed4d | blueswir1 | case 0x06d: /* VIS I fxors */ |
3878 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3879 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3880 | e9ebed4d | blueswir1 | break;
|
3881 | e9ebed4d | blueswir1 | case 0x06e: /* VIS I fnand */ |
3882 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3883 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], |
3884 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3885 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
|
3886 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3887 | e9ebed4d | blueswir1 | break;
|
3888 | e9ebed4d | blueswir1 | case 0x06f: /* VIS I fnands */ |
3889 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3890 | 81b5b816 | blueswir1 | tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]); |
3891 | e9ebed4d | blueswir1 | break;
|
3892 | e9ebed4d | blueswir1 | case 0x070: /* VIS I fand */ |
3893 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3894 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3895 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3896 | e2ea21b3 | blueswir1 | tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
|
3897 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3898 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3899 | e9ebed4d | blueswir1 | break;
|
3900 | e9ebed4d | blueswir1 | case 0x071: /* VIS I fands */ |
3901 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3902 | 1d01299d | blueswir1 | tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3903 | e9ebed4d | blueswir1 | break;
|
3904 | e9ebed4d | blueswir1 | case 0x072: /* VIS I fxnor */ |
3905 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3906 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
|
3907 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, |
3908 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3909 | e2ea21b3 | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); |
3910 | e2ea21b3 | blueswir1 | tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
|
3911 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3912 | e9ebed4d | blueswir1 | break;
|
3913 | e9ebed4d | blueswir1 | case 0x073: /* VIS I fxnors */ |
3914 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3915 | 1d01299d | blueswir1 | tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
|
3916 | 1d01299d | blueswir1 | tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]); |
3917 | e9ebed4d | blueswir1 | break;
|
3918 | 3299908c | blueswir1 | case 0x074: /* VIS I fsrc1 */ |
3919 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3920 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]); |
3921 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
|
3922 | 1d01299d | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3923 | 3299908c | blueswir1 | break;
|
3924 | 3299908c | blueswir1 | case 0x075: /* VIS I fsrc1s */ |
3925 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3926 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]); |
3927 | 3299908c | blueswir1 | break;
|
3928 | e9ebed4d | blueswir1 | case 0x076: /* VIS I fornot2 */ |
3929 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3930 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3931 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3932 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3933 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3934 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3935 | e9ebed4d | blueswir1 | break;
|
3936 | e9ebed4d | blueswir1 | case 0x077: /* VIS I fornot2s */ |
3937 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3938 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3939 | e9ebed4d | blueswir1 | break;
|
3940 | 3299908c | blueswir1 | case 0x078: /* VIS I fsrc2 */ |
3941 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3942 | 2382dc6b | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rs2)); |
3943 | 2382dc6b | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
3944 | 3299908c | blueswir1 | break;
|
3945 | 3299908c | blueswir1 | case 0x079: /* VIS I fsrc2s */ |
3946 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3947 | 1d01299d | blueswir1 | tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); |
3948 | 3299908c | blueswir1 | break;
|
3949 | e9ebed4d | blueswir1 | case 0x07a: /* VIS I fornot1 */ |
3950 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3951 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], |
3952 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1)]); |
3953 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
|
3954 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1],
|
3955 | 81b5b816 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1]);
|
3956 | e9ebed4d | blueswir1 | break;
|
3957 | e9ebed4d | blueswir1 | case 0x07b: /* VIS I fornot1s */ |
3958 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3959 | 81b5b816 | blueswir1 | tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]); |
3960 | e9ebed4d | blueswir1 | break;
|
3961 | e9ebed4d | blueswir1 | case 0x07c: /* VIS I for */ |
3962 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3963 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], |
3964 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2)]); |
3965 | e2ea21b3 | blueswir1 | tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
|
3966 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs1) + 1],
|
3967 | e2ea21b3 | blueswir1 | cpu_fpr[DFPREG(rs2) + 1]);
|
3968 | e9ebed4d | blueswir1 | break;
|
3969 | e9ebed4d | blueswir1 | case 0x07d: /* VIS I fors */ |
3970 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3971 | 1d01299d | blueswir1 | tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]); |
3972 | e9ebed4d | blueswir1 | break;
|
3973 | 3299908c | blueswir1 | case 0x07e: /* VIS I fone */ |
3974 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3975 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
|
3976 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1); |
3977 | 3299908c | blueswir1 | break;
|
3978 | 3299908c | blueswir1 | case 0x07f: /* VIS I fones */ |
3979 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, VIS1); |
3980 | 1d01299d | blueswir1 | tcg_gen_movi_i32(cpu_fpr[rd], -1);
|
3981 | 3299908c | blueswir1 | break;
|
3982 | e9ebed4d | blueswir1 | case 0x080: /* VIS I shutdown */ |
3983 | e9ebed4d | blueswir1 | case 0x081: /* VIS II siam */ |
3984 | e9ebed4d | blueswir1 | // XXX
|
3985 | e9ebed4d | blueswir1 | goto illegal_insn;
|
3986 | 3299908c | blueswir1 | default:
|
3987 | 3299908c | blueswir1 | goto illegal_insn;
|
3988 | 3299908c | blueswir1 | } |
3989 | 3299908c | blueswir1 | #else
|
3990 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3991 | 3299908c | blueswir1 | #endif
|
3992 | 3299908c | blueswir1 | } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ |
3993 | fcc72045 | blueswir1 | #ifdef TARGET_SPARC64
|
3994 | 0f8a249a | blueswir1 | goto illegal_insn;
|
3995 | fcc72045 | blueswir1 | #else
|
3996 | 0f8a249a | blueswir1 | goto ncp_insn;
|
3997 | fcc72045 | blueswir1 | #endif
|
3998 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
3999 | 0f8a249a | blueswir1 | } else if (xop == 0x39) { /* V9 return */ |
4000 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4001 | 2ea815ca | blueswir1 | |
4002 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4003 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4004 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4005 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4006 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4007 | 0f8a249a | blueswir1 | } else { /* register */ |
4008 | 3475187d | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4009 | 0f8a249a | blueswir1 | if (rs2) {
|
4010 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4011 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4012 | 6f551262 | blueswir1 | } else
|
4013 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4014 | 3475187d | bellard | } |
4015 | a7812ae4 | pbrook | gen_helper_restore(); |
4016 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4017 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4018 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4019 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4020 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4021 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4022 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4023 | 3475187d | bellard | #endif
|
4024 | 0f8a249a | blueswir1 | } else {
|
4025 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4026 | 0f8a249a | blueswir1 | if (IS_IMM) { /* immediate */ |
4027 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4028 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_dst, cpu_src1, simm); |
4029 | 0f8a249a | blueswir1 | } else { /* register */ |
4030 | e80cfcfc | bellard | rs2 = GET_FIELD(insn, 27, 31); |
4031 | 0f8a249a | blueswir1 | if (rs2) {
|
4032 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4033 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); |
4034 | 6f551262 | blueswir1 | } else
|
4035 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_dst, cpu_src1); |
4036 | cf495bcf | bellard | } |
4037 | 0f8a249a | blueswir1 | switch (xop) {
|
4038 | 0f8a249a | blueswir1 | case 0x38: /* jmpl */ |
4039 | 0f8a249a | blueswir1 | { |
4040 | a7812ae4 | pbrook | TCGv r_pc; |
4041 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4042 | 2ea815ca | blueswir1 | |
4043 | a7812ae4 | pbrook | r_pc = tcg_const_tl(dc->pc); |
4044 | a7812ae4 | pbrook | gen_movl_TN_reg(rd, r_pc); |
4045 | a7812ae4 | pbrook | tcg_temp_free(r_pc); |
4046 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4047 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4048 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4049 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4050 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4051 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4052 | 0f8a249a | blueswir1 | } |
4053 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4054 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4055 | 0f8a249a | blueswir1 | case 0x39: /* rett, V9 return */ |
4056 | 0f8a249a | blueswir1 | { |
4057 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4058 | 2ea815ca | blueswir1 | |
4059 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4060 | 0f8a249a | blueswir1 | goto priv_insn;
|
4061 | 6ae20372 | blueswir1 | gen_mov_pc_npc(dc, cpu_cond); |
4062 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(3);
|
4063 | a7812ae4 | pbrook | gen_helper_check_align(cpu_dst, r_const); |
4064 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4065 | 6ae20372 | blueswir1 | tcg_gen_mov_tl(cpu_npc, cpu_dst); |
4066 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4067 | a7812ae4 | pbrook | gen_helper_rett(); |
4068 | 0f8a249a | blueswir1 | } |
4069 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4070 | 0f8a249a | blueswir1 | #endif
|
4071 | 0f8a249a | blueswir1 | case 0x3b: /* flush */ |
4072 | 5578ceab | blueswir1 | if (!((dc)->def->features & CPU_FEATURE_FLUSH))
|
4073 | 64a88d5d | blueswir1 | goto unimp_flush;
|
4074 | a7812ae4 | pbrook | gen_helper_flush(cpu_dst); |
4075 | 0f8a249a | blueswir1 | break;
|
4076 | 0f8a249a | blueswir1 | case 0x3c: /* save */ |
4077 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4078 | a7812ae4 | pbrook | gen_helper_save(); |
4079 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4080 | 0f8a249a | blueswir1 | break;
|
4081 | 0f8a249a | blueswir1 | case 0x3d: /* restore */ |
4082 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4083 | a7812ae4 | pbrook | gen_helper_restore(); |
4084 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_dst); |
4085 | 0f8a249a | blueswir1 | break;
|
4086 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
|
4087 | 0f8a249a | blueswir1 | case 0x3e: /* V9 done/retry */ |
4088 | 0f8a249a | blueswir1 | { |
4089 | 0f8a249a | blueswir1 | switch (rd) {
|
4090 | 0f8a249a | blueswir1 | case 0: |
4091 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4092 | 0f8a249a | blueswir1 | goto priv_insn;
|
4093 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4094 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4095 | a7812ae4 | pbrook | gen_helper_done(); |
4096 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4097 | 0f8a249a | blueswir1 | case 1: |
4098 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4099 | 0f8a249a | blueswir1 | goto priv_insn;
|
4100 | 0f8a249a | blueswir1 | dc->npc = DYNAMIC_PC; |
4101 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4102 | a7812ae4 | pbrook | gen_helper_retry(); |
4103 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4104 | 0f8a249a | blueswir1 | default:
|
4105 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4106 | 0f8a249a | blueswir1 | } |
4107 | 0f8a249a | blueswir1 | } |
4108 | 0f8a249a | blueswir1 | break;
|
4109 | 0f8a249a | blueswir1 | #endif
|
4110 | 0f8a249a | blueswir1 | default:
|
4111 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4112 | 0f8a249a | blueswir1 | } |
4113 | cf495bcf | bellard | } |
4114 | 0f8a249a | blueswir1 | break;
|
4115 | 0f8a249a | blueswir1 | } |
4116 | 0f8a249a | blueswir1 | break;
|
4117 | 0f8a249a | blueswir1 | case 3: /* load/store instructions */ |
4118 | 0f8a249a | blueswir1 | { |
4119 | 0f8a249a | blueswir1 | unsigned int xop = GET_FIELD(insn, 7, 12); |
4120 | 9322a4bf | blueswir1 | |
4121 | cfa90513 | Blue Swirl | /* flush pending conditional evaluations before exposing
|
4122 | cfa90513 | Blue Swirl | cpu state */
|
4123 | cfa90513 | Blue Swirl | if (dc->cc_op != CC_OP_FLAGS) {
|
4124 | cfa90513 | Blue Swirl | dc->cc_op = CC_OP_FLAGS; |
4125 | cfa90513 | Blue Swirl | gen_helper_compute_psr(); |
4126 | cfa90513 | Blue Swirl | } |
4127 | 9322a4bf | blueswir1 | cpu_src1 = get_src1(insn, cpu_src1); |
4128 | 71817e48 | blueswir1 | if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa |
4129 | 81ad8ba2 | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4130 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4131 | 71817e48 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4132 | 71817e48 | blueswir1 | } else if (IS_IMM) { /* immediate */ |
4133 | 67526b20 | Blue Swirl | simm = GET_FIELDs(insn, 19, 31); |
4134 | 67526b20 | Blue Swirl | tcg_gen_addi_tl(cpu_addr, cpu_src1, simm); |
4135 | 0f8a249a | blueswir1 | } else { /* register */ |
4136 | 0f8a249a | blueswir1 | rs2 = GET_FIELD(insn, 27, 31); |
4137 | 0f8a249a | blueswir1 | if (rs2 != 0) { |
4138 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rs2, cpu_src2); |
4139 | 6ae20372 | blueswir1 | tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2); |
4140 | 6f551262 | blueswir1 | } else
|
4141 | 6f551262 | blueswir1 | tcg_gen_mov_tl(cpu_addr, cpu_src1); |
4142 | 0f8a249a | blueswir1 | } |
4143 | 2f2ecb83 | blueswir1 | if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || |
4144 | 2f2ecb83 | blueswir1 | (xop > 0x17 && xop <= 0x1d ) || |
4145 | 2f2ecb83 | blueswir1 | (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { |
4146 | 0f8a249a | blueswir1 | switch (xop) {
|
4147 | b89e94af | Blue Swirl | case 0x0: /* ld, V9 lduw, load unsigned word */ |
4148 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4149 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx); |
4150 | 0f8a249a | blueswir1 | break;
|
4151 | b89e94af | Blue Swirl | case 0x1: /* ldub, load unsigned byte */ |
4152 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4153 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx); |
4154 | 0f8a249a | blueswir1 | break;
|
4155 | b89e94af | Blue Swirl | case 0x2: /* lduh, load unsigned halfword */ |
4156 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4157 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx); |
4158 | 0f8a249a | blueswir1 | break;
|
4159 | b89e94af | Blue Swirl | case 0x3: /* ldd, load double word */ |
4160 | 0f8a249a | blueswir1 | if (rd & 1) |
4161 | d4218d99 | blueswir1 | goto illegal_insn;
|
4162 | 1a2fb1c0 | blueswir1 | else {
|
4163 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4164 | 2ea815ca | blueswir1 | |
4165 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4166 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4167 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4168 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4169 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4170 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4171 | 32b6c812 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); |
4172 | 32b6c812 | blueswir1 | tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
|
4173 | 32b6c812 | blueswir1 | gen_movl_TN_reg(rd + 1, cpu_tmp0);
|
4174 | 8911f501 | blueswir1 | tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
|
4175 | 6ae20372 | blueswir1 | tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64); |
4176 | 6ae20372 | blueswir1 | tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
|
4177 | 1a2fb1c0 | blueswir1 | } |
4178 | 0f8a249a | blueswir1 | break;
|
4179 | b89e94af | Blue Swirl | case 0x9: /* ldsb, load signed byte */ |
4180 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4181 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4182 | 0f8a249a | blueswir1 | break;
|
4183 | b89e94af | Blue Swirl | case 0xa: /* ldsh, load signed halfword */ |
4184 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4185 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx); |
4186 | 0f8a249a | blueswir1 | break;
|
4187 | 0f8a249a | blueswir1 | case 0xd: /* ldstub -- XXX: should be atomically */ |
4188 | 2ea815ca | blueswir1 | { |
4189 | 2ea815ca | blueswir1 | TCGv r_const; |
4190 | 2ea815ca | blueswir1 | |
4191 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4192 | 2ea815ca | blueswir1 | tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx); |
4193 | 2ea815ca | blueswir1 | r_const = tcg_const_tl(0xff);
|
4194 | 2ea815ca | blueswir1 | tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx); |
4195 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4196 | 2ea815ca | blueswir1 | } |
4197 | 0f8a249a | blueswir1 | break;
|
4198 | b89e94af | Blue Swirl | case 0x0f: /* swap, swap register with memory. Also |
4199 | 77f193da | blueswir1 | atomically */
|
4200 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4201 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4202 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4203 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4204 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4205 | 527067d8 | blueswir1 | tcg_gen_mov_tl(cpu_val, cpu_tmp0); |
4206 | 0f8a249a | blueswir1 | break;
|
4207 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4208 | b89e94af | Blue Swirl | case 0x10: /* lda, V9 lduwa, load word alternate */ |
4209 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4210 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4211 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4212 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4213 | 0f8a249a | blueswir1 | goto priv_insn;
|
4214 | 6ea4a6c8 | blueswir1 | #endif
|
4215 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4216 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0); |
4217 | 0f8a249a | blueswir1 | break;
|
4218 | b89e94af | Blue Swirl | case 0x11: /* lduba, load unsigned byte alternate */ |
4219 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4220 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4221 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4222 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4223 | 0f8a249a | blueswir1 | goto priv_insn;
|
4224 | 0f8a249a | blueswir1 | #endif
|
4225 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4226 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0); |
4227 | 0f8a249a | blueswir1 | break;
|
4228 | b89e94af | Blue Swirl | case 0x12: /* lduha, load unsigned halfword alternate */ |
4229 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4230 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4231 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4232 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4233 | 0f8a249a | blueswir1 | goto priv_insn;
|
4234 | 6ea4a6c8 | blueswir1 | #endif
|
4235 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4236 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0); |
4237 | 0f8a249a | blueswir1 | break;
|
4238 | b89e94af | Blue Swirl | case 0x13: /* ldda, load double word alternate */ |
4239 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4240 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4241 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4242 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4243 | 0f8a249a | blueswir1 | goto priv_insn;
|
4244 | 3475187d | bellard | #endif
|
4245 | 0f8a249a | blueswir1 | if (rd & 1) |
4246 | d4218d99 | blueswir1 | goto illegal_insn;
|
4247 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4248 | db166940 | blueswir1 | gen_ldda_asi(cpu_val, cpu_addr, insn, rd); |
4249 | db166940 | blueswir1 | goto skip_move;
|
4250 | b89e94af | Blue Swirl | case 0x19: /* ldsba, load signed byte alternate */ |
4251 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4252 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4253 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4254 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4255 | 0f8a249a | blueswir1 | goto priv_insn;
|
4256 | 0f8a249a | blueswir1 | #endif
|
4257 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4258 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1); |
4259 | 0f8a249a | blueswir1 | break;
|
4260 | b89e94af | Blue Swirl | case 0x1a: /* ldsha, load signed halfword alternate */ |
4261 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4262 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4263 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4264 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4265 | 0f8a249a | blueswir1 | goto priv_insn;
|
4266 | 6ea4a6c8 | blueswir1 | #endif
|
4267 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4268 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1); |
4269 | 0f8a249a | blueswir1 | break;
|
4270 | 0f8a249a | blueswir1 | case 0x1d: /* ldstuba -- XXX: should be atomically */ |
4271 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4272 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4273 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4274 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4275 | 0f8a249a | blueswir1 | goto priv_insn;
|
4276 | 0f8a249a | blueswir1 | #endif
|
4277 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4278 | 6ae20372 | blueswir1 | gen_ldstub_asi(cpu_val, cpu_addr, insn); |
4279 | 0f8a249a | blueswir1 | break;
|
4280 | b89e94af | Blue Swirl | case 0x1f: /* swapa, swap reg with alt. memory. Also |
4281 | 77f193da | blueswir1 | atomically */
|
4282 | 64a88d5d | blueswir1 | CHECK_IU_FEATURE(dc, SWAP); |
4283 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4284 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4285 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4286 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4287 | 0f8a249a | blueswir1 | goto priv_insn;
|
4288 | 6ea4a6c8 | blueswir1 | #endif
|
4289 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4290 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4291 | 6ae20372 | blueswir1 | gen_swap_asi(cpu_val, cpu_addr, insn); |
4292 | 0f8a249a | blueswir1 | break;
|
4293 | 3475187d | bellard | |
4294 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4295 | 0f8a249a | blueswir1 | case 0x30: /* ldc */ |
4296 | 0f8a249a | blueswir1 | case 0x31: /* ldcsr */ |
4297 | 0f8a249a | blueswir1 | case 0x33: /* lddc */ |
4298 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4299 | 3475187d | bellard | #endif
|
4300 | 3475187d | bellard | #endif
|
4301 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4302 | 0f8a249a | blueswir1 | case 0x08: /* V9 ldsw */ |
4303 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4304 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx); |
4305 | 0f8a249a | blueswir1 | break;
|
4306 | 0f8a249a | blueswir1 | case 0x0b: /* V9 ldx */ |
4307 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4308 | 6ae20372 | blueswir1 | tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx); |
4309 | 0f8a249a | blueswir1 | break;
|
4310 | 0f8a249a | blueswir1 | case 0x18: /* V9 ldswa */ |
4311 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4312 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1); |
4313 | 0f8a249a | blueswir1 | break;
|
4314 | 0f8a249a | blueswir1 | case 0x1b: /* V9 ldxa */ |
4315 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4316 | 6ae20372 | blueswir1 | gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0); |
4317 | 0f8a249a | blueswir1 | break;
|
4318 | 0f8a249a | blueswir1 | case 0x2d: /* V9 prefetch, no effect */ |
4319 | 0f8a249a | blueswir1 | goto skip_move;
|
4320 | 0f8a249a | blueswir1 | case 0x30: /* V9 ldfa */ |
4321 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4322 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 4, rd);
|
4323 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4324 | 0f8a249a | blueswir1 | case 0x33: /* V9 lddfa */ |
4325 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4326 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4327 | 81ad8ba2 | blueswir1 | goto skip_move;
|
4328 | 0f8a249a | blueswir1 | case 0x3d: /* V9 prefetcha, no effect */ |
4329 | 0f8a249a | blueswir1 | goto skip_move;
|
4330 | 0f8a249a | blueswir1 | case 0x32: /* V9 ldqfa */ |
4331 | 64a88d5d | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4332 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4333 | 6ae20372 | blueswir1 | gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4334 | 1f587329 | blueswir1 | goto skip_move;
|
4335 | 1f587329 | blueswir1 | #endif
|
4336 | 0f8a249a | blueswir1 | default:
|
4337 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4338 | 0f8a249a | blueswir1 | } |
4339 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4340 | db166940 | blueswir1 | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4341 | 0f8a249a | blueswir1 | skip_move: ;
|
4342 | 3475187d | bellard | #endif
|
4343 | 0f8a249a | blueswir1 | } else if (xop >= 0x20 && xop < 0x24) { |
4344 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4345 | a80dde08 | bellard | goto jmp_insn;
|
4346 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4347 | 0f8a249a | blueswir1 | switch (xop) {
|
4348 | b89e94af | Blue Swirl | case 0x20: /* ldf, load fpreg */ |
4349 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4350 | 527067d8 | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx); |
4351 | 527067d8 | blueswir1 | tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0); |
4352 | 0f8a249a | blueswir1 | break;
|
4353 | 3a3b925d | blueswir1 | case 0x21: /* ldfsr, V9 ldxfsr */ |
4354 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4355 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4356 | 3a3b925d | blueswir1 | if (rd == 1) { |
4357 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4358 | a7812ae4 | pbrook | gen_helper_ldxfsr(cpu_tmp64); |
4359 | 3a3b925d | blueswir1 | } else
|
4360 | 3a3b925d | blueswir1 | #else
|
4361 | 3a3b925d | blueswir1 | { |
4362 | 3a3b925d | blueswir1 | tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); |
4363 | a7812ae4 | pbrook | gen_helper_ldfsr(cpu_tmp32); |
4364 | 3a3b925d | blueswir1 | } |
4365 | 3a3b925d | blueswir1 | #endif
|
4366 | 0f8a249a | blueswir1 | break;
|
4367 | b89e94af | Blue Swirl | case 0x22: /* ldqf, load quad fpreg */ |
4368 | 2ea815ca | blueswir1 | { |
4369 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4370 | 2ea815ca | blueswir1 | |
4371 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4372 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4373 | a7812ae4 | pbrook | gen_helper_ldqf(cpu_addr, r_const); |
4374 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4375 | 2ea815ca | blueswir1 | gen_op_store_QT0_fpr(QFPREG(rd)); |
4376 | 2ea815ca | blueswir1 | } |
4377 | 1f587329 | blueswir1 | break;
|
4378 | b89e94af | Blue Swirl | case 0x23: /* lddf, load double fpreg */ |
4379 | 2ea815ca | blueswir1 | { |
4380 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4381 | 2ea815ca | blueswir1 | |
4382 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4383 | a7812ae4 | pbrook | gen_helper_lddf(cpu_addr, r_const); |
4384 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4385 | 2ea815ca | blueswir1 | gen_op_store_DT0_fpr(DFPREG(rd)); |
4386 | 2ea815ca | blueswir1 | } |
4387 | 0f8a249a | blueswir1 | break;
|
4388 | 0f8a249a | blueswir1 | default:
|
4389 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4390 | 0f8a249a | blueswir1 | } |
4391 | dc1a6971 | Blue Swirl | } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || |
4392 | 0f8a249a | blueswir1 | xop == 0xe || xop == 0x1e) { |
4393 | 6ae20372 | blueswir1 | gen_movl_reg_TN(rd, cpu_val); |
4394 | 0f8a249a | blueswir1 | switch (xop) {
|
4395 | b89e94af | Blue Swirl | case 0x4: /* st, store word */ |
4396 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4397 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx); |
4398 | 0f8a249a | blueswir1 | break;
|
4399 | b89e94af | Blue Swirl | case 0x5: /* stb, store byte */ |
4400 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4401 | 6ae20372 | blueswir1 | tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx); |
4402 | 0f8a249a | blueswir1 | break;
|
4403 | b89e94af | Blue Swirl | case 0x6: /* sth, store halfword */ |
4404 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4405 | 6ae20372 | blueswir1 | tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx); |
4406 | 0f8a249a | blueswir1 | break;
|
4407 | b89e94af | Blue Swirl | case 0x7: /* std, store double word */ |
4408 | 0f8a249a | blueswir1 | if (rd & 1) |
4409 | d4218d99 | blueswir1 | goto illegal_insn;
|
4410 | 1a2fb1c0 | blueswir1 | else {
|
4411 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4412 | 1a2fb1c0 | blueswir1 | |
4413 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4414 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4415 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4416 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); // XXX remove
|
4417 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4418 | a7ec4229 | blueswir1 | gen_movl_reg_TN(rd + 1, cpu_tmp0);
|
4419 | ab508019 | blueswir1 | tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val); |
4420 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4421 | 7fa76c0b | blueswir1 | } |
4422 | 0f8a249a | blueswir1 | break;
|
4423 | 3475187d | bellard | #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
|
4424 | b89e94af | Blue Swirl | case 0x14: /* sta, V9 stwa, store word alternate */ |
4425 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4426 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4427 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4428 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4429 | 0f8a249a | blueswir1 | goto priv_insn;
|
4430 | 3475187d | bellard | #endif
|
4431 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4432 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 4);
|
4433 | d39c0b99 | bellard | break;
|
4434 | b89e94af | Blue Swirl | case 0x15: /* stba, store byte alternate */ |
4435 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4436 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4437 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4438 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4439 | 0f8a249a | blueswir1 | goto priv_insn;
|
4440 | 3475187d | bellard | #endif
|
4441 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4442 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 1);
|
4443 | d39c0b99 | bellard | break;
|
4444 | b89e94af | Blue Swirl | case 0x16: /* stha, store halfword alternate */ |
4445 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4446 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4447 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4448 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4449 | 0f8a249a | blueswir1 | goto priv_insn;
|
4450 | 3475187d | bellard | #endif
|
4451 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4452 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 2);
|
4453 | d39c0b99 | bellard | break;
|
4454 | b89e94af | Blue Swirl | case 0x17: /* stda, store double word alternate */ |
4455 | 3475187d | bellard | #ifndef TARGET_SPARC64
|
4456 | 0f8a249a | blueswir1 | if (IS_IMM)
|
4457 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4458 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4459 | 0f8a249a | blueswir1 | goto priv_insn;
|
4460 | 3475187d | bellard | #endif
|
4461 | 0f8a249a | blueswir1 | if (rd & 1) |
4462 | d4218d99 | blueswir1 | goto illegal_insn;
|
4463 | 1a2fb1c0 | blueswir1 | else {
|
4464 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4465 | 6ae20372 | blueswir1 | gen_stda_asi(cpu_val, cpu_addr, insn, rd); |
4466 | 1a2fb1c0 | blueswir1 | } |
4467 | d39c0b99 | bellard | break;
|
4468 | e80cfcfc | bellard | #endif
|
4469 | 3475187d | bellard | #ifdef TARGET_SPARC64
|
4470 | 0f8a249a | blueswir1 | case 0x0e: /* V9 stx */ |
4471 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4472 | 6ae20372 | blueswir1 | tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx); |
4473 | 0f8a249a | blueswir1 | break;
|
4474 | 0f8a249a | blueswir1 | case 0x1e: /* V9 stxa */ |
4475 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4476 | 6ae20372 | blueswir1 | gen_st_asi(cpu_val, cpu_addr, insn, 8);
|
4477 | 0f8a249a | blueswir1 | break;
|
4478 | 3475187d | bellard | #endif
|
4479 | 0f8a249a | blueswir1 | default:
|
4480 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4481 | 0f8a249a | blueswir1 | } |
4482 | 0f8a249a | blueswir1 | } else if (xop > 0x23 && xop < 0x28) { |
4483 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4484 | a80dde08 | bellard | goto jmp_insn;
|
4485 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4486 | 0f8a249a | blueswir1 | switch (xop) {
|
4487 | b89e94af | Blue Swirl | case 0x24: /* stf, store fpreg */ |
4488 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4489 | 527067d8 | blueswir1 | tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]); |
4490 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx); |
4491 | 0f8a249a | blueswir1 | break;
|
4492 | 0f8a249a | blueswir1 | case 0x25: /* stfsr, V9 stxfsr */ |
4493 | 3a3b925d | blueswir1 | #ifdef TARGET_SPARC64
|
4494 | 2cade6a3 | blueswir1 | gen_address_mask(dc, cpu_addr); |
4495 | 3a3b925d | blueswir1 | tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr)); |
4496 | 3a3b925d | blueswir1 | if (rd == 1) |
4497 | 3a3b925d | blueswir1 | tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); |
4498 | 527067d8 | blueswir1 | else
|
4499 | 527067d8 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx); |
4500 | 3a3b925d | blueswir1 | #else
|
4501 | 3a3b925d | blueswir1 | tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr)); |
4502 | 6ae20372 | blueswir1 | tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx); |
4503 | 3a3b925d | blueswir1 | #endif
|
4504 | 0f8a249a | blueswir1 | break;
|
4505 | 1f587329 | blueswir1 | case 0x26: |
4506 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC64
|
4507 | 1f587329 | blueswir1 | /* V9 stqf, store quad fpreg */
|
4508 | 2ea815ca | blueswir1 | { |
4509 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4510 | 2ea815ca | blueswir1 | |
4511 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4512 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4513 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4514 | a7812ae4 | pbrook | gen_helper_stqf(cpu_addr, r_const); |
4515 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4516 | 2ea815ca | blueswir1 | } |
4517 | 1f587329 | blueswir1 | break;
|
4518 | 1f587329 | blueswir1 | #else /* !TARGET_SPARC64 */ |
4519 | 1f587329 | blueswir1 | /* stdfq, store floating point queue */
|
4520 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
4521 | 1f587329 | blueswir1 | goto illegal_insn;
|
4522 | 1f587329 | blueswir1 | #else
|
4523 | 0f8a249a | blueswir1 | if (!supervisor(dc))
|
4524 | 0f8a249a | blueswir1 | goto priv_insn;
|
4525 | 6ae20372 | blueswir1 | if (gen_trap_ifnofpu(dc, cpu_cond))
|
4526 | 0f8a249a | blueswir1 | goto jmp_insn;
|
4527 | 0f8a249a | blueswir1 | goto nfq_insn;
|
4528 | 0f8a249a | blueswir1 | #endif
|
4529 | 1f587329 | blueswir1 | #endif
|
4530 | b89e94af | Blue Swirl | case 0x27: /* stdf, store double fpreg */ |
4531 | 2ea815ca | blueswir1 | { |
4532 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4533 | 2ea815ca | blueswir1 | |
4534 | 2ea815ca | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4535 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(dc->mem_idx); |
4536 | a7812ae4 | pbrook | gen_helper_stdf(cpu_addr, r_const); |
4537 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4538 | 2ea815ca | blueswir1 | } |
4539 | 0f8a249a | blueswir1 | break;
|
4540 | 0f8a249a | blueswir1 | default:
|
4541 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4542 | 0f8a249a | blueswir1 | } |
4543 | 0f8a249a | blueswir1 | } else if (xop > 0x33 && xop < 0x3f) { |
4544 | c2bc0e38 | blueswir1 | save_state(dc, cpu_cond); |
4545 | 0f8a249a | blueswir1 | switch (xop) {
|
4546 | a4d17f19 | blueswir1 | #ifdef TARGET_SPARC64
|
4547 | 0f8a249a | blueswir1 | case 0x34: /* V9 stfa */ |
4548 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 4, rd);
|
4549 | 0f8a249a | blueswir1 | break;
|
4550 | 1f587329 | blueswir1 | case 0x36: /* V9 stqfa */ |
4551 | 2ea815ca | blueswir1 | { |
4552 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4553 | 2ea815ca | blueswir1 | |
4554 | 2ea815ca | blueswir1 | CHECK_FPU_FEATURE(dc, FLOAT128); |
4555 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(7);
|
4556 | a7812ae4 | pbrook | gen_helper_check_align(cpu_addr, r_const); |
4557 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4558 | 2ea815ca | blueswir1 | gen_op_load_fpr_QT0(QFPREG(rd)); |
4559 | 2ea815ca | blueswir1 | gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
|
4560 | 2ea815ca | blueswir1 | } |
4561 | 1f587329 | blueswir1 | break;
|
4562 | 0f8a249a | blueswir1 | case 0x37: /* V9 stdfa */ |
4563 | 3391c818 | blueswir1 | gen_op_load_fpr_DT0(DFPREG(rd)); |
4564 | 6ae20372 | blueswir1 | gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
|
4565 | 0f8a249a | blueswir1 | break;
|
4566 | 0f8a249a | blueswir1 | case 0x3c: /* V9 casa */ |
4567 | 71817e48 | blueswir1 | gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4568 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4569 | 0f8a249a | blueswir1 | break;
|
4570 | 0f8a249a | blueswir1 | case 0x3e: /* V9 casxa */ |
4571 | 71817e48 | blueswir1 | gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd); |
4572 | 6ae20372 | blueswir1 | gen_movl_TN_reg(rd, cpu_val); |
4573 | 0f8a249a | blueswir1 | break;
|
4574 | a4d17f19 | blueswir1 | #else
|
4575 | 0f8a249a | blueswir1 | case 0x34: /* stc */ |
4576 | 0f8a249a | blueswir1 | case 0x35: /* stcsr */ |
4577 | 0f8a249a | blueswir1 | case 0x36: /* stdcq */ |
4578 | 0f8a249a | blueswir1 | case 0x37: /* stdc */ |
4579 | 0f8a249a | blueswir1 | goto ncp_insn;
|
4580 | 0f8a249a | blueswir1 | #endif
|
4581 | 0f8a249a | blueswir1 | default:
|
4582 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4583 | 0f8a249a | blueswir1 | } |
4584 | dc1a6971 | Blue Swirl | } else
|
4585 | 0f8a249a | blueswir1 | goto illegal_insn;
|
4586 | 0f8a249a | blueswir1 | } |
4587 | 0f8a249a | blueswir1 | break;
|
4588 | cf495bcf | bellard | } |
4589 | cf495bcf | bellard | /* default case for non jump instructions */
|
4590 | 72cbca10 | bellard | if (dc->npc == DYNAMIC_PC) {
|
4591 | 0f8a249a | blueswir1 | dc->pc = DYNAMIC_PC; |
4592 | 0f8a249a | blueswir1 | gen_op_next_insn(); |
4593 | 72cbca10 | bellard | } else if (dc->npc == JUMP_PC) { |
4594 | 72cbca10 | bellard | /* we can do a static jump */
|
4595 | 6ae20372 | blueswir1 | gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); |
4596 | 72cbca10 | bellard | dc->is_br = 1;
|
4597 | 72cbca10 | bellard | } else {
|
4598 | 0f8a249a | blueswir1 | dc->pc = dc->npc; |
4599 | 0f8a249a | blueswir1 | dc->npc = dc->npc + 4;
|
4600 | cf495bcf | bellard | } |
4601 | e80cfcfc | bellard | jmp_insn:
|
4602 | cf495bcf | bellard | return;
|
4603 | cf495bcf | bellard | illegal_insn:
|
4604 | 2ea815ca | blueswir1 | { |
4605 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4606 | 2ea815ca | blueswir1 | |
4607 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4608 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_ILL_INSN); |
4609 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4610 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4611 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4612 | 2ea815ca | blueswir1 | } |
4613 | e8af50a3 | bellard | return;
|
4614 | 64a88d5d | blueswir1 | unimp_flush:
|
4615 | 2ea815ca | blueswir1 | { |
4616 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4617 | 2ea815ca | blueswir1 | |
4618 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4619 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_UNIMP_FLUSH); |
4620 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4621 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4622 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4623 | 2ea815ca | blueswir1 | } |
4624 | 64a88d5d | blueswir1 | return;
|
4625 | e80cfcfc | bellard | #if !defined(CONFIG_USER_ONLY)
|
4626 | e8af50a3 | bellard | priv_insn:
|
4627 | 2ea815ca | blueswir1 | { |
4628 | a7812ae4 | pbrook | TCGv_i32 r_const; |
4629 | 2ea815ca | blueswir1 | |
4630 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4631 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_PRIV_INSN); |
4632 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4633 | a7812ae4 | pbrook | tcg_temp_free_i32(r_const); |
4634 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4635 | 2ea815ca | blueswir1 | } |
4636 | e80cfcfc | bellard | return;
|
4637 | 64a88d5d | blueswir1 | #endif
|
4638 | e80cfcfc | bellard | nfpu_insn:
|
4639 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4640 | e80cfcfc | bellard | gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); |
4641 | e80cfcfc | bellard | dc->is_br = 1;
|
4642 | fcc72045 | blueswir1 | return;
|
4643 | 64a88d5d | blueswir1 | #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
|
4644 | 9143e598 | blueswir1 | nfq_insn:
|
4645 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4646 | 9143e598 | blueswir1 | gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); |
4647 | 9143e598 | blueswir1 | dc->is_br = 1;
|
4648 | 9143e598 | blueswir1 | return;
|
4649 | 9143e598 | blueswir1 | #endif
|
4650 | fcc72045 | blueswir1 | #ifndef TARGET_SPARC64
|
4651 | fcc72045 | blueswir1 | ncp_insn:
|
4652 | 2ea815ca | blueswir1 | { |
4653 | 2ea815ca | blueswir1 | TCGv r_const; |
4654 | 2ea815ca | blueswir1 | |
4655 | 2ea815ca | blueswir1 | save_state(dc, cpu_cond); |
4656 | 2ea815ca | blueswir1 | r_const = tcg_const_i32(TT_NCP_INSN); |
4657 | a7812ae4 | pbrook | gen_helper_raise_exception(r_const); |
4658 | 2ea815ca | blueswir1 | tcg_temp_free(r_const); |
4659 | 2ea815ca | blueswir1 | dc->is_br = 1;
|
4660 | 2ea815ca | blueswir1 | } |
4661 | fcc72045 | blueswir1 | return;
|
4662 | fcc72045 | blueswir1 | #endif
|
4663 | 7a3f1944 | bellard | } |
4664 | 7a3f1944 | bellard | |
4665 | 2cfc5f17 | ths | static inline void gen_intermediate_code_internal(TranslationBlock * tb, |
4666 | 2cfc5f17 | ths | int spc, CPUSPARCState *env)
|
4667 | 7a3f1944 | bellard | { |
4668 | 72cbca10 | bellard | target_ulong pc_start, last_pc; |
4669 | cf495bcf | bellard | uint16_t *gen_opc_end; |
4670 | cf495bcf | bellard | DisasContext dc1, *dc = &dc1; |
4671 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
4672 | e8af50a3 | bellard | int j, lj = -1; |
4673 | 2e70f6ef | pbrook | int num_insns;
|
4674 | 2e70f6ef | pbrook | int max_insns;
|
4675 | cf495bcf | bellard | |
4676 | cf495bcf | bellard | memset(dc, 0, sizeof(DisasContext)); |
4677 | cf495bcf | bellard | dc->tb = tb; |
4678 | 72cbca10 | bellard | pc_start = tb->pc; |
4679 | cf495bcf | bellard | dc->pc = pc_start; |
4680 | e80cfcfc | bellard | last_pc = dc->pc; |
4681 | 72cbca10 | bellard | dc->npc = (target_ulong) tb->cs_base; |
4682 | 8393617c | Blue Swirl | dc->cc_op = CC_OP_DYNAMIC; |
4683 | 6f27aba6 | blueswir1 | dc->mem_idx = cpu_mmu_index(env); |
4684 | 5578ceab | blueswir1 | dc->def = env->def; |
4685 | 5578ceab | blueswir1 | if ((dc->def->features & CPU_FEATURE_FLOAT))
|
4686 | 64a88d5d | blueswir1 | dc->fpu_enabled = cpu_fpu_enabled(env); |
4687 | 5578ceab | blueswir1 | else
|
4688 | 64a88d5d | blueswir1 | dc->fpu_enabled = 0;
|
4689 | 2cade6a3 | blueswir1 | #ifdef TARGET_SPARC64
|
4690 | 2cade6a3 | blueswir1 | dc->address_mask_32bit = env->pstate & PS_AM; |
4691 | 2cade6a3 | blueswir1 | #endif
|
4692 | cf495bcf | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
4693 | cf495bcf | bellard | |
4694 | a7812ae4 | pbrook | cpu_tmp0 = tcg_temp_new(); |
4695 | a7812ae4 | pbrook | cpu_tmp32 = tcg_temp_new_i32(); |
4696 | a7812ae4 | pbrook | cpu_tmp64 = tcg_temp_new_i64(); |
4697 | d987963a | blueswir1 | |
4698 | a7812ae4 | pbrook | cpu_dst = tcg_temp_local_new(); |
4699 | d987963a | blueswir1 | |
4700 | d987963a | blueswir1 | // loads and stores
|
4701 | a7812ae4 | pbrook | cpu_val = tcg_temp_local_new(); |
4702 | a7812ae4 | pbrook | cpu_addr = tcg_temp_local_new(); |
4703 | 1a2fb1c0 | blueswir1 | |
4704 | 2e70f6ef | pbrook | num_insns = 0;
|
4705 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
4706 | 2e70f6ef | pbrook | if (max_insns == 0) |
4707 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
4708 | 2e70f6ef | pbrook | gen_icount_start(); |
4709 | cf495bcf | bellard | do {
|
4710 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
4711 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
4712 | a1d1bb31 | aliguori | if (bp->pc == dc->pc) {
|
4713 | 0f8a249a | blueswir1 | if (dc->pc != pc_start)
|
4714 | 6ae20372 | blueswir1 | save_state(dc, cpu_cond); |
4715 | a7812ae4 | pbrook | gen_helper_debug(); |
4716 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4717 | 0f8a249a | blueswir1 | dc->is_br = 1;
|
4718 | e80cfcfc | bellard | goto exit_gen_loop;
|
4719 | e8af50a3 | bellard | } |
4720 | e8af50a3 | bellard | } |
4721 | e8af50a3 | bellard | } |
4722 | e8af50a3 | bellard | if (spc) {
|
4723 | 93fcfe39 | aliguori | qemu_log("Search PC...\n");
|
4724 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4725 | e8af50a3 | bellard | if (lj < j) {
|
4726 | e8af50a3 | bellard | lj++; |
4727 | e8af50a3 | bellard | while (lj < j)
|
4728 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4729 | e8af50a3 | bellard | gen_opc_pc[lj] = dc->pc; |
4730 | e8af50a3 | bellard | gen_opc_npc[lj] = dc->npc; |
4731 | e8af50a3 | bellard | gen_opc_instr_start[lj] = 1;
|
4732 | 2e70f6ef | pbrook | gen_opc_icount[lj] = num_insns; |
4733 | e8af50a3 | bellard | } |
4734 | e8af50a3 | bellard | } |
4735 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
4736 | 2e70f6ef | pbrook | gen_io_start(); |
4737 | 0f8a249a | blueswir1 | last_pc = dc->pc; |
4738 | 0f8a249a | blueswir1 | disas_sparc_insn(dc); |
4739 | 2e70f6ef | pbrook | num_insns++; |
4740 | 0f8a249a | blueswir1 | |
4741 | 0f8a249a | blueswir1 | if (dc->is_br)
|
4742 | 0f8a249a | blueswir1 | break;
|
4743 | 0f8a249a | blueswir1 | /* if the next PC is different, we abort now */
|
4744 | 0f8a249a | blueswir1 | if (dc->pc != (last_pc + 4)) |
4745 | 0f8a249a | blueswir1 | break;
|
4746 | d39c0b99 | bellard | /* if we reach a page boundary, we stop generation so that the
|
4747 | d39c0b99 | bellard | PC of a TT_TFAULT exception is always in the right page */
|
4748 | d39c0b99 | bellard | if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0) |
4749 | d39c0b99 | bellard | break;
|
4750 | e80cfcfc | bellard | /* if single step mode, we generate only one instruction and
|
4751 | e80cfcfc | bellard | generate an exception */
|
4752 | 1b530a6d | aurel32 | if (env->singlestep_enabled || singlestep) {
|
4753 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4754 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4755 | e80cfcfc | bellard | break;
|
4756 | e80cfcfc | bellard | } |
4757 | cf495bcf | bellard | } while ((gen_opc_ptr < gen_opc_end) &&
|
4758 | 2e70f6ef | pbrook | (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
|
4759 | 2e70f6ef | pbrook | num_insns < max_insns); |
4760 | e80cfcfc | bellard | |
4761 | e80cfcfc | bellard | exit_gen_loop:
|
4762 | d987963a | blueswir1 | tcg_temp_free(cpu_addr); |
4763 | 3f0436fe | blueswir1 | tcg_temp_free(cpu_val); |
4764 | d987963a | blueswir1 | tcg_temp_free(cpu_dst); |
4765 | a7812ae4 | pbrook | tcg_temp_free_i64(cpu_tmp64); |
4766 | a7812ae4 | pbrook | tcg_temp_free_i32(cpu_tmp32); |
4767 | 2ea815ca | blueswir1 | tcg_temp_free(cpu_tmp0); |
4768 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
4769 | 2e70f6ef | pbrook | gen_io_end(); |
4770 | 72cbca10 | bellard | if (!dc->is_br) {
|
4771 | 5fafdf24 | ths | if (dc->pc != DYNAMIC_PC &&
|
4772 | 72cbca10 | bellard | (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) { |
4773 | 72cbca10 | bellard | /* static PC and NPC: we can use direct chaining */
|
4774 | 2f5680ee | blueswir1 | gen_goto_tb(dc, 0, dc->pc, dc->npc);
|
4775 | 72cbca10 | bellard | } else {
|
4776 | 72cbca10 | bellard | if (dc->pc != DYNAMIC_PC)
|
4777 | 2f5680ee | blueswir1 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
4778 | 6ae20372 | blueswir1 | save_npc(dc, cpu_cond); |
4779 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
4780 | 72cbca10 | bellard | } |
4781 | 72cbca10 | bellard | } |
4782 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
4783 | cf495bcf | bellard | *gen_opc_ptr = INDEX_op_end; |
4784 | e8af50a3 | bellard | if (spc) {
|
4785 | e8af50a3 | bellard | j = gen_opc_ptr - gen_opc_buf; |
4786 | e8af50a3 | bellard | lj++; |
4787 | e8af50a3 | bellard | while (lj <= j)
|
4788 | e8af50a3 | bellard | gen_opc_instr_start[lj++] = 0;
|
4789 | e8af50a3 | bellard | #if 0
|
4790 | 93fcfe39 | aliguori | log_page_dump();
|
4791 | e8af50a3 | bellard | #endif
|
4792 | c3278b7b | bellard | gen_opc_jump_pc[0] = dc->jump_pc[0]; |
4793 | c3278b7b | bellard | gen_opc_jump_pc[1] = dc->jump_pc[1]; |
4794 | e8af50a3 | bellard | } else {
|
4795 | e80cfcfc | bellard | tb->size = last_pc + 4 - pc_start;
|
4796 | 2e70f6ef | pbrook | tb->icount = num_insns; |
4797 | e8af50a3 | bellard | } |
4798 | 7a3f1944 | bellard | #ifdef DEBUG_DISAS
|
4799 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
4800 | 93fcfe39 | aliguori | qemu_log("--------------\n");
|
4801 | 93fcfe39 | aliguori | qemu_log("IN: %s\n", lookup_symbol(pc_start));
|
4802 | 93fcfe39 | aliguori | log_target_disas(pc_start, last_pc + 4 - pc_start, 0); |
4803 | 93fcfe39 | aliguori | qemu_log("\n");
|
4804 | cf495bcf | bellard | } |
4805 | 7a3f1944 | bellard | #endif
|
4806 | 7a3f1944 | bellard | } |
4807 | 7a3f1944 | bellard | |
4808 | 2cfc5f17 | ths | void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
|
4809 | 7a3f1944 | bellard | { |
4810 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 0, env);
|
4811 | 7a3f1944 | bellard | } |
4812 | 7a3f1944 | bellard | |
4813 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
|
4814 | 7a3f1944 | bellard | { |
4815 | 2cfc5f17 | ths | gen_intermediate_code_internal(tb, 1, env);
|
4816 | 7a3f1944 | bellard | } |
4817 | 7a3f1944 | bellard | |
4818 | c48fcb47 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env)
|
4819 | e80cfcfc | bellard | { |
4820 | f5069b26 | blueswir1 | unsigned int i; |
4821 | c48fcb47 | blueswir1 | static int inited; |
4822 | f5069b26 | blueswir1 | static const char * const gregnames[8] = { |
4823 | f5069b26 | blueswir1 | NULL, // g0 not used |
4824 | f5069b26 | blueswir1 | "g1",
|
4825 | f5069b26 | blueswir1 | "g2",
|
4826 | f5069b26 | blueswir1 | "g3",
|
4827 | f5069b26 | blueswir1 | "g4",
|
4828 | f5069b26 | blueswir1 | "g5",
|
4829 | f5069b26 | blueswir1 | "g6",
|
4830 | f5069b26 | blueswir1 | "g7",
|
4831 | f5069b26 | blueswir1 | }; |
4832 | 714547bb | blueswir1 | static const char * const fregnames[64] = { |
4833 | 714547bb | blueswir1 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
4834 | 714547bb | blueswir1 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
4835 | 714547bb | blueswir1 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
4836 | 714547bb | blueswir1 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
4837 | 714547bb | blueswir1 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
4838 | 714547bb | blueswir1 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
4839 | 714547bb | blueswir1 | "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
4840 | 714547bb | blueswir1 | "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
4841 | 714547bb | blueswir1 | }; |
4842 | aaed909a | bellard | |
4843 | 1a2fb1c0 | blueswir1 | /* init various static tables */
|
4844 | 1a2fb1c0 | blueswir1 | if (!inited) {
|
4845 | 1a2fb1c0 | blueswir1 | inited = 1;
|
4846 | 1a2fb1c0 | blueswir1 | |
4847 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
4848 | a7812ae4 | pbrook | cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0, |
4849 | a7812ae4 | pbrook | offsetof(CPUState, regwptr), |
4850 | a7812ae4 | pbrook | "regwptr");
|
4851 | 1a2fb1c0 | blueswir1 | #ifdef TARGET_SPARC64
|
4852 | a7812ae4 | pbrook | cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc), |
4853 | a7812ae4 | pbrook | "xcc");
|
4854 | a7812ae4 | pbrook | cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi), |
4855 | a7812ae4 | pbrook | "asi");
|
4856 | a7812ae4 | pbrook | cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs), |
4857 | a7812ae4 | pbrook | "fprs");
|
4858 | a7812ae4 | pbrook | cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr), |
4859 | 255e1fcb | blueswir1 | "gsr");
|
4860 | a7812ae4 | pbrook | cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4861 | 255e1fcb | blueswir1 | offsetof(CPUState, tick_cmpr), |
4862 | 255e1fcb | blueswir1 | "tick_cmpr");
|
4863 | a7812ae4 | pbrook | cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4864 | 255e1fcb | blueswir1 | offsetof(CPUState, stick_cmpr), |
4865 | 255e1fcb | blueswir1 | "stick_cmpr");
|
4866 | a7812ae4 | pbrook | cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0, |
4867 | 255e1fcb | blueswir1 | offsetof(CPUState, hstick_cmpr), |
4868 | 255e1fcb | blueswir1 | "hstick_cmpr");
|
4869 | a7812ae4 | pbrook | cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp), |
4870 | 255e1fcb | blueswir1 | "hintp");
|
4871 | a7812ae4 | pbrook | cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba), |
4872 | a7812ae4 | pbrook | "htba");
|
4873 | a7812ae4 | pbrook | cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver), |
4874 | a7812ae4 | pbrook | "hver");
|
4875 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new(TCG_AREG0, |
4876 | 255e1fcb | blueswir1 | offsetof(CPUState, ssr), "ssr");
|
4877 | a7812ae4 | pbrook | cpu_ver = tcg_global_mem_new(TCG_AREG0, |
4878 | 255e1fcb | blueswir1 | offsetof(CPUState, version), "ver");
|
4879 | a7812ae4 | pbrook | cpu_softint = tcg_global_mem_new_i32(TCG_AREG0, |
4880 | a7812ae4 | pbrook | offsetof(CPUState, softint), |
4881 | a7812ae4 | pbrook | "softint");
|
4882 | 255e1fcb | blueswir1 | #else
|
4883 | a7812ae4 | pbrook | cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim), |
4884 | 255e1fcb | blueswir1 | "wim");
|
4885 | 1a2fb1c0 | blueswir1 | #endif
|
4886 | a7812ae4 | pbrook | cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond), |
4887 | 77f193da | blueswir1 | "cond");
|
4888 | a7812ae4 | pbrook | cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), |
4889 | dc99a3f2 | blueswir1 | "cc_src");
|
4890 | a7812ae4 | pbrook | cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, |
4891 | d9bdab86 | blueswir1 | offsetof(CPUState, cc_src2), |
4892 | d9bdab86 | blueswir1 | "cc_src2");
|
4893 | a7812ae4 | pbrook | cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), |
4894 | dc99a3f2 | blueswir1 | "cc_dst");
|
4895 | 8393617c | Blue Swirl | cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op), |
4896 | 8393617c | Blue Swirl | "cc_op");
|
4897 | a7812ae4 | pbrook | cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr), |
4898 | a7812ae4 | pbrook | "psr");
|
4899 | a7812ae4 | pbrook | cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr), |
4900 | 87e92502 | blueswir1 | "fsr");
|
4901 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc), |
4902 | 48d5c82b | blueswir1 | "pc");
|
4903 | a7812ae4 | pbrook | cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc), |
4904 | a7812ae4 | pbrook | "npc");
|
4905 | a7812ae4 | pbrook | cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
|
4906 | 255e1fcb | blueswir1 | #ifndef CONFIG_USER_ONLY
|
4907 | a7812ae4 | pbrook | cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr), |
4908 | 255e1fcb | blueswir1 | "tbr");
|
4909 | 255e1fcb | blueswir1 | #endif
|
4910 | f5069b26 | blueswir1 | for (i = 1; i < 8; i++) |
4911 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0, |
4912 | f5069b26 | blueswir1 | offsetof(CPUState, gregs[i]), |
4913 | f5069b26 | blueswir1 | gregnames[i]); |
4914 | 714547bb | blueswir1 | for (i = 0; i < TARGET_FPREGS; i++) |
4915 | a7812ae4 | pbrook | cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, |
4916 | a7812ae4 | pbrook | offsetof(CPUState, fpr[i]), |
4917 | a7812ae4 | pbrook | fregnames[i]); |
4918 | 714547bb | blueswir1 | |
4919 | c9e03d8f | blueswir1 | /* register helpers */
|
4920 | c9e03d8f | blueswir1 | |
4921 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
4922 | c9e03d8f | blueswir1 | #include "helper.h" |
4923 | 1a2fb1c0 | blueswir1 | } |
4924 | 658138bc | bellard | } |
4925 | d2856f1a | aurel32 | |
4926 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
4927 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
4928 | d2856f1a | aurel32 | { |
4929 | d2856f1a | aurel32 | target_ulong npc; |
4930 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
4931 | d2856f1a | aurel32 | npc = gen_opc_npc[pc_pos]; |
4932 | d2856f1a | aurel32 | if (npc == 1) { |
4933 | d2856f1a | aurel32 | /* dynamic NPC: already stored */
|
4934 | d2856f1a | aurel32 | } else if (npc == 2) { |
4935 | d7da2a10 | Blue Swirl | /* jump PC: use 'cond' and the jump targets of the translation */
|
4936 | d7da2a10 | Blue Swirl | if (env->cond) {
|
4937 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[0];
|
4938 | d7da2a10 | Blue Swirl | } else {
|
4939 | d2856f1a | aurel32 | env->npc = gen_opc_jump_pc[1];
|
4940 | d7da2a10 | Blue Swirl | } |
4941 | d2856f1a | aurel32 | } else {
|
4942 | d2856f1a | aurel32 | env->npc = npc; |
4943 | d2856f1a | aurel32 | } |
4944 | 14ed7adc | Igor Kovalenko | |
4945 | 14ed7adc | Igor Kovalenko | /* flush pending conditional evaluations before exposing cpu state */
|
4946 | 14ed7adc | Igor Kovalenko | if (CC_OP != CC_OP_FLAGS) {
|
4947 | 14ed7adc | Igor Kovalenko | helper_compute_psr(); |
4948 | 14ed7adc | Igor Kovalenko | } |
4949 | d2856f1a | aurel32 | } |