Revision d7f66b52

b/target-mips/translate.c
6099 6099 
            TCGv_i32 t1 = tcg_temp_new_i32();
6100 6100 
            tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
6101 6101 
            tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
6102 
            tcg_gen_nor_i32(t0, t0, t1);
6102 
            tcg_gen_nand_i32(t0, t0, t1);
6103 6103 
            tcg_temp_free_i32(t1);
6104 6104 
            tcg_gen_andi_i32(t0, t0, 1);
6105 6105 
            tcg_gen_extu_i32_tl(bcond, t0);
......
6123 6123 
            TCGv_i32 t1 = tcg_temp_new_i32();
6124 6124 
            tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
6125 6125 
            tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1));
6126 
            tcg_gen_or_i32(t0, t0, t1);
6126 
            tcg_gen_and_i32(t0, t0, t1);
6127 6127 
            tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
6128 
            tcg_gen_or_i32(t0, t0, t1);
6128 
            tcg_gen_and_i32(t0, t0, t1);
6129 6129 
            tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
6130 
            tcg_gen_nor_i32(t0, t0, t1);
6130 
            tcg_gen_nand_i32(t0, t0, t1);
6131 6131 
            tcg_temp_free_i32(t1);
6132 6132 
            tcg_gen_andi_i32(t0, t0, 1);
6133 6133 
            tcg_gen_extu_i32_tl(bcond, t0);

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