Revision d82287de

b/target-s390x/insn-data.def
15 15
    C(0xc208, AGFI,    RIL_a, EI,  r1, i2, r1, 0, add, adds64)
16 16
    C(0xeb7a, AGSI,    SIY,   GIE, m1_64, i2, new, m1_64, add, adds64)
17 17
    C(0xecd9, AGHIK,   RIE_d, DO,  r3, i2, r1, 0, add, adds64)
18
/* ADD HALFWORD */
19
    C(0x4a00, AH,      RX_a,  Z,   r1, m2_16s, new, r1_32, add, adds32)
20
    C(0xe37a, AHY,     RXY_a, LD,  r1, m2_16s, new, r1_32, add, adds32)
21
/* ADD HALFWORD IMMEDIATE */
22
    C(0xa70a, AHI,     RI_a,  Z,   r1, i2, new, r1_32, add, adds32)
23
    C(0xa70b, AGHI,    RI_a,  Z,   r1, i2, r1, 0, add, adds64)
24

  
18 25
/* ADD LOGICAL */
19 26
    C(0x1e00, ALR,     RR_a,  Z,   r1, r2, new, r1_32, add, addu32)
20 27
    C(0xb9fa, ALRK,    RRF_a, DO,  r2, r3, new, r1_32, add, addu32)
b/target-s390x/translate.c
559 559
    gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
560 560
}
561 561

  
562
static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
563
{
564
    gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr);
565
}
566

  
567 562
static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
568 563
                          TCGv_i64 vr)
569 564
{
......
2267 2262
                     int i2)
2268 2263
{
2269 2264
    TCGv_i64 tmp, tmp2;
2270
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
2265
    TCGv_i32 tmp32_1;
2271 2266
    int l1;
2272 2267

  
2273 2268
    LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
......
2342 2337
        store_reg(r1, tmp);
2343 2338
        tcg_temp_free_i64(tmp);
2344 2339
        break;
2345
    case 0xa: /* AHI     R1,I2     [RI] */
2346
        tmp32_1 = load_reg32(r1);
2347
        tmp32_2 = tcg_temp_new_i32();
2348
        tmp32_3 = tcg_const_i32(i2);
2349

  
2350
        if (i2 < 0) {
2351
            tcg_gen_subi_i32(tmp32_2, tmp32_1, -i2);
2352
        } else {
2353
            tcg_gen_add_i32(tmp32_2, tmp32_1, tmp32_3);
2354
        }
2355

  
2356
        store_reg32(r1, tmp32_2);
2357
        set_cc_add32(s, tmp32_1, tmp32_3, tmp32_2);
2358
        tcg_temp_free_i32(tmp32_1);
2359
        tcg_temp_free_i32(tmp32_2);
2360
        tcg_temp_free_i32(tmp32_3);
2361
        break;
2362
    case 0xb: /* aghi r1, i2 */
2363
        tmp = load_reg(r1);
2364
        tmp2 = tcg_const_i64(i2);
2365

  
2366
        if (i2 < 0) {
2367
            tcg_gen_subi_i64(regs[r1], tmp, -i2);
2368
        } else {
2369
            tcg_gen_add_i64(regs[r1], tmp, tmp2);
2370
        }
2371
        set_cc_add64(s, tmp, tmp2, regs[r1]);
2372
        tcg_temp_free_i64(tmp);
2373
        tcg_temp_free_i64(tmp2);
2374
        break;
2375 2340
    case 0xc: /* MHI     R1,I2     [RI] */
2376 2341
        tmp32_1 = load_reg32(r1);
2377 2342
        tcg_gen_muli_i32(tmp32_1, tmp32_1, i2);
......
5078 5043
    o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
5079 5044
}
5080 5045

  
5046
static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
5047
{
5048
    in2_a2(s, f, o);
5049
    tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
5050
}
5051

  
5081 5052
static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
5082 5053
{
5083 5054
    in2_a2(s, f, o);

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