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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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//#define DEBUG_PCI
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#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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#define PCI_COMMAND 0x04 /* 16 bits */ |
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
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#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
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#define PCI_MIN_GNT 0x3e /* 8 bits */ |
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#define PCI_MAX_LAT 0x3f /* 8 bits */ |
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/* just used for simpler irq handling. */
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#define PCI_DEVICES_MAX 64 |
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#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
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struct PCIBus {
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int bus_num;
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int devfn_min;
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void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level); |
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uint32_t config_reg; /* XXX: suppress */
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/* low level pic */
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SetIRQFunc *low_set_irq; |
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void *irq_opaque;
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PCIDevice *devices[256];
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}; |
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target_phys_addr_t pci_mem_base; |
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static int pci_irq_index; |
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static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
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static PCIBus *first_bus;
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static PCIBus *pci_register_bus(void) |
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{ |
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(PCIBus));
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first_bus = bus; |
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return bus;
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} |
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void generic_pci_save(QEMUFile* f, void *opaque) |
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{ |
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PCIDevice* s=(PCIDevice*)opaque; |
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qemu_put_buffer(f, s->config, 256);
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} |
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int generic_pci_load(QEMUFile* f, void *opaque, int version_id) |
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{ |
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PCIDevice* s=(PCIDevice*)opaque; |
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if (version_id != 1) |
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return -EINVAL;
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qemu_get_buffer(f, s->config, 256);
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return 0; |
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} |
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/* -1 for devfn means auto assign */
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PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
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int instance_size, int devfn, |
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PCIConfigReadFunc *config_read, |
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PCIConfigWriteFunc *config_write) |
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{ |
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PCIDevice *pci_dev; |
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if (pci_irq_index >= PCI_DEVICES_MAX)
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return NULL; |
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if (devfn < 0) { |
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for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
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if (!bus->devices[devfn])
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goto found;
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} |
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return NULL; |
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found: ;
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} |
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pci_dev = qemu_mallocz(instance_size); |
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if (!pci_dev)
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return NULL; |
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pci_dev->bus = bus; |
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pci_dev->devfn = devfn; |
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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if (!config_read)
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config_read = pci_default_read_config; |
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if (!config_write)
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config_write = pci_default_write_config; |
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pci_dev->config_read = config_read; |
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pci_dev->config_write = config_write; |
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pci_dev->irq_index = pci_irq_index++; |
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bus->devices[devfn] = pci_dev; |
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return pci_dev;
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} |
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void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func) |
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{ |
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PCIIORegion *r; |
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if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
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return;
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r = &pci_dev->io_regions[region_num]; |
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r->addr = -1;
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r->size = size; |
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r->type = type; |
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r->map_func = map_func; |
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} |
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static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
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{ |
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PCIBus *s = opaque; |
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s->config_reg = val; |
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} |
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static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
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{ |
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PCIBus *s = opaque; |
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return s->config_reg;
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} |
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static void pci_update_mappings(PCIDevice *d) |
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{ |
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PCIIORegion *r; |
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int cmd, i;
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uint32_t last_addr, new_addr, config_ofs; |
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
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for(i = 0; i < PCI_NUM_REGIONS; i++) { |
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r = &d->io_regions[i]; |
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if (i == PCI_ROM_SLOT) {
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config_ofs = 0x30;
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} else {
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config_ofs = 0x10 + i * 4; |
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} |
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if (r->size != 0) { |
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
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config_ofs)); |
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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if (last_addr <= new_addr || new_addr == 0 || |
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last_addr >= 0x10000) {
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new_addr = -1;
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} |
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} else {
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new_addr = -1;
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} |
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
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config_ofs)); |
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/* the ROM slot has a specific enable bit */
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if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
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goto no_mem_map;
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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/* XXX: as we cannot support really dynamic
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mappings, we handle specific values as invalid
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mappings. */
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if (last_addr <= new_addr || new_addr == 0 || |
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last_addr == -1) {
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new_addr = -1;
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} |
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} else {
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no_mem_map:
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new_addr = -1;
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} |
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} |
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/* now do the real mapping */
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if (new_addr != r->addr) {
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if (r->addr != -1) { |
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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int class;
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/* NOTE: specific hack for IDE in PC case:
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only one byte must be mapped. */
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class = d->config[0x0a] | (d->config[0x0b] << 8); |
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if (class == 0x0101 && r->size == 4) { |
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isa_unassign_ioport(r->addr + 2, 1); |
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} else {
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isa_unassign_ioport(r->addr, r->size); |
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} |
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} else {
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cpu_register_physical_memory(r->addr + pci_mem_base, |
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r->size, |
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IO_MEM_UNASSIGNED); |
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} |
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} |
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r->addr = new_addr; |
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if (r->addr != -1) { |
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r->map_func(d, i, r->addr, r->size, r->type); |
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} |
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} |
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} |
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} |
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} |
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uint32_t pci_default_read_config(PCIDevice *d, |
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uint32_t address, int len)
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{ |
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uint32_t val; |
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switch(len) {
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case 1: |
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val = d->config[address]; |
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break;
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case 2: |
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val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
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break;
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default:
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case 4: |
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val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
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break;
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} |
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return val;
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} |
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{ |
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int can_write, i;
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uint32_t end, addr; |
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if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
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(address >= 0x30 && address < 0x34))) { |
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PCIIORegion *r; |
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int reg;
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if ( address >= 0x30 ) { |
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reg = PCI_ROM_SLOT; |
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}else{
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reg = (address - 0x10) >> 2; |
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} |
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r = &d->io_regions[reg]; |
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if (r->size == 0) |
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goto default_config;
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/* compute the stored value */
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if (reg == PCI_ROM_SLOT) {
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/* keep ROM enable bit */
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val &= (~(r->size - 1)) | 1; |
270 |
} else {
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val &= ~(r->size - 1);
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val |= r->type; |
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} |
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*(uint32_t *)(d->config + address) = cpu_to_le32(val); |
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pci_update_mappings(d); |
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return;
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} |
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default_config:
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/* not efficient, but simple */
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addr = address; |
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for(i = 0; i < len; i++) { |
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/* default read/write accesses */
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switch(d->config[0x0e]) { |
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case 0x00: |
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case 0x80: |
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switch(addr) {
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case 0x00: |
288 |
case 0x01: |
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case 0x02: |
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case 0x03: |
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case 0x08: |
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case 0x09: |
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case 0x0a: |
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case 0x0b: |
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case 0x0e: |
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case 0x10 ... 0x27: /* base */ |
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case 0x30 ... 0x33: /* rom */ |
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case 0x3d: |
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can_write = 0;
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break;
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default:
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can_write = 1;
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break;
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} |
305 |
break;
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default:
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case 0x01: |
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switch(addr) {
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case 0x00: |
310 |
case 0x01: |
311 |
case 0x02: |
312 |
case 0x03: |
313 |
case 0x08: |
314 |
case 0x09: |
315 |
case 0x0a: |
316 |
case 0x0b: |
317 |
case 0x0e: |
318 |
case 0x38 ... 0x3b: /* rom */ |
319 |
case 0x3d: |
320 |
can_write = 0;
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break;
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default:
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323 |
can_write = 1;
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324 |
break;
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325 |
} |
326 |
break;
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327 |
} |
328 |
if (can_write) {
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d->config[addr] = val; |
330 |
} |
331 |
addr++; |
332 |
val >>= 8;
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} |
334 |
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end = address + len; |
336 |
if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
337 |
/* if the command register is modified, we must modify the mappings */
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pci_update_mappings(d); |
339 |
} |
340 |
} |
341 |
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342 |
static void pci_data_write(void *opaque, uint32_t addr, |
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uint32_t val, int len)
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344 |
{ |
345 |
PCIBus *s = opaque; |
346 |
PCIDevice *pci_dev; |
347 |
int config_addr, bus_num;
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348 |
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349 |
#if defined(DEBUG_PCI) && 0 |
350 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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s->config_reg, val, len); |
352 |
#endif
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353 |
if (!(s->config_reg & (1 << 31))) { |
354 |
return;
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355 |
} |
356 |
if ((s->config_reg & 0x3) != 0) { |
357 |
return;
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358 |
} |
359 |
bus_num = (s->config_reg >> 16) & 0xff; |
360 |
if (bus_num != 0) |
361 |
return;
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362 |
pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
363 |
if (!pci_dev)
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364 |
return;
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config_addr = (s->config_reg & 0xfc) | (addr & 3); |
366 |
#if defined(DEBUG_PCI)
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367 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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368 |
pci_dev->name, config_addr, val, len); |
369 |
#endif
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370 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
371 |
} |
372 |
|
373 |
static uint32_t pci_data_read(void *opaque, uint32_t addr, |
374 |
int len)
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375 |
{ |
376 |
PCIBus *s = opaque; |
377 |
PCIDevice *pci_dev; |
378 |
int config_addr, bus_num;
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379 |
uint32_t val; |
380 |
|
381 |
if (!(s->config_reg & (1 << 31))) |
382 |
goto fail;
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383 |
if ((s->config_reg & 0x3) != 0) |
384 |
goto fail;
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385 |
bus_num = (s->config_reg >> 16) & 0xff; |
386 |
if (bus_num != 0) |
387 |
goto fail;
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388 |
pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
389 |
if (!pci_dev) {
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390 |
fail:
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391 |
switch(len) {
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392 |
case 1: |
393 |
val = 0xff;
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394 |
break;
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395 |
case 2: |
396 |
val = 0xffff;
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397 |
break;
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398 |
default:
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399 |
case 4: |
400 |
val = 0xffffffff;
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401 |
break;
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402 |
} |
403 |
goto the_end;
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404 |
} |
405 |
config_addr = (s->config_reg & 0xfc) | (addr & 3); |
406 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
407 |
#if defined(DEBUG_PCI)
|
408 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
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409 |
pci_dev->name, config_addr, val, len); |
410 |
#endif
|
411 |
the_end:
|
412 |
#if defined(DEBUG_PCI) && 0 |
413 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
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414 |
s->config_reg, val, len); |
415 |
#endif
|
416 |
return val;
|
417 |
} |
418 |
|
419 |
static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
420 |
{ |
421 |
pci_data_write(opaque, addr, val, 1);
|
422 |
} |
423 |
|
424 |
static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
425 |
{ |
426 |
pci_data_write(opaque, addr, val, 2);
|
427 |
} |
428 |
|
429 |
static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
430 |
{ |
431 |
pci_data_write(opaque, addr, val, 4);
|
432 |
} |
433 |
|
434 |
static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
435 |
{ |
436 |
return pci_data_read(opaque, addr, 1); |
437 |
} |
438 |
|
439 |
static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
440 |
{ |
441 |
return pci_data_read(opaque, addr, 2); |
442 |
} |
443 |
|
444 |
static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
445 |
{ |
446 |
return pci_data_read(opaque, addr, 4); |
447 |
} |
448 |
|
449 |
/* i440FX PCI bridge */
|
450 |
|
451 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level); |
452 |
|
453 |
PCIBus *i440fx_init(void)
|
454 |
{ |
455 |
PCIBus *s; |
456 |
PCIDevice *d; |
457 |
|
458 |
s = pci_register_bus(); |
459 |
s->set_irq = piix3_set_irq; |
460 |
|
461 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
462 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
463 |
|
464 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
465 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
466 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
467 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
468 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
469 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
470 |
|
471 |
d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0, |
472 |
NULL, NULL); |
473 |
|
474 |
d->config[0x00] = 0x86; // vendor_id |
475 |
d->config[0x01] = 0x80; |
476 |
d->config[0x02] = 0x37; // device_id |
477 |
d->config[0x03] = 0x12; |
478 |
d->config[0x08] = 0x02; // revision |
479 |
d->config[0x0a] = 0x00; // class_sub = host2pci |
480 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
481 |
d->config[0x0e] = 0x00; // header_type |
482 |
return s;
|
483 |
} |
484 |
|
485 |
/* PIIX3 PCI to ISA bridge */
|
486 |
|
487 |
typedef struct PIIX3State { |
488 |
PCIDevice dev; |
489 |
} PIIX3State; |
490 |
|
491 |
PIIX3State *piix3_state; |
492 |
|
493 |
/* return the global irq number corresponding to a given device irq
|
494 |
pin. We could also use the bus number to have a more precise
|
495 |
mapping. */
|
496 |
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
497 |
{ |
498 |
int slot_addend;
|
499 |
slot_addend = (pci_dev->devfn >> 3) - 1; |
500 |
return (irq_num + slot_addend) & 3; |
501 |
} |
502 |
|
503 |
static inline int get_pci_irq_level(int irq_num) |
504 |
{ |
505 |
int pic_level;
|
506 |
#if (PCI_IRQ_WORDS == 2) |
507 |
pic_level = ((pci_irq_levels[irq_num][0] |
|
508 |
pci_irq_levels[irq_num][1]) != 0); |
509 |
#else
|
510 |
{ |
511 |
int i;
|
512 |
pic_level = 0;
|
513 |
for(i = 0; i < PCI_IRQ_WORDS; i++) { |
514 |
if (pci_irq_levels[irq_num][i]) {
|
515 |
pic_level = 1;
|
516 |
break;
|
517 |
} |
518 |
} |
519 |
} |
520 |
#endif
|
521 |
return pic_level;
|
522 |
} |
523 |
|
524 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
525 |
{ |
526 |
int irq_index, shift, pic_irq, pic_level;
|
527 |
uint32_t *p; |
528 |
|
529 |
irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
530 |
irq_index = pci_dev->irq_index; |
531 |
p = &pci_irq_levels[irq_num][irq_index >> 5];
|
532 |
shift = (irq_index & 0x1f);
|
533 |
*p = (*p & ~(1 << shift)) | (level << shift);
|
534 |
|
535 |
/* now we change the pic irq level according to the piix irq mappings */
|
536 |
/* XXX: optimize */
|
537 |
pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
538 |
if (pic_irq < 16) { |
539 |
/* the pic level is the logical OR of all the PCI irqs mapped
|
540 |
to it */
|
541 |
pic_level = 0;
|
542 |
if (pic_irq == piix3_state->dev.config[0x60]) |
543 |
pic_level |= get_pci_irq_level(0);
|
544 |
if (pic_irq == piix3_state->dev.config[0x61]) |
545 |
pic_level |= get_pci_irq_level(1);
|
546 |
if (pic_irq == piix3_state->dev.config[0x62]) |
547 |
pic_level |= get_pci_irq_level(2);
|
548 |
if (pic_irq == piix3_state->dev.config[0x63]) |
549 |
pic_level |= get_pci_irq_level(3);
|
550 |
pic_set_irq(pic_irq, pic_level); |
551 |
} |
552 |
} |
553 |
|
554 |
static void piix3_reset(PIIX3State *d) |
555 |
{ |
556 |
uint8_t *pci_conf = d->dev.config; |
557 |
|
558 |
pci_conf[0x04] = 0x07; // master, memory and I/O |
559 |
pci_conf[0x05] = 0x00; |
560 |
pci_conf[0x06] = 0x00; |
561 |
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
562 |
pci_conf[0x4c] = 0x4d; |
563 |
pci_conf[0x4e] = 0x03; |
564 |
pci_conf[0x4f] = 0x00; |
565 |
pci_conf[0x60] = 0x80; |
566 |
pci_conf[0x69] = 0x02; |
567 |
pci_conf[0x70] = 0x80; |
568 |
pci_conf[0x76] = 0x0c; |
569 |
pci_conf[0x77] = 0x0c; |
570 |
pci_conf[0x78] = 0x02; |
571 |
pci_conf[0x79] = 0x00; |
572 |
pci_conf[0x80] = 0x00; |
573 |
pci_conf[0x82] = 0x00; |
574 |
pci_conf[0xa0] = 0x08; |
575 |
pci_conf[0xa0] = 0x08; |
576 |
pci_conf[0xa2] = 0x00; |
577 |
pci_conf[0xa3] = 0x00; |
578 |
pci_conf[0xa4] = 0x00; |
579 |
pci_conf[0xa5] = 0x00; |
580 |
pci_conf[0xa6] = 0x00; |
581 |
pci_conf[0xa7] = 0x00; |
582 |
pci_conf[0xa8] = 0x0f; |
583 |
pci_conf[0xaa] = 0x00; |
584 |
pci_conf[0xab] = 0x00; |
585 |
pci_conf[0xac] = 0x00; |
586 |
pci_conf[0xae] = 0x00; |
587 |
} |
588 |
|
589 |
void piix3_init(PCIBus *bus)
|
590 |
{ |
591 |
PIIX3State *d; |
592 |
uint8_t *pci_conf; |
593 |
|
594 |
d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State), |
595 |
-1, NULL, NULL); |
596 |
register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d); |
597 |
|
598 |
piix3_state = d; |
599 |
pci_conf = d->dev.config; |
600 |
|
601 |
pci_conf[0x00] = 0x86; // Intel |
602 |
pci_conf[0x01] = 0x80; |
603 |
pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
604 |
pci_conf[0x03] = 0x70; |
605 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
606 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
607 |
pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
608 |
|
609 |
piix3_reset(d); |
610 |
} |
611 |
|
612 |
/* PREP pci init */
|
613 |
|
614 |
static inline void set_config(PCIBus *s, target_phys_addr_t addr) |
615 |
{ |
616 |
int devfn, i;
|
617 |
|
618 |
for(i = 0; i < 11; i++) { |
619 |
if ((addr & (1 << (11 + i))) != 0) |
620 |
break;
|
621 |
} |
622 |
devfn = ((addr >> 8) & 7) | (i << 3); |
623 |
s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8); |
624 |
} |
625 |
|
626 |
static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
627 |
{ |
628 |
PCIBus *s = opaque; |
629 |
set_config(s, addr); |
630 |
pci_data_write(s, addr, val, 1);
|
631 |
} |
632 |
|
633 |
static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
634 |
{ |
635 |
PCIBus *s = opaque; |
636 |
set_config(s, addr); |
637 |
#ifdef TARGET_WORDS_BIGENDIAN
|
638 |
val = bswap16(val); |
639 |
#endif
|
640 |
pci_data_write(s, addr, val, 2);
|
641 |
} |
642 |
|
643 |
static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
644 |
{ |
645 |
PCIBus *s = opaque; |
646 |
set_config(s, addr); |
647 |
#ifdef TARGET_WORDS_BIGENDIAN
|
648 |
val = bswap32(val); |
649 |
#endif
|
650 |
pci_data_write(s, addr, val, 4);
|
651 |
} |
652 |
|
653 |
static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
654 |
{ |
655 |
PCIBus *s = opaque; |
656 |
uint32_t val; |
657 |
set_config(s, addr); |
658 |
val = pci_data_read(s, addr, 1);
|
659 |
return val;
|
660 |
} |
661 |
|
662 |
static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
663 |
{ |
664 |
PCIBus *s = opaque; |
665 |
uint32_t val; |
666 |
set_config(s, addr); |
667 |
val = pci_data_read(s, addr, 2);
|
668 |
#ifdef TARGET_WORDS_BIGENDIAN
|
669 |
val = bswap16(val); |
670 |
#endif
|
671 |
return val;
|
672 |
} |
673 |
|
674 |
static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
675 |
{ |
676 |
PCIBus *s = opaque; |
677 |
uint32_t val; |
678 |
set_config(s, addr); |
679 |
val = pci_data_read(s, addr, 4);
|
680 |
#ifdef TARGET_WORDS_BIGENDIAN
|
681 |
val = bswap32(val); |
682 |
#endif
|
683 |
return val;
|
684 |
} |
685 |
|
686 |
static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
687 |
&PPC_PCIIO_writeb, |
688 |
&PPC_PCIIO_writew, |
689 |
&PPC_PCIIO_writel, |
690 |
}; |
691 |
|
692 |
static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
693 |
&PPC_PCIIO_readb, |
694 |
&PPC_PCIIO_readw, |
695 |
&PPC_PCIIO_readl, |
696 |
}; |
697 |
|
698 |
static void prep_set_irq(PCIDevice *d, int irq_num, int level) |
699 |
{ |
700 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to
|
701 |
set correctly for irq line field */
|
702 |
pic_set_irq(d->config[PCI_INTERRUPT_LINE], level); |
703 |
} |
704 |
|
705 |
PCIBus *pci_prep_init(void)
|
706 |
{ |
707 |
PCIBus *s; |
708 |
PCIDevice *d; |
709 |
int PPC_io_memory;
|
710 |
|
711 |
s = pci_register_bus(); |
712 |
s->set_irq = prep_set_irq; |
713 |
|
714 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
715 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
716 |
|
717 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
718 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
719 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
720 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
721 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
722 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
723 |
|
724 |
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
|
725 |
PPC_PCIIO_write, s); |
726 |
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
727 |
|
728 |
/* PCI host bridge */
|
729 |
d = pci_register_device(s, "PREP Host Bridge - Motorola Raven",
|
730 |
sizeof(PCIDevice), 0, NULL, NULL); |
731 |
d->config[0x00] = 0x57; // vendor_id : Motorola |
732 |
d->config[0x01] = 0x10; |
733 |
d->config[0x02] = 0x01; // device_id : Raven |
734 |
d->config[0x03] = 0x48; |
735 |
d->config[0x08] = 0x00; // revision |
736 |
d->config[0x0A] = 0x00; // class_sub = pci host |
737 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
738 |
d->config[0x0C] = 0x08; // cache_line_size |
739 |
d->config[0x0D] = 0x10; // latency_timer |
740 |
d->config[0x0E] = 0x00; // header_type |
741 |
d->config[0x34] = 0x00; // capabilities_pointer |
742 |
|
743 |
return s;
|
744 |
} |
745 |
|
746 |
|
747 |
/* Grackle PCI host */
|
748 |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
749 |
uint32_t val) |
750 |
{ |
751 |
PCIBus *s = opaque; |
752 |
#ifdef TARGET_WORDS_BIGENDIAN
|
753 |
val = bswap32(val); |
754 |
#endif
|
755 |
s->config_reg = val; |
756 |
} |
757 |
|
758 |
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
759 |
{ |
760 |
PCIBus *s = opaque; |
761 |
uint32_t val; |
762 |
|
763 |
val = s->config_reg; |
764 |
#ifdef TARGET_WORDS_BIGENDIAN
|
765 |
val = bswap32(val); |
766 |
#endif
|
767 |
return val;
|
768 |
} |
769 |
|
770 |
static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
|
771 |
&pci_grackle_config_writel, |
772 |
&pci_grackle_config_writel, |
773 |
&pci_grackle_config_writel, |
774 |
}; |
775 |
|
776 |
static CPUReadMemoryFunc *pci_grackle_config_read[] = {
|
777 |
&pci_grackle_config_readl, |
778 |
&pci_grackle_config_readl, |
779 |
&pci_grackle_config_readl, |
780 |
}; |
781 |
|
782 |
static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr, |
783 |
uint32_t val) |
784 |
{ |
785 |
PCIBus *s = opaque; |
786 |
pci_data_write(s, addr, val, 1);
|
787 |
} |
788 |
|
789 |
static void pci_grackle_writew (void *opaque, target_phys_addr_t addr, |
790 |
uint32_t val) |
791 |
{ |
792 |
PCIBus *s = opaque; |
793 |
#ifdef TARGET_WORDS_BIGENDIAN
|
794 |
val = bswap16(val); |
795 |
#endif
|
796 |
pci_data_write(s, addr, val, 2);
|
797 |
} |
798 |
|
799 |
static void pci_grackle_writel (void *opaque, target_phys_addr_t addr, |
800 |
uint32_t val) |
801 |
{ |
802 |
PCIBus *s = opaque; |
803 |
#ifdef TARGET_WORDS_BIGENDIAN
|
804 |
val = bswap32(val); |
805 |
#endif
|
806 |
pci_data_write(s, addr, val, 4);
|
807 |
} |
808 |
|
809 |
static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr) |
810 |
{ |
811 |
PCIBus *s = opaque; |
812 |
uint32_t val; |
813 |
val = pci_data_read(s, addr, 1);
|
814 |
return val;
|
815 |
} |
816 |
|
817 |
static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr) |
818 |
{ |
819 |
PCIBus *s = opaque; |
820 |
uint32_t val; |
821 |
val = pci_data_read(s, addr, 2);
|
822 |
#ifdef TARGET_WORDS_BIGENDIAN
|
823 |
val = bswap16(val); |
824 |
#endif
|
825 |
return val;
|
826 |
} |
827 |
|
828 |
static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr) |
829 |
{ |
830 |
PCIBus *s = opaque; |
831 |
uint32_t val; |
832 |
|
833 |
val = pci_data_read(s, addr, 4);
|
834 |
#ifdef TARGET_WORDS_BIGENDIAN
|
835 |
val = bswap32(val); |
836 |
#endif
|
837 |
return val;
|
838 |
} |
839 |
|
840 |
static CPUWriteMemoryFunc *pci_grackle_write[] = {
|
841 |
&pci_grackle_writeb, |
842 |
&pci_grackle_writew, |
843 |
&pci_grackle_writel, |
844 |
}; |
845 |
|
846 |
static CPUReadMemoryFunc *pci_grackle_read[] = {
|
847 |
&pci_grackle_readb, |
848 |
&pci_grackle_readw, |
849 |
&pci_grackle_readl, |
850 |
}; |
851 |
|
852 |
void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque) |
853 |
{ |
854 |
bus->low_set_irq = set_irq; |
855 |
bus->irq_opaque = irq_opaque; |
856 |
} |
857 |
|
858 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to
|
859 |
set correctly for irq line field */
|
860 |
static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level) |
861 |
{ |
862 |
PCIBus *s = d->bus; |
863 |
s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level); |
864 |
} |
865 |
|
866 |
PCIBus *pci_grackle_init(uint32_t base) |
867 |
{ |
868 |
PCIBus *s; |
869 |
PCIDevice *d; |
870 |
int pci_mem_config, pci_mem_data;
|
871 |
|
872 |
s = pci_register_bus(); |
873 |
s->set_irq = pci_set_irq_simple; |
874 |
|
875 |
pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
|
876 |
pci_grackle_config_write, s); |
877 |
pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
|
878 |
pci_grackle_write, s); |
879 |
cpu_register_physical_memory(base, 0x1000, pci_mem_config);
|
880 |
cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); |
881 |
d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice), |
882 |
0, NULL, NULL); |
883 |
d->config[0x00] = 0x57; // vendor_id |
884 |
d->config[0x01] = 0x10; |
885 |
d->config[0x02] = 0x02; // device_id |
886 |
d->config[0x03] = 0x00; |
887 |
d->config[0x08] = 0x00; // revision |
888 |
d->config[0x09] = 0x01; |
889 |
d->config[0x0a] = 0x00; // class_sub = host |
890 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
891 |
d->config[0x0e] = 0x00; // header_type |
892 |
|
893 |
d->config[0x18] = 0x00; // primary_bus |
894 |
d->config[0x19] = 0x01; // secondary_bus |
895 |
d->config[0x1a] = 0x00; // subordinate_bus |
896 |
d->config[0x1c] = 0x00; |
897 |
d->config[0x1d] = 0x00; |
898 |
|
899 |
d->config[0x20] = 0x00; // memory_base |
900 |
d->config[0x21] = 0x00; |
901 |
d->config[0x22] = 0x01; // memory_limit |
902 |
d->config[0x23] = 0x00; |
903 |
|
904 |
d->config[0x24] = 0x00; // prefetchable_memory_base |
905 |
d->config[0x25] = 0x00; |
906 |
d->config[0x26] = 0x00; // prefetchable_memory_limit |
907 |
d->config[0x27] = 0x00; |
908 |
|
909 |
#if 0
|
910 |
/* PCI2PCI bridge same values as PearPC - check this */
|
911 |
d->config[0x00] = 0x11; // vendor_id
|
912 |
d->config[0x01] = 0x10;
|
913 |
d->config[0x02] = 0x26; // device_id
|
914 |
d->config[0x03] = 0x00;
|
915 |
d->config[0x08] = 0x02; // revision
|
916 |
d->config[0x0a] = 0x04; // class_sub = pci2pci
|
917 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge
|
918 |
d->config[0x0e] = 0x01; // header_type
|
919 |
|
920 |
d->config[0x18] = 0x0; // primary_bus
|
921 |
d->config[0x19] = 0x1; // secondary_bus
|
922 |
d->config[0x1a] = 0x1; // subordinate_bus
|
923 |
d->config[0x1c] = 0x10; // io_base
|
924 |
d->config[0x1d] = 0x20; // io_limit
|
925 |
|
926 |
d->config[0x20] = 0x80; // memory_base
|
927 |
d->config[0x21] = 0x80;
|
928 |
d->config[0x22] = 0x90; // memory_limit
|
929 |
d->config[0x23] = 0x80;
|
930 |
|
931 |
d->config[0x24] = 0x00; // prefetchable_memory_base
|
932 |
d->config[0x25] = 0x84;
|
933 |
d->config[0x26] = 0x00; // prefetchable_memory_limit
|
934 |
d->config[0x27] = 0x85;
|
935 |
#endif
|
936 |
return s;
|
937 |
} |
938 |
|
939 |
/* Uninorth PCI host (for all Mac99 and newer machines */
|
940 |
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
941 |
uint32_t val) |
942 |
{ |
943 |
PCIBus *s = opaque; |
944 |
int i;
|
945 |
|
946 |
#ifdef TARGET_WORDS_BIGENDIAN
|
947 |
val = bswap32(val); |
948 |
#endif
|
949 |
|
950 |
for (i = 11; i < 32; i++) { |
951 |
if ((val & (1 << i)) != 0) |
952 |
break;
|
953 |
} |
954 |
#if 0
|
955 |
s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
|
956 |
#else
|
957 |
s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11); |
958 |
#endif
|
959 |
} |
960 |
|
961 |
static uint32_t pci_unin_main_config_readl (void *opaque, |
962 |
target_phys_addr_t addr) |
963 |
{ |
964 |
PCIBus *s = opaque; |
965 |
uint32_t val; |
966 |
int devfn;
|
967 |
|
968 |
devfn = (s->config_reg >> 8) & 0xFF; |
969 |
val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
970 |
#ifdef TARGET_WORDS_BIGENDIAN
|
971 |
val = bswap32(val); |
972 |
#endif
|
973 |
|
974 |
return val;
|
975 |
} |
976 |
|
977 |
static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
|
978 |
&pci_unin_main_config_writel, |
979 |
&pci_unin_main_config_writel, |
980 |
&pci_unin_main_config_writel, |
981 |
}; |
982 |
|
983 |
static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
|
984 |
&pci_unin_main_config_readl, |
985 |
&pci_unin_main_config_readl, |
986 |
&pci_unin_main_config_readl, |
987 |
}; |
988 |
|
989 |
static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr, |
990 |
uint32_t val) |
991 |
{ |
992 |
PCIBus *s = opaque; |
993 |
pci_data_write(s, addr & 7, val, 1); |
994 |
} |
995 |
|
996 |
static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr, |
997 |
uint32_t val) |
998 |
{ |
999 |
PCIBus *s = opaque; |
1000 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1001 |
val = bswap16(val); |
1002 |
#endif
|
1003 |
pci_data_write(s, addr & 7, val, 2); |
1004 |
} |
1005 |
|
1006 |
static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr, |
1007 |
uint32_t val) |
1008 |
{ |
1009 |
PCIBus *s = opaque; |
1010 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1011 |
val = bswap32(val); |
1012 |
#endif
|
1013 |
pci_data_write(s, addr & 7, val, 4); |
1014 |
} |
1015 |
|
1016 |
static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr) |
1017 |
{ |
1018 |
PCIBus *s = opaque; |
1019 |
uint32_t val; |
1020 |
|
1021 |
val = pci_data_read(s, addr & 7, 1); |
1022 |
|
1023 |
return val;
|
1024 |
} |
1025 |
|
1026 |
static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr) |
1027 |
{ |
1028 |
PCIBus *s = opaque; |
1029 |
uint32_t val; |
1030 |
|
1031 |
val = pci_data_read(s, addr & 7, 2); |
1032 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1033 |
val = bswap16(val); |
1034 |
#endif
|
1035 |
|
1036 |
return val;
|
1037 |
} |
1038 |
|
1039 |
static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr) |
1040 |
{ |
1041 |
PCIBus *s = opaque; |
1042 |
uint32_t val; |
1043 |
|
1044 |
val = pci_data_read(s, addr, 4);
|
1045 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1046 |
val = bswap32(val); |
1047 |
#endif
|
1048 |
|
1049 |
return val;
|
1050 |
} |
1051 |
|
1052 |
static CPUWriteMemoryFunc *pci_unin_main_write[] = {
|
1053 |
&pci_unin_main_writeb, |
1054 |
&pci_unin_main_writew, |
1055 |
&pci_unin_main_writel, |
1056 |
}; |
1057 |
|
1058 |
static CPUReadMemoryFunc *pci_unin_main_read[] = {
|
1059 |
&pci_unin_main_readb, |
1060 |
&pci_unin_main_readw, |
1061 |
&pci_unin_main_readl, |
1062 |
}; |
1063 |
|
1064 |
#if 0
|
1065 |
|
1066 |
static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
|
1067 |
uint32_t val)
|
1068 |
{
|
1069 |
PCIBus *s = opaque;
|
1070 |
|
1071 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1072 |
val = bswap32(val);
|
1073 |
#endif
|
1074 |
s->config_reg = 0x80000000 | (val & ~0x00000001); |
1075 |
} |
1076 |
|
1077 |
static uint32_t pci_unin_config_readl (void *opaque, |
1078 |
target_phys_addr_t addr) |
1079 |
{ |
1080 |
PCIBus *s = opaque; |
1081 |
uint32_t val; |
1082 |
|
1083 |
val = (s->config_reg | 0x00000001) & ~0x80000000; |
1084 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1085 |
val = bswap32(val); |
1086 |
#endif
|
1087 |
|
1088 |
return val;
|
1089 |
} |
1090 |
|
1091 |
static CPUWriteMemoryFunc *pci_unin_config_write[] = {
|
1092 |
&pci_unin_config_writel, |
1093 |
&pci_unin_config_writel, |
1094 |
&pci_unin_config_writel, |
1095 |
}; |
1096 |
|
1097 |
static CPUReadMemoryFunc *pci_unin_config_read[] = {
|
1098 |
&pci_unin_config_readl, |
1099 |
&pci_unin_config_readl, |
1100 |
&pci_unin_config_readl, |
1101 |
}; |
1102 |
|
1103 |
static void pci_unin_writeb (void *opaque, target_phys_addr_t addr, |
1104 |
uint32_t val) |
1105 |
{ |
1106 |
PCIBus *s = opaque; |
1107 |
pci_data_write(s, addr & 3, val, 1); |
1108 |
} |
1109 |
|
1110 |
static void pci_unin_writew (void *opaque, target_phys_addr_t addr, |
1111 |
uint32_t val) |
1112 |
{ |
1113 |
PCIBus *s = opaque; |
1114 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1115 |
val = bswap16(val); |
1116 |
#endif
|
1117 |
pci_data_write(s, addr & 3, val, 2); |
1118 |
} |
1119 |
|
1120 |
static void pci_unin_writel (void *opaque, target_phys_addr_t addr, |
1121 |
uint32_t val) |
1122 |
{ |
1123 |
PCIBus *s = opaque; |
1124 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1125 |
val = bswap32(val); |
1126 |
#endif
|
1127 |
pci_data_write(s, addr & 3, val, 4); |
1128 |
} |
1129 |
|
1130 |
static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr) |
1131 |
{ |
1132 |
PCIBus *s = opaque; |
1133 |
uint32_t val; |
1134 |
|
1135 |
val = pci_data_read(s, addr & 3, 1); |
1136 |
|
1137 |
return val;
|
1138 |
} |
1139 |
|
1140 |
static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr) |
1141 |
{ |
1142 |
PCIBus *s = opaque; |
1143 |
uint32_t val; |
1144 |
|
1145 |
val = pci_data_read(s, addr & 3, 2); |
1146 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1147 |
val = bswap16(val); |
1148 |
#endif
|
1149 |
|
1150 |
return val;
|
1151 |
} |
1152 |
|
1153 |
static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr) |
1154 |
{ |
1155 |
PCIBus *s = opaque; |
1156 |
uint32_t val; |
1157 |
|
1158 |
val = pci_data_read(s, addr & 3, 4); |
1159 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1160 |
val = bswap32(val); |
1161 |
#endif
|
1162 |
|
1163 |
return val;
|
1164 |
} |
1165 |
|
1166 |
static CPUWriteMemoryFunc *pci_unin_write[] = {
|
1167 |
&pci_unin_writeb, |
1168 |
&pci_unin_writew, |
1169 |
&pci_unin_writel, |
1170 |
}; |
1171 |
|
1172 |
static CPUReadMemoryFunc *pci_unin_read[] = {
|
1173 |
&pci_unin_readb, |
1174 |
&pci_unin_readw, |
1175 |
&pci_unin_readl, |
1176 |
}; |
1177 |
#endif
|
1178 |
|
1179 |
PCIBus *pci_pmac_init(void)
|
1180 |
{ |
1181 |
PCIBus *s; |
1182 |
PCIDevice *d; |
1183 |
int pci_mem_config, pci_mem_data;
|
1184 |
|
1185 |
/* Use values found on a real PowerMac */
|
1186 |
/* Uninorth main bus */
|
1187 |
s = pci_register_bus(); |
1188 |
s->set_irq = pci_set_irq_simple; |
1189 |
|
1190 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
|
1191 |
pci_unin_main_config_write, s); |
1192 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
|
1193 |
pci_unin_main_write, s); |
1194 |
cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config); |
1195 |
cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
1196 |
s->devfn_min = 11 << 3; |
1197 |
d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice), |
1198 |
11 << 3, NULL, NULL); |
1199 |
d->config[0x00] = 0x6b; // vendor_id : Apple |
1200 |
d->config[0x01] = 0x10; |
1201 |
d->config[0x02] = 0x1F; // device_id |
1202 |
d->config[0x03] = 0x00; |
1203 |
d->config[0x08] = 0x00; // revision |
1204 |
d->config[0x0A] = 0x00; // class_sub = pci host |
1205 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
1206 |
d->config[0x0C] = 0x08; // cache_line_size |
1207 |
d->config[0x0D] = 0x10; // latency_timer |
1208 |
d->config[0x0E] = 0x00; // header_type |
1209 |
d->config[0x34] = 0x00; // capabilities_pointer |
1210 |
|
1211 |
#if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
|
1212 |
/* pci-to-pci bridge */
|
1213 |
d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
|
1214 |
NULL, NULL);
|
1215 |
d->config[0x00] = 0x11; // vendor_id : TI
|
1216 |
d->config[0x01] = 0x10;
|
1217 |
d->config[0x02] = 0x26; // device_id
|
1218 |
d->config[0x03] = 0x00;
|
1219 |
d->config[0x08] = 0x05; // revision
|
1220 |
d->config[0x0A] = 0x04; // class_sub = pci2pci
|
1221 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1222 |
d->config[0x0C] = 0x08; // cache_line_size
|
1223 |
d->config[0x0D] = 0x20; // latency_timer
|
1224 |
d->config[0x0E] = 0x01; // header_type
|
1225 |
|
1226 |
d->config[0x18] = 0x01; // primary_bus
|
1227 |
d->config[0x19] = 0x02; // secondary_bus
|
1228 |
d->config[0x1A] = 0x02; // subordinate_bus
|
1229 |
d->config[0x1B] = 0x20; // secondary_latency_timer
|
1230 |
d->config[0x1C] = 0x11; // io_base
|
1231 |
d->config[0x1D] = 0x01; // io_limit
|
1232 |
d->config[0x20] = 0x00; // memory_base
|
1233 |
d->config[0x21] = 0x80;
|
1234 |
d->config[0x22] = 0x00; // memory_limit
|
1235 |
d->config[0x23] = 0x80;
|
1236 |
d->config[0x24] = 0x01; // prefetchable_memory_base
|
1237 |
d->config[0x25] = 0x80;
|
1238 |
d->config[0x26] = 0xF1; // prefectchable_memory_limit
|
1239 |
d->config[0x27] = 0x7F;
|
1240 |
// d->config[0x34] = 0xdc // capabilities_pointer
|
1241 |
#endif
|
1242 |
#if 0 // XXX: not needed for now
|
1243 |
/* Uninorth AGP bus */
|
1244 |
s = &pci_bridge[1];
|
1245 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1246 |
pci_unin_config_write, s);
|
1247 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1248 |
pci_unin_write, s);
|
1249 |
cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
|
1250 |
cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
|
1251 |
|
1252 |
d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
|
1253 |
NULL, NULL);
|
1254 |
d->config[0x00] = 0x6b; // vendor_id : Apple
|
1255 |
d->config[0x01] = 0x10;
|
1256 |
d->config[0x02] = 0x20; // device_id
|
1257 |
d->config[0x03] = 0x00;
|
1258 |
d->config[0x08] = 0x00; // revision
|
1259 |
d->config[0x0A] = 0x00; // class_sub = pci host
|
1260 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1261 |
d->config[0x0C] = 0x08; // cache_line_size
|
1262 |
d->config[0x0D] = 0x10; // latency_timer
|
1263 |
d->config[0x0E] = 0x00; // header_type
|
1264 |
// d->config[0x34] = 0x80; // capabilities_pointer
|
1265 |
#endif
|
1266 |
|
1267 |
#if 0 // XXX: not needed for now
|
1268 |
/* Uninorth internal bus */
|
1269 |
s = &pci_bridge[2];
|
1270 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1271 |
pci_unin_config_write, s);
|
1272 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1273 |
pci_unin_write, s);
|
1274 |
cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
|
1275 |
cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
|
1276 |
|
1277 |
d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
|
1278 |
3, 11 << 3, NULL, NULL);
|
1279 |
d->config[0x00] = 0x6b; // vendor_id : Apple
|
1280 |
d->config[0x01] = 0x10;
|
1281 |
d->config[0x02] = 0x1E; // device_id
|
1282 |
d->config[0x03] = 0x00;
|
1283 |
d->config[0x08] = 0x00; // revision
|
1284 |
d->config[0x0A] = 0x00; // class_sub = pci host
|
1285 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1286 |
d->config[0x0C] = 0x08; // cache_line_size
|
1287 |
d->config[0x0D] = 0x10; // latency_timer
|
1288 |
d->config[0x0E] = 0x00; // header_type
|
1289 |
d->config[0x34] = 0x00; // capabilities_pointer
|
1290 |
#endif
|
1291 |
return s;
|
1292 |
} |
1293 |
|
1294 |
/* Ultrasparc APB PCI host */
|
1295 |
static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr, |
1296 |
uint32_t val) |
1297 |
{ |
1298 |
PCIBus *s = opaque; |
1299 |
int i;
|
1300 |
|
1301 |
for (i = 11; i < 32; i++) { |
1302 |
if ((val & (1 << i)) != 0) |
1303 |
break;
|
1304 |
} |
1305 |
s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11); |
1306 |
} |
1307 |
|
1308 |
static uint32_t pci_apb_config_readl (void *opaque, |
1309 |
target_phys_addr_t addr) |
1310 |
{ |
1311 |
PCIBus *s = opaque; |
1312 |
uint32_t val; |
1313 |
int devfn;
|
1314 |
|
1315 |
devfn = (s->config_reg >> 8) & 0xFF; |
1316 |
val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
1317 |
return val;
|
1318 |
} |
1319 |
|
1320 |
static CPUWriteMemoryFunc *pci_apb_config_write[] = {
|
1321 |
&pci_apb_config_writel, |
1322 |
&pci_apb_config_writel, |
1323 |
&pci_apb_config_writel, |
1324 |
}; |
1325 |
|
1326 |
static CPUReadMemoryFunc *pci_apb_config_read[] = {
|
1327 |
&pci_apb_config_readl, |
1328 |
&pci_apb_config_readl, |
1329 |
&pci_apb_config_readl, |
1330 |
}; |
1331 |
|
1332 |
static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
1333 |
uint32_t val) |
1334 |
{ |
1335 |
//PCIBus *s = opaque;
|
1336 |
|
1337 |
switch (addr & 0x3f) { |
1338 |
case 0x00: // Control/Status |
1339 |
case 0x10: // AFSR |
1340 |
case 0x18: // AFAR |
1341 |
case 0x20: // Diagnostic |
1342 |
case 0x28: // Target address space |
1343 |
// XXX
|
1344 |
default:
|
1345 |
break;
|
1346 |
} |
1347 |
} |
1348 |
|
1349 |
static uint32_t apb_config_readl (void *opaque, |
1350 |
target_phys_addr_t addr) |
1351 |
{ |
1352 |
//PCIBus *s = opaque;
|
1353 |
uint32_t val; |
1354 |
|
1355 |
switch (addr & 0x3f) { |
1356 |
case 0x00: // Control/Status |
1357 |
case 0x10: // AFSR |
1358 |
case 0x18: // AFAR |
1359 |
case 0x20: // Diagnostic |
1360 |
case 0x28: // Target address space |
1361 |
// XXX
|
1362 |
default:
|
1363 |
val = 0;
|
1364 |
break;
|
1365 |
} |
1366 |
return val;
|
1367 |
} |
1368 |
|
1369 |
static CPUWriteMemoryFunc *apb_config_write[] = {
|
1370 |
&apb_config_writel, |
1371 |
&apb_config_writel, |
1372 |
&apb_config_writel, |
1373 |
}; |
1374 |
|
1375 |
static CPUReadMemoryFunc *apb_config_read[] = {
|
1376 |
&apb_config_readl, |
1377 |
&apb_config_readl, |
1378 |
&apb_config_readl, |
1379 |
}; |
1380 |
|
1381 |
static void pci_apb_writeb (void *opaque, target_phys_addr_t addr, |
1382 |
uint32_t val) |
1383 |
{ |
1384 |
PCIBus *s = opaque; |
1385 |
|
1386 |
pci_data_write(s, addr & 7, val, 1); |
1387 |
} |
1388 |
|
1389 |
static void pci_apb_writew (void *opaque, target_phys_addr_t addr, |
1390 |
uint32_t val) |
1391 |
{ |
1392 |
PCIBus *s = opaque; |
1393 |
|
1394 |
pci_data_write(s, addr & 7, val, 2); |
1395 |
} |
1396 |
|
1397 |
static void pci_apb_writel (void *opaque, target_phys_addr_t addr, |
1398 |
uint32_t val) |
1399 |
{ |
1400 |
PCIBus *s = opaque; |
1401 |
|
1402 |
pci_data_write(s, addr & 7, val, 4); |
1403 |
} |
1404 |
|
1405 |
static uint32_t pci_apb_readb (void *opaque, target_phys_addr_t addr) |
1406 |
{ |
1407 |
PCIBus *s = opaque; |
1408 |
uint32_t val; |
1409 |
|
1410 |
val = pci_data_read(s, addr & 7, 1); |
1411 |
return val;
|
1412 |
} |
1413 |
|
1414 |
static uint32_t pci_apb_readw (void *opaque, target_phys_addr_t addr) |
1415 |
{ |
1416 |
PCIBus *s = opaque; |
1417 |
uint32_t val; |
1418 |
|
1419 |
val = pci_data_read(s, addr & 7, 2); |
1420 |
return val;
|
1421 |
} |
1422 |
|
1423 |
static uint32_t pci_apb_readl (void *opaque, target_phys_addr_t addr) |
1424 |
{ |
1425 |
PCIBus *s = opaque; |
1426 |
uint32_t val; |
1427 |
|
1428 |
val = pci_data_read(s, addr, 4);
|
1429 |
return val;
|
1430 |
} |
1431 |
|
1432 |
static CPUWriteMemoryFunc *pci_apb_write[] = {
|
1433 |
&pci_apb_writeb, |
1434 |
&pci_apb_writew, |
1435 |
&pci_apb_writel, |
1436 |
}; |
1437 |
|
1438 |
static CPUReadMemoryFunc *pci_apb_read[] = {
|
1439 |
&pci_apb_readb, |
1440 |
&pci_apb_readw, |
1441 |
&pci_apb_readl, |
1442 |
}; |
1443 |
|
1444 |
static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, |
1445 |
uint32_t val) |
1446 |
{ |
1447 |
cpu_outb(NULL, addr & 0xffff, val); |
1448 |
} |
1449 |
|
1450 |
static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr, |
1451 |
uint32_t val) |
1452 |
{ |
1453 |
cpu_outw(NULL, addr & 0xffff, val); |
1454 |
} |
1455 |
|
1456 |
static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr, |
1457 |
uint32_t val) |
1458 |
{ |
1459 |
cpu_outl(NULL, addr & 0xffff, val); |
1460 |
} |
1461 |
|
1462 |
static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr) |
1463 |
{ |
1464 |
uint32_t val; |
1465 |
|
1466 |
val = cpu_inb(NULL, addr & 0xffff); |
1467 |
return val;
|
1468 |
} |
1469 |
|
1470 |
static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr) |
1471 |
{ |
1472 |
uint32_t val; |
1473 |
|
1474 |
val = cpu_inw(NULL, addr & 0xffff); |
1475 |
return val;
|
1476 |
} |
1477 |
|
1478 |
static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr) |
1479 |
{ |
1480 |
uint32_t val; |
1481 |
|
1482 |
val = cpu_inl(NULL, addr & 0xffff); |
1483 |
return val;
|
1484 |
} |
1485 |
|
1486 |
static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
|
1487 |
&pci_apb_iowriteb, |
1488 |
&pci_apb_iowritew, |
1489 |
&pci_apb_iowritel, |
1490 |
}; |
1491 |
|
1492 |
static CPUReadMemoryFunc *pci_apb_ioread[] = {
|
1493 |
&pci_apb_ioreadb, |
1494 |
&pci_apb_ioreadw, |
1495 |
&pci_apb_ioreadl, |
1496 |
}; |
1497 |
|
1498 |
PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base) |
1499 |
{ |
1500 |
PCIBus *s; |
1501 |
PCIDevice *d; |
1502 |
int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
|
1503 |
|
1504 |
/* Ultrasparc APB main bus */
|
1505 |
s = pci_register_bus(); |
1506 |
s->set_irq = pci_set_irq_simple; |
1507 |
|
1508 |
pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
|
1509 |
pci_apb_config_write, s); |
1510 |
apb_config = cpu_register_io_memory(0, apb_config_read,
|
1511 |
apb_config_write, s); |
1512 |
pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
|
1513 |
pci_apb_write, s); |
1514 |
pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
|
1515 |
pci_apb_iowrite, s); |
1516 |
|
1517 |
cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config); |
1518 |
cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config); |
1519 |
cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport); |
1520 |
cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom |
1521 |
|
1522 |
d = pci_register_device(s, "Advanced PCI Bus", sizeof(PCIDevice), |
1523 |
-1, NULL, NULL); |
1524 |
d->config[0x00] = 0x8e; // vendor_id : Sun |
1525 |
d->config[0x01] = 0x10; |
1526 |
d->config[0x02] = 0x00; // device_id |
1527 |
d->config[0x03] = 0xa0; |
1528 |
d->config[0x04] = 0x06; // command = bus master, pci mem |
1529 |
d->config[0x05] = 0x00; |
1530 |
d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
1531 |
d->config[0x07] = 0x03; // status = medium devsel |
1532 |
d->config[0x08] = 0x00; // revision |
1533 |
d->config[0x09] = 0x00; // programming i/f |
1534 |
d->config[0x0A] = 0x00; // class_sub = pci host |
1535 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
1536 |
d->config[0x0D] = 0x10; // latency_timer |
1537 |
d->config[0x0E] = 0x00; // header_type |
1538 |
return s;
|
1539 |
} |
1540 |
|
1541 |
/***********************************************************/
|
1542 |
/* generic PCI irq support */
|
1543 |
|
1544 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
1545 |
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
1546 |
{ |
1547 |
PCIBus *bus = pci_dev->bus; |
1548 |
bus->set_irq(pci_dev, irq_num, level); |
1549 |
} |
1550 |
|
1551 |
/***********************************************************/
|
1552 |
/* monitor info on PCI */
|
1553 |
|
1554 |
static void pci_info_device(PCIDevice *d) |
1555 |
{ |
1556 |
int i, class;
|
1557 |
PCIIORegion *r; |
1558 |
|
1559 |
term_printf(" Bus %2d, device %3d, function %d:\n",
|
1560 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
1561 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
1562 |
term_printf(" ");
|
1563 |
switch(class) {
|
1564 |
case 0x0101: |
1565 |
term_printf("IDE controller");
|
1566 |
break;
|
1567 |
case 0x0200: |
1568 |
term_printf("Ethernet controller");
|
1569 |
break;
|
1570 |
case 0x0300: |
1571 |
term_printf("VGA controller");
|
1572 |
break;
|
1573 |
default:
|
1574 |
term_printf("Class %04x", class);
|
1575 |
break;
|
1576 |
} |
1577 |
term_printf(": PCI device %04x:%04x\n",
|
1578 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
1579 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
1580 |
|
1581 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
1582 |
term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
1583 |
} |
1584 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
1585 |
r = &d->io_regions[i]; |
1586 |
if (r->size != 0) { |
1587 |
term_printf(" BAR%d: ", i);
|
1588 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
1589 |
term_printf("I/O at 0x%04x [0x%04x].\n",
|
1590 |
r->addr, r->addr + r->size - 1);
|
1591 |
} else {
|
1592 |
term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
1593 |
r->addr, r->addr + r->size - 1);
|
1594 |
} |
1595 |
} |
1596 |
} |
1597 |
} |
1598 |
|
1599 |
void pci_info(void) |
1600 |
{ |
1601 |
PCIBus *bus = first_bus; |
1602 |
PCIDevice *d; |
1603 |
int devfn;
|
1604 |
|
1605 |
if (bus) {
|
1606 |
for(devfn = 0; devfn < 256; devfn++) { |
1607 |
d = bus->devices[devfn]; |
1608 |
if (d)
|
1609 |
pci_info_device(d); |
1610 |
} |
1611 |
} |
1612 |
} |
1613 |
|
1614 |
/***********************************************************/
|
1615 |
/* XXX: the following should be moved to the PC BIOS */
|
1616 |
|
1617 |
static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
|
1618 |
{ |
1619 |
return cpu_inb(NULL, addr); |
1620 |
} |
1621 |
|
1622 |
static void isa_outb(uint32_t val, uint32_t addr) |
1623 |
{ |
1624 |
cpu_outb(NULL, addr, val);
|
1625 |
} |
1626 |
|
1627 |
static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
|
1628 |
{ |
1629 |
return cpu_inw(NULL, addr); |
1630 |
} |
1631 |
|
1632 |
static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) |
1633 |
{ |
1634 |
cpu_outw(NULL, addr, val);
|
1635 |
} |
1636 |
|
1637 |
static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
|
1638 |
{ |
1639 |
return cpu_inl(NULL, addr); |
1640 |
} |
1641 |
|
1642 |
static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) |
1643 |
{ |
1644 |
cpu_outl(NULL, addr, val);
|
1645 |
} |
1646 |
|
1647 |
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
1648 |
{ |
1649 |
PCIBus *s = d->bus; |
1650 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1651 |
(d->devfn << 8) | addr;
|
1652 |
pci_data_write(s, 0, val, 4); |
1653 |
} |
1654 |
|
1655 |
static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
1656 |
{ |
1657 |
PCIBus *s = d->bus; |
1658 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1659 |
(d->devfn << 8) | (addr & ~3); |
1660 |
pci_data_write(s, addr & 3, val, 2); |
1661 |
} |
1662 |
|
1663 |
static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
1664 |
{ |
1665 |
PCIBus *s = d->bus; |
1666 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1667 |
(d->devfn << 8) | (addr & ~3); |
1668 |
pci_data_write(s, addr & 3, val, 1); |
1669 |
} |
1670 |
|
1671 |
static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
1672 |
{ |
1673 |
PCIBus *s = d->bus; |
1674 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1675 |
(d->devfn << 8) | addr;
|
1676 |
return pci_data_read(s, 0, 4); |
1677 |
} |
1678 |
|
1679 |
static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
1680 |
{ |
1681 |
PCIBus *s = d->bus; |
1682 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1683 |
(d->devfn << 8) | (addr & ~3); |
1684 |
return pci_data_read(s, addr & 3, 2); |
1685 |
} |
1686 |
|
1687 |
static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
1688 |
{ |
1689 |
PCIBus *s = d->bus; |
1690 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1691 |
(d->devfn << 8) | (addr & ~3); |
1692 |
return pci_data_read(s, addr & 3, 1); |
1693 |
} |
1694 |
|
1695 |
static uint32_t pci_bios_io_addr;
|
1696 |
static uint32_t pci_bios_mem_addr;
|
1697 |
/* host irqs corresponding to PCI irqs A-D */
|
1698 |
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
1699 |
|
1700 |
static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
1701 |
{ |
1702 |
PCIIORegion *r; |
1703 |
uint16_t cmd; |
1704 |
uint32_t ofs; |
1705 |
|
1706 |
if ( region_num == PCI_ROM_SLOT ) {
|
1707 |
ofs = 0x30;
|
1708 |
}else{
|
1709 |
ofs = 0x10 + region_num * 4; |
1710 |
} |
1711 |
|
1712 |
pci_config_writel(d, ofs, addr); |
1713 |
r = &d->io_regions[region_num]; |
1714 |
|
1715 |
/* enable memory mappings */
|
1716 |
cmd = pci_config_readw(d, PCI_COMMAND); |
1717 |
if ( region_num == PCI_ROM_SLOT )
|
1718 |
cmd |= 2;
|
1719 |
else if (r->type & PCI_ADDRESS_SPACE_IO) |
1720 |
cmd |= 1;
|
1721 |
else
|
1722 |
cmd |= 2;
|
1723 |
pci_config_writew(d, PCI_COMMAND, cmd); |
1724 |
} |
1725 |
|
1726 |
static void pci_bios_init_device(PCIDevice *d) |
1727 |
{ |
1728 |
int class;
|
1729 |
PCIIORegion *r; |
1730 |
uint32_t *paddr; |
1731 |
int i, pin, pic_irq, vendor_id, device_id;
|
1732 |
|
1733 |
class = pci_config_readw(d, PCI_CLASS_DEVICE); |
1734 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1735 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1736 |
switch(class) {
|
1737 |
case 0x0101: |
1738 |
if (vendor_id == 0x8086 && device_id == 0x7010) { |
1739 |
/* PIIX3 IDE */
|
1740 |
pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
1741 |
pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
1742 |
goto default_map;
|
1743 |
} else {
|
1744 |
/* IDE: we map it as in ISA mode */
|
1745 |
pci_set_io_region_addr(d, 0, 0x1f0); |
1746 |
pci_set_io_region_addr(d, 1, 0x3f4); |
1747 |
pci_set_io_region_addr(d, 2, 0x170); |
1748 |
pci_set_io_region_addr(d, 3, 0x374); |
1749 |
} |
1750 |
break;
|
1751 |
case 0x0300: |
1752 |
if (vendor_id != 0x1234) |
1753 |
goto default_map;
|
1754 |
/* VGA: map frame buffer to default Bochs VBE address */
|
1755 |
pci_set_io_region_addr(d, 0, 0xE0000000); |
1756 |
break;
|
1757 |
case 0x0800: |
1758 |
/* PIC */
|
1759 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1760 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1761 |
if (vendor_id == 0x1014) { |
1762 |
/* IBM */
|
1763 |
if (device_id == 0x0046 || device_id == 0xFFFF) { |
1764 |
/* MPIC & MPIC2 */
|
1765 |
pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); |
1766 |
} |
1767 |
} |
1768 |
break;
|
1769 |
case 0xff00: |
1770 |
if (vendor_id == 0x0106b && |
1771 |
(device_id == 0x0017 || device_id == 0x0022)) { |
1772 |
/* macio bridge */
|
1773 |
pci_set_io_region_addr(d, 0, 0x80800000); |
1774 |
} |
1775 |
break;
|
1776 |
default:
|
1777 |
default_map:
|
1778 |
/* default memory mappings */
|
1779 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1780 |
r = &d->io_regions[i]; |
1781 |
if (r->size) {
|
1782 |
if (r->type & PCI_ADDRESS_SPACE_IO)
|
1783 |
paddr = &pci_bios_io_addr; |
1784 |
else
|
1785 |
paddr = &pci_bios_mem_addr; |
1786 |
*paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
1787 |
pci_set_io_region_addr(d, i, *paddr); |
1788 |
*paddr += r->size; |
1789 |
} |
1790 |
} |
1791 |
break;
|
1792 |
} |
1793 |
|
1794 |
/* map the interrupt */
|
1795 |
pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
1796 |
if (pin != 0) { |
1797 |
pin = pci_slot_get_pirq(d, pin - 1);
|
1798 |
pic_irq = pci_irqs[pin]; |
1799 |
pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
1800 |
} |
1801 |
} |
1802 |
|
1803 |
/*
|
1804 |
* This function initializes the PCI devices as a normal PCI BIOS
|
1805 |
* would do. It is provided just in case the BIOS has no support for
|
1806 |
* PCI.
|
1807 |
*/
|
1808 |
void pci_bios_init(void) |
1809 |
{ |
1810 |
PCIBus *bus; |
1811 |
PCIDevice *d; |
1812 |
int devfn, i, irq;
|
1813 |
uint8_t elcr[2];
|
1814 |
|
1815 |
pci_bios_io_addr = 0xc000;
|
1816 |
pci_bios_mem_addr = 0xf0000000;
|
1817 |
|
1818 |
/* activate IRQ mappings */
|
1819 |
elcr[0] = 0x00; |
1820 |
elcr[1] = 0x00; |
1821 |
for(i = 0; i < 4; i++) { |
1822 |
irq = pci_irqs[i]; |
1823 |
/* set to trigger level */
|
1824 |
elcr[irq >> 3] |= (1 << (irq & 7)); |
1825 |
/* activate irq remapping in PIIX */
|
1826 |
pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
1827 |
} |
1828 |
isa_outb(elcr[0], 0x4d0); |
1829 |
isa_outb(elcr[1], 0x4d1); |
1830 |
|
1831 |
bus = first_bus; |
1832 |
if (bus) {
|
1833 |
for(devfn = 0; devfn < 256; devfn++) { |
1834 |
d = bus->devices[devfn]; |
1835 |
if (d)
|
1836 |
pci_bios_init_device(d); |
1837 |
} |
1838 |
} |
1839 |
} |