Archipelago » qemu

/*

 * QEMU PowerPC 405 embedded processors emulation

 *

 * Copyright (c) 2007 Jocelyn Mayer

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "hw.h"

#include "ppc.h"

#include "ppc405.h"

#include "serial.h"

#include "qemu/timer.h"

#include "sysemu/sysemu.h"

#include "qemu/log.h"

#include "exec/address-spaces.h"

#define DEBUG_OPBA

#define DEBUG_SDRAM

#define DEBUG_GPIO

#define DEBUG_SERIAL

#define DEBUG_OCM

//#define DEBUG_I2C

#define DEBUG_GPT

#define DEBUG_MAL

#define DEBUG_CLOCKS

//#define DEBUG_CLOCKS_LL

ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,

                                uint32_t flags)

{

    ram_addr_t bdloc;

    int i, n;

    /* We put the bd structure at the top of memory */

    if (bd->bi_memsize >= 0x01000000UL)

        bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);

    else

        bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);

    stl_be_phys(bdloc + 0x00, bd->bi_memstart);

    stl_be_phys(bdloc + 0x04, bd->bi_memsize);

    stl_be_phys(bdloc + 0x08, bd->bi_flashstart);

    stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);

    stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);

    stl_be_phys(bdloc + 0x14, bd->bi_sramstart);

    stl_be_phys(bdloc + 0x18, bd->bi_sramsize);

    stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);

    stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);

    for (i = 0; i < 6; i++) {

        stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);

    }

    stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);

    stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);

    stl_be_phys(bdloc + 0x30, bd->bi_busfreq);

    stl_be_phys(bdloc + 0x34, bd->bi_baudrate);

    for (i = 0; i < 4; i++) {

        stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);

    }

    for (i = 0; i < 32; i++) {

        stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);

    }

    stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);

    stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);

    for (i = 0; i < 6; i++) {

        stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);

    }

    n = 0x6A;

    if (flags & 0x00000001) {

        for (i = 0; i < 6; i++)

            stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);

    }

    stl_be_phys(bdloc + n, bd->bi_opbfreq);

    n += 4;

    for (i = 0; i < 2; i++) {

        stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);

        n += 4;

    }

    return bdloc;

}

/*****************************************************************************/

/* Shared peripherals */

/*****************************************************************************/

/* Peripheral local bus arbitrer */

enum {

    PLB0_BESR = 0x084,

    PLB0_BEAR = 0x086,

    PLB0_ACR  = 0x087,

};

typedef struct ppc4xx_plb_t ppc4xx_plb_t;

struct ppc4xx_plb_t {

    uint32_t acr;

    uint32_t bear;

    uint32_t besr;

};

static uint32_t dcr_read_plb (void *opaque, int dcrn)

{

    ppc4xx_plb_t *plb;

    uint32_t ret;

    plb = opaque;

    switch (dcrn) {

    case PLB0_ACR:

        ret = plb->acr;

        break;

    case PLB0_BEAR:

        ret = plb->bear;

        break;

    case PLB0_BESR:

        ret = plb->besr;

        break;

    default:

        /* Avoid gcc warning */

        ret = 0;

        break;

    }

    return ret;

}

static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)

{

    ppc4xx_plb_t *plb;

    plb = opaque;

    switch (dcrn) {

    case PLB0_ACR:

        /* We don't care about the actual parameters written as

         * we don't manage any priorities on the bus

         */

        plb->acr = val & 0xF8000000;

        break;

    case PLB0_BEAR:

        /* Read only */

        break;

    case PLB0_BESR:

        /* Write-clear */

        plb->besr &= ~val;

        break;

    }

}

static void ppc4xx_plb_reset (void *opaque)

{

    ppc4xx_plb_t *plb;

    plb = opaque;

    plb->acr = 0x00000000;

    plb->bear = 0x00000000;

    plb->besr = 0x00000000;

}

static void ppc4xx_plb_init(CPUPPCState *env)

{

    ppc4xx_plb_t *plb;

    plb = g_malloc0(sizeof(ppc4xx_plb_t));

    ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);

    ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);

    ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);

    qemu_register_reset(ppc4xx_plb_reset, plb);

}

/*****************************************************************************/

/* PLB to OPB bridge */

enum {

    POB0_BESR0 = 0x0A0,

    POB0_BESR1 = 0x0A2,

    POB0_BEAR  = 0x0A4,

};

typedef struct ppc4xx_pob_t ppc4xx_pob_t;

struct ppc4xx_pob_t {

    uint32_t bear;

    uint32_t besr0;

    uint32_t besr1;

};

static uint32_t dcr_read_pob (void *opaque, int dcrn)

{

    ppc4xx_pob_t *pob;

    uint32_t ret;

    pob = opaque;

    switch (dcrn) {

    case POB0_BEAR:

        ret = pob->bear;

        break;

    case POB0_BESR0:

        ret = pob->besr0;

        break;

    case POB0_BESR1:

        ret = pob->besr1;

        break;

    default:

        /* Avoid gcc warning */

        ret = 0;

        break;

    }

    return ret;

}

static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)

{

    ppc4xx_pob_t *pob;

    pob = opaque;

    switch (dcrn) {

    case POB0_BEAR:

        /* Read only */

        break;

    case POB0_BESR0:

        /* Write-clear */

        pob->besr0 &= ~val;

        break;

    case POB0_BESR1:

        /* Write-clear */

        pob->besr1 &= ~val;

        break;

    }

}

static void ppc4xx_pob_reset (void *opaque)

{

    ppc4xx_pob_t *pob;

    pob = opaque;

    /* No error */

    pob->bear = 0x00000000;

    pob->besr0 = 0x0000000;

    pob->besr1 = 0x0000000;

}

static void ppc4xx_pob_init(CPUPPCState *env)

{

    ppc4xx_pob_t *pob;

    pob = g_malloc0(sizeof(ppc4xx_pob_t));

    ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);

    ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);

    ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);

    qemu_register_reset(ppc4xx_pob_reset, pob);

}

/*****************************************************************************/

/* OPB arbitrer */

typedef struct ppc4xx_opba_t ppc4xx_opba_t;

struct ppc4xx_opba_t {

    MemoryRegion io;

    uint8_t cr;

    uint8_t pr;

};

static uint32_t opba_readb (void *opaque, hwaddr addr)

{

    ppc4xx_opba_t *opba;

    uint32_t ret;

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    opba = opaque;

    switch (addr) {

    case 0x00:

        ret = opba->cr;

        break;

    case 0x01:

        ret = opba->pr;

        break;

    default:

        ret = 0x00;

        break;

    }

    return ret;

}

static void opba_writeb (void *opaque,

                         hwaddr addr, uint32_t value)

{

    ppc4xx_opba_t *opba;

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

    opba = opaque;

    switch (addr) {

    case 0x00:

        opba->cr = value & 0xF8;

        break;

    case 0x01:

        opba->pr = value & 0xFF;

        break;

    default:

        break;

    }

}

static uint32_t opba_readw (void *opaque, hwaddr addr)

{

    uint32_t ret;

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    ret = opba_readb(opaque, addr) << 8;

    ret |= opba_readb(opaque, addr + 1);

    return ret;

}

static void opba_writew (void *opaque,

                         hwaddr addr, uint32_t value)

{

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

    opba_writeb(opaque, addr, value >> 8);

    opba_writeb(opaque, addr + 1, value);

}

static uint32_t opba_readl (void *opaque, hwaddr addr)

{

    uint32_t ret;

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    ret = opba_readb(opaque, addr) << 24;

    ret |= opba_readb(opaque, addr + 1) << 16;

    return ret;

}

static void opba_writel (void *opaque,

                         hwaddr addr, uint32_t value)

{

#ifdef DEBUG_OPBA

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

    opba_writeb(opaque, addr, value >> 24);

    opba_writeb(opaque, addr + 1, value >> 16);

}

static const MemoryRegionOps opba_ops = {

    .old_mmio = {

        .read = { opba_readb, opba_readw, opba_readl, },

        .write = { opba_writeb, opba_writew, opba_writel, },

    },

    .endianness = DEVICE_NATIVE_ENDIAN,

};

static void ppc4xx_opba_reset (void *opaque)

{

    ppc4xx_opba_t *opba;

    opba = opaque;

    opba->cr = 0x00; /* No dynamic priorities - park disabled */

    opba->pr = 0x11;

}

static void ppc4xx_opba_init(hwaddr base)

{

    ppc4xx_opba_t *opba;

    opba = g_malloc0(sizeof(ppc4xx_opba_t));

#ifdef DEBUG_OPBA

    printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);

#endif

    memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);

    memory_region_add_subregion(get_system_memory(), base, &opba->io);

    qemu_register_reset(ppc4xx_opba_reset, opba);

}

/*****************************************************************************/

/* Code decompression controller */

/* XXX: TODO */

/*****************************************************************************/

/* Peripheral controller */

typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;

struct ppc4xx_ebc_t {

    uint32_t addr;

    uint32_t bcr[8];

    uint32_t bap[8];

    uint32_t bear;

    uint32_t besr0;

    uint32_t besr1;

    uint32_t cfg;

};

enum {

    EBC0_CFGADDR = 0x012,

    EBC0_CFGDATA = 0x013,

};

static uint32_t dcr_read_ebc (void *opaque, int dcrn)

{

    ppc4xx_ebc_t *ebc;

    uint32_t ret;

    ebc = opaque;

    switch (dcrn) {

    case EBC0_CFGADDR:

        ret = ebc->addr;

        break;

    case EBC0_CFGDATA:

        switch (ebc->addr) {

        case 0x00: /* B0CR */

            ret = ebc->bcr[0];

            break;

        case 0x01: /* B1CR */

            ret = ebc->bcr[1];

            break;

        case 0x02: /* B2CR */

            ret = ebc->bcr[2];

            break;

        case 0x03: /* B3CR */

            ret = ebc->bcr[3];

            break;

        case 0x04: /* B4CR */

            ret = ebc->bcr[4];

            break;

        case 0x05: /* B5CR */

            ret = ebc->bcr[5];

            break;

        case 0x06: /* B6CR */

            ret = ebc->bcr[6];

            break;

        case 0x07: /* B7CR */

            ret = ebc->bcr[7];

            break;

        case 0x10: /* B0AP */

            ret = ebc->bap[0];

            break;

        case 0x11: /* B1AP */

            ret = ebc->bap[1];

            break;

        case 0x12: /* B2AP */

            ret = ebc->bap[2];

            break;

        case 0x13: /* B3AP */

            ret = ebc->bap[3];

            break;

        case 0x14: /* B4AP */

            ret = ebc->bap[4];

            break;

        case 0x15: /* B5AP */

            ret = ebc->bap[5];

            break;

        case 0x16: /* B6AP */

            ret = ebc->bap[6];

            break;

        case 0x17: /* B7AP */

            ret = ebc->bap[7];

            break;

        case 0x20: /* BEAR */

            ret = ebc->bear;

            break;

        case 0x21: /* BESR0 */

            ret = ebc->besr0;

            break;

        case 0x22: /* BESR1 */

            ret = ebc->besr1;

            break;

        case 0x23: /* CFG */

            ret = ebc->cfg;

            break;

        default:

            ret = 0x00000000;

            break;

        }

        break;

    default:

        ret = 0x00000000;

        break;

    }

    return ret;

}

static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)

{

    ppc4xx_ebc_t *ebc;

    ebc = opaque;

    switch (dcrn) {

    case EBC0_CFGADDR:

        ebc->addr = val;

        break;

    case EBC0_CFGDATA:

        switch (ebc->addr) {

        case 0x00: /* B0CR */

            break;

        case 0x01: /* B1CR */

            break;

        case 0x02: /* B2CR */

            break;

        case 0x03: /* B3CR */

            break;

        case 0x04: /* B4CR */

            break;

        case 0x05: /* B5CR */

            break;

        case 0x06: /* B6CR */

            break;

        case 0x07: /* B7CR */

            break;

        case 0x10: /* B0AP */

            break;

        case 0x11: /* B1AP */

            break;

        case 0x12: /* B2AP */

            break;

        case 0x13: /* B3AP */

            break;

        case 0x14: /* B4AP */

            break;

        case 0x15: /* B5AP */

            break;

        case 0x16: /* B6AP */

            break;

        case 0x17: /* B7AP */

            break;

        case 0x20: /* BEAR */

            break;

        case 0x21: /* BESR0 */

            break;

        case 0x22: /* BESR1 */

            break;

        case 0x23: /* CFG */

            break;

        default:

            break;

        }

        break;

    default:

        break;

    }

}

static void ebc_reset (void *opaque)

{

    ppc4xx_ebc_t *ebc;

    int i;

    ebc = opaque;

    ebc->addr = 0x00000000;

    ebc->bap[0] = 0x7F8FFE80;

    ebc->bcr[0] = 0xFFE28000;

    for (i = 0; i < 8; i++) {

        ebc->bap[i] = 0x00000000;

        ebc->bcr[i] = 0x00000000;

    }

    ebc->besr0 = 0x00000000;

    ebc->besr1 = 0x00000000;

    ebc->cfg = 0x80400000;

}

static void ppc405_ebc_init(CPUPPCState *env)

{

    ppc4xx_ebc_t *ebc;

    ebc = g_malloc0(sizeof(ppc4xx_ebc_t));

    qemu_register_reset(&ebc_reset, ebc);

    ppc_dcr_register(env, EBC0_CFGADDR,

                     ebc, &dcr_read_ebc, &dcr_write_ebc);

    ppc_dcr_register(env, EBC0_CFGDATA,

                     ebc, &dcr_read_ebc, &dcr_write_ebc);

}

/*****************************************************************************/

/* DMA controller */

enum {

    DMA0_CR0 = 0x100,

    DMA0_CT0 = 0x101,

    DMA0_DA0 = 0x102,

    DMA0_SA0 = 0x103,

    DMA0_SG0 = 0x104,

    DMA0_CR1 = 0x108,

    DMA0_CT1 = 0x109,

    DMA0_DA1 = 0x10A,

    DMA0_SA1 = 0x10B,

    DMA0_SG1 = 0x10C,

    DMA0_CR2 = 0x110,

    DMA0_CT2 = 0x111,

    DMA0_DA2 = 0x112,

    DMA0_SA2 = 0x113,

    DMA0_SG2 = 0x114,

    DMA0_CR3 = 0x118,

    DMA0_CT3 = 0x119,

    DMA0_DA3 = 0x11A,

    DMA0_SA3 = 0x11B,

    DMA0_SG3 = 0x11C,

    DMA0_SR  = 0x120,

    DMA0_SGC = 0x123,

    DMA0_SLP = 0x125,

    DMA0_POL = 0x126,

};

typedef struct ppc405_dma_t ppc405_dma_t;

struct ppc405_dma_t {

    qemu_irq irqs[4];

    uint32_t cr[4];

    uint32_t ct[4];

    uint32_t da[4];

    uint32_t sa[4];

    uint32_t sg[4];

    uint32_t sr;

    uint32_t sgc;

    uint32_t slp;

    uint32_t pol;

};

static uint32_t dcr_read_dma (void *opaque, int dcrn)

{

    return 0;

}

static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)

{

}

static void ppc405_dma_reset (void *opaque)

{

    ppc405_dma_t *dma;

    int i;

    dma = opaque;

    for (i = 0; i < 4; i++) {

        dma->cr[i] = 0x00000000;

        dma->ct[i] = 0x00000000;

        dma->da[i] = 0x00000000;

        dma->sa[i] = 0x00000000;

        dma->sg[i] = 0x00000000;

    }

    dma->sr = 0x00000000;

    dma->sgc = 0x00000000;

    dma->slp = 0x7C000000;

    dma->pol = 0x00000000;

}

static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])

{

    ppc405_dma_t *dma;

    dma = g_malloc0(sizeof(ppc405_dma_t));

    memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));

    qemu_register_reset(&ppc405_dma_reset, dma);

    ppc_dcr_register(env, DMA0_CR0,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CT0,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_DA0,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SA0,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SG0,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CR1,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CT1,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_DA1,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SA1,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SG1,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CR2,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CT2,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_DA2,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SA2,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SG2,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CR3,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_CT3,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_DA3,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SA3,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SG3,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SR,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SGC,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_SLP,

                     dma, &dcr_read_dma, &dcr_write_dma);

    ppc_dcr_register(env, DMA0_POL,

                     dma, &dcr_read_dma, &dcr_write_dma);

}

/*****************************************************************************/

/* GPIO */

typedef struct ppc405_gpio_t ppc405_gpio_t;

struct ppc405_gpio_t {

    MemoryRegion io;

    uint32_t or;

    uint32_t tcr;

    uint32_t osrh;

    uint32_t osrl;

    uint32_t tsrh;

    uint32_t tsrl;

    uint32_t odr;

    uint32_t ir;

    uint32_t rr1;

    uint32_t isr1h;

    uint32_t isr1l;

};

static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    return 0;

}

static void ppc405_gpio_writeb (void *opaque,

                                hwaddr addr, uint32_t value)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

}

static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    return 0;

}

static void ppc405_gpio_writew (void *opaque,

                                hwaddr addr, uint32_t value)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

}

static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);

#endif

    return 0;

}

static void ppc405_gpio_writel (void *opaque,

                                hwaddr addr, uint32_t value)

{

#ifdef DEBUG_GPIO

    printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,

           value);

#endif

}

static const MemoryRegionOps ppc405_gpio_ops = {

    .old_mmio = {

        .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },

        .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },

    },

    .endianness = DEVICE_NATIVE_ENDIAN,

};

static void ppc405_gpio_reset (void *opaque)

{

}

static void ppc405_gpio_init(hwaddr base)

{

    ppc405_gpio_t *gpio;

    gpio = g_malloc0(sizeof(ppc405_gpio_t));

#ifdef DEBUG_GPIO

    printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);

#endif

    memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);

    memory_region_add_subregion(get_system_memory(), base, &gpio->io);

    qemu_register_reset(&ppc405_gpio_reset, gpio);

}

/*****************************************************************************/

/* On Chip Memory */

enum {

    OCM0_ISARC   = 0x018,

    OCM0_ISACNTL = 0x019,

    OCM0_DSARC   = 0x01A,

    OCM0_DSACNTL = 0x01B,

};

typedef struct ppc405_ocm_t ppc405_ocm_t;

struct ppc405_ocm_t {

    MemoryRegion ram;

    MemoryRegion isarc_ram;

    MemoryRegion dsarc_ram;

    uint32_t isarc;

    uint32_t isacntl;

    uint32_t dsarc;

    uint32_t dsacntl;

};

static void ocm_update_mappings (ppc405_ocm_t *ocm,

                                 uint32_t isarc, uint32_t isacntl,

                                 uint32_t dsarc, uint32_t dsacntl)

{

#ifdef DEBUG_OCM

    printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32

           " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32

           " (%08" PRIx32 " %08" PRIx32 ")\n",

           isarc, isacntl, dsarc, dsacntl,

           ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);

#endif

    if (ocm->isarc != isarc ||

        (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {

        if (ocm->isacntl & 0x80000000) {

            /* Unmap previously assigned memory region */

            printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);

            memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);

        }

        if (isacntl & 0x80000000) {

            /* Map new instruction memory region */

#ifdef DEBUG_OCM

            printf("OCM map ISA %08" PRIx32 "\n", isarc);

#endif

            memory_region_add_subregion(get_system_memory(), isarc,

                                        &ocm->isarc_ram);

        }

    }

    if (ocm->dsarc != dsarc ||

        (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {

        if (ocm->dsacntl & 0x80000000) {

            /* Beware not to unmap the region we just mapped */

            if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {

                /* Unmap previously assigned memory region */

#ifdef DEBUG_OCM

                printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);

#endif

                memory_region_del_subregion(get_system_memory(),

                                            &ocm->dsarc_ram);

            }

        }

        if (dsacntl & 0x80000000) {

            /* Beware not to remap the region we just mapped */