root / hw / sun4m.c @ d8c6d07f
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1 | 420557e8 | bellard | /*
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2 | ee76f82e | blueswir1 | * QEMU Sun4m & Sun4d & Sun4c System Emulator
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3 | 5fafdf24 | ths | *
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4 | b81b3b10 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
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12 | 420557e8 | bellard | *
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13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
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15 | 420557e8 | bellard | *
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16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 420557e8 | bellard | * THE SOFTWARE.
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23 | 420557e8 | bellard | */
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24 | 9d07d757 | Paul Brook | #include "sysbus.h" |
25 | 1de7afc9 | Paolo Bonzini | #include "qemu/timer.h" |
26 | 87ecb68b | pbrook | #include "sun4m.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
29 | 87ecb68b | pbrook | #include "fdc.h" |
30 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
31 | 1422e32d | Paolo Bonzini | #include "net/net.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 1cd3af54 | Gerd Hoffmann | #include "esp.h" |
35 | 22548760 | blueswir1 | #include "pc.h" |
36 | 22548760 | blueswir1 | #include "isa.h" |
37 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
38 | b4ed08e0 | blueswir1 | #include "escc.h" |
39 | 676d9b9b | Artyom Tarasenko | #include "empty_slot.h" |
40 | 4b48bf05 | Blue Swirl | #include "qdev-addr.h" |
41 | ca20cf32 | Blue Swirl | #include "loader.h" |
42 | ca20cf32 | Blue Swirl | #include "elf.h" |
43 | 9c17d615 | Paolo Bonzini | #include "sysemu/blockdev.h" |
44 | 97bf4851 | Blue Swirl | #include "trace.h" |
45 | 420557e8 | bellard | |
46 | 36cd9210 | blueswir1 | /*
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47 | 36cd9210 | blueswir1 | * Sun4m architecture was used in the following machines:
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48 | 36cd9210 | blueswir1 | *
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49 | 36cd9210 | blueswir1 | * SPARCserver 6xxMP/xx
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50 | 77f193da | blueswir1 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
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51 | 77f193da | blueswir1 | * SPARCclassic X (4/10)
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52 | 36cd9210 | blueswir1 | * SPARCstation LX/ZX (4/30)
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53 | 36cd9210 | blueswir1 | * SPARCstation Voyager
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54 | 36cd9210 | blueswir1 | * SPARCstation 10/xx, SPARCserver 10/xx
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55 | 36cd9210 | blueswir1 | * SPARCstation 5, SPARCserver 5
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56 | 36cd9210 | blueswir1 | * SPARCstation 20/xx, SPARCserver 20
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57 | 36cd9210 | blueswir1 | * SPARCstation 4
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58 | 36cd9210 | blueswir1 | *
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59 | 7d85892b | blueswir1 | * Sun4d architecture was used in the following machines:
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60 | 7d85892b | blueswir1 | *
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61 | 7d85892b | blueswir1 | * SPARCcenter 2000
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62 | 7d85892b | blueswir1 | * SPARCserver 1000
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63 | 7d85892b | blueswir1 | *
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64 | ee76f82e | blueswir1 | * Sun4c architecture was used in the following machines:
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65 | ee76f82e | blueswir1 | * SPARCstation 1/1+, SPARCserver 1/1+
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66 | ee76f82e | blueswir1 | * SPARCstation SLC
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67 | ee76f82e | blueswir1 | * SPARCstation IPC
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68 | ee76f82e | blueswir1 | * SPARCstation ELC
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69 | ee76f82e | blueswir1 | * SPARCstation IPX
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70 | ee76f82e | blueswir1 | *
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71 | 36cd9210 | blueswir1 | * See for example: http://www.sunhelp.org/faq/sunref1.html
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72 | 36cd9210 | blueswir1 | */
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73 | 36cd9210 | blueswir1 | |
74 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
75 | b6f479d3 | bellard | #define CMDLINE_ADDR 0x007ff000 |
76 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
77 | a7227727 | blueswir1 | #define PROM_SIZE_MAX (1024 * 1024) |
78 | 40ce0a9a | blueswir1 | #define PROM_VADDR 0xffd00000 |
79 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc32" |
80 | 3cce6243 | blueswir1 | #define CFG_ADDR 0xd00000510ULL |
81 | fbfcf955 | blueswir1 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
82 | b8174937 | bellard | |
83 | ba3c64fb | bellard | #define MAX_CPUS 16 |
84 | b3a23197 | blueswir1 | #define MAX_PILS 16 |
85 | 9a62fb24 | Bob Breuer | #define MAX_VSIMMS 4 |
86 | 420557e8 | bellard | |
87 | b4ed08e0 | blueswir1 | #define ESCC_CLOCK 4915200 |
88 | b4ed08e0 | blueswir1 | |
89 | 8137cde8 | blueswir1 | struct sun4m_hwdef {
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90 | a8170e5e | Avi Kivity | hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
91 | a8170e5e | Avi Kivity | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; |
92 | a8170e5e | Avi Kivity | hwaddr serial_base, fd_base; |
93 | a8170e5e | Avi Kivity | hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; |
94 | a8170e5e | Avi Kivity | hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; |
95 | a8170e5e | Avi Kivity | hwaddr bpp_base, dbri_base, sx_base; |
96 | 9a62fb24 | Bob Breuer | struct {
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97 | a8170e5e | Avi Kivity | hwaddr reg_base, vram_base; |
98 | 9a62fb24 | Bob Breuer | } vsimm[MAX_VSIMMS]; |
99 | a8170e5e | Avi Kivity | hwaddr ecc_base; |
100 | 3ebf5aaf | blueswir1 | uint64_t max_mem; |
101 | 3ebf5aaf | blueswir1 | const char * const default_cpu_model; |
102 | 61999750 | Blue Swirl | uint32_t ecc_version; |
103 | 61999750 | Blue Swirl | uint32_t iommu_version; |
104 | 61999750 | Blue Swirl | uint16_t machine_id; |
105 | 61999750 | Blue Swirl | uint8_t nvram_machine_id; |
106 | 36cd9210 | blueswir1 | }; |
107 | 36cd9210 | blueswir1 | |
108 | 7d85892b | blueswir1 | #define MAX_IOUNITS 5 |
109 | 7d85892b | blueswir1 | |
110 | 7d85892b | blueswir1 | struct sun4d_hwdef {
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111 | a8170e5e | Avi Kivity | hwaddr iounit_bases[MAX_IOUNITS], slavio_base; |
112 | a8170e5e | Avi Kivity | hwaddr counter_base, nvram_base, ms_kb_base; |
113 | a8170e5e | Avi Kivity | hwaddr serial_base; |
114 | a8170e5e | Avi Kivity | hwaddr espdma_base, esp_base; |
115 | a8170e5e | Avi Kivity | hwaddr ledma_base, le_base; |
116 | a8170e5e | Avi Kivity | hwaddr tcx_base; |
117 | a8170e5e | Avi Kivity | hwaddr sbi_base; |
118 | 7d85892b | blueswir1 | uint64_t max_mem; |
119 | 7d85892b | blueswir1 | const char * const default_cpu_model; |
120 | 61999750 | Blue Swirl | uint32_t iounit_version; |
121 | 61999750 | Blue Swirl | uint16_t machine_id; |
122 | 61999750 | Blue Swirl | uint8_t nvram_machine_id; |
123 | 7d85892b | blueswir1 | }; |
124 | 7d85892b | blueswir1 | |
125 | 8137cde8 | blueswir1 | struct sun4c_hwdef {
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126 | a8170e5e | Avi Kivity | hwaddr iommu_base, slavio_base; |
127 | a8170e5e | Avi Kivity | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; |
128 | a8170e5e | Avi Kivity | hwaddr serial_base, fd_base; |
129 | a8170e5e | Avi Kivity | hwaddr idreg_base, dma_base, esp_base, le_base; |
130 | a8170e5e | Avi Kivity | hwaddr tcx_base, aux1_base; |
131 | 8137cde8 | blueswir1 | uint64_t max_mem; |
132 | 8137cde8 | blueswir1 | const char * const default_cpu_model; |
133 | 61999750 | Blue Swirl | uint32_t iommu_version; |
134 | 61999750 | Blue Swirl | uint16_t machine_id; |
135 | 61999750 | Blue Swirl | uint8_t nvram_machine_id; |
136 | 8137cde8 | blueswir1 | }; |
137 | 8137cde8 | blueswir1 | |
138 | 6f7e9aec | bellard | int DMA_get_channel_mode (int nchan) |
139 | 6f7e9aec | bellard | { |
140 | 6f7e9aec | bellard | return 0; |
141 | 6f7e9aec | bellard | } |
142 | 6f7e9aec | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
143 | 6f7e9aec | bellard | { |
144 | 6f7e9aec | bellard | return 0; |
145 | 6f7e9aec | bellard | } |
146 | 6f7e9aec | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
147 | 6f7e9aec | bellard | { |
148 | 6f7e9aec | bellard | return 0; |
149 | 6f7e9aec | bellard | } |
150 | 6f7e9aec | bellard | void DMA_hold_DREQ (int nchan) {} |
151 | 6f7e9aec | bellard | void DMA_release_DREQ (int nchan) {} |
152 | 6f7e9aec | bellard | void DMA_schedule(int nchan) {} |
153 | 4556bd8b | Blue Swirl | |
154 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
155 | 4556bd8b | Blue Swirl | { |
156 | 4556bd8b | Blue Swirl | } |
157 | 4556bd8b | Blue Swirl | |
158 | 6f7e9aec | bellard | void DMA_register_channel (int nchan, |
159 | 6f7e9aec | bellard | DMA_transfer_handler transfer_handler, |
160 | 6f7e9aec | bellard | void *opaque)
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161 | 6f7e9aec | bellard | { |
162 | 6f7e9aec | bellard | } |
163 | 6f7e9aec | bellard | |
164 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
165 | 81864572 | blueswir1 | { |
166 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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167 | 81864572 | blueswir1 | return 0; |
168 | 81864572 | blueswir1 | } |
169 | 81864572 | blueswir1 | |
170 | 43a34704 | Blue Swirl | static void nvram_init(M48t59State *nvram, uint8_t *macaddr, |
171 | 43a34704 | Blue Swirl | const char *cmdline, const char *boot_devices, |
172 | 43a34704 | Blue Swirl | ram_addr_t RAM_size, uint32_t kernel_size, |
173 | f930d07e | blueswir1 | int width, int height, int depth, |
174 | 905fdcb5 | blueswir1 | int nvram_machine_id, const char *arch) |
175 | e80cfcfc | bellard | { |
176 | d2c63fc1 | blueswir1 | unsigned int i; |
177 | 66508601 | blueswir1 | uint32_t start, end; |
178 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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179 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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180 | d2c63fc1 | blueswir1 | |
181 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
182 | e80cfcfc | bellard | |
183 | 513f789f | blueswir1 | start = 0;
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184 | b6f479d3 | bellard | |
185 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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186 | 66508601 | blueswir1 | // Variable partition
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187 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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188 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
189 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
190 | 66508601 | blueswir1 | |
191 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
192 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
193 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
194 | d2c63fc1 | blueswir1 | |
195 | d2c63fc1 | blueswir1 | // End marker
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196 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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197 | 66508601 | blueswir1 | |
198 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
199 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
200 | 66508601 | blueswir1 | |
201 | 66508601 | blueswir1 | // free partition
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202 | 66508601 | blueswir1 | start = end; |
203 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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204 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
205 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
206 | 66508601 | blueswir1 | |
207 | 66508601 | blueswir1 | end = 0x1fd0;
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208 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
209 | d2c63fc1 | blueswir1 | |
210 | 905fdcb5 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
211 | 905fdcb5 | blueswir1 | nvram_machine_id); |
212 | d2c63fc1 | blueswir1 | |
213 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
214 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
215 | e80cfcfc | bellard | } |
216 | e80cfcfc | bellard | |
217 | d453c2c3 | Blue Swirl | static DeviceState *slavio_intctl;
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218 | e80cfcfc | bellard | |
219 | 84f2d0ea | Wenchao Xia | void sun4m_pic_info(Monitor *mon, const QDict *qdict) |
220 | e80cfcfc | bellard | { |
221 | 7d85892b | blueswir1 | if (slavio_intctl)
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222 | 376253ec | aliguori | slavio_pic_info(mon, slavio_intctl); |
223 | e80cfcfc | bellard | } |
224 | e80cfcfc | bellard | |
225 | 84f2d0ea | Wenchao Xia | void sun4m_irq_info(Monitor *mon, const QDict *qdict) |
226 | e80cfcfc | bellard | { |
227 | 7d85892b | blueswir1 | if (slavio_intctl)
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228 | 376253ec | aliguori | slavio_irq_info(mon, slavio_intctl); |
229 | e80cfcfc | bellard | } |
230 | e80cfcfc | bellard | |
231 | 98cec4a2 | Andreas Färber | void cpu_check_irqs(CPUSPARCState *env)
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232 | 327ac2e7 | blueswir1 | { |
233 | 327ac2e7 | blueswir1 | if (env->pil_in && (env->interrupt_index == 0 || |
234 | 327ac2e7 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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235 | 327ac2e7 | blueswir1 | unsigned int i; |
236 | 327ac2e7 | blueswir1 | |
237 | 327ac2e7 | blueswir1 | for (i = 15; i > 0; i--) { |
238 | 327ac2e7 | blueswir1 | if (env->pil_in & (1 << i)) { |
239 | 327ac2e7 | blueswir1 | int old_interrupt = env->interrupt_index;
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240 | 327ac2e7 | blueswir1 | |
241 | 327ac2e7 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
242 | f32d7ec5 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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243 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_interrupt(i); |
244 | 327ac2e7 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
245 | f32d7ec5 | blueswir1 | } |
246 | 327ac2e7 | blueswir1 | break;
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247 | 327ac2e7 | blueswir1 | } |
248 | 327ac2e7 | blueswir1 | } |
249 | 327ac2e7 | blueswir1 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { |
250 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
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251 | 327ac2e7 | blueswir1 | env->interrupt_index = 0;
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252 | 327ac2e7 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
253 | 327ac2e7 | blueswir1 | } |
254 | 327ac2e7 | blueswir1 | } |
255 | 327ac2e7 | blueswir1 | |
256 | 38c66cf2 | Andreas Färber | static void cpu_kick_irq(SPARCCPU *cpu) |
257 | 94ad5b00 | Paolo Bonzini | { |
258 | 38c66cf2 | Andreas Färber | CPUSPARCState *env = &cpu->env; |
259 | 38c66cf2 | Andreas Färber | |
260 | 94ad5b00 | Paolo Bonzini | env->halted = 0;
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261 | 94ad5b00 | Paolo Bonzini | cpu_check_irqs(env); |
262 | c08d7424 | Andreas Färber | qemu_cpu_kick(CPU(cpu)); |
263 | 94ad5b00 | Paolo Bonzini | } |
264 | 94ad5b00 | Paolo Bonzini | |
265 | b3a23197 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
266 | b3a23197 | blueswir1 | { |
267 | e0bbf9b5 | Andreas Färber | SPARCCPU *cpu = opaque; |
268 | e0bbf9b5 | Andreas Färber | CPUSPARCState *env = &cpu->env; |
269 | b3a23197 | blueswir1 | |
270 | b3a23197 | blueswir1 | if (level) {
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271 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_set_irq_raise(irq); |
272 | 327ac2e7 | blueswir1 | env->pil_in |= 1 << irq;
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273 | 38c66cf2 | Andreas Färber | cpu_kick_irq(cpu); |
274 | b3a23197 | blueswir1 | } else {
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275 | 97bf4851 | Blue Swirl | trace_sun4m_cpu_set_irq_lower(irq); |
276 | 327ac2e7 | blueswir1 | env->pil_in &= ~(1 << irq);
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277 | 327ac2e7 | blueswir1 | cpu_check_irqs(env); |
278 | b3a23197 | blueswir1 | } |
279 | b3a23197 | blueswir1 | } |
280 | b3a23197 | blueswir1 | |
281 | b3a23197 | blueswir1 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
282 | b3a23197 | blueswir1 | { |
283 | b3a23197 | blueswir1 | } |
284 | b3a23197 | blueswir1 | |
285 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
286 | c68ea704 | bellard | { |
287 | 5414dec6 | Andreas Färber | SPARCCPU *cpu = opaque; |
288 | 5414dec6 | Andreas Färber | CPUSPARCState *env = &cpu->env; |
289 | 3d29fbef | blueswir1 | |
290 | 5414dec6 | Andreas Färber | cpu_reset(CPU(cpu)); |
291 | 3d29fbef | blueswir1 | env->halted = 0;
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292 | 3d29fbef | blueswir1 | } |
293 | 3d29fbef | blueswir1 | |
294 | 3d29fbef | blueswir1 | static void secondary_cpu_reset(void *opaque) |
295 | 3d29fbef | blueswir1 | { |
296 | 5414dec6 | Andreas Färber | SPARCCPU *cpu = opaque; |
297 | 5414dec6 | Andreas Färber | CPUSPARCState *env = &cpu->env; |
298 | 3d29fbef | blueswir1 | |
299 | 5414dec6 | Andreas Färber | cpu_reset(CPU(cpu)); |
300 | 3d29fbef | blueswir1 | env->halted = 1;
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301 | c68ea704 | bellard | } |
302 | c68ea704 | bellard | |
303 | 6d0c293d | blueswir1 | static void cpu_halt_signal(void *opaque, int irq, int level) |
304 | 6d0c293d | blueswir1 | { |
305 | 6d0c293d | blueswir1 | if (level && cpu_single_env)
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306 | 6d0c293d | blueswir1 | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
307 | 6d0c293d | blueswir1 | } |
308 | 6d0c293d | blueswir1 | |
309 | 409dbce5 | Aurelien Jarno | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
310 | 409dbce5 | Aurelien Jarno | { |
311 | 409dbce5 | Aurelien Jarno | return addr - 0xf0000000ULL; |
312 | 409dbce5 | Aurelien Jarno | } |
313 | 409dbce5 | Aurelien Jarno | |
314 | 3ebf5aaf | blueswir1 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
315 | 293f78bc | blueswir1 | const char *initrd_filename, |
316 | c227f099 | Anthony Liguori | ram_addr_t RAM_size) |
317 | 3ebf5aaf | blueswir1 | { |
318 | 3ebf5aaf | blueswir1 | int linux_boot;
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319 | 3ebf5aaf | blueswir1 | unsigned int i; |
320 | 3ebf5aaf | blueswir1 | long initrd_size, kernel_size;
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321 | 3c178e72 | Gerd Hoffmann | uint8_t *ptr; |
322 | 3ebf5aaf | blueswir1 | |
323 | 3ebf5aaf | blueswir1 | linux_boot = (kernel_filename != NULL);
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324 | 3ebf5aaf | blueswir1 | |
325 | 3ebf5aaf | blueswir1 | kernel_size = 0;
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326 | 3ebf5aaf | blueswir1 | if (linux_boot) {
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327 | ca20cf32 | Blue Swirl | int bswap_needed;
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328 | ca20cf32 | Blue Swirl | |
329 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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330 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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331 | ca20cf32 | Blue Swirl | #else
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332 | ca20cf32 | Blue Swirl | bswap_needed = 0;
|
333 | ca20cf32 | Blue Swirl | #endif
|
334 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
|
335 | 409dbce5 | Aurelien Jarno | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
336 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
337 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
338 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
339 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
340 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) |
341 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
342 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
343 | 293f78bc | blueswir1 | RAM_size - KERNEL_LOAD_ADDR); |
344 | 3ebf5aaf | blueswir1 | if (kernel_size < 0) { |
345 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
346 | 3ebf5aaf | blueswir1 | kernel_filename); |
347 | 3ebf5aaf | blueswir1 | exit(1);
|
348 | 3ebf5aaf | blueswir1 | } |
349 | 3ebf5aaf | blueswir1 | |
350 | 3ebf5aaf | blueswir1 | /* load initrd */
|
351 | 3ebf5aaf | blueswir1 | initrd_size = 0;
|
352 | 3ebf5aaf | blueswir1 | if (initrd_filename) {
|
353 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
354 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
355 | 293f78bc | blueswir1 | RAM_size - INITRD_LOAD_ADDR); |
356 | 3ebf5aaf | blueswir1 | if (initrd_size < 0) { |
357 | 3ebf5aaf | blueswir1 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
358 | 3ebf5aaf | blueswir1 | initrd_filename); |
359 | 3ebf5aaf | blueswir1 | exit(1);
|
360 | 3ebf5aaf | blueswir1 | } |
361 | 3ebf5aaf | blueswir1 | } |
362 | 3ebf5aaf | blueswir1 | if (initrd_size > 0) { |
363 | 3ebf5aaf | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
364 | 3c178e72 | Gerd Hoffmann | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
365 | 3c178e72 | Gerd Hoffmann | if (ldl_p(ptr) == 0x48647253) { // HdrS |
366 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 16, INITRD_LOAD_ADDR);
|
367 | 3c178e72 | Gerd Hoffmann | stl_p(ptr + 20, initrd_size);
|
368 | 3ebf5aaf | blueswir1 | break;
|
369 | 3ebf5aaf | blueswir1 | } |
370 | 3ebf5aaf | blueswir1 | } |
371 | 3ebf5aaf | blueswir1 | } |
372 | 3ebf5aaf | blueswir1 | } |
373 | 3ebf5aaf | blueswir1 | return kernel_size;
|
374 | 3ebf5aaf | blueswir1 | } |
375 | 3ebf5aaf | blueswir1 | |
376 | a8170e5e | Avi Kivity | static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
377 | 4b48bf05 | Blue Swirl | { |
378 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
379 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
380 | 4b48bf05 | Blue Swirl | |
381 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "iommu"); |
382 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
383 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
384 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
385 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
386 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
387 | 4b48bf05 | Blue Swirl | |
388 | 4b48bf05 | Blue Swirl | return s;
|
389 | 4b48bf05 | Blue Swirl | } |
390 | 4b48bf05 | Blue Swirl | |
391 | a8170e5e | Avi Kivity | static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq, |
392 | 86d1c388 | Bob Breuer | void *iommu, qemu_irq *dev_irq, int is_ledma) |
393 | 74ff8d90 | Blue Swirl | { |
394 | 74ff8d90 | Blue Swirl | DeviceState *dev; |
395 | 74ff8d90 | Blue Swirl | SysBusDevice *s; |
396 | 74ff8d90 | Blue Swirl | |
397 | 74ff8d90 | Blue Swirl | dev = qdev_create(NULL, "sparc32_dma"); |
398 | 74ff8d90 | Blue Swirl | qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
|
399 | 86d1c388 | Bob Breuer | qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
|
400 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
401 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
402 | 74ff8d90 | Blue Swirl | sysbus_connect_irq(s, 0, parent_irq);
|
403 | 74ff8d90 | Blue Swirl | *dev_irq = qdev_get_gpio_in(dev, 0);
|
404 | 74ff8d90 | Blue Swirl | sysbus_mmio_map(s, 0, daddr);
|
405 | 74ff8d90 | Blue Swirl | |
406 | 74ff8d90 | Blue Swirl | return s;
|
407 | 74ff8d90 | Blue Swirl | } |
408 | 74ff8d90 | Blue Swirl | |
409 | a8170e5e | Avi Kivity | static void lance_init(NICInfo *nd, hwaddr leaddr, |
410 | 74ff8d90 | Blue Swirl | void *dma_opaque, qemu_irq irq)
|
411 | 9d07d757 | Paul Brook | { |
412 | 9d07d757 | Paul Brook | DeviceState *dev; |
413 | 9d07d757 | Paul Brook | SysBusDevice *s; |
414 | 74ff8d90 | Blue Swirl | qemu_irq reset; |
415 | 9d07d757 | Paul Brook | |
416 | 9d07d757 | Paul Brook | qemu_check_nic_model(&nd_table[0], "lance"); |
417 | 9d07d757 | Paul Brook | |
418 | 9d07d757 | Paul Brook | dev = qdev_create(NULL, "lance"); |
419 | 76224833 | Gerd Hoffmann | qdev_set_nic_properties(dev, nd); |
420 | daa65491 | Blue Swirl | qdev_prop_set_ptr(dev, "dma", dma_opaque);
|
421 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
422 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
423 | 9d07d757 | Paul Brook | sysbus_mmio_map(s, 0, leaddr);
|
424 | 9d07d757 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
425 | 74ff8d90 | Blue Swirl | reset = qdev_get_gpio_in(dev, 0);
|
426 | 74ff8d90 | Blue Swirl | qdev_connect_gpio_out(dma_opaque, 0, reset);
|
427 | 9d07d757 | Paul Brook | } |
428 | 9d07d757 | Paul Brook | |
429 | a8170e5e | Avi Kivity | static DeviceState *slavio_intctl_init(hwaddr addr,
|
430 | a8170e5e | Avi Kivity | hwaddr addrg, |
431 | 462eda24 | Blue Swirl | qemu_irq **parent_irq) |
432 | 4b48bf05 | Blue Swirl | { |
433 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
434 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
435 | 4b48bf05 | Blue Swirl | unsigned int i, j; |
436 | 4b48bf05 | Blue Swirl | |
437 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_intctl"); |
438 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
439 | 4b48bf05 | Blue Swirl | |
440 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
441 | 4b48bf05 | Blue Swirl | |
442 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
443 | 4b48bf05 | Blue Swirl | for (j = 0; j < MAX_PILS; j++) { |
444 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); |
445 | 4b48bf05 | Blue Swirl | } |
446 | 4b48bf05 | Blue Swirl | } |
447 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addrg);
|
448 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
449 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
|
450 | 4b48bf05 | Blue Swirl | } |
451 | 4b48bf05 | Blue Swirl | |
452 | 4b48bf05 | Blue Swirl | return dev;
|
453 | 4b48bf05 | Blue Swirl | } |
454 | 4b48bf05 | Blue Swirl | |
455 | 4b48bf05 | Blue Swirl | #define SYS_TIMER_OFFSET 0x10000ULL |
456 | 4b48bf05 | Blue Swirl | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) |
457 | 4b48bf05 | Blue Swirl | |
458 | a8170e5e | Avi Kivity | static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
459 | 4b48bf05 | Blue Swirl | qemu_irq *cpu_irqs, unsigned int num_cpus) |
460 | 4b48bf05 | Blue Swirl | { |
461 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
462 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
463 | 4b48bf05 | Blue Swirl | unsigned int i; |
464 | 4b48bf05 | Blue Swirl | |
465 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_timer"); |
466 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
|
467 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
468 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
469 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, master_irq);
|
470 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
|
471 | 4b48bf05 | Blue Swirl | |
472 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
473 | a8170e5e | Avi Kivity | sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
|
474 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
|
475 | 4b48bf05 | Blue Swirl | } |
476 | 4b48bf05 | Blue Swirl | } |
477 | 4b48bf05 | Blue Swirl | |
478 | bea42280 | Igor Mammedov | static qemu_irq slavio_system_powerdown;
|
479 | bea42280 | Igor Mammedov | |
480 | bea42280 | Igor Mammedov | static void slavio_powerdown_req(Notifier *n, void *opaque) |
481 | bea42280 | Igor Mammedov | { |
482 | bea42280 | Igor Mammedov | qemu_irq_raise(slavio_system_powerdown); |
483 | bea42280 | Igor Mammedov | } |
484 | bea42280 | Igor Mammedov | |
485 | bea42280 | Igor Mammedov | static Notifier slavio_system_powerdown_notifier = {
|
486 | bea42280 | Igor Mammedov | .notify = slavio_powerdown_req |
487 | bea42280 | Igor Mammedov | }; |
488 | bea42280 | Igor Mammedov | |
489 | 4b48bf05 | Blue Swirl | #define MISC_LEDS 0x01600000 |
490 | 4b48bf05 | Blue Swirl | #define MISC_CFG 0x01800000 |
491 | 4b48bf05 | Blue Swirl | #define MISC_DIAG 0x01a00000 |
492 | 4b48bf05 | Blue Swirl | #define MISC_MDM 0x01b00000 |
493 | 4b48bf05 | Blue Swirl | #define MISC_SYS 0x01f00000 |
494 | 4b48bf05 | Blue Swirl | |
495 | a8170e5e | Avi Kivity | static void slavio_misc_init(hwaddr base, |
496 | a8170e5e | Avi Kivity | hwaddr aux1_base, |
497 | a8170e5e | Avi Kivity | hwaddr aux2_base, qemu_irq irq, |
498 | b2b6f6ec | Blue Swirl | qemu_irq fdc_tc) |
499 | 4b48bf05 | Blue Swirl | { |
500 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
501 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
502 | 4b48bf05 | Blue Swirl | |
503 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "slavio_misc"); |
504 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
505 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
506 | 4b48bf05 | Blue Swirl | if (base) {
|
507 | 4b48bf05 | Blue Swirl | /* 8 bit registers */
|
508 | 4b48bf05 | Blue Swirl | /* Slavio control */
|
509 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base + MISC_CFG);
|
510 | 4b48bf05 | Blue Swirl | /* Diagnostics */
|
511 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + MISC_DIAG);
|
512 | 4b48bf05 | Blue Swirl | /* Modem control */
|
513 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, base + MISC_MDM);
|
514 | 4b48bf05 | Blue Swirl | /* 16 bit registers */
|
515 | 4b48bf05 | Blue Swirl | /* ss600mp diag LEDs */
|
516 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, base + MISC_LEDS);
|
517 | 4b48bf05 | Blue Swirl | /* 32 bit registers */
|
518 | 4b48bf05 | Blue Swirl | /* System control */
|
519 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, base + MISC_SYS);
|
520 | 4b48bf05 | Blue Swirl | } |
521 | 4b48bf05 | Blue Swirl | if (aux1_base) {
|
522 | 4b48bf05 | Blue Swirl | /* AUX 1 (Misc System Functions) */
|
523 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, aux1_base);
|
524 | 4b48bf05 | Blue Swirl | } |
525 | 4b48bf05 | Blue Swirl | if (aux2_base) {
|
526 | 4b48bf05 | Blue Swirl | /* AUX 2 (Software Powerdown Control) */
|
527 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 6, aux2_base);
|
528 | 4b48bf05 | Blue Swirl | } |
529 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
530 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 1, fdc_tc);
|
531 | bea42280 | Igor Mammedov | slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
|
532 | bea42280 | Igor Mammedov | qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); |
533 | 4b48bf05 | Blue Swirl | } |
534 | 4b48bf05 | Blue Swirl | |
535 | a8170e5e | Avi Kivity | static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
536 | 4b48bf05 | Blue Swirl | { |
537 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
538 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
539 | 4b48bf05 | Blue Swirl | |
540 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "eccmemctl"); |
541 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "version", version);
|
542 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
543 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
544 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, irq);
|
545 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, base);
|
546 | 4b48bf05 | Blue Swirl | if (version == 0) { // SS-600MP only |
547 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, base + 0x1000); |
548 | 4b48bf05 | Blue Swirl | } |
549 | 4b48bf05 | Blue Swirl | } |
550 | 4b48bf05 | Blue Swirl | |
551 | a8170e5e | Avi Kivity | static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
552 | 4b48bf05 | Blue Swirl | { |
553 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
554 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
555 | 4b48bf05 | Blue Swirl | |
556 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "apc"); |
557 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
558 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
559 | 4b48bf05 | Blue Swirl | /* Power management (APC) XXX: not a Slavio device */
|
560 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, power_base);
|
561 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, 0, cpu_halt);
|
562 | 4b48bf05 | Blue Swirl | } |
563 | 4b48bf05 | Blue Swirl | |
564 | a8170e5e | Avi Kivity | static void tcx_init(hwaddr addr, int vram_size, int width, |
565 | 4b48bf05 | Blue Swirl | int height, int depth) |
566 | 4b48bf05 | Blue Swirl | { |
567 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
568 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
569 | 4b48bf05 | Blue Swirl | |
570 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "SUNW,tcx"); |
571 | 4b48bf05 | Blue Swirl | qdev_prop_set_taddr(dev, "addr", addr);
|
572 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint32(dev, "vram_size", vram_size);
|
573 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "width", width);
|
574 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "height", height);
|
575 | 4b48bf05 | Blue Swirl | qdev_prop_set_uint16(dev, "depth", depth);
|
576 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
577 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
578 | 4b48bf05 | Blue Swirl | /* 8-bit plane */
|
579 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr + 0x00800000ULL); |
580 | 4b48bf05 | Blue Swirl | /* DAC */
|
581 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 1, addr + 0x00200000ULL); |
582 | 4b48bf05 | Blue Swirl | /* TEC (dummy) */
|
583 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 2, addr + 0x00700000ULL); |
584 | 4b48bf05 | Blue Swirl | /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
|
585 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 3, addr + 0x00301000ULL); |
586 | 4b48bf05 | Blue Swirl | if (depth == 24) { |
587 | 4b48bf05 | Blue Swirl | /* 24-bit plane */
|
588 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x02000000ULL); |
589 | 4b48bf05 | Blue Swirl | /* Control plane */
|
590 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 5, addr + 0x0a000000ULL); |
591 | 4b48bf05 | Blue Swirl | } else {
|
592 | 4b48bf05 | Blue Swirl | /* THC 8 bit (dummy) */
|
593 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 4, addr + 0x00300000ULL); |
594 | 4b48bf05 | Blue Swirl | } |
595 | 4b48bf05 | Blue Swirl | } |
596 | 4b48bf05 | Blue Swirl | |
597 | 325f2747 | Blue Swirl | /* NCR89C100/MACIO Internal ID register */
|
598 | 325f2747 | Blue Swirl | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
599 | 325f2747 | Blue Swirl | |
600 | a8170e5e | Avi Kivity | static void idreg_init(hwaddr addr) |
601 | 325f2747 | Blue Swirl | { |
602 | 325f2747 | Blue Swirl | DeviceState *dev; |
603 | 325f2747 | Blue Swirl | SysBusDevice *s; |
604 | 325f2747 | Blue Swirl | |
605 | 325f2747 | Blue Swirl | dev = qdev_create(NULL, "macio_idreg"); |
606 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
607 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
608 | 325f2747 | Blue Swirl | |
609 | 325f2747 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
610 | 325f2747 | Blue Swirl | cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
|
611 | 325f2747 | Blue Swirl | } |
612 | 325f2747 | Blue Swirl | |
613 | 3150fa50 | Avi Kivity | typedef struct IDRegState { |
614 | 3150fa50 | Avi Kivity | SysBusDevice busdev; |
615 | 3150fa50 | Avi Kivity | MemoryRegion mem; |
616 | 3150fa50 | Avi Kivity | } IDRegState; |
617 | 3150fa50 | Avi Kivity | |
618 | 81a322d4 | Gerd Hoffmann | static int idreg_init1(SysBusDevice *dev) |
619 | 325f2747 | Blue Swirl | { |
620 | 3150fa50 | Avi Kivity | IDRegState *s = FROM_SYSBUS(IDRegState, dev); |
621 | 325f2747 | Blue Swirl | |
622 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data)); |
623 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->mem); |
624 | 3150fa50 | Avi Kivity | memory_region_set_readonly(&s->mem, true);
|
625 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->mem); |
626 | 81a322d4 | Gerd Hoffmann | return 0; |
627 | 325f2747 | Blue Swirl | } |
628 | 325f2747 | Blue Swirl | |
629 | 999e12bb | Anthony Liguori | static void idreg_class_init(ObjectClass *klass, void *data) |
630 | 999e12bb | Anthony Liguori | { |
631 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
632 | 999e12bb | Anthony Liguori | |
633 | 999e12bb | Anthony Liguori | k->init = idreg_init1; |
634 | 999e12bb | Anthony Liguori | } |
635 | 999e12bb | Anthony Liguori | |
636 | 8c43a6f0 | Andreas Färber | static const TypeInfo idreg_info = { |
637 | 39bffca2 | Anthony Liguori | .name = "macio_idreg",
|
638 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
639 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(IDRegState),
|
640 | 39bffca2 | Anthony Liguori | .class_init = idreg_class_init, |
641 | 325f2747 | Blue Swirl | }; |
642 | 325f2747 | Blue Swirl | |
643 | 3150fa50 | Avi Kivity | typedef struct AFXState { |
644 | 3150fa50 | Avi Kivity | SysBusDevice busdev; |
645 | 3150fa50 | Avi Kivity | MemoryRegion mem; |
646 | 3150fa50 | Avi Kivity | } AFXState; |
647 | 3150fa50 | Avi Kivity | |
648 | c5de386a | Artyom Tarasenko | /* SS-5 TCX AFX register */
|
649 | a8170e5e | Avi Kivity | static void afx_init(hwaddr addr) |
650 | c5de386a | Artyom Tarasenko | { |
651 | c5de386a | Artyom Tarasenko | DeviceState *dev; |
652 | c5de386a | Artyom Tarasenko | SysBusDevice *s; |
653 | c5de386a | Artyom Tarasenko | |
654 | c5de386a | Artyom Tarasenko | dev = qdev_create(NULL, "tcx_afx"); |
655 | c5de386a | Artyom Tarasenko | qdev_init_nofail(dev); |
656 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
657 | c5de386a | Artyom Tarasenko | |
658 | c5de386a | Artyom Tarasenko | sysbus_mmio_map(s, 0, addr);
|
659 | c5de386a | Artyom Tarasenko | } |
660 | c5de386a | Artyom Tarasenko | |
661 | c5de386a | Artyom Tarasenko | static int afx_init1(SysBusDevice *dev) |
662 | c5de386a | Artyom Tarasenko | { |
663 | 3150fa50 | Avi Kivity | AFXState *s = FROM_SYSBUS(AFXState, dev); |
664 | c5de386a | Artyom Tarasenko | |
665 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->mem, "sun4m.afx", 4); |
666 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->mem); |
667 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->mem); |
668 | c5de386a | Artyom Tarasenko | return 0; |
669 | c5de386a | Artyom Tarasenko | } |
670 | c5de386a | Artyom Tarasenko | |
671 | 999e12bb | Anthony Liguori | static void afx_class_init(ObjectClass *klass, void *data) |
672 | 999e12bb | Anthony Liguori | { |
673 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
674 | 999e12bb | Anthony Liguori | |
675 | 999e12bb | Anthony Liguori | k->init = afx_init1; |
676 | 999e12bb | Anthony Liguori | } |
677 | 999e12bb | Anthony Liguori | |
678 | 8c43a6f0 | Andreas Färber | static const TypeInfo afx_info = { |
679 | 39bffca2 | Anthony Liguori | .name = "tcx_afx",
|
680 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
681 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(AFXState),
|
682 | 39bffca2 | Anthony Liguori | .class_init = afx_class_init, |
683 | c5de386a | Artyom Tarasenko | }; |
684 | c5de386a | Artyom Tarasenko | |
685 | 3150fa50 | Avi Kivity | typedef struct PROMState { |
686 | 3150fa50 | Avi Kivity | SysBusDevice busdev; |
687 | 3150fa50 | Avi Kivity | MemoryRegion prom; |
688 | 3150fa50 | Avi Kivity | } PROMState; |
689 | 3150fa50 | Avi Kivity | |
690 | f48f6569 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
691 | 409dbce5 | Aurelien Jarno | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
692 | 409dbce5 | Aurelien Jarno | { |
693 | a8170e5e | Avi Kivity | hwaddr *base_addr = (hwaddr *)opaque; |
694 | 409dbce5 | Aurelien Jarno | return addr + *base_addr - PROM_VADDR;
|
695 | 409dbce5 | Aurelien Jarno | } |
696 | 409dbce5 | Aurelien Jarno | |
697 | a8170e5e | Avi Kivity | static void prom_init(hwaddr addr, const char *bios_name) |
698 | f48f6569 | Blue Swirl | { |
699 | f48f6569 | Blue Swirl | DeviceState *dev; |
700 | f48f6569 | Blue Swirl | SysBusDevice *s; |
701 | f48f6569 | Blue Swirl | char *filename;
|
702 | f48f6569 | Blue Swirl | int ret;
|
703 | f48f6569 | Blue Swirl | |
704 | f48f6569 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
705 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
706 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
707 | f48f6569 | Blue Swirl | |
708 | f48f6569 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
709 | f48f6569 | Blue Swirl | |
710 | f48f6569 | Blue Swirl | /* load boot prom */
|
711 | f48f6569 | Blue Swirl | if (bios_name == NULL) { |
712 | f48f6569 | Blue Swirl | bios_name = PROM_FILENAME; |
713 | f48f6569 | Blue Swirl | } |
714 | f48f6569 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
715 | f48f6569 | Blue Swirl | if (filename) {
|
716 | 409dbce5 | Aurelien Jarno | ret = load_elf(filename, translate_prom_address, &addr, NULL,
|
717 | 409dbce5 | Aurelien Jarno | NULL, NULL, 1, ELF_MACHINE, 0); |
718 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
719 | f48f6569 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
720 | f48f6569 | Blue Swirl | } |
721 | 7267c094 | Anthony Liguori | g_free(filename); |
722 | f48f6569 | Blue Swirl | } else {
|
723 | f48f6569 | Blue Swirl | ret = -1;
|
724 | f48f6569 | Blue Swirl | } |
725 | f48f6569 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
726 | f48f6569 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
727 | f48f6569 | Blue Swirl | exit(1);
|
728 | f48f6569 | Blue Swirl | } |
729 | f48f6569 | Blue Swirl | } |
730 | f48f6569 | Blue Swirl | |
731 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
732 | f48f6569 | Blue Swirl | { |
733 | 3150fa50 | Avi Kivity | PROMState *s = FROM_SYSBUS(PROMState, dev); |
734 | f48f6569 | Blue Swirl | |
735 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
|
736 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->prom); |
737 | 3150fa50 | Avi Kivity | memory_region_set_readonly(&s->prom, true);
|
738 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->prom); |
739 | 81a322d4 | Gerd Hoffmann | return 0; |
740 | f48f6569 | Blue Swirl | } |
741 | f48f6569 | Blue Swirl | |
742 | 999e12bb | Anthony Liguori | static Property prom_properties[] = {
|
743 | 999e12bb | Anthony Liguori | {/* end of property list */},
|
744 | 999e12bb | Anthony Liguori | }; |
745 | 999e12bb | Anthony Liguori | |
746 | 999e12bb | Anthony Liguori | static void prom_class_init(ObjectClass *klass, void *data) |
747 | 999e12bb | Anthony Liguori | { |
748 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
749 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
750 | 999e12bb | Anthony Liguori | |
751 | 999e12bb | Anthony Liguori | k->init = prom_init1; |
752 | 39bffca2 | Anthony Liguori | dc->props = prom_properties; |
753 | 999e12bb | Anthony Liguori | } |
754 | 999e12bb | Anthony Liguori | |
755 | 8c43a6f0 | Andreas Färber | static const TypeInfo prom_info = { |
756 | 39bffca2 | Anthony Liguori | .name = "openprom",
|
757 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
758 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PROMState),
|
759 | 39bffca2 | Anthony Liguori | .class_init = prom_class_init, |
760 | f48f6569 | Blue Swirl | }; |
761 | f48f6569 | Blue Swirl | |
762 | ee6847d1 | Gerd Hoffmann | typedef struct RamDevice |
763 | ee6847d1 | Gerd Hoffmann | { |
764 | ee6847d1 | Gerd Hoffmann | SysBusDevice busdev; |
765 | 3150fa50 | Avi Kivity | MemoryRegion ram; |
766 | 04843626 | Blue Swirl | uint64_t size; |
767 | ee6847d1 | Gerd Hoffmann | } RamDevice; |
768 | ee6847d1 | Gerd Hoffmann | |
769 | a350db85 | Blue Swirl | /* System RAM */
|
770 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
771 | a350db85 | Blue Swirl | { |
772 | ee6847d1 | Gerd Hoffmann | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
773 | a350db85 | Blue Swirl | |
774 | c5705a77 | Avi Kivity | memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
|
775 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&d->ram); |
776 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &d->ram); |
777 | 81a322d4 | Gerd Hoffmann | return 0; |
778 | a350db85 | Blue Swirl | } |
779 | a350db85 | Blue Swirl | |
780 | a8170e5e | Avi Kivity | static void ram_init(hwaddr addr, ram_addr_t RAM_size, |
781 | a350db85 | Blue Swirl | uint64_t max_mem) |
782 | a350db85 | Blue Swirl | { |
783 | a350db85 | Blue Swirl | DeviceState *dev; |
784 | a350db85 | Blue Swirl | SysBusDevice *s; |
785 | ee6847d1 | Gerd Hoffmann | RamDevice *d; |
786 | a350db85 | Blue Swirl | |
787 | a350db85 | Blue Swirl | /* allocate RAM */
|
788 | a350db85 | Blue Swirl | if ((uint64_t)RAM_size > max_mem) {
|
789 | a350db85 | Blue Swirl | fprintf(stderr, |
790 | a350db85 | Blue Swirl | "qemu: Too much memory for this machine: %d, maximum %d\n",
|
791 | a350db85 | Blue Swirl | (unsigned int)(RAM_size / (1024 * 1024)), |
792 | a350db85 | Blue Swirl | (unsigned int)(max_mem / (1024 * 1024))); |
793 | a350db85 | Blue Swirl | exit(1);
|
794 | a350db85 | Blue Swirl | } |
795 | a350db85 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
796 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
797 | a350db85 | Blue Swirl | |
798 | ee6847d1 | Gerd Hoffmann | d = FROM_SYSBUS(RamDevice, s); |
799 | ee6847d1 | Gerd Hoffmann | d->size = RAM_size; |
800 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
801 | ee6847d1 | Gerd Hoffmann | |
802 | a350db85 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
803 | a350db85 | Blue Swirl | } |
804 | a350db85 | Blue Swirl | |
805 | 999e12bb | Anthony Liguori | static Property ram_properties[] = {
|
806 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
807 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
808 | 999e12bb | Anthony Liguori | }; |
809 | 999e12bb | Anthony Liguori | |
810 | 999e12bb | Anthony Liguori | static void ram_class_init(ObjectClass *klass, void *data) |
811 | 999e12bb | Anthony Liguori | { |
812 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
813 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
814 | 999e12bb | Anthony Liguori | |
815 | 999e12bb | Anthony Liguori | k->init = ram_init1; |
816 | 39bffca2 | Anthony Liguori | dc->props = ram_properties; |
817 | 999e12bb | Anthony Liguori | } |
818 | 999e12bb | Anthony Liguori | |
819 | 8c43a6f0 | Andreas Färber | static const TypeInfo ram_info = { |
820 | 39bffca2 | Anthony Liguori | .name = "memory",
|
821 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
822 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(RamDevice),
|
823 | 39bffca2 | Anthony Liguori | .class_init = ram_class_init, |
824 | a350db85 | Blue Swirl | }; |
825 | a350db85 | Blue Swirl | |
826 | 89835363 | Blue Swirl | static void cpu_devinit(const char *cpu_model, unsigned int id, |
827 | 89835363 | Blue Swirl | uint64_t prom_addr, qemu_irq **cpu_irqs) |
828 | 666713c0 | Blue Swirl | { |
829 | 8968f588 | Andreas Färber | SPARCCPU *cpu; |
830 | 98cec4a2 | Andreas Färber | CPUSPARCState *env; |
831 | 666713c0 | Blue Swirl | |
832 | 8968f588 | Andreas Färber | cpu = cpu_sparc_init(cpu_model); |
833 | 8968f588 | Andreas Färber | if (cpu == NULL) { |
834 | 666713c0 | Blue Swirl | fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
|
835 | 666713c0 | Blue Swirl | exit(1);
|
836 | 666713c0 | Blue Swirl | } |
837 | 8968f588 | Andreas Färber | env = &cpu->env; |
838 | 666713c0 | Blue Swirl | |
839 | 666713c0 | Blue Swirl | cpu_sparc_set_id(env, id); |
840 | 666713c0 | Blue Swirl | if (id == 0) { |
841 | 5414dec6 | Andreas Färber | qemu_register_reset(main_cpu_reset, cpu); |
842 | 666713c0 | Blue Swirl | } else {
|
843 | 5414dec6 | Andreas Färber | qemu_register_reset(secondary_cpu_reset, cpu); |
844 | 666713c0 | Blue Swirl | env->halted = 1;
|
845 | 666713c0 | Blue Swirl | } |
846 | e0bbf9b5 | Andreas Färber | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); |
847 | 666713c0 | Blue Swirl | env->prom_addr = prom_addr; |
848 | 666713c0 | Blue Swirl | } |
849 | 666713c0 | Blue Swirl | |
850 | acfbe712 | Blue Swirl | static void dummy_fdc_tc(void *opaque, int irq, int level) |
851 | acfbe712 | Blue Swirl | { |
852 | acfbe712 | Blue Swirl | } |
853 | acfbe712 | Blue Swirl | |
854 | c227f099 | Anthony Liguori | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size, |
855 | 3ebf5aaf | blueswir1 | const char *boot_device, |
856 | 3023f332 | aliguori | const char *kernel_filename, |
857 | 3ebf5aaf | blueswir1 | const char *kernel_cmdline, |
858 | 3ebf5aaf | blueswir1 | const char *initrd_filename, const char *cpu_model) |
859 | 420557e8 | bellard | { |
860 | 713c45fa | bellard | unsigned int i; |
861 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
862 | a1961a4b | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
|
863 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
864 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
865 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
866 | 6d0c293d | blueswir1 | qemu_irq *cpu_halt; |
867 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
868 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
869 | 3cce6243 | blueswir1 | void *fw_cfg;
|
870 | 9a62fb24 | Bob Breuer | unsigned int num_vsimms; |
871 | 420557e8 | bellard | |
872 | ba3c64fb | bellard | /* init CPUs */
|
873 | 3ebf5aaf | blueswir1 | if (!cpu_model)
|
874 | 3ebf5aaf | blueswir1 | cpu_model = hwdef->default_cpu_model; |
875 | b3a23197 | blueswir1 | |
876 | ba3c64fb | bellard | for(i = 0; i < smp_cpus; i++) { |
877 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
878 | ba3c64fb | bellard | } |
879 | b3a23197 | blueswir1 | |
880 | b3a23197 | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
881 | b3a23197 | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
882 | b3a23197 | blueswir1 | |
883 | 3ebf5aaf | blueswir1 | |
884 | 3ebf5aaf | blueswir1 | /* set up devices */
|
885 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
886 | 676d9b9b | Artyom Tarasenko | /* models without ECC don't trap when missing ram is accessed */
|
887 | 676d9b9b | Artyom Tarasenko | if (!hwdef->ecc_base) {
|
888 | 676d9b9b | Artyom Tarasenko | empty_slot_init(RAM_size, hwdef->max_mem - RAM_size); |
889 | 676d9b9b | Artyom Tarasenko | } |
890 | a350db85 | Blue Swirl | |
891 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
892 | f48f6569 | Blue Swirl | |
893 | d453c2c3 | Blue Swirl | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
894 | d453c2c3 | Blue Swirl | hwdef->intctl_base + 0x10000ULL,
|
895 | 462eda24 | Blue Swirl | cpu_irqs); |
896 | a1961a4b | Blue Swirl | |
897 | a1961a4b | Blue Swirl | for (i = 0; i < 32; i++) { |
898 | d453c2c3 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
899 | a1961a4b | Blue Swirl | } |
900 | a1961a4b | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
901 | d453c2c3 | Blue Swirl | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
|
902 | a1961a4b | Blue Swirl | } |
903 | b3a23197 | blueswir1 | |
904 | fe096129 | blueswir1 | if (hwdef->idreg_base) {
|
905 | 325f2747 | Blue Swirl | idreg_init(hwdef->idreg_base); |
906 | 4c2485de | blueswir1 | } |
907 | 4c2485de | blueswir1 | |
908 | c5de386a | Artyom Tarasenko | if (hwdef->afx_base) {
|
909 | c5de386a | Artyom Tarasenko | afx_init(hwdef->afx_base); |
910 | c5de386a | Artyom Tarasenko | } |
911 | c5de386a | Artyom Tarasenko | |
912 | ff403da6 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
913 | c533e0b3 | Blue Swirl | slavio_irq[30]);
|
914 | ff403da6 | blueswir1 | |
915 | 3386376c | Artyom Tarasenko | if (hwdef->iommu_pad_base) {
|
916 | 3386376c | Artyom Tarasenko | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
|
917 | 3386376c | Artyom Tarasenko | Software shouldn't use aliased addresses, neither should it crash
|
918 | 3386376c | Artyom Tarasenko | when does. Using empty_slot instead of aliasing can help with
|
919 | 3386376c | Artyom Tarasenko | debugging such accesses */
|
920 | 3386376c | Artyom Tarasenko | empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); |
921 | 3386376c | Artyom Tarasenko | } |
922 | 3386376c | Artyom Tarasenko | |
923 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
|
924 | 86d1c388 | Bob Breuer | iommu, &espdma_irq, 0);
|
925 | 2d069bab | blueswir1 | |
926 | 5aca8c3b | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
927 | 86d1c388 | Bob Breuer | slavio_irq[16], iommu, &ledma_irq, 1); |
928 | ba3c64fb | bellard | |
929 | eee0b836 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
930 | eee0b836 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
931 | eee0b836 | blueswir1 | exit (1);
|
932 | eee0b836 | blueswir1 | } |
933 | 9a62fb24 | Bob Breuer | num_vsimms = 0;
|
934 | 9a62fb24 | Bob Breuer | if (num_vsimms == 0) { |
935 | 9a62fb24 | Bob Breuer | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
936 | 9a62fb24 | Bob Breuer | graphic_depth); |
937 | 9a62fb24 | Bob Breuer | } |
938 | 9a62fb24 | Bob Breuer | |
939 | 9a62fb24 | Bob Breuer | for (i = num_vsimms; i < MAX_VSIMMS; i++) {
|
940 | 9a62fb24 | Bob Breuer | /* vsimm registers probed by OBP */
|
941 | 9a62fb24 | Bob Breuer | if (hwdef->vsimm[i].reg_base) {
|
942 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
|
943 | 9a62fb24 | Bob Breuer | } |
944 | 9a62fb24 | Bob Breuer | } |
945 | 9a62fb24 | Bob Breuer | |
946 | 9a62fb24 | Bob Breuer | if (hwdef->sx_base) {
|
947 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->sx_base, 0x2000);
|
948 | 9a62fb24 | Bob Breuer | } |
949 | dbe06e18 | blueswir1 | |
950 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
951 | dbe06e18 | blueswir1 | |
952 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
953 | 81732d19 | blueswir1 | |
954 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
|
955 | 81732d19 | blueswir1 | |
956 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
|
957 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
958 | 5cbdb3a3 | Stefan Weil | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
|
959 | 5cbdb3a3 | Stefan Weil | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
|
960 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
961 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
962 | 741402f9 | blueswir1 | |
963 | 6d0c293d | blueswir1 | cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1); |
964 | 2582cfa0 | Blue Swirl | if (hwdef->apc_base) {
|
965 | 2582cfa0 | Blue Swirl | apc_init(hwdef->apc_base, cpu_halt[0]);
|
966 | 2582cfa0 | Blue Swirl | } |
967 | 2be17ebd | blueswir1 | |
968 | fe096129 | blueswir1 | if (hwdef->fd_base) {
|
969 | e4bcb14c | ths | /* there is zero or one floppy drive */
|
970 | 309e60bd | blueswir1 | memset(fd, 0, sizeof(fd)); |
971 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
972 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
|
973 | 2582cfa0 | Blue Swirl | &fdc_tc); |
974 | acfbe712 | Blue Swirl | } else {
|
975 | acfbe712 | Blue Swirl | fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); |
976 | e4bcb14c | ths | } |
977 | e4bcb14c | ths | |
978 | acfbe712 | Blue Swirl | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
979 | acfbe712 | Blue Swirl | slavio_irq[30], fdc_tc);
|
980 | acfbe712 | Blue Swirl | |
981 | e4bcb14c | ths | if (drive_get_max_bus(IF_SCSI) > 0) { |
982 | e4bcb14c | ths | fprintf(stderr, "qemu: too many SCSI bus\n");
|
983 | e4bcb14c | ths | exit(1);
|
984 | e4bcb14c | ths | } |
985 | e4bcb14c | ths | |
986 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
987 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
988 | 73d74342 | Blue Swirl | espdma, espdma_irq, &esp_reset, &dma_enable); |
989 | 74ff8d90 | Blue Swirl | |
990 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 0, esp_reset);
|
991 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 1, dma_enable);
|
992 | f1587550 | ths | |
993 | fa28ec52 | Blue Swirl | if (hwdef->cs_base) {
|
994 | fa28ec52 | Blue Swirl | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
|
995 | c533e0b3 | Blue Swirl | slavio_irq[5]);
|
996 | fa28ec52 | Blue Swirl | } |
997 | b3ceef24 | blueswir1 | |
998 | 9a62fb24 | Bob Breuer | if (hwdef->dbri_base) {
|
999 | 9a62fb24 | Bob Breuer | /* ISDN chip with attached CS4215 audio codec */
|
1000 | 9a62fb24 | Bob Breuer | /* prom space */
|
1001 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->dbri_base+0x1000, 0x30); |
1002 | 9a62fb24 | Bob Breuer | /* reg space */
|
1003 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->dbri_base+0x10000, 0x100); |
1004 | 9a62fb24 | Bob Breuer | } |
1005 | 9a62fb24 | Bob Breuer | |
1006 | 9a62fb24 | Bob Breuer | if (hwdef->bpp_base) {
|
1007 | 9a62fb24 | Bob Breuer | /* parallel port */
|
1008 | 9a62fb24 | Bob Breuer | empty_slot_init(hwdef->bpp_base, 0x20);
|
1009 | 9a62fb24 | Bob Breuer | } |
1010 | 9a62fb24 | Bob Breuer | |
1011 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1012 | 293f78bc | blueswir1 | RAM_size); |
1013 | 36cd9210 | blueswir1 | |
1014 | 36cd9210 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1015 | b3ceef24 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1016 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1017 | 905fdcb5 | blueswir1 | "Sun4m");
|
1018 | 7eb0c8e8 | blueswir1 | |
1019 | fe096129 | blueswir1 | if (hwdef->ecc_base)
|
1020 | c533e0b3 | Blue Swirl | ecc_init(hwdef->ecc_base, slavio_irq[28],
|
1021 | e42c20b4 | blueswir1 | hwdef->ecc_version); |
1022 | 3cce6243 | blueswir1 | |
1023 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1024 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1025 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1026 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1027 | fbfcf955 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1028 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1029 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1030 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1031 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1032 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1033 | 0e0d2d62 | Markus Armbruster | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
1034 | 748a4ee3 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
1035 | 748a4ee3 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
1036 | 513f789f | blueswir1 | } else {
|
1037 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1038 | 748a4ee3 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
1039 | 513f789f | blueswir1 | } |
1040 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1041 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1042 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1043 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1044 | 36cd9210 | blueswir1 | } |
1045 | 36cd9210 | blueswir1 | |
1046 | 905fdcb5 | blueswir1 | enum {
|
1047 | 905fdcb5 | blueswir1 | ss2_id = 0,
|
1048 | 905fdcb5 | blueswir1 | ss5_id = 32,
|
1049 | 905fdcb5 | blueswir1 | vger_id, |
1050 | 905fdcb5 | blueswir1 | lx_id, |
1051 | 905fdcb5 | blueswir1 | ss4_id, |
1052 | 905fdcb5 | blueswir1 | scls_id, |
1053 | 905fdcb5 | blueswir1 | sbook_id, |
1054 | 905fdcb5 | blueswir1 | ss10_id = 64,
|
1055 | 905fdcb5 | blueswir1 | ss20_id, |
1056 | 905fdcb5 | blueswir1 | ss600mp_id, |
1057 | 905fdcb5 | blueswir1 | ss1000_id = 96,
|
1058 | 905fdcb5 | blueswir1 | ss2000_id, |
1059 | 905fdcb5 | blueswir1 | }; |
1060 | 905fdcb5 | blueswir1 | |
1061 | 8137cde8 | blueswir1 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
1062 | 36cd9210 | blueswir1 | /* SS-5 */
|
1063 | 36cd9210 | blueswir1 | { |
1064 | 36cd9210 | blueswir1 | .iommu_base = 0x10000000,
|
1065 | 3386376c | Artyom Tarasenko | .iommu_pad_base = 0x10004000,
|
1066 | 3386376c | Artyom Tarasenko | .iommu_pad_len = 0x0fffb000,
|
1067 | 36cd9210 | blueswir1 | .tcx_base = 0x50000000,
|
1068 | 36cd9210 | blueswir1 | .cs_base = 0x6c000000,
|
1069 | 384ccb5d | blueswir1 | .slavio_base = 0x70000000,
|
1070 | 36cd9210 | blueswir1 | .ms_kb_base = 0x71000000,
|
1071 | 36cd9210 | blueswir1 | .serial_base = 0x71100000,
|
1072 | 36cd9210 | blueswir1 | .nvram_base = 0x71200000,
|
1073 | 36cd9210 | blueswir1 | .fd_base = 0x71400000,
|
1074 | 36cd9210 | blueswir1 | .counter_base = 0x71d00000,
|
1075 | 36cd9210 | blueswir1 | .intctl_base = 0x71e00000,
|
1076 | 4c2485de | blueswir1 | .idreg_base = 0x78000000,
|
1077 | 36cd9210 | blueswir1 | .dma_base = 0x78400000,
|
1078 | 36cd9210 | blueswir1 | .esp_base = 0x78800000,
|
1079 | 36cd9210 | blueswir1 | .le_base = 0x78c00000,
|
1080 | 127fc407 | blueswir1 | .apc_base = 0x6a000000,
|
1081 | c5de386a | Artyom Tarasenko | .afx_base = 0x6e000000,
|
1082 | 0019ad53 | blueswir1 | .aux1_base = 0x71900000,
|
1083 | 0019ad53 | blueswir1 | .aux2_base = 0x71910000,
|
1084 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1085 | 905fdcb5 | blueswir1 | .machine_id = ss5_id, |
1086 | cf3102ac | blueswir1 | .iommu_version = 0x05000000,
|
1087 | 3ebf5aaf | blueswir1 | .max_mem = 0x10000000,
|
1088 | 3ebf5aaf | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1089 | e0353fe2 | blueswir1 | }, |
1090 | e0353fe2 | blueswir1 | /* SS-10 */
|
1091 | e0353fe2 | blueswir1 | { |
1092 | 5dcb6b91 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1093 | 5dcb6b91 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1094 | 5dcb6b91 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1095 | 5dcb6b91 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1096 | 5dcb6b91 | blueswir1 | .serial_base = 0xff1100000ULL,
|
1097 | 5dcb6b91 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1098 | 5dcb6b91 | blueswir1 | .fd_base = 0xff1700000ULL,
|
1099 | 5dcb6b91 | blueswir1 | .counter_base = 0xff1300000ULL,
|
1100 | 5dcb6b91 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1101 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
1102 | 5dcb6b91 | blueswir1 | .dma_base = 0xef0400000ULL,
|
1103 | 5dcb6b91 | blueswir1 | .esp_base = 0xef0800000ULL,
|
1104 | 5dcb6b91 | blueswir1 | .le_base = 0xef0c00000ULL,
|
1105 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1106 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1107 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
1108 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1109 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x10000000, // version 0, implementation 1 |
1110 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
1111 | 905fdcb5 | blueswir1 | .machine_id = ss10_id, |
1112 | 7fbfb139 | blueswir1 | .iommu_version = 0x03000000,
|
1113 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1114 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1115 | 36cd9210 | blueswir1 | }, |
1116 | 6a3b9cc9 | blueswir1 | /* SS-600MP */
|
1117 | 6a3b9cc9 | blueswir1 | { |
1118 | 6a3b9cc9 | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1119 | 6a3b9cc9 | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1120 | 6a3b9cc9 | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1121 | 6a3b9cc9 | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1122 | 6a3b9cc9 | blueswir1 | .serial_base = 0xff1100000ULL,
|
1123 | 6a3b9cc9 | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1124 | 6a3b9cc9 | blueswir1 | .counter_base = 0xff1300000ULL,
|
1125 | 6a3b9cc9 | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1126 | 6a3b9cc9 | blueswir1 | .dma_base = 0xef0081000ULL,
|
1127 | 6a3b9cc9 | blueswir1 | .esp_base = 0xef0080000ULL,
|
1128 | 6a3b9cc9 | blueswir1 | .le_base = 0xef0060000ULL,
|
1129 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1130 | 127fc407 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1131 | 127fc407 | blueswir1 | .aux2_base = 0xff1a01000ULL, // XXX should not exist |
1132 | 7eb0c8e8 | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1133 | 7eb0c8e8 | blueswir1 | .ecc_version = 0x00000000, // version 0, implementation 0 |
1134 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x71,
|
1135 | 905fdcb5 | blueswir1 | .machine_id = ss600mp_id, |
1136 | 7fbfb139 | blueswir1 | .iommu_version = 0x01000000,
|
1137 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1138 | 3ebf5aaf | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1139 | 6a3b9cc9 | blueswir1 | }, |
1140 | ae40972f | blueswir1 | /* SS-20 */
|
1141 | ae40972f | blueswir1 | { |
1142 | ae40972f | blueswir1 | .iommu_base = 0xfe0000000ULL,
|
1143 | ae40972f | blueswir1 | .tcx_base = 0xe20000000ULL,
|
1144 | ae40972f | blueswir1 | .slavio_base = 0xff0000000ULL,
|
1145 | ae40972f | blueswir1 | .ms_kb_base = 0xff1000000ULL,
|
1146 | ae40972f | blueswir1 | .serial_base = 0xff1100000ULL,
|
1147 | ae40972f | blueswir1 | .nvram_base = 0xff1200000ULL,
|
1148 | ae40972f | blueswir1 | .fd_base = 0xff1700000ULL,
|
1149 | ae40972f | blueswir1 | .counter_base = 0xff1300000ULL,
|
1150 | ae40972f | blueswir1 | .intctl_base = 0xff1400000ULL,
|
1151 | 4c2485de | blueswir1 | .idreg_base = 0xef0000000ULL,
|
1152 | ae40972f | blueswir1 | .dma_base = 0xef0400000ULL,
|
1153 | ae40972f | blueswir1 | .esp_base = 0xef0800000ULL,
|
1154 | ae40972f | blueswir1 | .le_base = 0xef0c00000ULL,
|
1155 | 9a62fb24 | Bob Breuer | .bpp_base = 0xef4800000ULL,
|
1156 | 0019ad53 | blueswir1 | .apc_base = 0xefa000000ULL, // XXX should not exist |
1157 | 577d8dd4 | blueswir1 | .aux1_base = 0xff1800000ULL,
|
1158 | 577d8dd4 | blueswir1 | .aux2_base = 0xff1a01000ULL,
|
1159 | 9a62fb24 | Bob Breuer | .dbri_base = 0xee0000000ULL,
|
1160 | 9a62fb24 | Bob Breuer | .sx_base = 0xf80000000ULL,
|
1161 | 9a62fb24 | Bob Breuer | .vsimm = { |
1162 | 9a62fb24 | Bob Breuer | { |
1163 | 9a62fb24 | Bob Breuer | .reg_base = 0x9c000000ULL,
|
1164 | 9a62fb24 | Bob Breuer | .vram_base = 0xfc000000ULL
|
1165 | 9a62fb24 | Bob Breuer | }, { |
1166 | 9a62fb24 | Bob Breuer | .reg_base = 0x90000000ULL,
|
1167 | 9a62fb24 | Bob Breuer | .vram_base = 0xf0000000ULL
|
1168 | 9a62fb24 | Bob Breuer | }, { |
1169 | 9a62fb24 | Bob Breuer | .reg_base = 0x94000000ULL
|
1170 | 9a62fb24 | Bob Breuer | }, { |
1171 | 9a62fb24 | Bob Breuer | .reg_base = 0x98000000ULL
|
1172 | 9a62fb24 | Bob Breuer | } |
1173 | 9a62fb24 | Bob Breuer | }, |
1174 | ae40972f | blueswir1 | .ecc_base = 0xf00000000ULL,
|
1175 | ae40972f | blueswir1 | .ecc_version = 0x20000000, // version 0, implementation 2 |
1176 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x72,
|
1177 | 905fdcb5 | blueswir1 | .machine_id = ss20_id, |
1178 | ae40972f | blueswir1 | .iommu_version = 0x13000000,
|
1179 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1180 | ae40972f | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1181 | ae40972f | blueswir1 | }, |
1182 | a526a31c | blueswir1 | /* Voyager */
|
1183 | a526a31c | blueswir1 | { |
1184 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1185 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1186 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1187 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1188 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1189 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1190 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1191 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1192 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1193 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1194 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1195 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1196 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1197 | a526a31c | blueswir1 | .apc_base = 0x71300000, // pmc |
1198 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1199 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1200 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1201 | 905fdcb5 | blueswir1 | .machine_id = vger_id, |
1202 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1203 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1204 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1205 | a526a31c | blueswir1 | }, |
1206 | a526a31c | blueswir1 | /* LX */
|
1207 | a526a31c | blueswir1 | { |
1208 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1209 | 3386376c | Artyom Tarasenko | .iommu_pad_base = 0x10004000,
|
1210 | 3386376c | Artyom Tarasenko | .iommu_pad_len = 0x0fffb000,
|
1211 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1212 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1213 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1214 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1215 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1216 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1217 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1218 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1219 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1220 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1221 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1222 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1223 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1224 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1225 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1226 | 905fdcb5 | blueswir1 | .machine_id = lx_id, |
1227 | a526a31c | blueswir1 | .iommu_version = 0x04000000,
|
1228 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1229 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1230 | a526a31c | blueswir1 | }, |
1231 | a526a31c | blueswir1 | /* SS-4 */
|
1232 | a526a31c | blueswir1 | { |
1233 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1234 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1235 | a526a31c | blueswir1 | .cs_base = 0x6c000000,
|
1236 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1237 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1238 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1239 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1240 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1241 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1242 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1243 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1244 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1245 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1246 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1247 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1248 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1249 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1250 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1251 | 905fdcb5 | blueswir1 | .machine_id = ss4_id, |
1252 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1253 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1254 | a526a31c | blueswir1 | .default_cpu_model = "Fujitsu MB86904",
|
1255 | a526a31c | blueswir1 | }, |
1256 | a526a31c | blueswir1 | /* SPARCClassic */
|
1257 | a526a31c | blueswir1 | { |
1258 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1259 | a526a31c | blueswir1 | .tcx_base = 0x50000000,
|
1260 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1261 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1262 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1263 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1264 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1265 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1266 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1267 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1268 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1269 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1270 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1271 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1272 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1273 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1274 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1275 | 905fdcb5 | blueswir1 | .machine_id = scls_id, |
1276 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1277 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1278 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1279 | a526a31c | blueswir1 | }, |
1280 | a526a31c | blueswir1 | /* SPARCbook */
|
1281 | a526a31c | blueswir1 | { |
1282 | a526a31c | blueswir1 | .iommu_base = 0x10000000,
|
1283 | a526a31c | blueswir1 | .tcx_base = 0x50000000, // XXX |
1284 | a526a31c | blueswir1 | .slavio_base = 0x70000000,
|
1285 | a526a31c | blueswir1 | .ms_kb_base = 0x71000000,
|
1286 | a526a31c | blueswir1 | .serial_base = 0x71100000,
|
1287 | a526a31c | blueswir1 | .nvram_base = 0x71200000,
|
1288 | a526a31c | blueswir1 | .fd_base = 0x71400000,
|
1289 | a526a31c | blueswir1 | .counter_base = 0x71d00000,
|
1290 | a526a31c | blueswir1 | .intctl_base = 0x71e00000,
|
1291 | a526a31c | blueswir1 | .idreg_base = 0x78000000,
|
1292 | a526a31c | blueswir1 | .dma_base = 0x78400000,
|
1293 | a526a31c | blueswir1 | .esp_base = 0x78800000,
|
1294 | a526a31c | blueswir1 | .le_base = 0x78c00000,
|
1295 | a526a31c | blueswir1 | .apc_base = 0x6a000000,
|
1296 | a526a31c | blueswir1 | .aux1_base = 0x71900000,
|
1297 | a526a31c | blueswir1 | .aux2_base = 0x71910000,
|
1298 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1299 | 905fdcb5 | blueswir1 | .machine_id = sbook_id, |
1300 | a526a31c | blueswir1 | .iommu_version = 0x05000000,
|
1301 | a526a31c | blueswir1 | .max_mem = 0x10000000,
|
1302 | a526a31c | blueswir1 | .default_cpu_model = "TI MicroSparc I",
|
1303 | a526a31c | blueswir1 | }, |
1304 | 36cd9210 | blueswir1 | }; |
1305 | 36cd9210 | blueswir1 | |
1306 | 36cd9210 | blueswir1 | /* SPARCstation 5 hardware initialisation */
|
1307 | 5f072e1f | Eduardo Habkost | static void ss5_init(QEMUMachineInitArgs *args) |
1308 | 36cd9210 | blueswir1 | { |
1309 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1310 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1311 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1312 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1313 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1314 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1315 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1316 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1317 | 420557e8 | bellard | } |
1318 | c0e564d5 | bellard | |
1319 | e0353fe2 | blueswir1 | /* SPARCstation 10 hardware initialisation */
|
1320 | 5f072e1f | Eduardo Habkost | static void ss10_init(QEMUMachineInitArgs *args) |
1321 | e0353fe2 | blueswir1 | { |
1322 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1323 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1324 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1325 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1326 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1327 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1328 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1329 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1330 | e0353fe2 | blueswir1 | } |
1331 | e0353fe2 | blueswir1 | |
1332 | 6a3b9cc9 | blueswir1 | /* SPARCserver 600MP hardware initialisation */
|
1333 | 5f072e1f | Eduardo Habkost | static void ss600mp_init(QEMUMachineInitArgs *args) |
1334 | 6a3b9cc9 | blueswir1 | { |
1335 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1336 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1337 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1338 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1339 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1340 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1341 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
|
1342 | 3ebf5aaf | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1343 | 6a3b9cc9 | blueswir1 | } |
1344 | 6a3b9cc9 | blueswir1 | |
1345 | ae40972f | blueswir1 | /* SPARCstation 20 hardware initialisation */
|
1346 | 5f072e1f | Eduardo Habkost | static void ss20_init(QEMUMachineInitArgs *args) |
1347 | ae40972f | blueswir1 | { |
1348 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1349 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1350 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1351 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1352 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1353 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1354 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
|
1355 | ee76f82e | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1356 | ee76f82e | blueswir1 | } |
1357 | ee76f82e | blueswir1 | |
1358 | a526a31c | blueswir1 | /* SPARCstation Voyager hardware initialisation */
|
1359 | 5f072e1f | Eduardo Habkost | static void vger_init(QEMUMachineInitArgs *args) |
1360 | a526a31c | blueswir1 | { |
1361 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1362 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1363 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1364 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1365 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1366 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1367 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
|
1368 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1369 | a526a31c | blueswir1 | } |
1370 | a526a31c | blueswir1 | |
1371 | a526a31c | blueswir1 | /* SPARCstation LX hardware initialisation */
|
1372 | 5f072e1f | Eduardo Habkost | static void ss_lx_init(QEMUMachineInitArgs *args) |
1373 | a526a31c | blueswir1 | { |
1374 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1375 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1376 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1377 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1378 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1379 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1380 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
|
1381 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1382 | a526a31c | blueswir1 | } |
1383 | a526a31c | blueswir1 | |
1384 | a526a31c | blueswir1 | /* SPARCstation 4 hardware initialisation */
|
1385 | 5f072e1f | Eduardo Habkost | static void ss4_init(QEMUMachineInitArgs *args) |
1386 | a526a31c | blueswir1 | { |
1387 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1388 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1389 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1390 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1391 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1392 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1393 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
|
1394 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1395 | a526a31c | blueswir1 | } |
1396 | a526a31c | blueswir1 | |
1397 | a526a31c | blueswir1 | /* SPARCClassic hardware initialisation */
|
1398 | 5f072e1f | Eduardo Habkost | static void scls_init(QEMUMachineInitArgs *args) |
1399 | a526a31c | blueswir1 | { |
1400 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1401 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1402 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1403 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1404 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1405 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1406 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
|
1407 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1408 | a526a31c | blueswir1 | } |
1409 | a526a31c | blueswir1 | |
1410 | a526a31c | blueswir1 | /* SPARCbook hardware initialisation */
|
1411 | 5f072e1f | Eduardo Habkost | static void sbook_init(QEMUMachineInitArgs *args) |
1412 | a526a31c | blueswir1 | { |
1413 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1414 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1415 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1416 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1417 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1418 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1419 | 3023f332 | aliguori | sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
|
1420 | a526a31c | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1421 | a526a31c | blueswir1 | } |
1422 | a526a31c | blueswir1 | |
1423 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss5_machine = {
|
1424 | 66de733b | blueswir1 | .name = "SS-5",
|
1425 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 5",
|
1426 | 66de733b | blueswir1 | .init = ss5_init, |
1427 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1428 | 0c257437 | Anthony Liguori | .is_default = 1,
|
1429 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1430 | c0e564d5 | bellard | }; |
1431 | e0353fe2 | blueswir1 | |
1432 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss10_machine = {
|
1433 | 66de733b | blueswir1 | .name = "SS-10",
|
1434 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 10",
|
1435 | 66de733b | blueswir1 | .init = ss10_init, |
1436 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1437 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1438 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1439 | e0353fe2 | blueswir1 | }; |
1440 | 6a3b9cc9 | blueswir1 | |
1441 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss600mp_machine = {
|
1442 | 66de733b | blueswir1 | .name = "SS-600MP",
|
1443 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCserver 600MP",
|
1444 | 66de733b | blueswir1 | .init = ss600mp_init, |
1445 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1446 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1447 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1448 | 6a3b9cc9 | blueswir1 | }; |
1449 | ae40972f | blueswir1 | |
1450 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss20_machine = {
|
1451 | 66de733b | blueswir1 | .name = "SS-20",
|
1452 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 20",
|
1453 | 66de733b | blueswir1 | .init = ss20_init, |
1454 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1455 | 1bcee014 | blueswir1 | .max_cpus = 4,
|
1456 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1457 | ae40972f | blueswir1 | }; |
1458 | ae40972f | blueswir1 | |
1459 | f80f9ec9 | Anthony Liguori | static QEMUMachine voyager_machine = {
|
1460 | 66de733b | blueswir1 | .name = "Voyager",
|
1461 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation Voyager",
|
1462 | 66de733b | blueswir1 | .init = vger_init, |
1463 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1464 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1465 | a526a31c | blueswir1 | }; |
1466 | a526a31c | blueswir1 | |
1467 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss_lx_machine = {
|
1468 | 66de733b | blueswir1 | .name = "LX",
|
1469 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation LX",
|
1470 | 66de733b | blueswir1 | .init = ss_lx_init, |
1471 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1472 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1473 | a526a31c | blueswir1 | }; |
1474 | a526a31c | blueswir1 | |
1475 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss4_machine = {
|
1476 | 66de733b | blueswir1 | .name = "SS-4",
|
1477 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCstation 4",
|
1478 | 66de733b | blueswir1 | .init = ss4_init, |
1479 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1480 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1481 | a526a31c | blueswir1 | }; |
1482 | a526a31c | blueswir1 | |
1483 | f80f9ec9 | Anthony Liguori | static QEMUMachine scls_machine = {
|
1484 | 66de733b | blueswir1 | .name = "SPARCClassic",
|
1485 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCClassic",
|
1486 | 66de733b | blueswir1 | .init = scls_init, |
1487 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1488 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1489 | a526a31c | blueswir1 | }; |
1490 | a526a31c | blueswir1 | |
1491 | f80f9ec9 | Anthony Liguori | static QEMUMachine sbook_machine = {
|
1492 | 66de733b | blueswir1 | .name = "SPARCbook",
|
1493 | 66de733b | blueswir1 | .desc = "Sun4m platform, SPARCbook",
|
1494 | 66de733b | blueswir1 | .init = sbook_init, |
1495 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1496 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1497 | a526a31c | blueswir1 | }; |
1498 | a526a31c | blueswir1 | |
1499 | 7d85892b | blueswir1 | static const struct sun4d_hwdef sun4d_hwdefs[] = { |
1500 | 7d85892b | blueswir1 | /* SS-1000 */
|
1501 | 7d85892b | blueswir1 | { |
1502 | 7d85892b | blueswir1 | .iounit_bases = { |
1503 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1504 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1505 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1506 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1507 | 7d85892b | blueswir1 | -1,
|
1508 | 7d85892b | blueswir1 | }, |
1509 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1510 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1511 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1512 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1513 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1514 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1515 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1516 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1517 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1518 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1519 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1520 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1521 | 905fdcb5 | blueswir1 | .machine_id = ss1000_id, |
1522 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1523 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1524 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1525 | 7d85892b | blueswir1 | }, |
1526 | 7d85892b | blueswir1 | /* SS-2000 */
|
1527 | 7d85892b | blueswir1 | { |
1528 | 7d85892b | blueswir1 | .iounit_bases = { |
1529 | 7d85892b | blueswir1 | 0xfe0200000ULL,
|
1530 | 7d85892b | blueswir1 | 0xfe1200000ULL,
|
1531 | 7d85892b | blueswir1 | 0xfe2200000ULL,
|
1532 | 7d85892b | blueswir1 | 0xfe3200000ULL,
|
1533 | 7d85892b | blueswir1 | 0xfe4200000ULL,
|
1534 | 7d85892b | blueswir1 | }, |
1535 | 7d85892b | blueswir1 | .tcx_base = 0x820000000ULL,
|
1536 | 7d85892b | blueswir1 | .slavio_base = 0xf00000000ULL,
|
1537 | 7d85892b | blueswir1 | .ms_kb_base = 0xf00240000ULL,
|
1538 | 7d85892b | blueswir1 | .serial_base = 0xf00200000ULL,
|
1539 | 7d85892b | blueswir1 | .nvram_base = 0xf00280000ULL,
|
1540 | 7d85892b | blueswir1 | .counter_base = 0xf00300000ULL,
|
1541 | 7d85892b | blueswir1 | .espdma_base = 0x800081000ULL,
|
1542 | 7d85892b | blueswir1 | .esp_base = 0x800080000ULL,
|
1543 | 7d85892b | blueswir1 | .ledma_base = 0x800040000ULL,
|
1544 | 7d85892b | blueswir1 | .le_base = 0x800060000ULL,
|
1545 | 7d85892b | blueswir1 | .sbi_base = 0xf02800000ULL,
|
1546 | 905fdcb5 | blueswir1 | .nvram_machine_id = 0x80,
|
1547 | 905fdcb5 | blueswir1 | .machine_id = ss2000_id, |
1548 | 7d85892b | blueswir1 | .iounit_version = 0x03000000,
|
1549 | 6ef05b95 | blueswir1 | .max_mem = 0xf00000000ULL,
|
1550 | 7d85892b | blueswir1 | .default_cpu_model = "TI SuperSparc II",
|
1551 | 7d85892b | blueswir1 | }, |
1552 | 7d85892b | blueswir1 | }; |
1553 | 7d85892b | blueswir1 | |
1554 | a8170e5e | Avi Kivity | static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
|
1555 | 4b48bf05 | Blue Swirl | { |
1556 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1557 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1558 | 4b48bf05 | Blue Swirl | unsigned int i; |
1559 | 4b48bf05 | Blue Swirl | |
1560 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sbi"); |
1561 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1562 | 4b48bf05 | Blue Swirl | |
1563 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
1564 | 4b48bf05 | Blue Swirl | |
1565 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1566 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, *parent_irq[i]); |
1567 | 4b48bf05 | Blue Swirl | } |
1568 | 4b48bf05 | Blue Swirl | |
1569 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1570 | 4b48bf05 | Blue Swirl | |
1571 | 4b48bf05 | Blue Swirl | return dev;
|
1572 | 4b48bf05 | Blue Swirl | } |
1573 | 4b48bf05 | Blue Swirl | |
1574 | c227f099 | Anthony Liguori | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size, |
1575 | 7d85892b | blueswir1 | const char *boot_device, |
1576 | 3023f332 | aliguori | const char *kernel_filename, |
1577 | 7d85892b | blueswir1 | const char *kernel_cmdline, |
1578 | 7d85892b | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1579 | 7d85892b | blueswir1 | { |
1580 | 7d85892b | blueswir1 | unsigned int i; |
1581 | 7fc06735 | Blue Swirl | void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
|
1582 | 7fc06735 | Blue Swirl | qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
|
1583 | 6f6260c7 | Blue Swirl | espdma_irq, ledma_irq; |
1584 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
1585 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1586 | 3cce6243 | blueswir1 | void *fw_cfg;
|
1587 | 7fc06735 | Blue Swirl | DeviceState *dev; |
1588 | 7d85892b | blueswir1 | |
1589 | 7d85892b | blueswir1 | /* init CPUs */
|
1590 | 7d85892b | blueswir1 | if (!cpu_model)
|
1591 | 7d85892b | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1592 | 7d85892b | blueswir1 | |
1593 | 666713c0 | Blue Swirl | for(i = 0; i < smp_cpus; i++) { |
1594 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]); |
1595 | 7d85892b | blueswir1 | } |
1596 | 7d85892b | blueswir1 | |
1597 | 7d85892b | blueswir1 | for (i = smp_cpus; i < MAX_CPUS; i++)
|
1598 | 7d85892b | blueswir1 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
|
1599 | 7d85892b | blueswir1 | |
1600 | 7d85892b | blueswir1 | /* set up devices */
|
1601 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1602 | a350db85 | Blue Swirl | |
1603 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1604 | f48f6569 | Blue Swirl | |
1605 | 7fc06735 | Blue Swirl | dev = sbi_init(hwdef->sbi_base, cpu_irqs); |
1606 | 7fc06735 | Blue Swirl | |
1607 | 7fc06735 | Blue Swirl | for (i = 0; i < 32; i++) { |
1608 | 7fc06735 | Blue Swirl | sbi_irq[i] = qdev_get_gpio_in(dev, i); |
1609 | 7fc06735 | Blue Swirl | } |
1610 | 7fc06735 | Blue Swirl | for (i = 0; i < MAX_CPUS; i++) { |
1611 | 7fc06735 | Blue Swirl | sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
|
1612 | 7fc06735 | Blue Swirl | } |
1613 | 7d85892b | blueswir1 | |
1614 | 7d85892b | blueswir1 | for (i = 0; i < MAX_IOUNITS; i++) |
1615 | a8170e5e | Avi Kivity | if (hwdef->iounit_bases[i] != (hwaddr)-1) |
1616 | ff403da6 | blueswir1 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1617 | ff403da6 | blueswir1 | hwdef->iounit_version, |
1618 | c533e0b3 | Blue Swirl | sbi_irq[0]);
|
1619 | 7d85892b | blueswir1 | |
1620 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
|
1621 | 86d1c388 | Bob Breuer | iounits[0], &espdma_irq, 0); |
1622 | 7d85892b | blueswir1 | |
1623 | 86d1c388 | Bob Breuer | /* should be lebuffer instead */
|
1624 | c533e0b3 | Blue Swirl | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
|
1625 | 86d1c388 | Bob Breuer | iounits[0], &ledma_irq, 0); |
1626 | 7d85892b | blueswir1 | |
1627 | 7d85892b | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1628 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1629 | 7d85892b | blueswir1 | exit (1);
|
1630 | 7d85892b | blueswir1 | } |
1631 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1632 | dc828ca1 | pbrook | graphic_depth); |
1633 | 7d85892b | blueswir1 | |
1634 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1635 | 7d85892b | blueswir1 | |
1636 | d95d8f1c | Blue Swirl | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8); |
1637 | 7d85892b | blueswir1 | |
1638 | c533e0b3 | Blue Swirl | slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
|
1639 | 7d85892b | blueswir1 | |
1640 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
|
1641 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1642 | 5cbdb3a3 | Stefan Weil | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
|
1643 | 5cbdb3a3 | Stefan Weil | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
|
1644 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12], |
1645 | aeeb69c7 | aurel32 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
1646 | 7d85892b | blueswir1 | |
1647 | 7d85892b | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1648 | 7d85892b | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1649 | 7d85892b | blueswir1 | exit(1);
|
1650 | 7d85892b | blueswir1 | } |
1651 | 7d85892b | blueswir1 | |
1652 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1653 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1654 | 73d74342 | Blue Swirl | espdma, espdma_irq, &esp_reset, &dma_enable); |
1655 | 73d74342 | Blue Swirl | |
1656 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 0, esp_reset);
|
1657 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 1, dma_enable);
|
1658 | 7d85892b | blueswir1 | |
1659 | 293f78bc | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1660 | 293f78bc | blueswir1 | RAM_size); |
1661 | 7d85892b | blueswir1 | |
1662 | 7d85892b | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1663 | 7d85892b | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1664 | 905fdcb5 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1665 | 905fdcb5 | blueswir1 | "Sun4d");
|
1666 | 3cce6243 | blueswir1 | |
1667 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1668 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1669 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1670 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1671 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1672 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1673 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1674 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1675 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1676 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1677 | 0e0d2d62 | Markus Armbruster | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
1678 | 513f789f | blueswir1 | } else {
|
1679 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1680 | 513f789f | blueswir1 | } |
1681 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1682 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1683 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1684 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1685 | 7d85892b | blueswir1 | } |
1686 | 7d85892b | blueswir1 | |
1687 | 7d85892b | blueswir1 | /* SPARCserver 1000 hardware initialisation */
|
1688 | 5f072e1f | Eduardo Habkost | static void ss1000_init(QEMUMachineInitArgs *args) |
1689 | 7d85892b | blueswir1 | { |
1690 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1691 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1692 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1693 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1694 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1695 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1696 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1697 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1698 | 7d85892b | blueswir1 | } |
1699 | 7d85892b | blueswir1 | |
1700 | 7d85892b | blueswir1 | /* SPARCcenter 2000 hardware initialisation */
|
1701 | 5f072e1f | Eduardo Habkost | static void ss2000_init(QEMUMachineInitArgs *args) |
1702 | 7d85892b | blueswir1 | { |
1703 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1704 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1705 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1706 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1707 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1708 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1709 | 3023f332 | aliguori | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
|
1710 | 7d85892b | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1711 | 7d85892b | blueswir1 | } |
1712 | 7d85892b | blueswir1 | |
1713 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss1000_machine = {
|
1714 | 66de733b | blueswir1 | .name = "SS-1000",
|
1715 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCserver 1000",
|
1716 | 66de733b | blueswir1 | .init = ss1000_init, |
1717 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1718 | 1bcee014 | blueswir1 | .max_cpus = 8,
|
1719 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1720 | 7d85892b | blueswir1 | }; |
1721 | 7d85892b | blueswir1 | |
1722 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2000_machine = {
|
1723 | 66de733b | blueswir1 | .name = "SS-2000",
|
1724 | 66de733b | blueswir1 | .desc = "Sun4d platform, SPARCcenter 2000",
|
1725 | 66de733b | blueswir1 | .init = ss2000_init, |
1726 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1727 | 1bcee014 | blueswir1 | .max_cpus = 20,
|
1728 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1729 | 7d85892b | blueswir1 | }; |
1730 | 8137cde8 | blueswir1 | |
1731 | 8137cde8 | blueswir1 | static const struct sun4c_hwdef sun4c_hwdefs[] = { |
1732 | 8137cde8 | blueswir1 | /* SS-2 */
|
1733 | 8137cde8 | blueswir1 | { |
1734 | 8137cde8 | blueswir1 | .iommu_base = 0xf8000000,
|
1735 | 8137cde8 | blueswir1 | .tcx_base = 0xfe000000,
|
1736 | 8137cde8 | blueswir1 | .slavio_base = 0xf6000000,
|
1737 | 8137cde8 | blueswir1 | .intctl_base = 0xf5000000,
|
1738 | 8137cde8 | blueswir1 | .counter_base = 0xf3000000,
|
1739 | 8137cde8 | blueswir1 | .ms_kb_base = 0xf0000000,
|
1740 | 8137cde8 | blueswir1 | .serial_base = 0xf1000000,
|
1741 | 8137cde8 | blueswir1 | .nvram_base = 0xf2000000,
|
1742 | 8137cde8 | blueswir1 | .fd_base = 0xf7200000,
|
1743 | 8137cde8 | blueswir1 | .dma_base = 0xf8400000,
|
1744 | 8137cde8 | blueswir1 | .esp_base = 0xf8800000,
|
1745 | 8137cde8 | blueswir1 | .le_base = 0xf8c00000,
|
1746 | 8137cde8 | blueswir1 | .aux1_base = 0xf7400003,
|
1747 | 8137cde8 | blueswir1 | .nvram_machine_id = 0x55,
|
1748 | 8137cde8 | blueswir1 | .machine_id = ss2_id, |
1749 | 8137cde8 | blueswir1 | .max_mem = 0x10000000,
|
1750 | 8137cde8 | blueswir1 | .default_cpu_model = "Cypress CY7C601",
|
1751 | 8137cde8 | blueswir1 | }, |
1752 | 8137cde8 | blueswir1 | }; |
1753 | 8137cde8 | blueswir1 | |
1754 | a8170e5e | Avi Kivity | static DeviceState *sun4c_intctl_init(hwaddr addr,
|
1755 | 4b48bf05 | Blue Swirl | qemu_irq *parent_irq) |
1756 | 4b48bf05 | Blue Swirl | { |
1757 | 4b48bf05 | Blue Swirl | DeviceState *dev; |
1758 | 4b48bf05 | Blue Swirl | SysBusDevice *s; |
1759 | 4b48bf05 | Blue Swirl | unsigned int i; |
1760 | 4b48bf05 | Blue Swirl | |
1761 | 4b48bf05 | Blue Swirl | dev = qdev_create(NULL, "sun4c_intctl"); |
1762 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
1763 | 4b48bf05 | Blue Swirl | |
1764 | 1356b98d | Andreas Färber | s = SYS_BUS_DEVICE(dev); |
1765 | 4b48bf05 | Blue Swirl | |
1766 | 4b48bf05 | Blue Swirl | for (i = 0; i < MAX_PILS; i++) { |
1767 | 4b48bf05 | Blue Swirl | sysbus_connect_irq(s, i, parent_irq[i]); |
1768 | 4b48bf05 | Blue Swirl | } |
1769 | 4b48bf05 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
1770 | 4b48bf05 | Blue Swirl | |
1771 | 4b48bf05 | Blue Swirl | return dev;
|
1772 | 4b48bf05 | Blue Swirl | } |
1773 | 4b48bf05 | Blue Swirl | |
1774 | c227f099 | Anthony Liguori | static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size, |
1775 | 8137cde8 | blueswir1 | const char *boot_device, |
1776 | 3023f332 | aliguori | const char *kernel_filename, |
1777 | 8137cde8 | blueswir1 | const char *kernel_cmdline, |
1778 | 8137cde8 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
1779 | 8137cde8 | blueswir1 | { |
1780 | cfb9de9c | Paul Brook | void *iommu, *espdma, *ledma, *nvram;
|
1781 | e32cba29 | Blue Swirl | qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
|
1782 | 73d74342 | Blue Swirl | qemu_irq esp_reset, dma_enable; |
1783 | 2582cfa0 | Blue Swirl | qemu_irq fdc_tc; |
1784 | 5c6602c5 | blueswir1 | unsigned long kernel_size; |
1785 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
1786 | 8137cde8 | blueswir1 | void *fw_cfg;
|
1787 | e32cba29 | Blue Swirl | DeviceState *dev; |
1788 | e32cba29 | Blue Swirl | unsigned int i; |
1789 | 8137cde8 | blueswir1 | |
1790 | 8137cde8 | blueswir1 | /* init CPU */
|
1791 | 8137cde8 | blueswir1 | if (!cpu_model)
|
1792 | 8137cde8 | blueswir1 | cpu_model = hwdef->default_cpu_model; |
1793 | 8137cde8 | blueswir1 | |
1794 | 89835363 | Blue Swirl | cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
|
1795 | 8137cde8 | blueswir1 | |
1796 | 8137cde8 | blueswir1 | /* set up devices */
|
1797 | a350db85 | Blue Swirl | ram_init(0, RAM_size, hwdef->max_mem);
|
1798 | a350db85 | Blue Swirl | |
1799 | f48f6569 | Blue Swirl | prom_init(hwdef->slavio_base, bios_name); |
1800 | f48f6569 | Blue Swirl | |
1801 | e32cba29 | Blue Swirl | dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs); |
1802 | e32cba29 | Blue Swirl | |
1803 | e32cba29 | Blue Swirl | for (i = 0; i < 8; i++) { |
1804 | e32cba29 | Blue Swirl | slavio_irq[i] = qdev_get_gpio_in(dev, i); |
1805 | e32cba29 | Blue Swirl | } |
1806 | 8137cde8 | blueswir1 | |
1807 | 8137cde8 | blueswir1 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
1808 | c533e0b3 | Blue Swirl | slavio_irq[1]);
|
1809 | 8137cde8 | blueswir1 | |
1810 | c533e0b3 | Blue Swirl | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
|
1811 | 86d1c388 | Bob Breuer | iommu, &espdma_irq, 0);
|
1812 | 8137cde8 | blueswir1 | |
1813 | 8137cde8 | blueswir1 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
|
1814 | 86d1c388 | Bob Breuer | slavio_irq[3], iommu, &ledma_irq, 1); |
1815 | 8137cde8 | blueswir1 | |
1816 | 8137cde8 | blueswir1 | if (graphic_depth != 8 && graphic_depth != 24) { |
1817 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
|
1818 | 8137cde8 | blueswir1 | exit (1);
|
1819 | 8137cde8 | blueswir1 | } |
1820 | d95d8f1c | Blue Swirl | tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
|
1821 | dc828ca1 | pbrook | graphic_depth); |
1822 | 8137cde8 | blueswir1 | |
1823 | 74ff8d90 | Blue Swirl | lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
|
1824 | 8137cde8 | blueswir1 | |
1825 | d95d8f1c | Blue Swirl | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2); |
1826 | 8137cde8 | blueswir1 | |
1827 | c533e0b3 | Blue Swirl | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
|
1828 | 993fbfdb | Anthony Liguori | display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
|
1829 | 5cbdb3a3 | Stefan Weil | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
|
1830 | 5cbdb3a3 | Stefan Weil | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
|
1831 | c533e0b3 | Blue Swirl | escc_init(hwdef->serial_base, slavio_irq[1],
|
1832 | c533e0b3 | Blue Swirl | slavio_irq[1], serial_hds[0], serial_hds[1], |
1833 | aeeb69c7 | aurel32 | ESCC_CLOCK, 1);
|
1834 | 8137cde8 | blueswir1 | |
1835 | a8170e5e | Avi Kivity | if (hwdef->fd_base != (hwaddr)-1) { |
1836 | 8137cde8 | blueswir1 | /* there is zero or one floppy drive */
|
1837 | ce802585 | blueswir1 | memset(fd, 0, sizeof(fd)); |
1838 | fd8014e1 | Gerd Hoffmann | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
1839 | c533e0b3 | Blue Swirl | sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
|
1840 | 2582cfa0 | Blue Swirl | &fdc_tc); |
1841 | acfbe712 | Blue Swirl | } else {
|
1842 | acfbe712 | Blue Swirl | fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1); |
1843 | 8137cde8 | blueswir1 | } |
1844 | 8137cde8 | blueswir1 | |
1845 | acfbe712 | Blue Swirl | slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc); |
1846 | acfbe712 | Blue Swirl | |
1847 | 8137cde8 | blueswir1 | if (drive_get_max_bus(IF_SCSI) > 0) { |
1848 | 8137cde8 | blueswir1 | fprintf(stderr, "qemu: too many SCSI bus\n");
|
1849 | 8137cde8 | blueswir1 | exit(1);
|
1850 | 8137cde8 | blueswir1 | } |
1851 | 8137cde8 | blueswir1 | |
1852 | cfb9de9c | Paul Brook | esp_init(hwdef->esp_base, 2,
|
1853 | cfb9de9c | Paul Brook | espdma_memory_read, espdma_memory_write, |
1854 | 73d74342 | Blue Swirl | espdma, espdma_irq, &esp_reset, &dma_enable); |
1855 | 73d74342 | Blue Swirl | |
1856 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 0, esp_reset);
|
1857 | 73d74342 | Blue Swirl | qdev_connect_gpio_out(espdma, 1, dma_enable);
|
1858 | 8137cde8 | blueswir1 | |
1859 | 8137cde8 | blueswir1 | kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename, |
1860 | 8137cde8 | blueswir1 | RAM_size); |
1861 | 8137cde8 | blueswir1 | |
1862 | 8137cde8 | blueswir1 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
|
1863 | 8137cde8 | blueswir1 | boot_device, RAM_size, kernel_size, graphic_width, |
1864 | 8137cde8 | blueswir1 | graphic_height, graphic_depth, hwdef->nvram_machine_id, |
1865 | 8137cde8 | blueswir1 | "Sun4c");
|
1866 | 8137cde8 | blueswir1 | |
1867 | 8137cde8 | blueswir1 | fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); |
1868 | 8137cde8 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
1869 | 8137cde8 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1870 | 8137cde8 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
1871 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
1872 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1873 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
1874 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
1875 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
1876 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
|
1877 | 0e0d2d62 | Markus Armbruster | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline); |
1878 | 513f789f | blueswir1 | } else {
|
1879 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
1880 | 513f789f | blueswir1 | } |
1881 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
1882 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used |
1883 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
|
1884 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
1885 | 8137cde8 | blueswir1 | } |
1886 | 8137cde8 | blueswir1 | |
1887 | 8137cde8 | blueswir1 | /* SPARCstation 2 hardware initialisation */
|
1888 | 5f072e1f | Eduardo Habkost | static void ss2_init(QEMUMachineInitArgs *args) |
1889 | 8137cde8 | blueswir1 | { |
1890 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
1891 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
1892 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
1893 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
1894 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
1895 | 5f072e1f | Eduardo Habkost | const char *boot_device = args->boot_device; |
1896 | 3023f332 | aliguori | sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
|
1897 | 8137cde8 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model); |
1898 | 8137cde8 | blueswir1 | } |
1899 | 8137cde8 | blueswir1 | |
1900 | f80f9ec9 | Anthony Liguori | static QEMUMachine ss2_machine = {
|
1901 | 8137cde8 | blueswir1 | .name = "SS-2",
|
1902 | 8137cde8 | blueswir1 | .desc = "Sun4c platform, SPARCstation 2",
|
1903 | 8137cde8 | blueswir1 | .init = ss2_init, |
1904 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
1905 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
1906 | 8137cde8 | blueswir1 | }; |
1907 | f80f9ec9 | Anthony Liguori | |
1908 | 83f7d43a | Andreas Färber | static void sun4m_register_types(void) |
1909 | 83f7d43a | Andreas Färber | { |
1910 | 83f7d43a | Andreas Färber | type_register_static(&idreg_info); |
1911 | 83f7d43a | Andreas Färber | type_register_static(&afx_info); |
1912 | 83f7d43a | Andreas Färber | type_register_static(&prom_info); |
1913 | 83f7d43a | Andreas Färber | type_register_static(&ram_info); |
1914 | 83f7d43a | Andreas Färber | } |
1915 | 83f7d43a | Andreas Färber | |
1916 | f80f9ec9 | Anthony Liguori | static void ss2_machine_init(void) |
1917 | f80f9ec9 | Anthony Liguori | { |
1918 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss5_machine); |
1919 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss10_machine); |
1920 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss600mp_machine); |
1921 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss20_machine); |
1922 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&voyager_machine); |
1923 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss_lx_machine); |
1924 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss4_machine); |
1925 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&scls_machine); |
1926 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sbook_machine); |
1927 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss1000_machine); |
1928 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2000_machine); |
1929 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&ss2_machine); |
1930 | f80f9ec9 | Anthony Liguori | } |
1931 | f80f9ec9 | Anthony Liguori | |
1932 | 83f7d43a | Andreas Färber | type_init(sun4m_register_types) |
1933 | f80f9ec9 | Anthony Liguori | machine_init(ss2_machine_init); |