root / hw / omap_mmc.c @ d8ed79ae
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1 | b30bb3a2 | balrog | /*
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2 | b30bb3a2 | balrog | * OMAP on-chip MMC/SD host emulation.
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3 | b30bb3a2 | balrog | *
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4 | b30bb3a2 | balrog | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | b30bb3a2 | balrog | *
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6 | b30bb3a2 | balrog | * This program is free software; you can redistribute it and/or
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7 | b30bb3a2 | balrog | * modify it under the terms of the GNU General Public License as
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8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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10 | b30bb3a2 | balrog | *
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11 | b30bb3a2 | balrog | * This program is distributed in the hope that it will be useful,
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12 | b30bb3a2 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b30bb3a2 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | b30bb3a2 | balrog | * GNU General Public License for more details.
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15 | b30bb3a2 | balrog | *
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16 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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17 | 8167ee88 | Blue Swirl | * with this program; if not, see <http://www.gnu.org/licenses/>.
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18 | b30bb3a2 | balrog | */
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19 | 87ecb68b | pbrook | #include "hw.h" |
20 | 87ecb68b | pbrook | #include "omap.h" |
21 | b30bb3a2 | balrog | #include "sd.h" |
22 | b30bb3a2 | balrog | |
23 | b30bb3a2 | balrog | struct omap_mmc_s {
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24 | b30bb3a2 | balrog | qemu_irq irq; |
25 | b30bb3a2 | balrog | qemu_irq *dma; |
26 | 827df9f3 | balrog | qemu_irq coverswitch; |
27 | b30bb3a2 | balrog | omap_clk clk; |
28 | b30bb3a2 | balrog | SDState *card; |
29 | b30bb3a2 | balrog | uint16_t last_cmd; |
30 | b30bb3a2 | balrog | uint16_t sdio; |
31 | b30bb3a2 | balrog | uint16_t rsp[8];
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32 | b30bb3a2 | balrog | uint32_t arg; |
33 | 827df9f3 | balrog | int lines;
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34 | b30bb3a2 | balrog | int dw;
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35 | b30bb3a2 | balrog | int mode;
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36 | b30bb3a2 | balrog | int enable;
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37 | 827df9f3 | balrog | int be;
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38 | 827df9f3 | balrog | int rev;
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39 | b30bb3a2 | balrog | uint16_t status; |
40 | b30bb3a2 | balrog | uint16_t mask; |
41 | b30bb3a2 | balrog | uint8_t cto; |
42 | b30bb3a2 | balrog | uint16_t dto; |
43 | 827df9f3 | balrog | int clkdiv;
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44 | b30bb3a2 | balrog | uint16_t fifo[32];
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45 | b30bb3a2 | balrog | int fifo_start;
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46 | b30bb3a2 | balrog | int fifo_len;
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47 | b30bb3a2 | balrog | uint16_t blen; |
48 | b30bb3a2 | balrog | uint16_t blen_counter; |
49 | b30bb3a2 | balrog | uint16_t nblk; |
50 | b30bb3a2 | balrog | uint16_t nblk_counter; |
51 | b30bb3a2 | balrog | int tx_dma;
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52 | b30bb3a2 | balrog | int rx_dma;
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53 | b30bb3a2 | balrog | int af_level;
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54 | b30bb3a2 | balrog | int ae_level;
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55 | b30bb3a2 | balrog | |
56 | b30bb3a2 | balrog | int ddir;
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57 | b30bb3a2 | balrog | int transfer;
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58 | 827df9f3 | balrog | |
59 | 827df9f3 | balrog | int cdet_wakeup;
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60 | 827df9f3 | balrog | int cdet_enable;
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61 | 827df9f3 | balrog | int cdet_state;
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62 | 827df9f3 | balrog | qemu_irq cdet; |
63 | b30bb3a2 | balrog | }; |
64 | b30bb3a2 | balrog | |
65 | b30bb3a2 | balrog | static void omap_mmc_interrupts_update(struct omap_mmc_s *s) |
66 | b30bb3a2 | balrog | { |
67 | b30bb3a2 | balrog | qemu_set_irq(s->irq, !!(s->status & s->mask)); |
68 | b30bb3a2 | balrog | } |
69 | b30bb3a2 | balrog | |
70 | b30bb3a2 | balrog | static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) |
71 | b30bb3a2 | balrog | { |
72 | b30bb3a2 | balrog | if (!host->transfer && !host->fifo_len) {
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73 | b30bb3a2 | balrog | host->status &= 0xf3ff;
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74 | b30bb3a2 | balrog | return;
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75 | b30bb3a2 | balrog | } |
76 | b30bb3a2 | balrog | |
77 | b30bb3a2 | balrog | if (host->fifo_len > host->af_level && host->ddir) {
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78 | b30bb3a2 | balrog | if (host->rx_dma) {
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79 | b30bb3a2 | balrog | host->status &= 0xfbff;
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80 | b30bb3a2 | balrog | qemu_irq_raise(host->dma[1]);
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81 | b30bb3a2 | balrog | } else
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82 | b30bb3a2 | balrog | host->status |= 0x0400;
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83 | b30bb3a2 | balrog | } else {
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84 | b30bb3a2 | balrog | host->status &= 0xfbff;
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85 | b30bb3a2 | balrog | qemu_irq_lower(host->dma[1]);
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86 | b30bb3a2 | balrog | } |
87 | b30bb3a2 | balrog | |
88 | b30bb3a2 | balrog | if (host->fifo_len < host->ae_level && !host->ddir) {
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89 | b30bb3a2 | balrog | if (host->tx_dma) {
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90 | b30bb3a2 | balrog | host->status &= 0xf7ff;
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91 | b30bb3a2 | balrog | qemu_irq_raise(host->dma[0]);
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92 | b30bb3a2 | balrog | } else
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93 | b30bb3a2 | balrog | host->status |= 0x0800;
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94 | b30bb3a2 | balrog | } else {
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95 | b30bb3a2 | balrog | qemu_irq_lower(host->dma[0]);
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96 | b30bb3a2 | balrog | host->status &= 0xf7ff;
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97 | b30bb3a2 | balrog | } |
98 | b30bb3a2 | balrog | } |
99 | b30bb3a2 | balrog | |
100 | b30bb3a2 | balrog | typedef enum { |
101 | b30bb3a2 | balrog | sd_nore = 0, /* no response */ |
102 | b30bb3a2 | balrog | sd_r1, /* normal response command */
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103 | b30bb3a2 | balrog | sd_r2, /* CID, CSD registers */
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104 | b30bb3a2 | balrog | sd_r3, /* OCR register */
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105 | b30bb3a2 | balrog | sd_r6 = 6, /* Published RCA response */ |
106 | b30bb3a2 | balrog | sd_r1b = -1,
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107 | c227f099 | Anthony Liguori | } sd_rsp_type_t; |
108 | b30bb3a2 | balrog | |
109 | b30bb3a2 | balrog | static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, |
110 | c227f099 | Anthony Liguori | sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) |
111 | b30bb3a2 | balrog | { |
112 | b30bb3a2 | balrog | uint32_t rspstatus, mask; |
113 | b30bb3a2 | balrog | int rsplen, timeout;
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114 | bc24a225 | Paul Brook | SDRequest request; |
115 | b30bb3a2 | balrog | uint8_t response[16];
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116 | b30bb3a2 | balrog | |
117 | 827df9f3 | balrog | if (init && cmd == 0) { |
118 | 827df9f3 | balrog | host->status |= 0x0001;
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119 | 827df9f3 | balrog | return;
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120 | 827df9f3 | balrog | } |
121 | 827df9f3 | balrog | |
122 | b30bb3a2 | balrog | if (resptype == sd_r1 && busy)
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123 | b30bb3a2 | balrog | resptype = sd_r1b; |
124 | b30bb3a2 | balrog | |
125 | b30bb3a2 | balrog | if (type == sd_adtc) {
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126 | b30bb3a2 | balrog | host->fifo_start = 0;
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127 | b30bb3a2 | balrog | host->fifo_len = 0;
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128 | b30bb3a2 | balrog | host->transfer = 1;
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129 | b30bb3a2 | balrog | host->ddir = dir; |
130 | b30bb3a2 | balrog | } else
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131 | b30bb3a2 | balrog | host->transfer = 0;
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132 | b30bb3a2 | balrog | timeout = 0;
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133 | b30bb3a2 | balrog | mask = 0;
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134 | b30bb3a2 | balrog | rspstatus = 0;
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135 | b30bb3a2 | balrog | |
136 | b30bb3a2 | balrog | request.cmd = cmd; |
137 | b30bb3a2 | balrog | request.arg = host->arg; |
138 | b30bb3a2 | balrog | request.crc = 0; /* FIXME */ |
139 | b30bb3a2 | balrog | |
140 | b30bb3a2 | balrog | rsplen = sd_do_command(host->card, &request, response); |
141 | b30bb3a2 | balrog | |
142 | b30bb3a2 | balrog | /* TODO: validate CRCs */
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143 | b30bb3a2 | balrog | switch (resptype) {
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144 | b30bb3a2 | balrog | case sd_nore:
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145 | b30bb3a2 | balrog | rsplen = 0;
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146 | b30bb3a2 | balrog | break;
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147 | b30bb3a2 | balrog | |
148 | b30bb3a2 | balrog | case sd_r1:
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149 | b30bb3a2 | balrog | case sd_r1b:
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150 | b30bb3a2 | balrog | if (rsplen < 4) { |
151 | b30bb3a2 | balrog | timeout = 1;
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152 | b30bb3a2 | balrog | break;
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153 | b30bb3a2 | balrog | } |
154 | b30bb3a2 | balrog | rsplen = 4;
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155 | b30bb3a2 | balrog | |
156 | b30bb3a2 | balrog | mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | |
157 | b30bb3a2 | balrog | ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | |
158 | b30bb3a2 | balrog | LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | |
159 | b30bb3a2 | balrog | CARD_ECC_FAILED | CC_ERROR | SD_ERROR | |
160 | b30bb3a2 | balrog | CID_CSD_OVERWRITE; |
161 | b30bb3a2 | balrog | if (host->sdio & (1 << 13)) |
162 | b30bb3a2 | balrog | mask |= AKE_SEQ_ERROR; |
163 | b30bb3a2 | balrog | rspstatus = (response[0] << 24) | (response[1] << 16) | |
164 | b30bb3a2 | balrog | (response[2] << 8) | (response[3] << 0); |
165 | b30bb3a2 | balrog | break;
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166 | b30bb3a2 | balrog | |
167 | b30bb3a2 | balrog | case sd_r2:
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168 | b30bb3a2 | balrog | if (rsplen < 16) { |
169 | b30bb3a2 | balrog | timeout = 1;
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170 | b30bb3a2 | balrog | break;
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171 | b30bb3a2 | balrog | } |
172 | b30bb3a2 | balrog | rsplen = 16;
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173 | b30bb3a2 | balrog | break;
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174 | b30bb3a2 | balrog | |
175 | b30bb3a2 | balrog | case sd_r3:
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176 | b30bb3a2 | balrog | if (rsplen < 4) { |
177 | b30bb3a2 | balrog | timeout = 1;
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178 | b30bb3a2 | balrog | break;
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179 | b30bb3a2 | balrog | } |
180 | b30bb3a2 | balrog | rsplen = 4;
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181 | b30bb3a2 | balrog | |
182 | b30bb3a2 | balrog | rspstatus = (response[0] << 24) | (response[1] << 16) | |
183 | b30bb3a2 | balrog | (response[2] << 8) | (response[3] << 0); |
184 | b30bb3a2 | balrog | if (rspstatus & 0x80000000) |
185 | b30bb3a2 | balrog | host->status &= 0xe000;
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186 | b30bb3a2 | balrog | else
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187 | b30bb3a2 | balrog | host->status |= 0x1000;
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188 | b30bb3a2 | balrog | break;
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189 | b30bb3a2 | balrog | |
190 | b30bb3a2 | balrog | case sd_r6:
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191 | b30bb3a2 | balrog | if (rsplen < 4) { |
192 | b30bb3a2 | balrog | timeout = 1;
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193 | b30bb3a2 | balrog | break;
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194 | b30bb3a2 | balrog | } |
195 | b30bb3a2 | balrog | rsplen = 4;
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196 | b30bb3a2 | balrog | |
197 | b30bb3a2 | balrog | mask = 0xe000 | AKE_SEQ_ERROR;
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198 | b30bb3a2 | balrog | rspstatus = (response[2] << 8) | (response[3] << 0); |
199 | b30bb3a2 | balrog | } |
200 | b30bb3a2 | balrog | |
201 | b30bb3a2 | balrog | if (rspstatus & mask)
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202 | b30bb3a2 | balrog | host->status |= 0x4000;
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203 | b30bb3a2 | balrog | else
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204 | b30bb3a2 | balrog | host->status &= 0xb000;
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205 | b30bb3a2 | balrog | |
206 | b30bb3a2 | balrog | if (rsplen)
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207 | b30bb3a2 | balrog | for (rsplen = 0; rsplen < 8; rsplen ++) |
208 | b30bb3a2 | balrog | host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | |
209 | b30bb3a2 | balrog | (response[(rsplen << 1) | 0] << 8); |
210 | b30bb3a2 | balrog | |
211 | b30bb3a2 | balrog | if (timeout)
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212 | b30bb3a2 | balrog | host->status |= 0x0080;
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213 | b30bb3a2 | balrog | else if (cmd == 12) |
214 | b30bb3a2 | balrog | host->status |= 0x0005; /* Makes it more real */ |
215 | b30bb3a2 | balrog | else
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216 | b30bb3a2 | balrog | host->status |= 0x0001;
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217 | b30bb3a2 | balrog | } |
218 | b30bb3a2 | balrog | |
219 | b30bb3a2 | balrog | static void omap_mmc_transfer(struct omap_mmc_s *host) |
220 | b30bb3a2 | balrog | { |
221 | b30bb3a2 | balrog | uint8_t value; |
222 | b30bb3a2 | balrog | |
223 | b30bb3a2 | balrog | if (!host->transfer)
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224 | b30bb3a2 | balrog | return;
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225 | b30bb3a2 | balrog | |
226 | b30bb3a2 | balrog | while (1) { |
227 | b30bb3a2 | balrog | if (host->ddir) {
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228 | b30bb3a2 | balrog | if (host->fifo_len > host->af_level)
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229 | b30bb3a2 | balrog | break;
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230 | b30bb3a2 | balrog | |
231 | b30bb3a2 | balrog | value = sd_read_data(host->card); |
232 | b30bb3a2 | balrog | host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
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233 | b30bb3a2 | balrog | if (-- host->blen_counter) {
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234 | b30bb3a2 | balrog | value = sd_read_data(host->card); |
235 | b30bb3a2 | balrog | host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
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236 | b30bb3a2 | balrog | value << 8;
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237 | b30bb3a2 | balrog | host->blen_counter --; |
238 | b30bb3a2 | balrog | } |
239 | b30bb3a2 | balrog | |
240 | b30bb3a2 | balrog | host->fifo_len ++; |
241 | b30bb3a2 | balrog | } else {
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242 | b30bb3a2 | balrog | if (!host->fifo_len)
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243 | b30bb3a2 | balrog | break;
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244 | b30bb3a2 | balrog | |
245 | b30bb3a2 | balrog | value = host->fifo[host->fifo_start] & 0xff;
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246 | b30bb3a2 | balrog | sd_write_data(host->card, value); |
247 | b30bb3a2 | balrog | if (-- host->blen_counter) {
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248 | b30bb3a2 | balrog | value = host->fifo[host->fifo_start] >> 8;
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249 | b30bb3a2 | balrog | sd_write_data(host->card, value); |
250 | b30bb3a2 | balrog | host->blen_counter --; |
251 | b30bb3a2 | balrog | } |
252 | b30bb3a2 | balrog | |
253 | b30bb3a2 | balrog | host->fifo_start ++; |
254 | b30bb3a2 | balrog | host->fifo_len --; |
255 | b30bb3a2 | balrog | host->fifo_start &= 31;
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256 | b30bb3a2 | balrog | } |
257 | b30bb3a2 | balrog | |
258 | b30bb3a2 | balrog | if (host->blen_counter == 0) { |
259 | b30bb3a2 | balrog | host->nblk_counter --; |
260 | b30bb3a2 | balrog | host->blen_counter = host->blen; |
261 | b30bb3a2 | balrog | |
262 | b30bb3a2 | balrog | if (host->nblk_counter == 0) { |
263 | b30bb3a2 | balrog | host->nblk_counter = host->nblk; |
264 | b30bb3a2 | balrog | host->transfer = 0;
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265 | b30bb3a2 | balrog | host->status |= 0x0008;
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266 | b30bb3a2 | balrog | break;
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267 | b30bb3a2 | balrog | } |
268 | b30bb3a2 | balrog | } |
269 | b30bb3a2 | balrog | } |
270 | b30bb3a2 | balrog | } |
271 | b30bb3a2 | balrog | |
272 | b30bb3a2 | balrog | static void omap_mmc_update(void *opaque) |
273 | b30bb3a2 | balrog | { |
274 | b30bb3a2 | balrog | struct omap_mmc_s *s = opaque;
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275 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
276 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
277 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
278 | b30bb3a2 | balrog | } |
279 | b30bb3a2 | balrog | |
280 | 827df9f3 | balrog | void omap_mmc_reset(struct omap_mmc_s *host) |
281 | 827df9f3 | balrog | { |
282 | 827df9f3 | balrog | host->last_cmd = 0;
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283 | 827df9f3 | balrog | memset(host->rsp, 0, sizeof(host->rsp)); |
284 | 827df9f3 | balrog | host->arg = 0;
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285 | 827df9f3 | balrog | host->dw = 0;
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286 | 827df9f3 | balrog | host->mode = 0;
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287 | 827df9f3 | balrog | host->enable = 0;
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288 | 827df9f3 | balrog | host->status = 0;
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289 | 827df9f3 | balrog | host->mask = 0;
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290 | 827df9f3 | balrog | host->cto = 0;
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291 | 827df9f3 | balrog | host->dto = 0;
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292 | 827df9f3 | balrog | host->fifo_len = 0;
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293 | 827df9f3 | balrog | host->blen = 0;
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294 | 827df9f3 | balrog | host->blen_counter = 0;
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295 | 827df9f3 | balrog | host->nblk = 0;
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296 | 827df9f3 | balrog | host->nblk_counter = 0;
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297 | 827df9f3 | balrog | host->tx_dma = 0;
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298 | 827df9f3 | balrog | host->rx_dma = 0;
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299 | 827df9f3 | balrog | host->ae_level = 0x00;
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300 | 827df9f3 | balrog | host->af_level = 0x1f;
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301 | 827df9f3 | balrog | host->transfer = 0;
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302 | 827df9f3 | balrog | host->cdet_wakeup = 0;
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303 | 827df9f3 | balrog | host->cdet_enable = 0;
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304 | 827df9f3 | balrog | qemu_set_irq(host->coverswitch, host->cdet_state); |
305 | 827df9f3 | balrog | host->clkdiv = 0;
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306 | 827df9f3 | balrog | } |
307 | 827df9f3 | balrog | |
308 | c227f099 | Anthony Liguori | static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset) |
309 | b30bb3a2 | balrog | { |
310 | b30bb3a2 | balrog | uint16_t i; |
311 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
312 | cf965d24 | balrog | offset &= OMAP_MPUI_REG_MASK; |
313 | b30bb3a2 | balrog | |
314 | b30bb3a2 | balrog | switch (offset) {
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315 | b30bb3a2 | balrog | case 0x00: /* MMC_CMD */ |
316 | b30bb3a2 | balrog | return s->last_cmd;
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317 | b30bb3a2 | balrog | |
318 | b30bb3a2 | balrog | case 0x04: /* MMC_ARGL */ |
319 | b30bb3a2 | balrog | return s->arg & 0x0000ffff; |
320 | b30bb3a2 | balrog | |
321 | b30bb3a2 | balrog | case 0x08: /* MMC_ARGH */ |
322 | b30bb3a2 | balrog | return s->arg >> 16; |
323 | b30bb3a2 | balrog | |
324 | b30bb3a2 | balrog | case 0x0c: /* MMC_CON */ |
325 | 827df9f3 | balrog | return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | |
326 | 827df9f3 | balrog | (s->be << 10) | s->clkdiv;
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327 | b30bb3a2 | balrog | |
328 | b30bb3a2 | balrog | case 0x10: /* MMC_STAT */ |
329 | b30bb3a2 | balrog | return s->status;
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330 | b30bb3a2 | balrog | |
331 | b30bb3a2 | balrog | case 0x14: /* MMC_IE */ |
332 | b30bb3a2 | balrog | return s->mask;
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333 | b30bb3a2 | balrog | |
334 | b30bb3a2 | balrog | case 0x18: /* MMC_CTO */ |
335 | b30bb3a2 | balrog | return s->cto;
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336 | b30bb3a2 | balrog | |
337 | b30bb3a2 | balrog | case 0x1c: /* MMC_DTO */ |
338 | b30bb3a2 | balrog | return s->dto;
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339 | b30bb3a2 | balrog | |
340 | b30bb3a2 | balrog | case 0x20: /* MMC_DATA */ |
341 | b30bb3a2 | balrog | /* TODO: support 8-bit access */
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342 | b30bb3a2 | balrog | i = s->fifo[s->fifo_start]; |
343 | b30bb3a2 | balrog | if (s->fifo_len == 0) { |
344 | b30bb3a2 | balrog | printf("MMC: FIFO underrun\n");
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345 | b30bb3a2 | balrog | return i;
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346 | b30bb3a2 | balrog | } |
347 | b30bb3a2 | balrog | s->fifo_start ++; |
348 | b30bb3a2 | balrog | s->fifo_len --; |
349 | b30bb3a2 | balrog | s->fifo_start &= 31;
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350 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
351 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
352 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
353 | b30bb3a2 | balrog | return i;
|
354 | b30bb3a2 | balrog | |
355 | b30bb3a2 | balrog | case 0x24: /* MMC_BLEN */ |
356 | b30bb3a2 | balrog | return s->blen_counter;
|
357 | b30bb3a2 | balrog | |
358 | b30bb3a2 | balrog | case 0x28: /* MMC_NBLK */ |
359 | b30bb3a2 | balrog | return s->nblk_counter;
|
360 | b30bb3a2 | balrog | |
361 | b30bb3a2 | balrog | case 0x2c: /* MMC_BUF */ |
362 | b30bb3a2 | balrog | return (s->rx_dma << 15) | (s->af_level << 8) | |
363 | b30bb3a2 | balrog | (s->tx_dma << 7) | s->ae_level;
|
364 | b30bb3a2 | balrog | |
365 | b30bb3a2 | balrog | case 0x30: /* MMC_SPI */ |
366 | b30bb3a2 | balrog | return 0x0000; |
367 | b30bb3a2 | balrog | case 0x34: /* MMC_SDIO */ |
368 | 827df9f3 | balrog | return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; |
369 | b30bb3a2 | balrog | case 0x38: /* MMC_SYST */ |
370 | b30bb3a2 | balrog | return 0x0000; |
371 | b30bb3a2 | balrog | |
372 | b30bb3a2 | balrog | case 0x3c: /* MMC_REV */ |
373 | 827df9f3 | balrog | return s->rev;
|
374 | b30bb3a2 | balrog | |
375 | b30bb3a2 | balrog | case 0x40: /* MMC_RSP0 */ |
376 | b30bb3a2 | balrog | case 0x44: /* MMC_RSP1 */ |
377 | b30bb3a2 | balrog | case 0x48: /* MMC_RSP2 */ |
378 | b30bb3a2 | balrog | case 0x4c: /* MMC_RSP3 */ |
379 | b30bb3a2 | balrog | case 0x50: /* MMC_RSP4 */ |
380 | b30bb3a2 | balrog | case 0x54: /* MMC_RSP5 */ |
381 | b30bb3a2 | balrog | case 0x58: /* MMC_RSP6 */ |
382 | b30bb3a2 | balrog | case 0x5c: /* MMC_RSP7 */ |
383 | b30bb3a2 | balrog | return s->rsp[(offset - 0x40) >> 2]; |
384 | 827df9f3 | balrog | |
385 | 827df9f3 | balrog | /* OMAP2-specific */
|
386 | 827df9f3 | balrog | case 0x60: /* MMC_IOSR */ |
387 | 827df9f3 | balrog | case 0x64: /* MMC_SYSC */ |
388 | 827df9f3 | balrog | return 0; |
389 | 827df9f3 | balrog | case 0x68: /* MMC_SYSS */ |
390 | 827df9f3 | balrog | return 1; /* RSTD */ |
391 | b30bb3a2 | balrog | } |
392 | b30bb3a2 | balrog | |
393 | b30bb3a2 | balrog | OMAP_BAD_REG(offset); |
394 | b30bb3a2 | balrog | return 0; |
395 | b30bb3a2 | balrog | } |
396 | b30bb3a2 | balrog | |
397 | c227f099 | Anthony Liguori | static void omap_mmc_write(void *opaque, target_phys_addr_t offset, |
398 | b30bb3a2 | balrog | uint32_t value) |
399 | b30bb3a2 | balrog | { |
400 | b30bb3a2 | balrog | int i;
|
401 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
402 | cf965d24 | balrog | offset &= OMAP_MPUI_REG_MASK; |
403 | b30bb3a2 | balrog | |
404 | b30bb3a2 | balrog | switch (offset) {
|
405 | b30bb3a2 | balrog | case 0x00: /* MMC_CMD */ |
406 | b30bb3a2 | balrog | if (!s->enable)
|
407 | b30bb3a2 | balrog | break;
|
408 | b30bb3a2 | balrog | |
409 | b30bb3a2 | balrog | s->last_cmd = value; |
410 | b30bb3a2 | balrog | for (i = 0; i < 8; i ++) |
411 | b30bb3a2 | balrog | s->rsp[i] = 0x0000;
|
412 | b30bb3a2 | balrog | omap_mmc_command(s, value & 63, (value >> 15) & 1, |
413 | c227f099 | Anthony Liguori | (sd_cmd_type_t) ((value >> 12) & 3), |
414 | b30bb3a2 | balrog | (value >> 11) & 1, |
415 | c227f099 | Anthony Liguori | (sd_rsp_type_t) ((value >> 8) & 7), |
416 | b30bb3a2 | balrog | (value >> 7) & 1); |
417 | b30bb3a2 | balrog | omap_mmc_update(s); |
418 | b30bb3a2 | balrog | break;
|
419 | b30bb3a2 | balrog | |
420 | b30bb3a2 | balrog | case 0x04: /* MMC_ARGL */ |
421 | b30bb3a2 | balrog | s->arg &= 0xffff0000;
|
422 | b30bb3a2 | balrog | s->arg |= 0x0000ffff & value;
|
423 | b30bb3a2 | balrog | break;
|
424 | b30bb3a2 | balrog | |
425 | b30bb3a2 | balrog | case 0x08: /* MMC_ARGH */ |
426 | b30bb3a2 | balrog | s->arg &= 0x0000ffff;
|
427 | b30bb3a2 | balrog | s->arg |= value << 16;
|
428 | b30bb3a2 | balrog | break;
|
429 | b30bb3a2 | balrog | |
430 | b30bb3a2 | balrog | case 0x0c: /* MMC_CON */ |
431 | b30bb3a2 | balrog | s->dw = (value >> 15) & 1; |
432 | b30bb3a2 | balrog | s->mode = (value >> 12) & 3; |
433 | b30bb3a2 | balrog | s->enable = (value >> 11) & 1; |
434 | 827df9f3 | balrog | s->be = (value >> 10) & 1; |
435 | 827df9f3 | balrog | s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); |
436 | b30bb3a2 | balrog | if (s->mode != 0) |
437 | b30bb3a2 | balrog | printf("SD mode %i unimplemented!\n", s->mode);
|
438 | 827df9f3 | balrog | if (s->be != 0) |
439 | 827df9f3 | balrog | printf("SD FIFO byte sex unimplemented!\n");
|
440 | 827df9f3 | balrog | if (s->dw != 0 && s->lines < 4) |
441 | b30bb3a2 | balrog | printf("4-bit SD bus enabled\n");
|
442 | 827df9f3 | balrog | if (!s->enable)
|
443 | 827df9f3 | balrog | omap_mmc_reset(s); |
444 | b30bb3a2 | balrog | break;
|
445 | b30bb3a2 | balrog | |
446 | b30bb3a2 | balrog | case 0x10: /* MMC_STAT */ |
447 | b30bb3a2 | balrog | s->status &= ~value; |
448 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
449 | b30bb3a2 | balrog | break;
|
450 | b30bb3a2 | balrog | |
451 | b30bb3a2 | balrog | case 0x14: /* MMC_IE */ |
452 | 827df9f3 | balrog | s->mask = value & 0x7fff;
|
453 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
454 | b30bb3a2 | balrog | break;
|
455 | b30bb3a2 | balrog | |
456 | b30bb3a2 | balrog | case 0x18: /* MMC_CTO */ |
457 | b30bb3a2 | balrog | s->cto = value & 0xff;
|
458 | 827df9f3 | balrog | if (s->cto > 0xfd && s->rev <= 1) |
459 | b30bb3a2 | balrog | printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
|
460 | b30bb3a2 | balrog | break;
|
461 | b30bb3a2 | balrog | |
462 | b30bb3a2 | balrog | case 0x1c: /* MMC_DTO */ |
463 | b30bb3a2 | balrog | s->dto = value & 0xffff;
|
464 | b30bb3a2 | balrog | break;
|
465 | b30bb3a2 | balrog | |
466 | b30bb3a2 | balrog | case 0x20: /* MMC_DATA */ |
467 | b30bb3a2 | balrog | /* TODO: support 8-bit access */
|
468 | b30bb3a2 | balrog | if (s->fifo_len == 32) |
469 | b30bb3a2 | balrog | break;
|
470 | b30bb3a2 | balrog | s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
|
471 | b30bb3a2 | balrog | s->fifo_len ++; |
472 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
473 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
474 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
475 | b30bb3a2 | balrog | break;
|
476 | b30bb3a2 | balrog | |
477 | b30bb3a2 | balrog | case 0x24: /* MMC_BLEN */ |
478 | b30bb3a2 | balrog | s->blen = (value & 0x07ff) + 1; |
479 | b30bb3a2 | balrog | s->blen_counter = s->blen; |
480 | b30bb3a2 | balrog | break;
|
481 | b30bb3a2 | balrog | |
482 | b30bb3a2 | balrog | case 0x28: /* MMC_NBLK */ |
483 | b30bb3a2 | balrog | s->nblk = (value & 0x07ff) + 1; |
484 | b30bb3a2 | balrog | s->nblk_counter = s->nblk; |
485 | b30bb3a2 | balrog | s->blen_counter = s->blen; |
486 | b30bb3a2 | balrog | break;
|
487 | b30bb3a2 | balrog | |
488 | b30bb3a2 | balrog | case 0x2c: /* MMC_BUF */ |
489 | b30bb3a2 | balrog | s->rx_dma = (value >> 15) & 1; |
490 | b30bb3a2 | balrog | s->af_level = (value >> 8) & 0x1f; |
491 | b30bb3a2 | balrog | s->tx_dma = (value >> 7) & 1; |
492 | b30bb3a2 | balrog | s->ae_level = value & 0x1f;
|
493 | b30bb3a2 | balrog | |
494 | b30bb3a2 | balrog | if (s->rx_dma)
|
495 | b30bb3a2 | balrog | s->status &= 0xfbff;
|
496 | b30bb3a2 | balrog | if (s->tx_dma)
|
497 | b30bb3a2 | balrog | s->status &= 0xf7ff;
|
498 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
499 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
500 | b30bb3a2 | balrog | break;
|
501 | b30bb3a2 | balrog | |
502 | b30bb3a2 | balrog | /* SPI, SDIO and TEST modes unimplemented */
|
503 | 827df9f3 | balrog | case 0x30: /* MMC_SPI (OMAP1 only) */ |
504 | b30bb3a2 | balrog | break;
|
505 | b30bb3a2 | balrog | case 0x34: /* MMC_SDIO */ |
506 | 827df9f3 | balrog | s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); |
507 | 827df9f3 | balrog | s->cdet_wakeup = (value >> 9) & 1; |
508 | 827df9f3 | balrog | s->cdet_enable = (value >> 2) & 1; |
509 | b30bb3a2 | balrog | break;
|
510 | b30bb3a2 | balrog | case 0x38: /* MMC_SYST */ |
511 | b30bb3a2 | balrog | break;
|
512 | b30bb3a2 | balrog | |
513 | b30bb3a2 | balrog | case 0x3c: /* MMC_REV */ |
514 | b30bb3a2 | balrog | case 0x40: /* MMC_RSP0 */ |
515 | b30bb3a2 | balrog | case 0x44: /* MMC_RSP1 */ |
516 | b30bb3a2 | balrog | case 0x48: /* MMC_RSP2 */ |
517 | b30bb3a2 | balrog | case 0x4c: /* MMC_RSP3 */ |
518 | b30bb3a2 | balrog | case 0x50: /* MMC_RSP4 */ |
519 | b30bb3a2 | balrog | case 0x54: /* MMC_RSP5 */ |
520 | b30bb3a2 | balrog | case 0x58: /* MMC_RSP6 */ |
521 | b30bb3a2 | balrog | case 0x5c: /* MMC_RSP7 */ |
522 | b30bb3a2 | balrog | OMAP_RO_REG(offset); |
523 | b30bb3a2 | balrog | break;
|
524 | b30bb3a2 | balrog | |
525 | 827df9f3 | balrog | /* OMAP2-specific */
|
526 | 827df9f3 | balrog | case 0x60: /* MMC_IOSR */ |
527 | 827df9f3 | balrog | if (value & 0xf) |
528 | 827df9f3 | balrog | printf("MMC: SDIO bits used!\n");
|
529 | 827df9f3 | balrog | break;
|
530 | 827df9f3 | balrog | case 0x64: /* MMC_SYSC */ |
531 | 827df9f3 | balrog | if (value & (1 << 2)) /* SRTS */ |
532 | 827df9f3 | balrog | omap_mmc_reset(s); |
533 | 827df9f3 | balrog | break;
|
534 | 827df9f3 | balrog | case 0x68: /* MMC_SYSS */ |
535 | 827df9f3 | balrog | OMAP_RO_REG(offset); |
536 | 827df9f3 | balrog | break;
|
537 | 827df9f3 | balrog | |
538 | b30bb3a2 | balrog | default:
|
539 | b30bb3a2 | balrog | OMAP_BAD_REG(offset); |
540 | b30bb3a2 | balrog | } |
541 | b30bb3a2 | balrog | } |
542 | b30bb3a2 | balrog | |
543 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const omap_mmc_readfn[] = { |
544 | b30bb3a2 | balrog | omap_badwidth_read16, |
545 | b30bb3a2 | balrog | omap_mmc_read, |
546 | b30bb3a2 | balrog | omap_badwidth_read16, |
547 | b30bb3a2 | balrog | }; |
548 | b30bb3a2 | balrog | |
549 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const omap_mmc_writefn[] = { |
550 | b30bb3a2 | balrog | omap_badwidth_write16, |
551 | b30bb3a2 | balrog | omap_mmc_write, |
552 | b30bb3a2 | balrog | omap_badwidth_write16, |
553 | b30bb3a2 | balrog | }; |
554 | b30bb3a2 | balrog | |
555 | 827df9f3 | balrog | static void omap_mmc_cover_cb(void *opaque, int line, int level) |
556 | b30bb3a2 | balrog | { |
557 | 827df9f3 | balrog | struct omap_mmc_s *host = (struct omap_mmc_s *) opaque; |
558 | 827df9f3 | balrog | |
559 | 827df9f3 | balrog | if (!host->cdet_state && level) {
|
560 | 827df9f3 | balrog | host->status |= 0x0002;
|
561 | 827df9f3 | balrog | omap_mmc_interrupts_update(host); |
562 | 827df9f3 | balrog | if (host->cdet_wakeup)
|
563 | 827df9f3 | balrog | /* TODO: Assert wake-up */;
|
564 | 827df9f3 | balrog | } |
565 | 827df9f3 | balrog | |
566 | 827df9f3 | balrog | if (host->cdet_state != level) {
|
567 | 827df9f3 | balrog | qemu_set_irq(host->coverswitch, level); |
568 | 827df9f3 | balrog | host->cdet_state = level; |
569 | 827df9f3 | balrog | } |
570 | b30bb3a2 | balrog | } |
571 | b30bb3a2 | balrog | |
572 | c227f099 | Anthony Liguori | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
573 | 87ecb68b | pbrook | BlockDriverState *bd, |
574 | b30bb3a2 | balrog | qemu_irq irq, qemu_irq dma[], omap_clk clk) |
575 | b30bb3a2 | balrog | { |
576 | b30bb3a2 | balrog | int iomemtype;
|
577 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) |
578 | b30bb3a2 | balrog | qemu_mallocz(sizeof(struct omap_mmc_s)); |
579 | b30bb3a2 | balrog | |
580 | b30bb3a2 | balrog | s->irq = irq; |
581 | b30bb3a2 | balrog | s->dma = dma; |
582 | b30bb3a2 | balrog | s->clk = clk; |
583 | 827df9f3 | balrog | s->lines = 1; /* TODO: needs to be settable per-board */ |
584 | 827df9f3 | balrog | s->rev = 1;
|
585 | 827df9f3 | balrog | |
586 | 827df9f3 | balrog | omap_mmc_reset(s); |
587 | b30bb3a2 | balrog | |
588 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(omap_mmc_readfn, |
589 | b30bb3a2 | balrog | omap_mmc_writefn, s); |
590 | 8da3ff18 | pbrook | cpu_register_physical_memory(base, 0x800, iomemtype);
|
591 | b30bb3a2 | balrog | |
592 | b30bb3a2 | balrog | /* Instantiate the storage */
|
593 | 775616c3 | pbrook | s->card = sd_init(bd, 0);
|
594 | b30bb3a2 | balrog | |
595 | b30bb3a2 | balrog | return s;
|
596 | b30bb3a2 | balrog | } |
597 | b30bb3a2 | balrog | |
598 | 827df9f3 | balrog | struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
599 | 827df9f3 | balrog | BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
600 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk) |
601 | 827df9f3 | balrog | { |
602 | 827df9f3 | balrog | int iomemtype;
|
603 | 827df9f3 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) |
604 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_mmc_s)); |
605 | 827df9f3 | balrog | |
606 | 827df9f3 | balrog | s->irq = irq; |
607 | 827df9f3 | balrog | s->dma = dma; |
608 | 827df9f3 | balrog | s->clk = fclk; |
609 | 827df9f3 | balrog | s->lines = 4;
|
610 | 827df9f3 | balrog | s->rev = 2;
|
611 | 827df9f3 | balrog | |
612 | 827df9f3 | balrog | omap_mmc_reset(s); |
613 | 827df9f3 | balrog | |
614 | 1eed09cb | Avi Kivity | iomemtype = l4_register_io_memory(omap_mmc_readfn, |
615 | 827df9f3 | balrog | omap_mmc_writefn, s); |
616 | 8da3ff18 | pbrook | omap_l4_attach(ta, 0, iomemtype);
|
617 | 827df9f3 | balrog | |
618 | 827df9f3 | balrog | /* Instantiate the storage */
|
619 | 827df9f3 | balrog | s->card = sd_init(bd, 0);
|
620 | 827df9f3 | balrog | |
621 | 827df9f3 | balrog | s->cdet = qemu_allocate_irqs(omap_mmc_cover_cb, s, 1)[0]; |
622 | b9d38e95 | Blue Swirl | sd_set_cb(s->card, NULL, s->cdet);
|
623 | 827df9f3 | balrog | |
624 | 827df9f3 | balrog | return s;
|
625 | 827df9f3 | balrog | } |
626 | 827df9f3 | balrog | |
627 | 8e129e07 | balrog | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) |
628 | 8e129e07 | balrog | { |
629 | 827df9f3 | balrog | if (s->cdet) {
|
630 | 827df9f3 | balrog | sd_set_cb(s->card, ro, s->cdet); |
631 | 827df9f3 | balrog | s->coverswitch = cover; |
632 | 827df9f3 | balrog | qemu_set_irq(cover, s->cdet_state); |
633 | 827df9f3 | balrog | } else
|
634 | 827df9f3 | balrog | sd_set_cb(s->card, ro, cover); |
635 | 827df9f3 | balrog | } |
636 | 827df9f3 | balrog | |
637 | 827df9f3 | balrog | void omap_mmc_enable(struct omap_mmc_s *s, int enable) |
638 | 827df9f3 | balrog | { |
639 | 827df9f3 | balrog | sd_enable(s->card, enable); |
640 | 8e129e07 | balrog | } |