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/*
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* Marvell MV88W8618 / Freecom MusicPal emulation.
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*
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* Copyright (c) 2008 Jan Kiszka
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*
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* This code is licenced under the GNU GPL v2.
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*/
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#include "sysbus.h" |
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#include "arm-misc.h" |
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#include "devices.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "boards.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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#include "block.h" |
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#include "flash.h" |
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#include "console.h" |
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#include "i2c.h" |
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|
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#define MP_MISC_BASE 0x80002000 |
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#define MP_MISC_SIZE 0x00001000 |
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|
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#define MP_ETH_BASE 0x80008000 |
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#define MP_ETH_SIZE 0x00001000 |
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|
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#define MP_WLAN_BASE 0x8000C000 |
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#define MP_WLAN_SIZE 0x00000800 |
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|
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#define MP_UART1_BASE 0x8000C840 |
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#define MP_UART2_BASE 0x8000C940 |
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|
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#define MP_GPIO_BASE 0x8000D000 |
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#define MP_GPIO_SIZE 0x00001000 |
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|
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#define MP_FLASHCFG_BASE 0x90006000 |
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#define MP_FLASHCFG_SIZE 0x00001000 |
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|
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#define MP_AUDIO_BASE 0x90007000 |
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|
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#define MP_PIC_BASE 0x90008000 |
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#define MP_PIC_SIZE 0x00001000 |
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|
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#define MP_PIT_BASE 0x90009000 |
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#define MP_PIT_SIZE 0x00001000 |
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|
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#define MP_LCD_BASE 0x9000c000 |
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#define MP_LCD_SIZE 0x00001000 |
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|
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#define MP_SRAM_BASE 0xC0000000 |
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#define MP_SRAM_SIZE 0x00020000 |
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|
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#define MP_RAM_DEFAULT_SIZE 32*1024*1024 |
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#define MP_FLASH_SIZE_MAX 32*1024*1024 |
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|
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#define MP_TIMER1_IRQ 4 |
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#define MP_TIMER2_IRQ 5 |
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#define MP_TIMER3_IRQ 6 |
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#define MP_TIMER4_IRQ 7 |
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#define MP_EHCI_IRQ 8 |
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#define MP_ETH_IRQ 9 |
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#define MP_UART1_IRQ 11 |
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#define MP_UART2_IRQ 11 |
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#define MP_GPIO_IRQ 12 |
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#define MP_RTC_IRQ 28 |
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#define MP_AUDIO_IRQ 30 |
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|
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/* Wolfson 8750 I2C address */
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#define MP_WM_ADDR 0x34 |
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|
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/* Ethernet register offsets */
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#define MP_ETH_SMIR 0x010 |
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#define MP_ETH_PCXR 0x408 |
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#define MP_ETH_SDCMR 0x448 |
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#define MP_ETH_ICR 0x450 |
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#define MP_ETH_IMR 0x458 |
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#define MP_ETH_FRDP0 0x480 |
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#define MP_ETH_FRDP1 0x484 |
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#define MP_ETH_FRDP2 0x488 |
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#define MP_ETH_FRDP3 0x48C |
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#define MP_ETH_CRDP0 0x4A0 |
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#define MP_ETH_CRDP1 0x4A4 |
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#define MP_ETH_CRDP2 0x4A8 |
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#define MP_ETH_CRDP3 0x4AC |
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#define MP_ETH_CTDP0 0x4E0 |
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#define MP_ETH_CTDP1 0x4E4 |
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#define MP_ETH_CTDP2 0x4E8 |
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#define MP_ETH_CTDP3 0x4EC |
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|
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/* MII PHY access */
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#define MP_ETH_SMIR_DATA 0x0000FFFF |
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#define MP_ETH_SMIR_ADDR 0x03FF0000 |
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#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ |
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#define MP_ETH_SMIR_RDVALID (1 << 27) |
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|
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/* PHY registers */
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#define MP_ETH_PHY1_BMSR 0x00210000 |
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#define MP_ETH_PHY1_PHYSID1 0x00410000 |
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#define MP_ETH_PHY1_PHYSID2 0x00610000 |
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#define MP_PHY_BMSR_LINK 0x0004 |
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#define MP_PHY_BMSR_AUTONEG 0x0008 |
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|
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#define MP_PHY_88E3015 0x01410E20 |
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|
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/* TX descriptor status */
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#define MP_ETH_TX_OWN (1 << 31) |
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|
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/* RX descriptor status */
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#define MP_ETH_RX_OWN (1 << 31) |
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|
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/* Interrupt cause/mask bits */
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#define MP_ETH_IRQ_RX_BIT 0 |
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#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) |
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#define MP_ETH_IRQ_TXHI_BIT 2 |
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#define MP_ETH_IRQ_TXLO_BIT 3 |
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|
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/* Port config bits */
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#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ |
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|
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/* SDMA command bits */
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#define MP_ETH_CMD_TXHI (1 << 23) |
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#define MP_ETH_CMD_TXLO (1 << 22) |
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|
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typedef struct mv88w8618_tx_desc { |
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uint32_t cmdstat; |
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uint16_t res; |
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uint16_t bytes; |
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uint32_t buffer; |
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uint32_t next; |
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} mv88w8618_tx_desc; |
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typedef struct mv88w8618_rx_desc { |
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uint32_t cmdstat; |
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uint16_t bytes; |
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uint16_t buffer_size; |
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uint32_t buffer; |
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uint32_t next; |
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} mv88w8618_rx_desc; |
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typedef struct mv88w8618_eth_state { |
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SysBusDevice busdev; |
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qemu_irq irq; |
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uint32_t smir; |
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uint32_t icr; |
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uint32_t imr; |
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int mmio_index;
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uint32_t vlan_header; |
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uint32_t tx_queue[2];
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uint32_t rx_queue[4];
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uint32_t frx_queue[4];
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uint32_t cur_rx[4];
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VLANClientState *vc; |
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} mv88w8618_eth_state; |
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static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
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{ |
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cpu_to_le32s(&desc->cmdstat); |
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cpu_to_le16s(&desc->bytes); |
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cpu_to_le16s(&desc->buffer_size); |
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cpu_to_le32s(&desc->buffer); |
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cpu_to_le32s(&desc->next); |
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cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
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} |
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static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) |
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{ |
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cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
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le32_to_cpus(&desc->cmdstat); |
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le16_to_cpus(&desc->bytes); |
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le16_to_cpus(&desc->buffer_size); |
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le32_to_cpus(&desc->buffer); |
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le32_to_cpus(&desc->next); |
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} |
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static int eth_can_receive(VLANClientState *vc) |
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{ |
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return 1; |
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} |
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static ssize_t eth_receive(VLANClientState *vc, const uint8_t *buf, size_t size) |
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{ |
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mv88w8618_eth_state *s = vc->opaque; |
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uint32_t desc_addr; |
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mv88w8618_rx_desc desc; |
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int i;
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for (i = 0; i < 4; i++) { |
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desc_addr = s->cur_rx[i]; |
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if (!desc_addr) {
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continue;
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} |
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do {
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eth_rx_desc_get(desc_addr, &desc); |
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if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
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cpu_physical_memory_write(desc.buffer + s->vlan_header, |
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buf, size); |
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desc.bytes = size + s->vlan_header; |
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desc.cmdstat &= ~MP_ETH_RX_OWN; |
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s->cur_rx[i] = desc.next; |
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s->icr |= MP_ETH_IRQ_RX; |
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if (s->icr & s->imr) {
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qemu_irq_raise(s->irq); |
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} |
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eth_rx_desc_put(desc_addr, &desc); |
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return size;
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} |
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desc_addr = desc.next; |
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} while (desc_addr != s->rx_queue[i]);
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} |
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return size;
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} |
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static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
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{ |
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cpu_to_le32s(&desc->cmdstat); |
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cpu_to_le16s(&desc->res); |
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cpu_to_le16s(&desc->bytes); |
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cpu_to_le32s(&desc->buffer); |
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cpu_to_le32s(&desc->next); |
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cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
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} |
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static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) |
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{ |
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cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
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le32_to_cpus(&desc->cmdstat); |
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le16_to_cpus(&desc->res); |
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le16_to_cpus(&desc->bytes); |
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le32_to_cpus(&desc->buffer); |
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le32_to_cpus(&desc->next); |
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} |
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static void eth_send(mv88w8618_eth_state *s, int queue_index) |
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{ |
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uint32_t desc_addr = s->tx_queue[queue_index]; |
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mv88w8618_tx_desc desc; |
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uint8_t buf[2048];
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int len;
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if (!desc_addr) {
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return;
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} |
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do {
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eth_tx_desc_get(desc_addr, &desc); |
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if (desc.cmdstat & MP_ETH_TX_OWN) {
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len = desc.bytes; |
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if (len < 2048) { |
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cpu_physical_memory_read(desc.buffer, buf, len); |
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qemu_send_packet(s->vc, buf, len); |
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} |
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desc.cmdstat &= ~MP_ETH_TX_OWN; |
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s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
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eth_tx_desc_put(desc_addr, &desc); |
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} |
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desc_addr = desc.next; |
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} while (desc_addr != s->tx_queue[queue_index]);
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} |
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static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
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{ |
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mv88w8618_eth_state *s = opaque; |
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switch (offset) {
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case MP_ETH_SMIR:
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if (s->smir & MP_ETH_SMIR_OPCODE) {
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switch (s->smir & MP_ETH_SMIR_ADDR) {
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case MP_ETH_PHY1_BMSR:
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return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
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MP_ETH_SMIR_RDVALID; |
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case MP_ETH_PHY1_PHYSID1:
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return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; |
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case MP_ETH_PHY1_PHYSID2:
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return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; |
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default:
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return MP_ETH_SMIR_RDVALID;
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} |
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} |
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return 0; |
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|
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case MP_ETH_ICR:
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return s->icr;
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|
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case MP_ETH_IMR:
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return s->imr;
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|
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case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
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|
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case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
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|
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case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
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|
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default:
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return 0; |
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} |
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} |
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|
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static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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mv88w8618_eth_state *s = opaque; |
307 |
|
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switch (offset) {
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case MP_ETH_SMIR:
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s->smir = value; |
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break;
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|
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case MP_ETH_PCXR:
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s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; |
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break;
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|
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case MP_ETH_SDCMR:
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if (value & MP_ETH_CMD_TXHI) {
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eth_send(s, 1);
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} |
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if (value & MP_ETH_CMD_TXLO) {
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eth_send(s, 0);
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} |
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if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
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qemu_irq_raise(s->irq); |
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} |
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break;
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|
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case MP_ETH_ICR:
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s->icr &= value; |
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break;
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|
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case MP_ETH_IMR:
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s->imr = value; |
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if (s->icr & s->imr) {
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qemu_irq_raise(s->irq); |
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} |
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break;
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|
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case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
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break;
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|
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case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
|
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s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
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break;
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|
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case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
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break;
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} |
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} |
354 |
|
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static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = { |
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mv88w8618_eth_read, |
357 |
mv88w8618_eth_read, |
358 |
mv88w8618_eth_read |
359 |
}; |
360 |
|
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static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = { |
362 |
mv88w8618_eth_write, |
363 |
mv88w8618_eth_write, |
364 |
mv88w8618_eth_write |
365 |
}; |
366 |
|
367 |
static void eth_cleanup(VLANClientState *vc) |
368 |
{ |
369 |
mv88w8618_eth_state *s = vc->opaque; |
370 |
|
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cpu_unregister_io_memory(s->mmio_index); |
372 |
|
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qemu_free(s); |
374 |
} |
375 |
|
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static int mv88w8618_eth_init(SysBusDevice *dev) |
377 |
{ |
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mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev); |
379 |
|
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sysbus_init_irq(dev, &s->irq); |
381 |
s->vc = qdev_get_vlan_client(&dev->qdev, |
382 |
eth_can_receive, eth_receive, NULL,
|
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eth_cleanup, s); |
384 |
s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, |
385 |
mv88w8618_eth_writefn, s); |
386 |
sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); |
387 |
return 0; |
388 |
} |
389 |
|
390 |
static const VMStateDescription mv88w8618_eth_vmsd = { |
391 |
.name = "mv88w8618_eth",
|
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.version_id = 1,
|
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.minimum_version_id = 1,
|
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.minimum_version_id_old = 1,
|
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.fields = (VMStateField[]) { |
396 |
VMSTATE_UINT32(smir, mv88w8618_eth_state), |
397 |
VMSTATE_UINT32(icr, mv88w8618_eth_state), |
398 |
VMSTATE_UINT32(imr, mv88w8618_eth_state), |
399 |
VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), |
400 |
VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
|
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VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
|
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VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
|
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VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
|
404 |
VMSTATE_END_OF_LIST() |
405 |
} |
406 |
}; |
407 |
|
408 |
static SysBusDeviceInfo mv88w8618_eth_info = {
|
409 |
.init = mv88w8618_eth_init, |
410 |
.qdev.name = "mv88w8618_eth",
|
411 |
.qdev.size = sizeof(mv88w8618_eth_state),
|
412 |
.qdev.vmsd = &mv88w8618_eth_vmsd, |
413 |
}; |
414 |
|
415 |
/* LCD register offsets */
|
416 |
#define MP_LCD_IRQCTRL 0x180 |
417 |
#define MP_LCD_IRQSTAT 0x184 |
418 |
#define MP_LCD_SPICTRL 0x1ac |
419 |
#define MP_LCD_INST 0x1bc |
420 |
#define MP_LCD_DATA 0x1c0 |
421 |
|
422 |
/* Mode magics */
|
423 |
#define MP_LCD_SPI_DATA 0x00100011 |
424 |
#define MP_LCD_SPI_CMD 0x00104011 |
425 |
#define MP_LCD_SPI_INVALID 0x00000000 |
426 |
|
427 |
/* Commmands */
|
428 |
#define MP_LCD_INST_SETPAGE0 0xB0 |
429 |
/* ... */
|
430 |
#define MP_LCD_INST_SETPAGE7 0xB7 |
431 |
|
432 |
#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ |
433 |
|
434 |
typedef struct musicpal_lcd_state { |
435 |
SysBusDevice busdev; |
436 |
uint32_t brightness; |
437 |
uint32_t mode; |
438 |
uint32_t irqctrl; |
439 |
uint32_t page; |
440 |
uint32_t page_off; |
441 |
DisplayState *ds; |
442 |
uint8_t video_ram[128*64/8]; |
443 |
} musicpal_lcd_state; |
444 |
|
445 |
static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
|
446 |
{ |
447 |
switch (s->brightness) {
|
448 |
case 7: |
449 |
return col;
|
450 |
case 0: |
451 |
return 0; |
452 |
default:
|
453 |
return (col * s->brightness) / 7; |
454 |
} |
455 |
} |
456 |
|
457 |
#define SET_LCD_PIXEL(depth, type) \
|
458 |
static inline void glue(set_lcd_pixel, depth) \ |
459 |
(musicpal_lcd_state *s, int x, int y, type col) \ |
460 |
{ \ |
461 |
int dx, dy; \
|
462 |
type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
463 |
\ |
464 |
for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ |
465 |
for (dx = 0; dx < 3; dx++, pixel++) \ |
466 |
*pixel = col; \ |
467 |
} |
468 |
SET_LCD_PIXEL(8, uint8_t)
|
469 |
SET_LCD_PIXEL(16, uint16_t)
|
470 |
SET_LCD_PIXEL(32, uint32_t)
|
471 |
|
472 |
#include "pixel_ops.h" |
473 |
|
474 |
static void lcd_refresh(void *opaque) |
475 |
{ |
476 |
musicpal_lcd_state *s = opaque; |
477 |
int x, y, col;
|
478 |
|
479 |
switch (ds_get_bits_per_pixel(s->ds)) {
|
480 |
case 0: |
481 |
return;
|
482 |
#define LCD_REFRESH(depth, func) \
|
483 |
case depth: \
|
484 |
col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
485 |
scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ |
486 |
scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
|
487 |
for (x = 0; x < 128; x++) { \ |
488 |
for (y = 0; y < 64; y++) { \ |
489 |
if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ |
490 |
glue(set_lcd_pixel, depth)(s, x, y, col); \ |
491 |
} else { \
|
492 |
glue(set_lcd_pixel, depth)(s, x, y, 0); \
|
493 |
} \ |
494 |
} \ |
495 |
} \ |
496 |
break;
|
497 |
LCD_REFRESH(8, rgb_to_pixel8)
|
498 |
LCD_REFRESH(16, rgb_to_pixel16)
|
499 |
LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
|
500 |
rgb_to_pixel32bgr : rgb_to_pixel32)) |
501 |
default:
|
502 |
hw_error("unsupported colour depth %i\n",
|
503 |
ds_get_bits_per_pixel(s->ds)); |
504 |
} |
505 |
|
506 |
dpy_update(s->ds, 0, 0, 128*3, 64*3); |
507 |
} |
508 |
|
509 |
static void lcd_invalidate(void *opaque) |
510 |
{ |
511 |
} |
512 |
|
513 |
static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) |
514 |
{ |
515 |
musicpal_lcd_state *s = opaque; |
516 |
s->brightness &= ~(1 << irq);
|
517 |
s->brightness |= level << irq; |
518 |
} |
519 |
|
520 |
static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
521 |
{ |
522 |
musicpal_lcd_state *s = opaque; |
523 |
|
524 |
switch (offset) {
|
525 |
case MP_LCD_IRQCTRL:
|
526 |
return s->irqctrl;
|
527 |
|
528 |
default:
|
529 |
return 0; |
530 |
} |
531 |
} |
532 |
|
533 |
static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
534 |
uint32_t value) |
535 |
{ |
536 |
musicpal_lcd_state *s = opaque; |
537 |
|
538 |
switch (offset) {
|
539 |
case MP_LCD_IRQCTRL:
|
540 |
s->irqctrl = value; |
541 |
break;
|
542 |
|
543 |
case MP_LCD_SPICTRL:
|
544 |
if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
|
545 |
s->mode = value; |
546 |
} else {
|
547 |
s->mode = MP_LCD_SPI_INVALID; |
548 |
} |
549 |
break;
|
550 |
|
551 |
case MP_LCD_INST:
|
552 |
if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
|
553 |
s->page = value - MP_LCD_INST_SETPAGE0; |
554 |
s->page_off = 0;
|
555 |
} |
556 |
break;
|
557 |
|
558 |
case MP_LCD_DATA:
|
559 |
if (s->mode == MP_LCD_SPI_CMD) {
|
560 |
if (value >= MP_LCD_INST_SETPAGE0 &&
|
561 |
value <= MP_LCD_INST_SETPAGE7) { |
562 |
s->page = value - MP_LCD_INST_SETPAGE0; |
563 |
s->page_off = 0;
|
564 |
} |
565 |
} else if (s->mode == MP_LCD_SPI_DATA) { |
566 |
s->video_ram[s->page*128 + s->page_off] = value;
|
567 |
s->page_off = (s->page_off + 1) & 127; |
568 |
} |
569 |
break;
|
570 |
} |
571 |
} |
572 |
|
573 |
static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = { |
574 |
musicpal_lcd_read, |
575 |
musicpal_lcd_read, |
576 |
musicpal_lcd_read |
577 |
}; |
578 |
|
579 |
static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = { |
580 |
musicpal_lcd_write, |
581 |
musicpal_lcd_write, |
582 |
musicpal_lcd_write |
583 |
}; |
584 |
|
585 |
static int musicpal_lcd_init(SysBusDevice *dev) |
586 |
{ |
587 |
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); |
588 |
int iomemtype;
|
589 |
|
590 |
s->brightness = 7;
|
591 |
|
592 |
iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, |
593 |
musicpal_lcd_writefn, s); |
594 |
sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); |
595 |
|
596 |
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
597 |
NULL, NULL, s); |
598 |
qemu_console_resize(s->ds, 128*3, 64*3); |
599 |
|
600 |
qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
|
601 |
|
602 |
return 0; |
603 |
} |
604 |
|
605 |
static const VMStateDescription musicpal_lcd_vmsd = { |
606 |
.name = "musicpal_lcd",
|
607 |
.version_id = 1,
|
608 |
.minimum_version_id = 1,
|
609 |
.minimum_version_id_old = 1,
|
610 |
.fields = (VMStateField[]) { |
611 |
VMSTATE_UINT32(brightness, musicpal_lcd_state), |
612 |
VMSTATE_UINT32(mode, musicpal_lcd_state), |
613 |
VMSTATE_UINT32(irqctrl, musicpal_lcd_state), |
614 |
VMSTATE_UINT32(page, musicpal_lcd_state), |
615 |
VMSTATE_UINT32(page_off, musicpal_lcd_state), |
616 |
VMSTATE_BUFFER(video_ram, musicpal_lcd_state), |
617 |
VMSTATE_END_OF_LIST() |
618 |
} |
619 |
}; |
620 |
|
621 |
static SysBusDeviceInfo musicpal_lcd_info = {
|
622 |
.init = musicpal_lcd_init, |
623 |
.qdev.name = "musicpal_lcd",
|
624 |
.qdev.size = sizeof(musicpal_lcd_state),
|
625 |
.qdev.vmsd = &musicpal_lcd_vmsd, |
626 |
}; |
627 |
|
628 |
/* PIC register offsets */
|
629 |
#define MP_PIC_STATUS 0x00 |
630 |
#define MP_PIC_ENABLE_SET 0x08 |
631 |
#define MP_PIC_ENABLE_CLR 0x0C |
632 |
|
633 |
typedef struct mv88w8618_pic_state |
634 |
{ |
635 |
SysBusDevice busdev; |
636 |
uint32_t level; |
637 |
uint32_t enabled; |
638 |
qemu_irq parent_irq; |
639 |
} mv88w8618_pic_state; |
640 |
|
641 |
static void mv88w8618_pic_update(mv88w8618_pic_state *s) |
642 |
{ |
643 |
qemu_set_irq(s->parent_irq, (s->level & s->enabled)); |
644 |
} |
645 |
|
646 |
static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) |
647 |
{ |
648 |
mv88w8618_pic_state *s = opaque; |
649 |
|
650 |
if (level) {
|
651 |
s->level |= 1 << irq;
|
652 |
} else {
|
653 |
s->level &= ~(1 << irq);
|
654 |
} |
655 |
mv88w8618_pic_update(s); |
656 |
} |
657 |
|
658 |
static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
659 |
{ |
660 |
mv88w8618_pic_state *s = opaque; |
661 |
|
662 |
switch (offset) {
|
663 |
case MP_PIC_STATUS:
|
664 |
return s->level & s->enabled;
|
665 |
|
666 |
default:
|
667 |
return 0; |
668 |
} |
669 |
} |
670 |
|
671 |
static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
672 |
uint32_t value) |
673 |
{ |
674 |
mv88w8618_pic_state *s = opaque; |
675 |
|
676 |
switch (offset) {
|
677 |
case MP_PIC_ENABLE_SET:
|
678 |
s->enabled |= value; |
679 |
break;
|
680 |
|
681 |
case MP_PIC_ENABLE_CLR:
|
682 |
s->enabled &= ~value; |
683 |
s->level &= ~value; |
684 |
break;
|
685 |
} |
686 |
mv88w8618_pic_update(s); |
687 |
} |
688 |
|
689 |
static void mv88w8618_pic_reset(DeviceState *d) |
690 |
{ |
691 |
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, |
692 |
sysbus_from_qdev(d)); |
693 |
|
694 |
s->level = 0;
|
695 |
s->enabled = 0;
|
696 |
} |
697 |
|
698 |
static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = { |
699 |
mv88w8618_pic_read, |
700 |
mv88w8618_pic_read, |
701 |
mv88w8618_pic_read |
702 |
}; |
703 |
|
704 |
static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = { |
705 |
mv88w8618_pic_write, |
706 |
mv88w8618_pic_write, |
707 |
mv88w8618_pic_write |
708 |
}; |
709 |
|
710 |
static int mv88w8618_pic_init(SysBusDevice *dev) |
711 |
{ |
712 |
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev); |
713 |
int iomemtype;
|
714 |
|
715 |
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
|
716 |
sysbus_init_irq(dev, &s->parent_irq); |
717 |
iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, |
718 |
mv88w8618_pic_writefn, s); |
719 |
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); |
720 |
return 0; |
721 |
} |
722 |
|
723 |
static const VMStateDescription mv88w8618_pic_vmsd = { |
724 |
.name = "mv88w8618_pic",
|
725 |
.version_id = 1,
|
726 |
.minimum_version_id = 1,
|
727 |
.minimum_version_id_old = 1,
|
728 |
.fields = (VMStateField[]) { |
729 |
VMSTATE_UINT32(level, mv88w8618_pic_state), |
730 |
VMSTATE_UINT32(enabled, mv88w8618_pic_state), |
731 |
VMSTATE_END_OF_LIST() |
732 |
} |
733 |
}; |
734 |
|
735 |
static SysBusDeviceInfo mv88w8618_pic_info = {
|
736 |
.init = mv88w8618_pic_init, |
737 |
.qdev.name = "mv88w8618_pic",
|
738 |
.qdev.size = sizeof(mv88w8618_pic_state),
|
739 |
.qdev.reset = mv88w8618_pic_reset, |
740 |
.qdev.vmsd = &mv88w8618_pic_vmsd, |
741 |
}; |
742 |
|
743 |
/* PIT register offsets */
|
744 |
#define MP_PIT_TIMER1_LENGTH 0x00 |
745 |
/* ... */
|
746 |
#define MP_PIT_TIMER4_LENGTH 0x0C |
747 |
#define MP_PIT_CONTROL 0x10 |
748 |
#define MP_PIT_TIMER1_VALUE 0x14 |
749 |
/* ... */
|
750 |
#define MP_PIT_TIMER4_VALUE 0x20 |
751 |
#define MP_BOARD_RESET 0x34 |
752 |
|
753 |
/* Magic board reset value (probably some watchdog behind it) */
|
754 |
#define MP_BOARD_RESET_MAGIC 0x10000 |
755 |
|
756 |
typedef struct mv88w8618_timer_state { |
757 |
ptimer_state *ptimer; |
758 |
uint32_t limit; |
759 |
int freq;
|
760 |
qemu_irq irq; |
761 |
} mv88w8618_timer_state; |
762 |
|
763 |
typedef struct mv88w8618_pit_state { |
764 |
SysBusDevice busdev; |
765 |
mv88w8618_timer_state timer[4];
|
766 |
} mv88w8618_pit_state; |
767 |
|
768 |
static void mv88w8618_timer_tick(void *opaque) |
769 |
{ |
770 |
mv88w8618_timer_state *s = opaque; |
771 |
|
772 |
qemu_irq_raise(s->irq); |
773 |
} |
774 |
|
775 |
static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
776 |
uint32_t freq) |
777 |
{ |
778 |
QEMUBH *bh; |
779 |
|
780 |
sysbus_init_irq(dev, &s->irq); |
781 |
s->freq = freq; |
782 |
|
783 |
bh = qemu_bh_new(mv88w8618_timer_tick, s); |
784 |
s->ptimer = ptimer_init(bh); |
785 |
} |
786 |
|
787 |
static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
788 |
{ |
789 |
mv88w8618_pit_state *s = opaque; |
790 |
mv88w8618_timer_state *t; |
791 |
|
792 |
switch (offset) {
|
793 |
case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
|
794 |
t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
|
795 |
return ptimer_get_count(t->ptimer);
|
796 |
|
797 |
default:
|
798 |
return 0; |
799 |
} |
800 |
} |
801 |
|
802 |
static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
803 |
uint32_t value) |
804 |
{ |
805 |
mv88w8618_pit_state *s = opaque; |
806 |
mv88w8618_timer_state *t; |
807 |
int i;
|
808 |
|
809 |
switch (offset) {
|
810 |
case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
|
811 |
t = &s->timer[offset >> 2];
|
812 |
t->limit = value; |
813 |
if (t->limit > 0) { |
814 |
ptimer_set_limit(t->ptimer, t->limit, 1);
|
815 |
} else {
|
816 |
ptimer_stop(t->ptimer); |
817 |
} |
818 |
break;
|
819 |
|
820 |
case MP_PIT_CONTROL:
|
821 |
for (i = 0; i < 4; i++) { |
822 |
t = &s->timer[i]; |
823 |
if (value & 0xf && t->limit > 0) { |
824 |
ptimer_set_limit(t->ptimer, t->limit, 0);
|
825 |
ptimer_set_freq(t->ptimer, t->freq); |
826 |
ptimer_run(t->ptimer, 0);
|
827 |
} else {
|
828 |
ptimer_stop(t->ptimer); |
829 |
} |
830 |
value >>= 4;
|
831 |
} |
832 |
break;
|
833 |
|
834 |
case MP_BOARD_RESET:
|
835 |
if (value == MP_BOARD_RESET_MAGIC) {
|
836 |
qemu_system_reset_request(); |
837 |
} |
838 |
break;
|
839 |
} |
840 |
} |
841 |
|
842 |
static void mv88w8618_pit_reset(DeviceState *d) |
843 |
{ |
844 |
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, |
845 |
sysbus_from_qdev(d)); |
846 |
int i;
|
847 |
|
848 |
for (i = 0; i < 4; i++) { |
849 |
ptimer_stop(s->timer[i].ptimer); |
850 |
s->timer[i].limit = 0;
|
851 |
} |
852 |
} |
853 |
|
854 |
static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = { |
855 |
mv88w8618_pit_read, |
856 |
mv88w8618_pit_read, |
857 |
mv88w8618_pit_read |
858 |
}; |
859 |
|
860 |
static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = { |
861 |
mv88w8618_pit_write, |
862 |
mv88w8618_pit_write, |
863 |
mv88w8618_pit_write |
864 |
}; |
865 |
|
866 |
static int mv88w8618_pit_init(SysBusDevice *dev) |
867 |
{ |
868 |
int iomemtype;
|
869 |
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev); |
870 |
int i;
|
871 |
|
872 |
/* Letting them all run at 1 MHz is likely just a pragmatic
|
873 |
* simplification. */
|
874 |
for (i = 0; i < 4; i++) { |
875 |
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
|
876 |
} |
877 |
|
878 |
iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, |
879 |
mv88w8618_pit_writefn, s); |
880 |
sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); |
881 |
return 0; |
882 |
} |
883 |
|
884 |
static const VMStateDescription mv88w8618_timer_vmsd = { |
885 |
.name = "timer",
|
886 |
.version_id = 1,
|
887 |
.minimum_version_id = 1,
|
888 |
.minimum_version_id_old = 1,
|
889 |
.fields = (VMStateField[]) { |
890 |
VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), |
891 |
VMSTATE_UINT32(limit, mv88w8618_timer_state), |
892 |
VMSTATE_END_OF_LIST() |
893 |
} |
894 |
}; |
895 |
|
896 |
static const VMStateDescription mv88w8618_pit_vmsd = { |
897 |
.name = "mv88w8618_pit",
|
898 |
.version_id = 1,
|
899 |
.minimum_version_id = 1,
|
900 |
.minimum_version_id_old = 1,
|
901 |
.fields = (VMStateField[]) { |
902 |
VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, |
903 |
mv88w8618_timer_vmsd, mv88w8618_timer_state), |
904 |
VMSTATE_END_OF_LIST() |
905 |
} |
906 |
}; |
907 |
|
908 |
static SysBusDeviceInfo mv88w8618_pit_info = {
|
909 |
.init = mv88w8618_pit_init, |
910 |
.qdev.name = "mv88w8618_pit",
|
911 |
.qdev.size = sizeof(mv88w8618_pit_state),
|
912 |
.qdev.reset = mv88w8618_pit_reset, |
913 |
.qdev.vmsd = &mv88w8618_pit_vmsd, |
914 |
}; |
915 |
|
916 |
/* Flash config register offsets */
|
917 |
#define MP_FLASHCFG_CFGR0 0x04 |
918 |
|
919 |
typedef struct mv88w8618_flashcfg_state { |
920 |
SysBusDevice busdev; |
921 |
uint32_t cfgr0; |
922 |
} mv88w8618_flashcfg_state; |
923 |
|
924 |
static uint32_t mv88w8618_flashcfg_read(void *opaque, |
925 |
target_phys_addr_t offset) |
926 |
{ |
927 |
mv88w8618_flashcfg_state *s = opaque; |
928 |
|
929 |
switch (offset) {
|
930 |
case MP_FLASHCFG_CFGR0:
|
931 |
return s->cfgr0;
|
932 |
|
933 |
default:
|
934 |
return 0; |
935 |
} |
936 |
} |
937 |
|
938 |
static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
939 |
uint32_t value) |
940 |
{ |
941 |
mv88w8618_flashcfg_state *s = opaque; |
942 |
|
943 |
switch (offset) {
|
944 |
case MP_FLASHCFG_CFGR0:
|
945 |
s->cfgr0 = value; |
946 |
break;
|
947 |
} |
948 |
} |
949 |
|
950 |
static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = { |
951 |
mv88w8618_flashcfg_read, |
952 |
mv88w8618_flashcfg_read, |
953 |
mv88w8618_flashcfg_read |
954 |
}; |
955 |
|
956 |
static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = { |
957 |
mv88w8618_flashcfg_write, |
958 |
mv88w8618_flashcfg_write, |
959 |
mv88w8618_flashcfg_write |
960 |
}; |
961 |
|
962 |
static int mv88w8618_flashcfg_init(SysBusDevice *dev) |
963 |
{ |
964 |
int iomemtype;
|
965 |
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev); |
966 |
|
967 |
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
968 |
iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, |
969 |
mv88w8618_flashcfg_writefn, s); |
970 |
sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); |
971 |
return 0; |
972 |
} |
973 |
|
974 |
static const VMStateDescription mv88w8618_flashcfg_vmsd = { |
975 |
.name = "mv88w8618_flashcfg",
|
976 |
.version_id = 1,
|
977 |
.minimum_version_id = 1,
|
978 |
.minimum_version_id_old = 1,
|
979 |
.fields = (VMStateField[]) { |
980 |
VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), |
981 |
VMSTATE_END_OF_LIST() |
982 |
} |
983 |
}; |
984 |
|
985 |
static SysBusDeviceInfo mv88w8618_flashcfg_info = {
|
986 |
.init = mv88w8618_flashcfg_init, |
987 |
.qdev.name = "mv88w8618_flashcfg",
|
988 |
.qdev.size = sizeof(mv88w8618_flashcfg_state),
|
989 |
.qdev.vmsd = &mv88w8618_flashcfg_vmsd, |
990 |
}; |
991 |
|
992 |
/* Misc register offsets */
|
993 |
#define MP_MISC_BOARD_REVISION 0x18 |
994 |
|
995 |
#define MP_BOARD_REVISION 0x31 |
996 |
|
997 |
static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) |
998 |
{ |
999 |
switch (offset) {
|
1000 |
case MP_MISC_BOARD_REVISION:
|
1001 |
return MP_BOARD_REVISION;
|
1002 |
|
1003 |
default:
|
1004 |
return 0; |
1005 |
} |
1006 |
} |
1007 |
|
1008 |
static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, |
1009 |
uint32_t value) |
1010 |
{ |
1011 |
} |
1012 |
|
1013 |
static CPUReadMemoryFunc * const musicpal_misc_readfn[] = { |
1014 |
musicpal_misc_read, |
1015 |
musicpal_misc_read, |
1016 |
musicpal_misc_read, |
1017 |
}; |
1018 |
|
1019 |
static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = { |
1020 |
musicpal_misc_write, |
1021 |
musicpal_misc_write, |
1022 |
musicpal_misc_write, |
1023 |
}; |
1024 |
|
1025 |
static void musicpal_misc_init(void) |
1026 |
{ |
1027 |
int iomemtype;
|
1028 |
|
1029 |
iomemtype = cpu_register_io_memory(musicpal_misc_readfn, |
1030 |
musicpal_misc_writefn, NULL);
|
1031 |
cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); |
1032 |
} |
1033 |
|
1034 |
/* WLAN register offsets */
|
1035 |
#define MP_WLAN_MAGIC1 0x11c |
1036 |
#define MP_WLAN_MAGIC2 0x124 |
1037 |
|
1038 |
static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) |
1039 |
{ |
1040 |
switch (offset) {
|
1041 |
/* Workaround to allow loading the binary-only wlandrv.ko crap
|
1042 |
* from the original Freecom firmware. */
|
1043 |
case MP_WLAN_MAGIC1:
|
1044 |
return ~3; |
1045 |
case MP_WLAN_MAGIC2:
|
1046 |
return -1; |
1047 |
|
1048 |
default:
|
1049 |
return 0; |
1050 |
} |
1051 |
} |
1052 |
|
1053 |
static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, |
1054 |
uint32_t value) |
1055 |
{ |
1056 |
} |
1057 |
|
1058 |
static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = { |
1059 |
mv88w8618_wlan_read, |
1060 |
mv88w8618_wlan_read, |
1061 |
mv88w8618_wlan_read, |
1062 |
}; |
1063 |
|
1064 |
static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = { |
1065 |
mv88w8618_wlan_write, |
1066 |
mv88w8618_wlan_write, |
1067 |
mv88w8618_wlan_write, |
1068 |
}; |
1069 |
|
1070 |
static int mv88w8618_wlan_init(SysBusDevice *dev) |
1071 |
{ |
1072 |
int iomemtype;
|
1073 |
|
1074 |
iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, |
1075 |
mv88w8618_wlan_writefn, NULL);
|
1076 |
sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); |
1077 |
return 0; |
1078 |
} |
1079 |
|
1080 |
/* GPIO register offsets */
|
1081 |
#define MP_GPIO_OE_LO 0x008 |
1082 |
#define MP_GPIO_OUT_LO 0x00c |
1083 |
#define MP_GPIO_IN_LO 0x010 |
1084 |
#define MP_GPIO_IER_LO 0x014 |
1085 |
#define MP_GPIO_IMR_LO 0x018 |
1086 |
#define MP_GPIO_ISR_LO 0x020 |
1087 |
#define MP_GPIO_OE_HI 0x508 |
1088 |
#define MP_GPIO_OUT_HI 0x50c |
1089 |
#define MP_GPIO_IN_HI 0x510 |
1090 |
#define MP_GPIO_IER_HI 0x514 |
1091 |
#define MP_GPIO_IMR_HI 0x518 |
1092 |
#define MP_GPIO_ISR_HI 0x520 |
1093 |
|
1094 |
/* GPIO bits & masks */
|
1095 |
#define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
1096 |
#define MP_GPIO_I2C_DATA_BIT 29 |
1097 |
#define MP_GPIO_I2C_CLOCK_BIT 30 |
1098 |
|
1099 |
/* LCD brightness bits in GPIO_OE_HI */
|
1100 |
#define MP_OE_LCD_BRIGHTNESS 0x0007 |
1101 |
|
1102 |
typedef struct musicpal_gpio_state { |
1103 |
SysBusDevice busdev; |
1104 |
uint32_t lcd_brightness; |
1105 |
uint32_t out_state; |
1106 |
uint32_t in_state; |
1107 |
uint32_t ier; |
1108 |
uint32_t imr; |
1109 |
uint32_t isr; |
1110 |
qemu_irq irq; |
1111 |
qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ |
1112 |
} musicpal_gpio_state; |
1113 |
|
1114 |
static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { |
1115 |
int i;
|
1116 |
uint32_t brightness; |
1117 |
|
1118 |
/* compute brightness ratio */
|
1119 |
switch (s->lcd_brightness) {
|
1120 |
case 0x00000007: |
1121 |
brightness = 0;
|
1122 |
break;
|
1123 |
|
1124 |
case 0x00020000: |
1125 |
brightness = 1;
|
1126 |
break;
|
1127 |
|
1128 |
case 0x00020001: |
1129 |
brightness = 2;
|
1130 |
break;
|
1131 |
|
1132 |
case 0x00040000: |
1133 |
brightness = 3;
|
1134 |
break;
|
1135 |
|
1136 |
case 0x00010006: |
1137 |
brightness = 4;
|
1138 |
break;
|
1139 |
|
1140 |
case 0x00020005: |
1141 |
brightness = 5;
|
1142 |
break;
|
1143 |
|
1144 |
case 0x00040003: |
1145 |
brightness = 6;
|
1146 |
break;
|
1147 |
|
1148 |
case 0x00030004: |
1149 |
default:
|
1150 |
brightness = 7;
|
1151 |
} |
1152 |
|
1153 |
/* set lcd brightness GPIOs */
|
1154 |
for (i = 0; i <= 2; i++) { |
1155 |
qemu_set_irq(s->out[i], (brightness >> i) & 1);
|
1156 |
} |
1157 |
} |
1158 |
|
1159 |
static void musicpal_gpio_pin_event(void *opaque, int pin, int level) |
1160 |
{ |
1161 |
musicpal_gpio_state *s = opaque; |
1162 |
uint32_t mask = 1 << pin;
|
1163 |
uint32_t delta = level << pin; |
1164 |
uint32_t old = s->in_state & mask; |
1165 |
|
1166 |
s->in_state &= ~mask; |
1167 |
s->in_state |= delta; |
1168 |
|
1169 |
if ((old ^ delta) &&
|
1170 |
((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { |
1171 |
s->isr = mask; |
1172 |
qemu_irq_raise(s->irq); |
1173 |
} |
1174 |
} |
1175 |
|
1176 |
static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
1177 |
{ |
1178 |
musicpal_gpio_state *s = opaque; |
1179 |
|
1180 |
switch (offset) {
|
1181 |
case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1182 |
return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
|
1183 |
|
1184 |
case MP_GPIO_OUT_LO:
|
1185 |
return s->out_state & 0xFFFF; |
1186 |
case MP_GPIO_OUT_HI:
|
1187 |
return s->out_state >> 16; |
1188 |
|
1189 |
case MP_GPIO_IN_LO:
|
1190 |
return s->in_state & 0xFFFF; |
1191 |
case MP_GPIO_IN_HI:
|
1192 |
return s->in_state >> 16; |
1193 |
|
1194 |
case MP_GPIO_IER_LO:
|
1195 |
return s->ier & 0xFFFF; |
1196 |
case MP_GPIO_IER_HI:
|
1197 |
return s->ier >> 16; |
1198 |
|
1199 |
case MP_GPIO_IMR_LO:
|
1200 |
return s->imr & 0xFFFF; |
1201 |
case MP_GPIO_IMR_HI:
|
1202 |
return s->imr >> 16; |
1203 |
|
1204 |
case MP_GPIO_ISR_LO:
|
1205 |
return s->isr & 0xFFFF; |
1206 |
case MP_GPIO_ISR_HI:
|
1207 |
return s->isr >> 16; |
1208 |
|
1209 |
default:
|
1210 |
return 0; |
1211 |
} |
1212 |
} |
1213 |
|
1214 |
static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
1215 |
uint32_t value) |
1216 |
{ |
1217 |
musicpal_gpio_state *s = opaque; |
1218 |
switch (offset) {
|
1219 |
case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1220 |
s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
1221 |
(value & MP_OE_LCD_BRIGHTNESS); |
1222 |
musicpal_gpio_brightness_update(s); |
1223 |
break;
|
1224 |
|
1225 |
case MP_GPIO_OUT_LO:
|
1226 |
s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
1227 |
break;
|
1228 |
case MP_GPIO_OUT_HI:
|
1229 |
s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1230 |
s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
|
1231 |
(s->out_state & MP_GPIO_LCD_BRIGHTNESS); |
1232 |
musicpal_gpio_brightness_update(s); |
1233 |
qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1234 |
qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); |
1235 |
break;
|
1236 |
|
1237 |
case MP_GPIO_IER_LO:
|
1238 |
s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); |
1239 |
break;
|
1240 |
case MP_GPIO_IER_HI:
|
1241 |
s->ier = (s->ier & 0xFFFF) | (value << 16); |
1242 |
break;
|
1243 |
|
1244 |
case MP_GPIO_IMR_LO:
|
1245 |
s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); |
1246 |
break;
|
1247 |
case MP_GPIO_IMR_HI:
|
1248 |
s->imr = (s->imr & 0xFFFF) | (value << 16); |
1249 |
break;
|
1250 |
} |
1251 |
} |
1252 |
|
1253 |
static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = { |
1254 |
musicpal_gpio_read, |
1255 |
musicpal_gpio_read, |
1256 |
musicpal_gpio_read, |
1257 |
}; |
1258 |
|
1259 |
static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = { |
1260 |
musicpal_gpio_write, |
1261 |
musicpal_gpio_write, |
1262 |
musicpal_gpio_write, |
1263 |
}; |
1264 |
|
1265 |
static void musicpal_gpio_reset(DeviceState *d) |
1266 |
{ |
1267 |
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, |
1268 |
sysbus_from_qdev(d)); |
1269 |
|
1270 |
s->lcd_brightness = 0;
|
1271 |
s->out_state = 0;
|
1272 |
s->in_state = 0xffffffff;
|
1273 |
s->ier = 0;
|
1274 |
s->imr = 0;
|
1275 |
s->isr = 0;
|
1276 |
} |
1277 |
|
1278 |
static int musicpal_gpio_init(SysBusDevice *dev) |
1279 |
{ |
1280 |
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev); |
1281 |
int iomemtype;
|
1282 |
|
1283 |
sysbus_init_irq(dev, &s->irq); |
1284 |
|
1285 |
iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, |
1286 |
musicpal_gpio_writefn, s); |
1287 |
sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); |
1288 |
|
1289 |
musicpal_gpio_reset(&dev->qdev); |
1290 |
|
1291 |
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1292 |
|
1293 |
qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
|
1294 |
|
1295 |
return 0; |
1296 |
} |
1297 |
|
1298 |
static const VMStateDescription musicpal_gpio_vmsd = { |
1299 |
.name = "musicpal_gpio",
|
1300 |
.version_id = 1,
|
1301 |
.minimum_version_id = 1,
|
1302 |
.minimum_version_id_old = 1,
|
1303 |
.fields = (VMStateField[]) { |
1304 |
VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), |
1305 |
VMSTATE_UINT32(out_state, musicpal_gpio_state), |
1306 |
VMSTATE_UINT32(in_state, musicpal_gpio_state), |
1307 |
VMSTATE_UINT32(ier, musicpal_gpio_state), |
1308 |
VMSTATE_UINT32(imr, musicpal_gpio_state), |
1309 |
VMSTATE_UINT32(isr, musicpal_gpio_state), |
1310 |
VMSTATE_END_OF_LIST() |
1311 |
} |
1312 |
}; |
1313 |
|
1314 |
static SysBusDeviceInfo musicpal_gpio_info = {
|
1315 |
.init = musicpal_gpio_init, |
1316 |
.qdev.name = "musicpal_gpio",
|
1317 |
.qdev.size = sizeof(musicpal_gpio_state),
|
1318 |
.qdev.reset = musicpal_gpio_reset, |
1319 |
.qdev.vmsd = &musicpal_gpio_vmsd, |
1320 |
}; |
1321 |
|
1322 |
/* Keyboard codes & masks */
|
1323 |
#define KEY_RELEASED 0x80 |
1324 |
#define KEY_CODE 0x7f |
1325 |
|
1326 |
#define KEYCODE_TAB 0x0f |
1327 |
#define KEYCODE_ENTER 0x1c |
1328 |
#define KEYCODE_F 0x21 |
1329 |
#define KEYCODE_M 0x32 |
1330 |
|
1331 |
#define KEYCODE_EXTENDED 0xe0 |
1332 |
#define KEYCODE_UP 0x48 |
1333 |
#define KEYCODE_DOWN 0x50 |
1334 |
#define KEYCODE_LEFT 0x4b |
1335 |
#define KEYCODE_RIGHT 0x4d |
1336 |
|
1337 |
#define MP_KEY_WHEEL_VOL (1 << 0) |
1338 |
#define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1339 |
#define MP_KEY_WHEEL_NAV (1 << 2) |
1340 |
#define MP_KEY_WHEEL_NAV_INV (1 << 3) |
1341 |
#define MP_KEY_BTN_FAVORITS (1 << 4) |
1342 |
#define MP_KEY_BTN_MENU (1 << 5) |
1343 |
#define MP_KEY_BTN_VOLUME (1 << 6) |
1344 |
#define MP_KEY_BTN_NAVIGATION (1 << 7) |
1345 |
|
1346 |
typedef struct musicpal_key_state { |
1347 |
SysBusDevice busdev; |
1348 |
uint32_t kbd_extended; |
1349 |
uint32_t pressed_keys; |
1350 |
qemu_irq out[8];
|
1351 |
} musicpal_key_state; |
1352 |
|
1353 |
static void musicpal_key_event(void *opaque, int keycode) |
1354 |
{ |
1355 |
musicpal_key_state *s = opaque; |
1356 |
uint32_t event = 0;
|
1357 |
int i;
|
1358 |
|
1359 |
if (keycode == KEYCODE_EXTENDED) {
|
1360 |
s->kbd_extended = 1;
|
1361 |
return;
|
1362 |
} |
1363 |
|
1364 |
if (s->kbd_extended) {
|
1365 |
switch (keycode & KEY_CODE) {
|
1366 |
case KEYCODE_UP:
|
1367 |
event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
1368 |
break;
|
1369 |
|
1370 |
case KEYCODE_DOWN:
|
1371 |
event = MP_KEY_WHEEL_NAV; |
1372 |
break;
|
1373 |
|
1374 |
case KEYCODE_LEFT:
|
1375 |
event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
1376 |
break;
|
1377 |
|
1378 |
case KEYCODE_RIGHT:
|
1379 |
event = MP_KEY_WHEEL_VOL; |
1380 |
break;
|
1381 |
} |
1382 |
} else {
|
1383 |
switch (keycode & KEY_CODE) {
|
1384 |
case KEYCODE_F:
|
1385 |
event = MP_KEY_BTN_FAVORITS; |
1386 |
break;
|
1387 |
|
1388 |
case KEYCODE_TAB:
|
1389 |
event = MP_KEY_BTN_VOLUME; |
1390 |
break;
|
1391 |
|
1392 |
case KEYCODE_ENTER:
|
1393 |
event = MP_KEY_BTN_NAVIGATION; |
1394 |
break;
|
1395 |
|
1396 |
case KEYCODE_M:
|
1397 |
event = MP_KEY_BTN_MENU; |
1398 |
break;
|
1399 |
} |
1400 |
/* Do not repeat already pressed buttons */
|
1401 |
if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1402 |
event = 0;
|
1403 |
} |
1404 |
} |
1405 |
|
1406 |
if (event) {
|
1407 |
/* Raise GPIO pin first if repeating a key */
|
1408 |
if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1409 |
for (i = 0; i <= 7; i++) { |
1410 |
if (event & (1 << i)) { |
1411 |
qemu_set_irq(s->out[i], 1);
|
1412 |
} |
1413 |
} |
1414 |
} |
1415 |
for (i = 0; i <= 7; i++) { |
1416 |
if (event & (1 << i)) { |
1417 |
qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); |
1418 |
} |
1419 |
} |
1420 |
if (keycode & KEY_RELEASED) {
|
1421 |
s->pressed_keys &= ~event; |
1422 |
} else {
|
1423 |
s->pressed_keys |= event; |
1424 |
} |
1425 |
} |
1426 |
|
1427 |
s->kbd_extended = 0;
|
1428 |
} |
1429 |
|
1430 |
static int musicpal_key_init(SysBusDevice *dev) |
1431 |
{ |
1432 |
musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev); |
1433 |
|
1434 |
sysbus_init_mmio(dev, 0x0, 0); |
1435 |
|
1436 |
s->kbd_extended = 0;
|
1437 |
s->pressed_keys = 0;
|
1438 |
|
1439 |
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1440 |
|
1441 |
qemu_add_kbd_event_handler(musicpal_key_event, s); |
1442 |
|
1443 |
return 0; |
1444 |
} |
1445 |
|
1446 |
static const VMStateDescription musicpal_key_vmsd = { |
1447 |
.name = "musicpal_key",
|
1448 |
.version_id = 1,
|
1449 |
.minimum_version_id = 1,
|
1450 |
.minimum_version_id_old = 1,
|
1451 |
.fields = (VMStateField[]) { |
1452 |
VMSTATE_UINT32(kbd_extended, musicpal_key_state), |
1453 |
VMSTATE_UINT32(pressed_keys, musicpal_key_state), |
1454 |
VMSTATE_END_OF_LIST() |
1455 |
} |
1456 |
}; |
1457 |
|
1458 |
static SysBusDeviceInfo musicpal_key_info = {
|
1459 |
.init = musicpal_key_init, |
1460 |
.qdev.name = "musicpal_key",
|
1461 |
.qdev.size = sizeof(musicpal_key_state),
|
1462 |
.qdev.vmsd = &musicpal_key_vmsd, |
1463 |
}; |
1464 |
|
1465 |
static struct arm_boot_info musicpal_binfo = { |
1466 |
.loader_start = 0x0,
|
1467 |
.board_id = 0x20e,
|
1468 |
}; |
1469 |
|
1470 |
static void musicpal_init(ram_addr_t ram_size, |
1471 |
const char *boot_device, |
1472 |
const char *kernel_filename, const char *kernel_cmdline, |
1473 |
const char *initrd_filename, const char *cpu_model) |
1474 |
{ |
1475 |
CPUState *env; |
1476 |
qemu_irq *cpu_pic; |
1477 |
qemu_irq pic[32];
|
1478 |
DeviceState *dev; |
1479 |
DeviceState *i2c_dev; |
1480 |
DeviceState *lcd_dev; |
1481 |
DeviceState *key_dev; |
1482 |
#ifdef HAS_AUDIO
|
1483 |
DeviceState *wm8750_dev; |
1484 |
SysBusDevice *s; |
1485 |
#endif
|
1486 |
i2c_bus *i2c; |
1487 |
int i;
|
1488 |
unsigned long flash_size; |
1489 |
DriveInfo *dinfo; |
1490 |
ram_addr_t sram_off; |
1491 |
|
1492 |
if (!cpu_model) {
|
1493 |
cpu_model = "arm926";
|
1494 |
} |
1495 |
env = cpu_init(cpu_model); |
1496 |
if (!env) {
|
1497 |
fprintf(stderr, "Unable to find CPU definition\n");
|
1498 |
exit(1);
|
1499 |
} |
1500 |
cpu_pic = arm_pic_init_cpu(env); |
1501 |
|
1502 |
/* For now we use a fixed - the original - RAM size */
|
1503 |
cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
|
1504 |
qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); |
1505 |
|
1506 |
sram_off = qemu_ram_alloc(MP_SRAM_SIZE); |
1507 |
cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); |
1508 |
|
1509 |
dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
|
1510 |
cpu_pic[ARM_PIC_CPU_IRQ]); |
1511 |
for (i = 0; i < 32; i++) { |
1512 |
pic[i] = qdev_get_gpio_in(dev, i); |
1513 |
} |
1514 |
sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
|
1515 |
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
1516 |
pic[MP_TIMER4_IRQ], NULL);
|
1517 |
|
1518 |
if (serial_hds[0]) { |
1519 |
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1520 |
serial_hds[0], 1); |
1521 |
} |
1522 |
if (serial_hds[1]) { |
1523 |
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1524 |
serial_hds[1], 1); |
1525 |
} |
1526 |
|
1527 |
/* Register flash */
|
1528 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
1529 |
if (dinfo) {
|
1530 |
flash_size = bdrv_getlength(dinfo->bdrv); |
1531 |
if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1532 |
flash_size != 32*1024*1024) { |
1533 |
fprintf(stderr, "Invalid flash image size\n");
|
1534 |
exit(1);
|
1535 |
} |
1536 |
|
1537 |
/*
|
1538 |
* The original U-Boot accesses the flash at 0xFE000000 instead of
|
1539 |
* 0xFF800000 (if there is 8 MB flash). So remap flash access if the
|
1540 |
* image is smaller than 32 MB.
|
1541 |
*/
|
1542 |
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
|
1543 |
dinfo->bdrv, 0x10000,
|
1544 |
(flash_size + 0xffff) >> 16, |
1545 |
MP_FLASH_SIZE_MAX / flash_size, |
1546 |
2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1547 |
0x5555, 0x2AAA); |
1548 |
} |
1549 |
sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); |
1550 |
|
1551 |
qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1552 |
dev = qdev_create(NULL, "mv88w8618_eth"); |
1553 |
dev->nd = &nd_table[0];
|
1554 |
qdev_init_nofail(dev); |
1555 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
|
1556 |
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
|
1557 |
|
1558 |
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
1559 |
|
1560 |
musicpal_misc_init(); |
1561 |
|
1562 |
dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
|
1563 |
i2c_dev = sysbus_create_simple("bitbang_i2c", 0, NULL); |
1564 |
i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
|
1565 |
|
1566 |
lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL); |
1567 |
key_dev = sysbus_create_simple("musicpal_key", 0, NULL); |
1568 |
|
1569 |
/* I2C read data */
|
1570 |
qdev_connect_gpio_out(i2c_dev, 0,
|
1571 |
qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); |
1572 |
/* I2C data */
|
1573 |
qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); |
1574 |
/* I2C clock */
|
1575 |
qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); |
1576 |
|
1577 |
for (i = 0; i < 3; i++) { |
1578 |
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
1579 |
} |
1580 |
for (i = 0; i < 4; i++) { |
1581 |
qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
|
1582 |
} |
1583 |
for (i = 4; i < 8; i++) { |
1584 |
qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
|
1585 |
} |
1586 |
|
1587 |
#ifdef HAS_AUDIO
|
1588 |
wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
|
1589 |
dev = qdev_create(NULL, "mv88w8618_audio"); |
1590 |
s = sysbus_from_qdev(dev); |
1591 |
qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
|
1592 |
qdev_init_nofail(dev); |
1593 |
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
|
1594 |
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
|
1595 |
#endif
|
1596 |
|
1597 |
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1598 |
musicpal_binfo.kernel_filename = kernel_filename; |
1599 |
musicpal_binfo.kernel_cmdline = kernel_cmdline; |
1600 |
musicpal_binfo.initrd_filename = initrd_filename; |
1601 |
arm_load_kernel(env, &musicpal_binfo); |
1602 |
} |
1603 |
|
1604 |
static QEMUMachine musicpal_machine = {
|
1605 |
.name = "musicpal",
|
1606 |
.desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
|
1607 |
.init = musicpal_init, |
1608 |
}; |
1609 |
|
1610 |
static void musicpal_machine_init(void) |
1611 |
{ |
1612 |
qemu_register_machine(&musicpal_machine); |
1613 |
} |
1614 |
|
1615 |
machine_init(musicpal_machine_init); |
1616 |
|
1617 |
static void musicpal_register_devices(void) |
1618 |
{ |
1619 |
sysbus_register_withprop(&mv88w8618_pic_info); |
1620 |
sysbus_register_withprop(&mv88w8618_pit_info); |
1621 |
sysbus_register_withprop(&mv88w8618_flashcfg_info); |
1622 |
sysbus_register_withprop(&mv88w8618_eth_info); |
1623 |
sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice), |
1624 |
mv88w8618_wlan_init); |
1625 |
sysbus_register_withprop(&musicpal_lcd_info); |
1626 |
sysbus_register_withprop(&musicpal_gpio_info); |
1627 |
sysbus_register_withprop(&musicpal_key_info); |
1628 |
} |
1629 |
|
1630 |
device_init(musicpal_register_devices) |