Revision d8ee0384
| b/hw/kvm/ioapic.c | ||
|---|---|---|
| 15 | 15 |
#include "hw/apic_internal.h" |
| 16 | 16 |
#include "kvm.h" |
| 17 | 17 |
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/* PC Utility function */ |
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void kvm_pc_setup_irq_routing(bool pci_enabled) |
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{
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KVMState *s = kvm_state; |
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int i; |
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if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
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for (i = 0; i < 8; ++i) {
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if (i == 2) {
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continue; |
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} |
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i); |
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} |
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for (i = 8; i < 16; ++i) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8); |
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} |
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if (pci_enabled) {
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for (i = 0; i < 24; ++i) {
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if (i == 0) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2); |
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} else if (i != 2) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i); |
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} |
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} |
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} |
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} |
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} |
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void kvm_pc_gsi_handler(void *opaque, int n, int level) |
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{
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GSIState *s = opaque; |
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if (n < ISA_NUM_IRQS) {
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/* Kernel will forward to both PIC and IOAPIC */ |
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qemu_set_irq(s->i8259_irq[n], level); |
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} else {
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qemu_set_irq(s->ioapic_irq[n], level); |
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} |
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} |
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typedef struct KVMIOAPICState KVMIOAPICState; |
| 19 | 59 |
|
| 20 | 60 |
struct KVMIOAPICState {
|
| b/hw/pc_piix.c | ||
|---|---|---|
| 54 | 54 |
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
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| 55 | 55 |
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
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static void kvm_piix3_setup_irq_routing(bool pci_enabled) |
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{
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#ifdef CONFIG_KVM |
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KVMState *s = kvm_state; |
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int i; |
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if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
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for (i = 0; i < 8; ++i) {
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if (i == 2) {
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continue; |
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} |
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i); |
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} |
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for (i = 8; i < 16; ++i) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8); |
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} |
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if (pci_enabled) {
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for (i = 0; i < 24; ++i) {
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if (i == 0) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2); |
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} else if (i != 2) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i); |
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} |
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} |
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} |
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} |
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#endif /* CONFIG_KVM */ |
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} |
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static void kvm_piix3_gsi_handler(void *opaque, int n, int level) |
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{
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GSIState *s = opaque; |
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if (n < ISA_NUM_IRQS) {
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/* Kernel will forward to both PIC and IOAPIC */ |
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qemu_set_irq(s->i8259_irq[n], level); |
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} else {
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qemu_set_irq(s->ioapic_irq[n], level); |
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} |
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} |
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| 98 | 57 |
/* PC hardware initialisation */ |
| 99 | 58 |
static void pc_init1(MemoryRegion *system_memory, |
| 100 | 59 |
MemoryRegion *system_io, |
| ... | ... | |
| 160 | 119 |
|
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gsi_state = g_malloc0(sizeof(*gsi_state)); |
| 162 | 121 |
if (kvm_irqchip_in_kernel()) {
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kvm_piix3_setup_irq_routing(pci_enabled);
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gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
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kvm_pc_setup_irq_routing(pci_enabled);
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gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
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GSI_NUM_PINS); |
| 166 | 125 |
} else {
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gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); |
| b/kvm.h | ||
|---|---|---|
| 275 | 275 |
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| 276 | 276 |
int kvm_irqchip_add_irqfd_notifier(KVMState *s, EventNotifier *n, int virq); |
| 277 | 277 |
int kvm_irqchip_remove_irqfd_notifier(KVMState *s, EventNotifier *n, int virq); |
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void kvm_pc_gsi_handler(void *opaque, int n, int level); |
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void kvm_pc_setup_irq_routing(bool pci_enabled); |
|
| 278 | 280 |
#endif |
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