root / hw / arm_timer.c @ d92551f2
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1 | 5fafdf24 | ths | /*
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2 | cdbdb648 | pbrook | * ARM PrimeCell Timer modules.
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3 | cdbdb648 | pbrook | *
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4 | cdbdb648 | pbrook | * Copyright (c) 2005-2006 CodeSourcery.
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5 | cdbdb648 | pbrook | * Written by Paul Brook
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6 | cdbdb648 | pbrook | *
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7 | cdbdb648 | pbrook | * This code is licenced under the GPL.
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8 | cdbdb648 | pbrook | */
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9 | cdbdb648 | pbrook | |
10 | 6a824ec3 | Paul Brook | #include "sysbus.h" |
11 | 87ecb68b | pbrook | #include "qemu-timer.h" |
12 | cdbdb648 | pbrook | |
13 | cdbdb648 | pbrook | /* Common timer implementation. */
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14 | cdbdb648 | pbrook | |
15 | cdbdb648 | pbrook | #define TIMER_CTRL_ONESHOT (1 << 0) |
16 | cdbdb648 | pbrook | #define TIMER_CTRL_32BIT (1 << 1) |
17 | cdbdb648 | pbrook | #define TIMER_CTRL_DIV1 (0 << 2) |
18 | cdbdb648 | pbrook | #define TIMER_CTRL_DIV16 (1 << 2) |
19 | cdbdb648 | pbrook | #define TIMER_CTRL_DIV256 (2 << 2) |
20 | cdbdb648 | pbrook | #define TIMER_CTRL_IE (1 << 5) |
21 | cdbdb648 | pbrook | #define TIMER_CTRL_PERIODIC (1 << 6) |
22 | cdbdb648 | pbrook | #define TIMER_CTRL_ENABLE (1 << 7) |
23 | cdbdb648 | pbrook | |
24 | cdbdb648 | pbrook | typedef struct { |
25 | 423f0742 | pbrook | ptimer_state *timer; |
26 | cdbdb648 | pbrook | uint32_t control; |
27 | cdbdb648 | pbrook | uint32_t limit; |
28 | cdbdb648 | pbrook | int freq;
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29 | cdbdb648 | pbrook | int int_level;
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30 | d537cf6c | pbrook | qemu_irq irq; |
31 | cdbdb648 | pbrook | } arm_timer_state; |
32 | cdbdb648 | pbrook | |
33 | cdbdb648 | pbrook | /* Check all active timers, and schedule the next timer interrupt. */
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34 | cdbdb648 | pbrook | |
35 | 423f0742 | pbrook | static void arm_timer_update(arm_timer_state *s) |
36 | cdbdb648 | pbrook | { |
37 | cdbdb648 | pbrook | /* Update interrupts. */
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38 | cdbdb648 | pbrook | if (s->int_level && (s->control & TIMER_CTRL_IE)) {
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39 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
40 | cdbdb648 | pbrook | } else {
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41 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
42 | cdbdb648 | pbrook | } |
43 | cdbdb648 | pbrook | } |
44 | cdbdb648 | pbrook | |
45 | c227f099 | Anthony Liguori | static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset) |
46 | cdbdb648 | pbrook | { |
47 | cdbdb648 | pbrook | arm_timer_state *s = (arm_timer_state *)opaque; |
48 | cdbdb648 | pbrook | |
49 | cdbdb648 | pbrook | switch (offset >> 2) { |
50 | cdbdb648 | pbrook | case 0: /* TimerLoad */ |
51 | cdbdb648 | pbrook | case 6: /* TimerBGLoad */ |
52 | cdbdb648 | pbrook | return s->limit;
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53 | cdbdb648 | pbrook | case 1: /* TimerValue */ |
54 | 423f0742 | pbrook | return ptimer_get_count(s->timer);
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55 | cdbdb648 | pbrook | case 2: /* TimerControl */ |
56 | cdbdb648 | pbrook | return s->control;
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57 | cdbdb648 | pbrook | case 4: /* TimerRIS */ |
58 | cdbdb648 | pbrook | return s->int_level;
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59 | cdbdb648 | pbrook | case 5: /* TimerMIS */ |
60 | cdbdb648 | pbrook | if ((s->control & TIMER_CTRL_IE) == 0) |
61 | cdbdb648 | pbrook | return 0; |
62 | cdbdb648 | pbrook | return s->int_level;
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63 | cdbdb648 | pbrook | default:
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64 | 2ac71179 | Paul Brook | hw_error("arm_timer_read: Bad offset %x\n", (int)offset); |
65 | cdbdb648 | pbrook | return 0; |
66 | cdbdb648 | pbrook | } |
67 | cdbdb648 | pbrook | } |
68 | cdbdb648 | pbrook | |
69 | 423f0742 | pbrook | /* Reset the timer limit after settings have changed. */
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70 | 423f0742 | pbrook | static void arm_timer_recalibrate(arm_timer_state *s, int reload) |
71 | 423f0742 | pbrook | { |
72 | 423f0742 | pbrook | uint32_t limit; |
73 | 423f0742 | pbrook | |
74 | a9cf98d9 | Rabin Vincent | if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { |
75 | 423f0742 | pbrook | /* Free running. */
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76 | 423f0742 | pbrook | if (s->control & TIMER_CTRL_32BIT)
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77 | 423f0742 | pbrook | limit = 0xffffffff;
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78 | 423f0742 | pbrook | else
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79 | 423f0742 | pbrook | limit = 0xffff;
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80 | 423f0742 | pbrook | } else {
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81 | 423f0742 | pbrook | /* Periodic. */
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82 | 423f0742 | pbrook | limit = s->limit; |
83 | 423f0742 | pbrook | } |
84 | 423f0742 | pbrook | ptimer_set_limit(s->timer, limit, reload); |
85 | 423f0742 | pbrook | } |
86 | 423f0742 | pbrook | |
87 | c227f099 | Anthony Liguori | static void arm_timer_write(void *opaque, target_phys_addr_t offset, |
88 | cdbdb648 | pbrook | uint32_t value) |
89 | cdbdb648 | pbrook | { |
90 | cdbdb648 | pbrook | arm_timer_state *s = (arm_timer_state *)opaque; |
91 | 423f0742 | pbrook | int freq;
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92 | cdbdb648 | pbrook | |
93 | cdbdb648 | pbrook | switch (offset >> 2) { |
94 | cdbdb648 | pbrook | case 0: /* TimerLoad */ |
95 | cdbdb648 | pbrook | s->limit = value; |
96 | 423f0742 | pbrook | arm_timer_recalibrate(s, 1);
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97 | cdbdb648 | pbrook | break;
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98 | cdbdb648 | pbrook | case 1: /* TimerValue */ |
99 | cdbdb648 | pbrook | /* ??? Linux seems to want to write to this readonly register.
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100 | cdbdb648 | pbrook | Ignore it. */
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101 | cdbdb648 | pbrook | break;
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102 | cdbdb648 | pbrook | case 2: /* TimerControl */ |
103 | cdbdb648 | pbrook | if (s->control & TIMER_CTRL_ENABLE) {
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104 | cdbdb648 | pbrook | /* Pause the timer if it is running. This may cause some
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105 | cdbdb648 | pbrook | inaccuracy dure to rounding, but avoids a whole lot of other
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106 | cdbdb648 | pbrook | messyness. */
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107 | 423f0742 | pbrook | ptimer_stop(s->timer); |
108 | cdbdb648 | pbrook | } |
109 | cdbdb648 | pbrook | s->control = value; |
110 | 423f0742 | pbrook | freq = s->freq; |
111 | cdbdb648 | pbrook | /* ??? Need to recalculate expiry time after changing divisor. */
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112 | cdbdb648 | pbrook | switch ((value >> 2) & 3) { |
113 | 423f0742 | pbrook | case 1: freq >>= 4; break; |
114 | 423f0742 | pbrook | case 2: freq >>= 8; break; |
115 | cdbdb648 | pbrook | } |
116 | d6759902 | Rabin Vincent | arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); |
117 | 423f0742 | pbrook | ptimer_set_freq(s->timer, freq); |
118 | cdbdb648 | pbrook | if (s->control & TIMER_CTRL_ENABLE) {
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119 | cdbdb648 | pbrook | /* Restart the timer if still enabled. */
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120 | 423f0742 | pbrook | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
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121 | cdbdb648 | pbrook | } |
122 | cdbdb648 | pbrook | break;
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123 | cdbdb648 | pbrook | case 3: /* TimerIntClr */ |
124 | cdbdb648 | pbrook | s->int_level = 0;
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125 | cdbdb648 | pbrook | break;
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126 | cdbdb648 | pbrook | case 6: /* TimerBGLoad */ |
127 | cdbdb648 | pbrook | s->limit = value; |
128 | 423f0742 | pbrook | arm_timer_recalibrate(s, 0);
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129 | cdbdb648 | pbrook | break;
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130 | cdbdb648 | pbrook | default:
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131 | 2ac71179 | Paul Brook | hw_error("arm_timer_write: Bad offset %x\n", (int)offset); |
132 | cdbdb648 | pbrook | } |
133 | 423f0742 | pbrook | arm_timer_update(s); |
134 | cdbdb648 | pbrook | } |
135 | cdbdb648 | pbrook | |
136 | cdbdb648 | pbrook | static void arm_timer_tick(void *opaque) |
137 | cdbdb648 | pbrook | { |
138 | 423f0742 | pbrook | arm_timer_state *s = (arm_timer_state *)opaque; |
139 | 423f0742 | pbrook | s->int_level = 1;
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140 | 423f0742 | pbrook | arm_timer_update(s); |
141 | cdbdb648 | pbrook | } |
142 | cdbdb648 | pbrook | |
143 | eecd33a5 | Juan Quintela | static const VMStateDescription vmstate_arm_timer = { |
144 | eecd33a5 | Juan Quintela | .name = "arm_timer",
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145 | eecd33a5 | Juan Quintela | .version_id = 1,
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146 | eecd33a5 | Juan Quintela | .minimum_version_id = 1,
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147 | eecd33a5 | Juan Quintela | .minimum_version_id_old = 1,
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148 | eecd33a5 | Juan Quintela | .fields = (VMStateField[]) { |
149 | eecd33a5 | Juan Quintela | VMSTATE_UINT32(control, arm_timer_state), |
150 | eecd33a5 | Juan Quintela | VMSTATE_UINT32(limit, arm_timer_state), |
151 | eecd33a5 | Juan Quintela | VMSTATE_INT32(int_level, arm_timer_state), |
152 | eecd33a5 | Juan Quintela | VMSTATE_PTIMER(timer, arm_timer_state), |
153 | eecd33a5 | Juan Quintela | VMSTATE_END_OF_LIST() |
154 | eecd33a5 | Juan Quintela | } |
155 | eecd33a5 | Juan Quintela | }; |
156 | 23e39294 | pbrook | |
157 | 6a824ec3 | Paul Brook | static arm_timer_state *arm_timer_init(uint32_t freq)
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158 | cdbdb648 | pbrook | { |
159 | cdbdb648 | pbrook | arm_timer_state *s; |
160 | 423f0742 | pbrook | QEMUBH *bh; |
161 | cdbdb648 | pbrook | |
162 | cdbdb648 | pbrook | s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
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163 | 423f0742 | pbrook | s->freq = freq; |
164 | cdbdb648 | pbrook | s->control = TIMER_CTRL_IE; |
165 | cdbdb648 | pbrook | |
166 | 423f0742 | pbrook | bh = qemu_bh_new(arm_timer_tick, s); |
167 | 423f0742 | pbrook | s->timer = ptimer_init(bh); |
168 | eecd33a5 | Juan Quintela | vmstate_register(NULL, -1, &vmstate_arm_timer, s); |
169 | cdbdb648 | pbrook | return s;
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170 | cdbdb648 | pbrook | } |
171 | cdbdb648 | pbrook | |
172 | cdbdb648 | pbrook | /* ARM PrimeCell SP804 dual timer module.
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173 | cdbdb648 | pbrook | Docs for this device don't seem to be publicly available. This
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174 | d85fb99b | pbrook | implementation is based on guesswork, the linux kernel sources and the
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175 | cdbdb648 | pbrook | Integrator/CP timer modules. */
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176 | cdbdb648 | pbrook | |
177 | cdbdb648 | pbrook | typedef struct { |
178 | 6a824ec3 | Paul Brook | SysBusDevice busdev; |
179 | 6a824ec3 | Paul Brook | arm_timer_state *timer[2];
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180 | cdbdb648 | pbrook | int level[2]; |
181 | d537cf6c | pbrook | qemu_irq irq; |
182 | cdbdb648 | pbrook | } sp804_state; |
183 | cdbdb648 | pbrook | |
184 | d537cf6c | pbrook | /* Merge the IRQs from the two component devices. */
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185 | cdbdb648 | pbrook | static void sp804_set_irq(void *opaque, int irq, int level) |
186 | cdbdb648 | pbrook | { |
187 | cdbdb648 | pbrook | sp804_state *s = (sp804_state *)opaque; |
188 | cdbdb648 | pbrook | |
189 | cdbdb648 | pbrook | s->level[irq] = level; |
190 | d537cf6c | pbrook | qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
191 | cdbdb648 | pbrook | } |
192 | cdbdb648 | pbrook | |
193 | c227f099 | Anthony Liguori | static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) |
194 | cdbdb648 | pbrook | { |
195 | cdbdb648 | pbrook | sp804_state *s = (sp804_state *)opaque; |
196 | cdbdb648 | pbrook | |
197 | cdbdb648 | pbrook | /* ??? Don't know the PrimeCell ID for this device. */
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198 | cdbdb648 | pbrook | if (offset < 0x20) { |
199 | cdbdb648 | pbrook | return arm_timer_read(s->timer[0], offset); |
200 | cdbdb648 | pbrook | } else {
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201 | cdbdb648 | pbrook | return arm_timer_read(s->timer[1], offset - 0x20); |
202 | cdbdb648 | pbrook | } |
203 | cdbdb648 | pbrook | } |
204 | cdbdb648 | pbrook | |
205 | c227f099 | Anthony Liguori | static void sp804_write(void *opaque, target_phys_addr_t offset, |
206 | cdbdb648 | pbrook | uint32_t value) |
207 | cdbdb648 | pbrook | { |
208 | cdbdb648 | pbrook | sp804_state *s = (sp804_state *)opaque; |
209 | cdbdb648 | pbrook | |
210 | cdbdb648 | pbrook | if (offset < 0x20) { |
211 | cdbdb648 | pbrook | arm_timer_write(s->timer[0], offset, value);
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212 | cdbdb648 | pbrook | } else {
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213 | cdbdb648 | pbrook | arm_timer_write(s->timer[1], offset - 0x20, value); |
214 | cdbdb648 | pbrook | } |
215 | cdbdb648 | pbrook | } |
216 | cdbdb648 | pbrook | |
217 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const sp804_readfn[] = { |
218 | cdbdb648 | pbrook | sp804_read, |
219 | cdbdb648 | pbrook | sp804_read, |
220 | cdbdb648 | pbrook | sp804_read |
221 | cdbdb648 | pbrook | }; |
222 | cdbdb648 | pbrook | |
223 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const sp804_writefn[] = { |
224 | cdbdb648 | pbrook | sp804_write, |
225 | cdbdb648 | pbrook | sp804_write, |
226 | cdbdb648 | pbrook | sp804_write |
227 | cdbdb648 | pbrook | }; |
228 | cdbdb648 | pbrook | |
229 | 23e39294 | pbrook | |
230 | 81986ac4 | Juan Quintela | static const VMStateDescription vmstate_sp804 = { |
231 | 81986ac4 | Juan Quintela | .name = "sp804",
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232 | 81986ac4 | Juan Quintela | .version_id = 1,
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233 | 81986ac4 | Juan Quintela | .minimum_version_id = 1,
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234 | 81986ac4 | Juan Quintela | .minimum_version_id_old = 1,
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235 | 81986ac4 | Juan Quintela | .fields = (VMStateField[]) { |
236 | 81986ac4 | Juan Quintela | VMSTATE_INT32_ARRAY(level, sp804_state, 2),
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237 | 81986ac4 | Juan Quintela | VMSTATE_END_OF_LIST() |
238 | 81986ac4 | Juan Quintela | } |
239 | 81986ac4 | Juan Quintela | }; |
240 | 23e39294 | pbrook | |
241 | 81a322d4 | Gerd Hoffmann | static int sp804_init(SysBusDevice *dev) |
242 | cdbdb648 | pbrook | { |
243 | cdbdb648 | pbrook | int iomemtype;
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244 | 6a824ec3 | Paul Brook | sp804_state *s = FROM_SYSBUS(sp804_state, dev); |
245 | d537cf6c | pbrook | qemu_irq *qi; |
246 | cdbdb648 | pbrook | |
247 | d537cf6c | pbrook | qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
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248 | 6a824ec3 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
249 | cdbdb648 | pbrook | /* ??? The timers are actually configurable between 32kHz and 1MHz, but
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250 | cdbdb648 | pbrook | we don't implement that. */
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251 | 6a824ec3 | Paul Brook | s->timer[0] = arm_timer_init(1000000); |
252 | 6a824ec3 | Paul Brook | s->timer[1] = arm_timer_init(1000000); |
253 | 6a824ec3 | Paul Brook | s->timer[0]->irq = qi[0]; |
254 | 6a824ec3 | Paul Brook | s->timer[1]->irq = qi[1]; |
255 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(sp804_readfn, |
256 | 2507c12a | Alexander Graf | sp804_writefn, s, DEVICE_NATIVE_ENDIAN); |
257 | 6a824ec3 | Paul Brook | sysbus_init_mmio(dev, 0x1000, iomemtype);
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258 | 81986ac4 | Juan Quintela | vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
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259 | 81a322d4 | Gerd Hoffmann | return 0; |
260 | cdbdb648 | pbrook | } |
261 | cdbdb648 | pbrook | |
262 | cdbdb648 | pbrook | |
263 | cdbdb648 | pbrook | /* Integrator/CP timer module. */
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264 | cdbdb648 | pbrook | |
265 | cdbdb648 | pbrook | typedef struct { |
266 | 6a824ec3 | Paul Brook | SysBusDevice busdev; |
267 | 6a824ec3 | Paul Brook | arm_timer_state *timer[3];
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268 | cdbdb648 | pbrook | } icp_pit_state; |
269 | cdbdb648 | pbrook | |
270 | c227f099 | Anthony Liguori | static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) |
271 | cdbdb648 | pbrook | { |
272 | cdbdb648 | pbrook | icp_pit_state *s = (icp_pit_state *)opaque; |
273 | cdbdb648 | pbrook | int n;
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274 | cdbdb648 | pbrook | |
275 | cdbdb648 | pbrook | /* ??? Don't know the PrimeCell ID for this device. */
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276 | cdbdb648 | pbrook | n = offset >> 8;
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277 | 2ac71179 | Paul Brook | if (n > 3) { |
278 | 2ac71179 | Paul Brook | hw_error("sp804_read: Bad timer %d\n", n);
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279 | 2ac71179 | Paul Brook | } |
280 | cdbdb648 | pbrook | |
281 | cdbdb648 | pbrook | return arm_timer_read(s->timer[n], offset & 0xff); |
282 | cdbdb648 | pbrook | } |
283 | cdbdb648 | pbrook | |
284 | c227f099 | Anthony Liguori | static void icp_pit_write(void *opaque, target_phys_addr_t offset, |
285 | cdbdb648 | pbrook | uint32_t value) |
286 | cdbdb648 | pbrook | { |
287 | cdbdb648 | pbrook | icp_pit_state *s = (icp_pit_state *)opaque; |
288 | cdbdb648 | pbrook | int n;
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289 | cdbdb648 | pbrook | |
290 | cdbdb648 | pbrook | n = offset >> 8;
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291 | 2ac71179 | Paul Brook | if (n > 3) { |
292 | 2ac71179 | Paul Brook | hw_error("sp804_write: Bad timer %d\n", n);
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293 | 2ac71179 | Paul Brook | } |
294 | cdbdb648 | pbrook | |
295 | cdbdb648 | pbrook | arm_timer_write(s->timer[n], offset & 0xff, value);
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296 | cdbdb648 | pbrook | } |
297 | cdbdb648 | pbrook | |
298 | cdbdb648 | pbrook | |
299 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const icp_pit_readfn[] = { |
300 | cdbdb648 | pbrook | icp_pit_read, |
301 | cdbdb648 | pbrook | icp_pit_read, |
302 | cdbdb648 | pbrook | icp_pit_read |
303 | cdbdb648 | pbrook | }; |
304 | cdbdb648 | pbrook | |
305 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const icp_pit_writefn[] = { |
306 | cdbdb648 | pbrook | icp_pit_write, |
307 | cdbdb648 | pbrook | icp_pit_write, |
308 | cdbdb648 | pbrook | icp_pit_write |
309 | cdbdb648 | pbrook | }; |
310 | cdbdb648 | pbrook | |
311 | 81a322d4 | Gerd Hoffmann | static int icp_pit_init(SysBusDevice *dev) |
312 | cdbdb648 | pbrook | { |
313 | cdbdb648 | pbrook | int iomemtype;
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314 | 6a824ec3 | Paul Brook | icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev); |
315 | cdbdb648 | pbrook | |
316 | cdbdb648 | pbrook | /* Timer 0 runs at the system clock speed (40MHz). */
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317 | 6a824ec3 | Paul Brook | s->timer[0] = arm_timer_init(40000000); |
318 | cdbdb648 | pbrook | /* The other two timers run at 1MHz. */
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319 | 6a824ec3 | Paul Brook | s->timer[1] = arm_timer_init(1000000); |
320 | 6a824ec3 | Paul Brook | s->timer[2] = arm_timer_init(1000000); |
321 | 6a824ec3 | Paul Brook | |
322 | 6a824ec3 | Paul Brook | sysbus_init_irq(dev, &s->timer[0]->irq);
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323 | 6a824ec3 | Paul Brook | sysbus_init_irq(dev, &s->timer[1]->irq);
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324 | 6a824ec3 | Paul Brook | sysbus_init_irq(dev, &s->timer[2]->irq);
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325 | cdbdb648 | pbrook | |
326 | 1eed09cb | Avi Kivity | iomemtype = cpu_register_io_memory(icp_pit_readfn, |
327 | 2507c12a | Alexander Graf | icp_pit_writefn, s, |
328 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
329 | 6a824ec3 | Paul Brook | sysbus_init_mmio(dev, 0x1000, iomemtype);
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330 | 23e39294 | pbrook | /* This device has no state to save/restore. The component timers will
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331 | 23e39294 | pbrook | save themselves. */
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332 | 81a322d4 | Gerd Hoffmann | return 0; |
333 | cdbdb648 | pbrook | } |
334 | 6a824ec3 | Paul Brook | |
335 | 6a824ec3 | Paul Brook | static void arm_timer_register_devices(void) |
336 | 6a824ec3 | Paul Brook | { |
337 | 6a824ec3 | Paul Brook | sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init); |
338 | 6a824ec3 | Paul Brook | sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init); |
339 | 6a824ec3 | Paul Brook | } |
340 | 6a824ec3 | Paul Brook | |
341 | 6a824ec3 | Paul Brook | device_init(arm_timer_register_devices) |