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1 | 6f7e9aec | bellard | /*
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2 | 67e999be | bellard | * QEMU ESP/NCR53C9x emulation
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3 | 5fafdf24 | ths | *
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4 | 4e9aec74 | pbrook | * Copyright (c) 2005-2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 6f7e9aec | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 6f7e9aec | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 6f7e9aec | bellard | * in the Software without restriction, including without limitation the rights
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9 | 6f7e9aec | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 6f7e9aec | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 6f7e9aec | bellard | * furnished to do so, subject to the following conditions:
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12 | 6f7e9aec | bellard | *
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13 | 6f7e9aec | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 6f7e9aec | bellard | * all copies or substantial portions of the Software.
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15 | 6f7e9aec | bellard | *
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16 | 6f7e9aec | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 6f7e9aec | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 6f7e9aec | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 6f7e9aec | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 6f7e9aec | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 6f7e9aec | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 6f7e9aec | bellard | * THE SOFTWARE.
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23 | 6f7e9aec | bellard | */
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24 | 5d20fa6b | blueswir1 | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "scsi-disk.h" |
27 | 8b17de88 | blueswir1 | #include "scsi.h" |
28 | 6f7e9aec | bellard | |
29 | 6f7e9aec | bellard | /* debug ESP card */
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30 | 2f275b8f | bellard | //#define DEBUG_ESP
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31 | 6f7e9aec | bellard | |
32 | 67e999be | bellard | /*
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33 | 5ad6bb97 | blueswir1 | * On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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34 | 5ad6bb97 | blueswir1 | * also produced as NCR89C100. See
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35 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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36 | 67e999be | bellard | * and
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37 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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38 | 67e999be | bellard | */
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39 | 67e999be | bellard | |
40 | 6f7e9aec | bellard | #ifdef DEBUG_ESP
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41 | 6f7e9aec | bellard | #define DPRINTF(fmt, args...) \
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42 | 6f7e9aec | bellard | do { printf("ESP: " fmt , ##args); } while (0) |
43 | 6f7e9aec | bellard | #else
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44 | 22548760 | blueswir1 | #define DPRINTF(fmt, args...) do {} while (0) |
45 | 6f7e9aec | bellard | #endif
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46 | 6f7e9aec | bellard | |
47 | 8dea1dd4 | blueswir1 | #define ESP_ERROR(fmt, args...) \
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48 | 8dea1dd4 | blueswir1 | do { printf("ESP ERROR: %s: " fmt, __func__ , ##args); } while (0) |
49 | 8dea1dd4 | blueswir1 | |
50 | 5aca8c3b | blueswir1 | #define ESP_REGS 16 |
51 | 8dea1dd4 | blueswir1 | #define TI_BUFSZ 16 |
52 | 67e999be | bellard | |
53 | 4e9aec74 | pbrook | typedef struct ESPState ESPState; |
54 | 6f7e9aec | bellard | |
55 | 4e9aec74 | pbrook | struct ESPState {
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56 | 5d20fa6b | blueswir1 | uint32_t it_shift; |
57 | 70c0de96 | blueswir1 | qemu_irq irq; |
58 | 5aca8c3b | blueswir1 | uint8_t rregs[ESP_REGS]; |
59 | 5aca8c3b | blueswir1 | uint8_t wregs[ESP_REGS]; |
60 | 67e999be | bellard | int32_t ti_size; |
61 | 4f6200f0 | bellard | uint32_t ti_rptr, ti_wptr; |
62 | 4f6200f0 | bellard | uint8_t ti_buf[TI_BUFSZ]; |
63 | 22548760 | blueswir1 | uint32_t sense; |
64 | 22548760 | blueswir1 | uint32_t dma; |
65 | e4bcb14c | ths | SCSIDevice *scsi_dev[ESP_MAX_DEVS]; |
66 | 2e5d83bb | pbrook | SCSIDevice *current_dev; |
67 | 9f149aa9 | pbrook | uint8_t cmdbuf[TI_BUFSZ]; |
68 | 22548760 | blueswir1 | uint32_t cmdlen; |
69 | 22548760 | blueswir1 | uint32_t do_cmd; |
70 | 4d611c9a | pbrook | |
71 | 6787f5fa | pbrook | /* The amount of data left in the current DMA transfer. */
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72 | 4d611c9a | pbrook | uint32_t dma_left; |
73 | 6787f5fa | pbrook | /* The size of the current DMA transfer. Zero if no transfer is in
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74 | 6787f5fa | pbrook | progress. */
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75 | 6787f5fa | pbrook | uint32_t dma_counter; |
76 | a917d384 | pbrook | uint8_t *async_buf; |
77 | 4d611c9a | pbrook | uint32_t async_len; |
78 | 8b17de88 | blueswir1 | |
79 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_read; |
80 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_write; |
81 | 67e999be | bellard | void *dma_opaque;
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82 | 4e9aec74 | pbrook | }; |
83 | 6f7e9aec | bellard | |
84 | 5ad6bb97 | blueswir1 | #define ESP_TCLO 0x0 |
85 | 5ad6bb97 | blueswir1 | #define ESP_TCMID 0x1 |
86 | 5ad6bb97 | blueswir1 | #define ESP_FIFO 0x2 |
87 | 5ad6bb97 | blueswir1 | #define ESP_CMD 0x3 |
88 | 5ad6bb97 | blueswir1 | #define ESP_RSTAT 0x4 |
89 | 5ad6bb97 | blueswir1 | #define ESP_WBUSID 0x4 |
90 | 5ad6bb97 | blueswir1 | #define ESP_RINTR 0x5 |
91 | 5ad6bb97 | blueswir1 | #define ESP_WSEL 0x5 |
92 | 5ad6bb97 | blueswir1 | #define ESP_RSEQ 0x6 |
93 | 5ad6bb97 | blueswir1 | #define ESP_WSYNTP 0x6 |
94 | 5ad6bb97 | blueswir1 | #define ESP_RFLAGS 0x7 |
95 | 5ad6bb97 | blueswir1 | #define ESP_WSYNO 0x7 |
96 | 5ad6bb97 | blueswir1 | #define ESP_CFG1 0x8 |
97 | 5ad6bb97 | blueswir1 | #define ESP_RRES1 0x9 |
98 | 5ad6bb97 | blueswir1 | #define ESP_WCCF 0x9 |
99 | 5ad6bb97 | blueswir1 | #define ESP_RRES2 0xa |
100 | 5ad6bb97 | blueswir1 | #define ESP_WTEST 0xa |
101 | 5ad6bb97 | blueswir1 | #define ESP_CFG2 0xb |
102 | 5ad6bb97 | blueswir1 | #define ESP_CFG3 0xc |
103 | 5ad6bb97 | blueswir1 | #define ESP_RES3 0xd |
104 | 5ad6bb97 | blueswir1 | #define ESP_TCHI 0xe |
105 | 5ad6bb97 | blueswir1 | #define ESP_RES4 0xf |
106 | 5ad6bb97 | blueswir1 | |
107 | 5ad6bb97 | blueswir1 | #define CMD_DMA 0x80 |
108 | 5ad6bb97 | blueswir1 | #define CMD_CMD 0x7f |
109 | 5ad6bb97 | blueswir1 | |
110 | 5ad6bb97 | blueswir1 | #define CMD_NOP 0x00 |
111 | 5ad6bb97 | blueswir1 | #define CMD_FLUSH 0x01 |
112 | 5ad6bb97 | blueswir1 | #define CMD_RESET 0x02 |
113 | 5ad6bb97 | blueswir1 | #define CMD_BUSRESET 0x03 |
114 | 5ad6bb97 | blueswir1 | #define CMD_TI 0x10 |
115 | 5ad6bb97 | blueswir1 | #define CMD_ICCS 0x11 |
116 | 5ad6bb97 | blueswir1 | #define CMD_MSGACC 0x12 |
117 | 5ad6bb97 | blueswir1 | #define CMD_SATN 0x1a |
118 | 5ad6bb97 | blueswir1 | #define CMD_SELATN 0x42 |
119 | 5ad6bb97 | blueswir1 | #define CMD_SELATNS 0x43 |
120 | 5ad6bb97 | blueswir1 | #define CMD_ENSEL 0x44 |
121 | 5ad6bb97 | blueswir1 | |
122 | 2f275b8f | bellard | #define STAT_DO 0x00 |
123 | 2f275b8f | bellard | #define STAT_DI 0x01 |
124 | 2f275b8f | bellard | #define STAT_CD 0x02 |
125 | 2f275b8f | bellard | #define STAT_ST 0x03 |
126 | 8dea1dd4 | blueswir1 | #define STAT_MO 0x06 |
127 | 8dea1dd4 | blueswir1 | #define STAT_MI 0x07 |
128 | 5ad6bb97 | blueswir1 | #define STAT_PIO_MASK 0x06 |
129 | 2f275b8f | bellard | |
130 | 2f275b8f | bellard | #define STAT_TC 0x10 |
131 | 4d611c9a | pbrook | #define STAT_PE 0x20 |
132 | 4d611c9a | pbrook | #define STAT_GE 0x40 |
133 | c73f96fd | blueswir1 | #define STAT_INT 0x80 |
134 | 2f275b8f | bellard | |
135 | 8dea1dd4 | blueswir1 | #define BUSID_DID 0x07 |
136 | 8dea1dd4 | blueswir1 | |
137 | 2f275b8f | bellard | #define INTR_FC 0x08 |
138 | 2f275b8f | bellard | #define INTR_BS 0x10 |
139 | 2f275b8f | bellard | #define INTR_DC 0x20 |
140 | 9e61bde5 | bellard | #define INTR_RST 0x80 |
141 | 2f275b8f | bellard | |
142 | 2f275b8f | bellard | #define SEQ_0 0x0 |
143 | 2f275b8f | bellard | #define SEQ_CD 0x4 |
144 | 2f275b8f | bellard | |
145 | 5ad6bb97 | blueswir1 | #define CFG1_RESREPT 0x40 |
146 | 5ad6bb97 | blueswir1 | |
147 | 5ad6bb97 | blueswir1 | #define TCHI_FAS100A 0x4 |
148 | 5ad6bb97 | blueswir1 | |
149 | c73f96fd | blueswir1 | static void esp_raise_irq(ESPState *s) |
150 | c73f96fd | blueswir1 | { |
151 | c73f96fd | blueswir1 | if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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152 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_INT; |
153 | c73f96fd | blueswir1 | qemu_irq_raise(s->irq); |
154 | c73f96fd | blueswir1 | } |
155 | c73f96fd | blueswir1 | } |
156 | c73f96fd | blueswir1 | |
157 | c73f96fd | blueswir1 | static void esp_lower_irq(ESPState *s) |
158 | c73f96fd | blueswir1 | { |
159 | c73f96fd | blueswir1 | if (s->rregs[ESP_RSTAT] & STAT_INT) {
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160 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_INT; |
161 | c73f96fd | blueswir1 | qemu_irq_lower(s->irq); |
162 | c73f96fd | blueswir1 | } |
163 | c73f96fd | blueswir1 | } |
164 | c73f96fd | blueswir1 | |
165 | 22548760 | blueswir1 | static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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166 | 2f275b8f | bellard | { |
167 | a917d384 | pbrook | uint32_t dmalen; |
168 | 2f275b8f | bellard | int target;
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169 | 2f275b8f | bellard | |
170 | 8dea1dd4 | blueswir1 | target = s->wregs[ESP_WBUSID] & BUSID_DID; |
171 | 4f6200f0 | bellard | if (s->dma) {
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172 | fc4d65da | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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173 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, buf, dmalen); |
174 | 4f6200f0 | bellard | } else {
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175 | fc4d65da | blueswir1 | dmalen = s->ti_size; |
176 | fc4d65da | blueswir1 | memcpy(buf, s->ti_buf, dmalen); |
177 | f930d07e | blueswir1 | buf[0] = 0; |
178 | 4f6200f0 | bellard | } |
179 | fc4d65da | blueswir1 | DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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180 | 2e5d83bb | pbrook | |
181 | 2f275b8f | bellard | s->ti_size = 0;
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182 | 4f6200f0 | bellard | s->ti_rptr = 0;
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183 | 4f6200f0 | bellard | s->ti_wptr = 0;
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184 | 2f275b8f | bellard | |
185 | a917d384 | pbrook | if (s->current_dev) {
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186 | a917d384 | pbrook | /* Started a new command before the old one finished. Cancel it. */
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187 | 8ccc2ace | ths | s->current_dev->cancel_io(s->current_dev, 0);
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188 | a917d384 | pbrook | s->async_len = 0;
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189 | a917d384 | pbrook | } |
190 | a917d384 | pbrook | |
191 | e4bcb14c | ths | if (target >= ESP_MAX_DEVS || !s->scsi_dev[target]) {
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192 | 2e5d83bb | pbrook | // No such drive
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193 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = 0;
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194 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
195 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_0; |
196 | c73f96fd | blueswir1 | esp_raise_irq(s); |
197 | f930d07e | blueswir1 | return 0; |
198 | 2f275b8f | bellard | } |
199 | 2e5d83bb | pbrook | s->current_dev = s->scsi_dev[target]; |
200 | 9f149aa9 | pbrook | return dmalen;
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201 | 9f149aa9 | pbrook | } |
202 | 9f149aa9 | pbrook | |
203 | 9f149aa9 | pbrook | static void do_cmd(ESPState *s, uint8_t *buf) |
204 | 9f149aa9 | pbrook | { |
205 | 9f149aa9 | pbrook | int32_t datalen; |
206 | 9f149aa9 | pbrook | int lun;
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207 | 9f149aa9 | pbrook | |
208 | 9f149aa9 | pbrook | DPRINTF("do_cmd: busid 0x%x\n", buf[0]); |
209 | 9f149aa9 | pbrook | lun = buf[0] & 7; |
210 | 8ccc2ace | ths | datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun); |
211 | 67e999be | bellard | s->ti_size = datalen; |
212 | 67e999be | bellard | if (datalen != 0) { |
213 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC; |
214 | a917d384 | pbrook | s->dma_left = 0;
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215 | 6787f5fa | pbrook | s->dma_counter = 0;
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216 | 2e5d83bb | pbrook | if (datalen > 0) { |
217 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DI; |
218 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, 0);
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219 | 2e5d83bb | pbrook | } else {
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220 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_DO; |
221 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, 0);
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222 | b9788fc4 | bellard | } |
223 | 2f275b8f | bellard | } |
224 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
225 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
226 | c73f96fd | blueswir1 | esp_raise_irq(s); |
227 | 2f275b8f | bellard | } |
228 | 2f275b8f | bellard | |
229 | 9f149aa9 | pbrook | static void handle_satn(ESPState *s) |
230 | 9f149aa9 | pbrook | { |
231 | 9f149aa9 | pbrook | uint8_t buf[32];
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232 | 9f149aa9 | pbrook | int len;
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233 | 9f149aa9 | pbrook | |
234 | 9f149aa9 | pbrook | len = get_cmd(s, buf); |
235 | 9f149aa9 | pbrook | if (len)
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236 | 9f149aa9 | pbrook | do_cmd(s, buf); |
237 | 9f149aa9 | pbrook | } |
238 | 9f149aa9 | pbrook | |
239 | 9f149aa9 | pbrook | static void handle_satn_stop(ESPState *s) |
240 | 9f149aa9 | pbrook | { |
241 | 9f149aa9 | pbrook | s->cmdlen = get_cmd(s, s->cmdbuf); |
242 | 9f149aa9 | pbrook | if (s->cmdlen) {
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243 | 9f149aa9 | pbrook | DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
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244 | 9f149aa9 | pbrook | s->do_cmd = 1;
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245 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD; |
246 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
247 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
248 | c73f96fd | blueswir1 | esp_raise_irq(s); |
249 | 9f149aa9 | pbrook | } |
250 | 9f149aa9 | pbrook | } |
251 | 9f149aa9 | pbrook | |
252 | 0fc5c15a | pbrook | static void write_response(ESPState *s) |
253 | 2f275b8f | bellard | { |
254 | 0fc5c15a | pbrook | DPRINTF("Transfer status (sense=%d)\n", s->sense);
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255 | 0fc5c15a | pbrook | s->ti_buf[0] = s->sense;
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256 | 0fc5c15a | pbrook | s->ti_buf[1] = 0; |
257 | 4f6200f0 | bellard | if (s->dma) {
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258 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
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259 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST; |
260 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS | INTR_FC; |
261 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = SEQ_CD; |
262 | 4f6200f0 | bellard | } else {
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263 | f930d07e | blueswir1 | s->ti_size = 2;
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264 | f930d07e | blueswir1 | s->ti_rptr = 0;
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265 | f930d07e | blueswir1 | s->ti_wptr = 0;
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266 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 2;
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267 | 4f6200f0 | bellard | } |
268 | c73f96fd | blueswir1 | esp_raise_irq(s); |
269 | 2f275b8f | bellard | } |
270 | 4f6200f0 | bellard | |
271 | a917d384 | pbrook | static void esp_dma_done(ESPState *s) |
272 | a917d384 | pbrook | { |
273 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_TC; |
274 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_BS; |
275 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
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276 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RFLAGS] = 0;
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277 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = 0;
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278 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = 0;
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279 | c73f96fd | blueswir1 | esp_raise_irq(s); |
280 | a917d384 | pbrook | } |
281 | a917d384 | pbrook | |
282 | 4d611c9a | pbrook | static void esp_do_dma(ESPState *s) |
283 | 4d611c9a | pbrook | { |
284 | 67e999be | bellard | uint32_t len; |
285 | 4d611c9a | pbrook | int to_device;
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286 | a917d384 | pbrook | |
287 | 67e999be | bellard | to_device = (s->ti_size < 0);
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288 | a917d384 | pbrook | len = s->dma_left; |
289 | 4d611c9a | pbrook | if (s->do_cmd) {
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290 | 4d611c9a | pbrook | DPRINTF("command len %d + %d\n", s->cmdlen, len);
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291 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len); |
292 | 4d611c9a | pbrook | s->ti_size = 0;
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293 | 4d611c9a | pbrook | s->cmdlen = 0;
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294 | 4d611c9a | pbrook | s->do_cmd = 0;
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295 | 4d611c9a | pbrook | do_cmd(s, s->cmdbuf); |
296 | 4d611c9a | pbrook | return;
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297 | a917d384 | pbrook | } |
298 | a917d384 | pbrook | if (s->async_len == 0) { |
299 | a917d384 | pbrook | /* Defer until data is available. */
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300 | a917d384 | pbrook | return;
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301 | a917d384 | pbrook | } |
302 | a917d384 | pbrook | if (len > s->async_len) {
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303 | a917d384 | pbrook | len = s->async_len; |
304 | a917d384 | pbrook | } |
305 | a917d384 | pbrook | if (to_device) {
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306 | 8b17de88 | blueswir1 | s->dma_memory_read(s->dma_opaque, s->async_buf, len); |
307 | 4d611c9a | pbrook | } else {
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308 | 8b17de88 | blueswir1 | s->dma_memory_write(s->dma_opaque, s->async_buf, len); |
309 | a917d384 | pbrook | } |
310 | a917d384 | pbrook | s->dma_left -= len; |
311 | a917d384 | pbrook | s->async_buf += len; |
312 | a917d384 | pbrook | s->async_len -= len; |
313 | 6787f5fa | pbrook | if (to_device)
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314 | 6787f5fa | pbrook | s->ti_size += len; |
315 | 6787f5fa | pbrook | else
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316 | 6787f5fa | pbrook | s->ti_size -= len; |
317 | a917d384 | pbrook | if (s->async_len == 0) { |
318 | 4d611c9a | pbrook | if (to_device) {
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319 | 67e999be | bellard | // ti_size is negative
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320 | 8ccc2ace | ths | s->current_dev->write_data(s->current_dev, 0);
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321 | 4d611c9a | pbrook | } else {
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322 | 8ccc2ace | ths | s->current_dev->read_data(s->current_dev, 0);
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323 | 6787f5fa | pbrook | /* If there is still data to be read from the device then
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324 | 8dea1dd4 | blueswir1 | complete the DMA operation immediately. Otherwise defer
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325 | 6787f5fa | pbrook | until the scsi layer has completed. */
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326 | 6787f5fa | pbrook | if (s->dma_left == 0 && s->ti_size > 0) { |
327 | 6787f5fa | pbrook | esp_dma_done(s); |
328 | 6787f5fa | pbrook | } |
329 | 4d611c9a | pbrook | } |
330 | 6787f5fa | pbrook | } else {
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331 | 6787f5fa | pbrook | /* Partially filled a scsi buffer. Complete immediately. */
|
332 | a917d384 | pbrook | esp_dma_done(s); |
333 | a917d384 | pbrook | } |
334 | 4d611c9a | pbrook | } |
335 | 4d611c9a | pbrook | |
336 | a917d384 | pbrook | static void esp_command_complete(void *opaque, int reason, uint32_t tag, |
337 | a917d384 | pbrook | uint32_t arg) |
338 | 2e5d83bb | pbrook | { |
339 | 2e5d83bb | pbrook | ESPState *s = (ESPState *)opaque; |
340 | 2e5d83bb | pbrook | |
341 | 4d611c9a | pbrook | if (reason == SCSI_REASON_DONE) {
|
342 | 4d611c9a | pbrook | DPRINTF("SCSI Command complete\n");
|
343 | 4d611c9a | pbrook | if (s->ti_size != 0) |
344 | 4d611c9a | pbrook | DPRINTF("SCSI command completed unexpectedly\n");
|
345 | 4d611c9a | pbrook | s->ti_size = 0;
|
346 | a917d384 | pbrook | s->dma_left = 0;
|
347 | a917d384 | pbrook | s->async_len = 0;
|
348 | a917d384 | pbrook | if (arg)
|
349 | 4d611c9a | pbrook | DPRINTF("Command failed\n");
|
350 | a917d384 | pbrook | s->sense = arg; |
351 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] = STAT_ST; |
352 | a917d384 | pbrook | esp_dma_done(s); |
353 | a917d384 | pbrook | s->current_dev = NULL;
|
354 | 4d611c9a | pbrook | } else {
|
355 | 4d611c9a | pbrook | DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
|
356 | a917d384 | pbrook | s->async_len = arg; |
357 | 8ccc2ace | ths | s->async_buf = s->current_dev->get_buf(s->current_dev, 0);
|
358 | 6787f5fa | pbrook | if (s->dma_left) {
|
359 | a917d384 | pbrook | esp_do_dma(s); |
360 | 6787f5fa | pbrook | } else if (s->dma_counter != 0 && s->ti_size <= 0) { |
361 | 6787f5fa | pbrook | /* If this was the last part of a DMA transfer then the
|
362 | 6787f5fa | pbrook | completion interrupt is deferred to here. */
|
363 | 6787f5fa | pbrook | esp_dma_done(s); |
364 | 6787f5fa | pbrook | } |
365 | 4d611c9a | pbrook | } |
366 | 2e5d83bb | pbrook | } |
367 | 2e5d83bb | pbrook | |
368 | 2f275b8f | bellard | static void handle_ti(ESPState *s) |
369 | 2f275b8f | bellard | { |
370 | 4d611c9a | pbrook | uint32_t dmalen, minlen; |
371 | 2f275b8f | bellard | |
372 | 5ad6bb97 | blueswir1 | dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
|
373 | db59203d | pbrook | if (dmalen==0) { |
374 | db59203d | pbrook | dmalen=0x10000;
|
375 | db59203d | pbrook | } |
376 | 6787f5fa | pbrook | s->dma_counter = dmalen; |
377 | db59203d | pbrook | |
378 | 9f149aa9 | pbrook | if (s->do_cmd)
|
379 | 9f149aa9 | pbrook | minlen = (dmalen < 32) ? dmalen : 32; |
380 | 67e999be | bellard | else if (s->ti_size < 0) |
381 | 67e999be | bellard | minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size; |
382 | 9f149aa9 | pbrook | else
|
383 | 9f149aa9 | pbrook | minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size; |
384 | db59203d | pbrook | DPRINTF("Transfer Information len %d\n", minlen);
|
385 | 4f6200f0 | bellard | if (s->dma) {
|
386 | 4d611c9a | pbrook | s->dma_left = minlen; |
387 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
388 | 4d611c9a | pbrook | esp_do_dma(s); |
389 | 9f149aa9 | pbrook | } else if (s->do_cmd) { |
390 | 9f149aa9 | pbrook | DPRINTF("command len %d\n", s->cmdlen);
|
391 | 9f149aa9 | pbrook | s->ti_size = 0;
|
392 | 9f149aa9 | pbrook | s->cmdlen = 0;
|
393 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
394 | 9f149aa9 | pbrook | do_cmd(s, s->cmdbuf); |
395 | 9f149aa9 | pbrook | return;
|
396 | 9f149aa9 | pbrook | } |
397 | 2f275b8f | bellard | } |
398 | 2f275b8f | bellard | |
399 | 5aca8c3b | blueswir1 | static void esp_reset(void *opaque) |
400 | 6f7e9aec | bellard | { |
401 | 6f7e9aec | bellard | ESPState *s = opaque; |
402 | 67e999be | bellard | |
403 | c73f96fd | blueswir1 | esp_lower_irq(s); |
404 | c73f96fd | blueswir1 | |
405 | 5aca8c3b | blueswir1 | memset(s->rregs, 0, ESP_REGS);
|
406 | 5aca8c3b | blueswir1 | memset(s->wregs, 0, ESP_REGS);
|
407 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a
|
408 | 4e9aec74 | pbrook | s->ti_size = 0;
|
409 | 4e9aec74 | pbrook | s->ti_rptr = 0;
|
410 | 4e9aec74 | pbrook | s->ti_wptr = 0;
|
411 | 4e9aec74 | pbrook | s->dma = 0;
|
412 | 9f149aa9 | pbrook | s->do_cmd = 0;
|
413 | 8dea1dd4 | blueswir1 | |
414 | 8dea1dd4 | blueswir1 | s->rregs[ESP_CFG1] = 7;
|
415 | 6f7e9aec | bellard | } |
416 | 6f7e9aec | bellard | |
417 | 2d069bab | blueswir1 | static void parent_esp_reset(void *opaque, int irq, int level) |
418 | 2d069bab | blueswir1 | { |
419 | 2d069bab | blueswir1 | if (level)
|
420 | 2d069bab | blueswir1 | esp_reset(opaque); |
421 | 2d069bab | blueswir1 | } |
422 | 2d069bab | blueswir1 | |
423 | 6f7e9aec | bellard | static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
424 | 6f7e9aec | bellard | { |
425 | 6f7e9aec | bellard | ESPState *s = opaque; |
426 | 6f7e9aec | bellard | uint32_t saddr; |
427 | 6f7e9aec | bellard | |
428 | e64d7d59 | blueswir1 | saddr = addr >> s->it_shift; |
429 | 9e61bde5 | bellard | DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
|
430 | 6f7e9aec | bellard | switch (saddr) {
|
431 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
432 | f930d07e | blueswir1 | if (s->ti_size > 0) { |
433 | f930d07e | blueswir1 | s->ti_size--; |
434 | 5ad6bb97 | blueswir1 | if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) { |
435 | 8dea1dd4 | blueswir1 | /* Data out. */
|
436 | 8dea1dd4 | blueswir1 | ESP_ERROR("PIO data read not implemented\n");
|
437 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = 0;
|
438 | 2e5d83bb | pbrook | } else {
|
439 | 5ad6bb97 | blueswir1 | s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++]; |
440 | 2e5d83bb | pbrook | } |
441 | c73f96fd | blueswir1 | esp_raise_irq(s); |
442 | f930d07e | blueswir1 | } |
443 | f930d07e | blueswir1 | if (s->ti_size == 0) { |
444 | 4f6200f0 | bellard | s->ti_rptr = 0;
|
445 | 4f6200f0 | bellard | s->ti_wptr = 0;
|
446 | 4f6200f0 | bellard | } |
447 | f930d07e | blueswir1 | break;
|
448 | 5ad6bb97 | blueswir1 | case ESP_RINTR:
|
449 | 4d611c9a | pbrook | // Clear interrupt/error status bits
|
450 | c73f96fd | blueswir1 | s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE); |
451 | c73f96fd | blueswir1 | esp_lower_irq(s); |
452 | 9e61bde5 | bellard | break;
|
453 | 6f7e9aec | bellard | default:
|
454 | f930d07e | blueswir1 | break;
|
455 | 6f7e9aec | bellard | } |
456 | 2f275b8f | bellard | return s->rregs[saddr];
|
457 | 6f7e9aec | bellard | } |
458 | 6f7e9aec | bellard | |
459 | 6f7e9aec | bellard | static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
460 | 6f7e9aec | bellard | { |
461 | 6f7e9aec | bellard | ESPState *s = opaque; |
462 | 6f7e9aec | bellard | uint32_t saddr; |
463 | 6f7e9aec | bellard | |
464 | e64d7d59 | blueswir1 | saddr = addr >> s->it_shift; |
465 | 5ad6bb97 | blueswir1 | DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
|
466 | 5ad6bb97 | blueswir1 | val); |
467 | 6f7e9aec | bellard | switch (saddr) {
|
468 | 5ad6bb97 | blueswir1 | case ESP_TCLO:
|
469 | 5ad6bb97 | blueswir1 | case ESP_TCMID:
|
470 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSTAT] &= ~STAT_TC; |
471 | 4f6200f0 | bellard | break;
|
472 | 5ad6bb97 | blueswir1 | case ESP_FIFO:
|
473 | 9f149aa9 | pbrook | if (s->do_cmd) {
|
474 | 9f149aa9 | pbrook | s->cmdbuf[s->cmdlen++] = val & 0xff;
|
475 | 8dea1dd4 | blueswir1 | } else if (s->ti_size == TI_BUFSZ - 1) { |
476 | 8dea1dd4 | blueswir1 | ESP_ERROR("fifo overrun\n");
|
477 | 2e5d83bb | pbrook | } else {
|
478 | 2e5d83bb | pbrook | s->ti_size++; |
479 | 2e5d83bb | pbrook | s->ti_buf[s->ti_wptr++] = val & 0xff;
|
480 | 2e5d83bb | pbrook | } |
481 | f930d07e | blueswir1 | break;
|
482 | 5ad6bb97 | blueswir1 | case ESP_CMD:
|
483 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
484 | 5ad6bb97 | blueswir1 | if (val & CMD_DMA) {
|
485 | f930d07e | blueswir1 | s->dma = 1;
|
486 | 6787f5fa | pbrook | /* Reload DMA counter. */
|
487 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO]; |
488 | 5ad6bb97 | blueswir1 | s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID]; |
489 | f930d07e | blueswir1 | } else {
|
490 | f930d07e | blueswir1 | s->dma = 0;
|
491 | f930d07e | blueswir1 | } |
492 | 5ad6bb97 | blueswir1 | switch(val & CMD_CMD) {
|
493 | 5ad6bb97 | blueswir1 | case CMD_NOP:
|
494 | f930d07e | blueswir1 | DPRINTF("NOP (%2.2x)\n", val);
|
495 | f930d07e | blueswir1 | break;
|
496 | 5ad6bb97 | blueswir1 | case CMD_FLUSH:
|
497 | f930d07e | blueswir1 | DPRINTF("Flush FIFO (%2.2x)\n", val);
|
498 | 9e61bde5 | bellard | //s->ti_size = 0;
|
499 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_FC; |
500 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
501 | a214c598 | blueswir1 | s->rregs[ESP_RFLAGS] = 0;
|
502 | f930d07e | blueswir1 | break;
|
503 | 5ad6bb97 | blueswir1 | case CMD_RESET:
|
504 | f930d07e | blueswir1 | DPRINTF("Chip reset (%2.2x)\n", val);
|
505 | f930d07e | blueswir1 | esp_reset(s); |
506 | f930d07e | blueswir1 | break;
|
507 | 5ad6bb97 | blueswir1 | case CMD_BUSRESET:
|
508 | f930d07e | blueswir1 | DPRINTF("Bus reset (%2.2x)\n", val);
|
509 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_RST; |
510 | 5ad6bb97 | blueswir1 | if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
511 | c73f96fd | blueswir1 | esp_raise_irq(s); |
512 | 9e61bde5 | bellard | } |
513 | f930d07e | blueswir1 | break;
|
514 | 5ad6bb97 | blueswir1 | case CMD_TI:
|
515 | f930d07e | blueswir1 | handle_ti(s); |
516 | f930d07e | blueswir1 | break;
|
517 | 5ad6bb97 | blueswir1 | case CMD_ICCS:
|
518 | f930d07e | blueswir1 | DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
|
519 | f930d07e | blueswir1 | write_response(s); |
520 | 4bf5801d | blueswir1 | s->rregs[ESP_RINTR] = INTR_FC; |
521 | 4bf5801d | blueswir1 | s->rregs[ESP_RSTAT] |= STAT_MI; |
522 | f930d07e | blueswir1 | break;
|
523 | 5ad6bb97 | blueswir1 | case CMD_MSGACC:
|
524 | f930d07e | blueswir1 | DPRINTF("Message Accepted (%2.2x)\n", val);
|
525 | f930d07e | blueswir1 | write_response(s); |
526 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RINTR] = INTR_DC; |
527 | 5ad6bb97 | blueswir1 | s->rregs[ESP_RSEQ] = 0;
|
528 | f930d07e | blueswir1 | break;
|
529 | 5ad6bb97 | blueswir1 | case CMD_SATN:
|
530 | f930d07e | blueswir1 | DPRINTF("Set ATN (%2.2x)\n", val);
|
531 | f930d07e | blueswir1 | break;
|
532 | 5ad6bb97 | blueswir1 | case CMD_SELATN:
|
533 | f930d07e | blueswir1 | DPRINTF("Set ATN (%2.2x)\n", val);
|
534 | f930d07e | blueswir1 | handle_satn(s); |
535 | f930d07e | blueswir1 | break;
|
536 | 5ad6bb97 | blueswir1 | case CMD_SELATNS:
|
537 | f930d07e | blueswir1 | DPRINTF("Set ATN & stop (%2.2x)\n", val);
|
538 | f930d07e | blueswir1 | handle_satn_stop(s); |
539 | f930d07e | blueswir1 | break;
|
540 | 5ad6bb97 | blueswir1 | case CMD_ENSEL:
|
541 | 74ec6048 | blueswir1 | DPRINTF("Enable selection (%2.2x)\n", val);
|
542 | e3926838 | blueswir1 | s->rregs[ESP_RINTR] = 0;
|
543 | 74ec6048 | blueswir1 | break;
|
544 | f930d07e | blueswir1 | default:
|
545 | 8dea1dd4 | blueswir1 | ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
|
546 | f930d07e | blueswir1 | break;
|
547 | f930d07e | blueswir1 | } |
548 | f930d07e | blueswir1 | break;
|
549 | 5ad6bb97 | blueswir1 | case ESP_WBUSID ... ESP_WSYNO:
|
550 | f930d07e | blueswir1 | break;
|
551 | 5ad6bb97 | blueswir1 | case ESP_CFG1:
|
552 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
553 | 4f6200f0 | bellard | break;
|
554 | 5ad6bb97 | blueswir1 | case ESP_WCCF ... ESP_WTEST:
|
555 | 4f6200f0 | bellard | break;
|
556 | b44c08fa | blueswir1 | case ESP_CFG2 ... ESP_RES4:
|
557 | 4f6200f0 | bellard | s->rregs[saddr] = val; |
558 | 4f6200f0 | bellard | break;
|
559 | 6f7e9aec | bellard | default:
|
560 | 8dea1dd4 | blueswir1 | ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
|
561 | 8dea1dd4 | blueswir1 | return;
|
562 | 6f7e9aec | bellard | } |
563 | 2f275b8f | bellard | s->wregs[saddr] = val; |
564 | 6f7e9aec | bellard | } |
565 | 6f7e9aec | bellard | |
566 | 6f7e9aec | bellard | static CPUReadMemoryFunc *esp_mem_read[3] = { |
567 | 6f7e9aec | bellard | esp_mem_readb, |
568 | 7c560456 | blueswir1 | NULL,
|
569 | 7c560456 | blueswir1 | NULL,
|
570 | 6f7e9aec | bellard | }; |
571 | 6f7e9aec | bellard | |
572 | 6f7e9aec | bellard | static CPUWriteMemoryFunc *esp_mem_write[3] = { |
573 | 6f7e9aec | bellard | esp_mem_writeb, |
574 | 7c560456 | blueswir1 | NULL,
|
575 | daa41b00 | blueswir1 | esp_mem_writeb, |
576 | 6f7e9aec | bellard | }; |
577 | 6f7e9aec | bellard | |
578 | 6f7e9aec | bellard | static void esp_save(QEMUFile *f, void *opaque) |
579 | 6f7e9aec | bellard | { |
580 | 6f7e9aec | bellard | ESPState *s = opaque; |
581 | 2f275b8f | bellard | |
582 | 5aca8c3b | blueswir1 | qemu_put_buffer(f, s->rregs, ESP_REGS); |
583 | 5aca8c3b | blueswir1 | qemu_put_buffer(f, s->wregs, ESP_REGS); |
584 | b6c4f71f | blueswir1 | qemu_put_sbe32s(f, &s->ti_size); |
585 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_rptr); |
586 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->ti_wptr); |
587 | 4f6200f0 | bellard | qemu_put_buffer(f, s->ti_buf, TI_BUFSZ); |
588 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->sense); |
589 | 4f6200f0 | bellard | qemu_put_be32s(f, &s->dma); |
590 | 5425a216 | blueswir1 | qemu_put_buffer(f, s->cmdbuf, TI_BUFSZ); |
591 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->cmdlen); |
592 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->do_cmd); |
593 | 5425a216 | blueswir1 | qemu_put_be32s(f, &s->dma_left); |
594 | 5425a216 | blueswir1 | // There should be no transfers in progress, so dma_counter is not saved
|
595 | 6f7e9aec | bellard | } |
596 | 6f7e9aec | bellard | |
597 | 6f7e9aec | bellard | static int esp_load(QEMUFile *f, void *opaque, int version_id) |
598 | 6f7e9aec | bellard | { |
599 | 6f7e9aec | bellard | ESPState *s = opaque; |
600 | 3b46e624 | ths | |
601 | 5425a216 | blueswir1 | if (version_id != 3) |
602 | 5425a216 | blueswir1 | return -EINVAL; // Cannot emulate 2 |
603 | 6f7e9aec | bellard | |
604 | 5aca8c3b | blueswir1 | qemu_get_buffer(f, s->rregs, ESP_REGS); |
605 | 5aca8c3b | blueswir1 | qemu_get_buffer(f, s->wregs, ESP_REGS); |
606 | b6c4f71f | blueswir1 | qemu_get_sbe32s(f, &s->ti_size); |
607 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_rptr); |
608 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->ti_wptr); |
609 | 4f6200f0 | bellard | qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); |
610 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->sense); |
611 | 4f6200f0 | bellard | qemu_get_be32s(f, &s->dma); |
612 | 5425a216 | blueswir1 | qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); |
613 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->cmdlen); |
614 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->do_cmd); |
615 | 5425a216 | blueswir1 | qemu_get_be32s(f, &s->dma_left); |
616 | 2f275b8f | bellard | |
617 | 6f7e9aec | bellard | return 0; |
618 | 6f7e9aec | bellard | } |
619 | 6f7e9aec | bellard | |
620 | fa1fb14c | ths | void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id) |
621 | fa1fb14c | ths | { |
622 | fa1fb14c | ths | ESPState *s = (ESPState *)opaque; |
623 | fa1fb14c | ths | |
624 | fa1fb14c | ths | if (id < 0) { |
625 | fa1fb14c | ths | for (id = 0; id < ESP_MAX_DEVS; id++) { |
626 | 8dea1dd4 | blueswir1 | if (id == (s->rregs[ESP_CFG1] & 0x7)) |
627 | 8dea1dd4 | blueswir1 | continue;
|
628 | fa1fb14c | ths | if (s->scsi_dev[id] == NULL) |
629 | fa1fb14c | ths | break;
|
630 | fa1fb14c | ths | } |
631 | fa1fb14c | ths | } |
632 | fa1fb14c | ths | if (id >= ESP_MAX_DEVS) {
|
633 | fa1fb14c | ths | DPRINTF("Bad Device ID %d\n", id);
|
634 | fa1fb14c | ths | return;
|
635 | fa1fb14c | ths | } |
636 | fa1fb14c | ths | if (s->scsi_dev[id]) {
|
637 | fa1fb14c | ths | DPRINTF("Destroying device %d\n", id);
|
638 | 8ccc2ace | ths | s->scsi_dev[id]->destroy(s->scsi_dev[id]); |
639 | fa1fb14c | ths | } |
640 | fa1fb14c | ths | DPRINTF("Attaching block device %d\n", id);
|
641 | fa1fb14c | ths | /* Command queueing is not implemented. */
|
642 | 985a03b0 | ths | s->scsi_dev[id] = scsi_generic_init(bd, 0, esp_command_complete, s);
|
643 | 985a03b0 | ths | if (s->scsi_dev[id] == NULL) |
644 | 985a03b0 | ths | s->scsi_dev[id] = scsi_disk_init(bd, 0, esp_command_complete, s);
|
645 | fa1fb14c | ths | } |
646 | fa1fb14c | ths | |
647 | 5d20fa6b | blueswir1 | void *esp_init(target_phys_addr_t espaddr, int it_shift, |
648 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_read, |
649 | 8b17de88 | blueswir1 | espdma_memory_read_write dma_memory_write, |
650 | 2d069bab | blueswir1 | void *dma_opaque, qemu_irq irq, qemu_irq *reset)
|
651 | 6f7e9aec | bellard | { |
652 | 6f7e9aec | bellard | ESPState *s; |
653 | 67e999be | bellard | int esp_io_memory;
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654 | 6f7e9aec | bellard | |
655 | 6f7e9aec | bellard | s = qemu_mallocz(sizeof(ESPState));
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656 | 6f7e9aec | bellard | |
657 | 70c0de96 | blueswir1 | s->irq = irq; |
658 | 5d20fa6b | blueswir1 | s->it_shift = it_shift; |
659 | 8b17de88 | blueswir1 | s->dma_memory_read = dma_memory_read; |
660 | 8b17de88 | blueswir1 | s->dma_memory_write = dma_memory_write; |
661 | 67e999be | bellard | s->dma_opaque = dma_opaque; |
662 | 6f7e9aec | bellard | |
663 | 6f7e9aec | bellard | esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
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664 | 5d20fa6b | blueswir1 | cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory); |
665 | 6f7e9aec | bellard | |
666 | 6f7e9aec | bellard | esp_reset(s); |
667 | 6f7e9aec | bellard | |
668 | 5425a216 | blueswir1 | register_savevm("esp", espaddr, 3, esp_save, esp_load, s); |
669 | 6f7e9aec | bellard | qemu_register_reset(esp_reset, s); |
670 | 6f7e9aec | bellard | |
671 | 2d069bab | blueswir1 | *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1);
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672 | 2d069bab | blueswir1 | |
673 | 67e999be | bellard | return s;
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674 | 67e999be | bellard | } |