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1 | d0f7453d | Huacai Chen | /*
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2 | d0f7453d | Huacai Chen | * bonito north bridge support
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3 | d0f7453d | Huacai Chen | *
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4 | d0f7453d | Huacai Chen | * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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5 | d0f7453d | Huacai Chen | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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6 | d0f7453d | Huacai Chen | *
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7 | d0f7453d | Huacai Chen | * This code is licensed under the GNU GPL v2.
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8 | d0f7453d | Huacai Chen | */
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9 | d0f7453d | Huacai Chen | |
10 | d0f7453d | Huacai Chen | /*
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11 | d0f7453d | Huacai Chen | * fulong 2e mini pc has a bonito north bridge.
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12 | d0f7453d | Huacai Chen | */
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13 | d0f7453d | Huacai Chen | |
14 | d0f7453d | Huacai Chen | /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
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15 | d0f7453d | Huacai Chen | *
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16 | d0f7453d | Huacai Chen | * devfn pci_slot<<3 + funno
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17 | d0f7453d | Huacai Chen | * one pci bus can have 32 devices and each device can have 8 functions.
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18 | d0f7453d | Huacai Chen | *
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19 | d0f7453d | Huacai Chen | * In bonito north bridge, pci slot = IDSEL bit - 12.
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20 | d0f7453d | Huacai Chen | * For example, PCI_IDSEL_VIA686B = 17,
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21 | d0f7453d | Huacai Chen | * pci slot = 17-12=5
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22 | d0f7453d | Huacai Chen | *
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23 | d0f7453d | Huacai Chen | * so
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24 | d0f7453d | Huacai Chen | * VT686B_FUN0's devfn = (5<<3)+0
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25 | d0f7453d | Huacai Chen | * VT686B_FUN1's devfn = (5<<3)+1
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26 | d0f7453d | Huacai Chen | *
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27 | d0f7453d | Huacai Chen | * qemu also uses pci address for north bridge to access pci config register.
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28 | d0f7453d | Huacai Chen | * bus_no [23:16]
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29 | d0f7453d | Huacai Chen | * dev_no [15:11]
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30 | d0f7453d | Huacai Chen | * fun_no [10:8]
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31 | d0f7453d | Huacai Chen | * reg_no [7:2]
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32 | d0f7453d | Huacai Chen | *
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33 | d0f7453d | Huacai Chen | * so function bonito_sbridge_pciaddr for the translation from
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34 | d0f7453d | Huacai Chen | * north bridge address to pci address.
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35 | d0f7453d | Huacai Chen | */
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36 | d0f7453d | Huacai Chen | |
37 | d0f7453d | Huacai Chen | #include <assert.h> |
38 | d0f7453d | Huacai Chen | |
39 | d0f7453d | Huacai Chen | #include "hw.h" |
40 | d0f7453d | Huacai Chen | #include "pci.h" |
41 | d0f7453d | Huacai Chen | #include "pc.h" |
42 | d0f7453d | Huacai Chen | #include "mips.h" |
43 | d0f7453d | Huacai Chen | #include "pci_host.h" |
44 | d0f7453d | Huacai Chen | #include "sysemu.h" |
45 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
46 | d0f7453d | Huacai Chen | |
47 | d0f7453d | Huacai Chen | //#define DEBUG_BONITO
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48 | d0f7453d | Huacai Chen | |
49 | d0f7453d | Huacai Chen | #ifdef DEBUG_BONITO
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50 | d0f7453d | Huacai Chen | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
51 | d0f7453d | Huacai Chen | #else
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52 | d0f7453d | Huacai Chen | #define DPRINTF(fmt, ...)
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53 | d0f7453d | Huacai Chen | #endif
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54 | d0f7453d | Huacai Chen | |
55 | d0f7453d | Huacai Chen | /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
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56 | d0f7453d | Huacai Chen | #define BONITO_BOOT_BASE 0x1fc00000 |
57 | d0f7453d | Huacai Chen | #define BONITO_BOOT_SIZE 0x00100000 |
58 | d0f7453d | Huacai Chen | #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) |
59 | d0f7453d | Huacai Chen | #define BONITO_FLASH_BASE 0x1c000000 |
60 | d0f7453d | Huacai Chen | #define BONITO_FLASH_SIZE 0x03000000 |
61 | d0f7453d | Huacai Chen | #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) |
62 | d0f7453d | Huacai Chen | #define BONITO_SOCKET_BASE 0x1f800000 |
63 | d0f7453d | Huacai Chen | #define BONITO_SOCKET_SIZE 0x00400000 |
64 | d0f7453d | Huacai Chen | #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) |
65 | d0f7453d | Huacai Chen | #define BONITO_REG_BASE 0x1fe00000 |
66 | d0f7453d | Huacai Chen | #define BONITO_REG_SIZE 0x00040000 |
67 | d0f7453d | Huacai Chen | #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) |
68 | d0f7453d | Huacai Chen | #define BONITO_DEV_BASE 0x1ff00000 |
69 | d0f7453d | Huacai Chen | #define BONITO_DEV_SIZE 0x00100000 |
70 | d0f7453d | Huacai Chen | #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) |
71 | d0f7453d | Huacai Chen | #define BONITO_PCILO_BASE 0x10000000 |
72 | d0f7453d | Huacai Chen | #define BONITO_PCILO_BASE_VA 0xb0000000 |
73 | d0f7453d | Huacai Chen | #define BONITO_PCILO_SIZE 0x0c000000 |
74 | d0f7453d | Huacai Chen | #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) |
75 | d0f7453d | Huacai Chen | #define BONITO_PCILO0_BASE 0x10000000 |
76 | d0f7453d | Huacai Chen | #define BONITO_PCILO1_BASE 0x14000000 |
77 | d0f7453d | Huacai Chen | #define BONITO_PCILO2_BASE 0x18000000 |
78 | d0f7453d | Huacai Chen | #define BONITO_PCIHI_BASE 0x20000000 |
79 | d0f7453d | Huacai Chen | #define BONITO_PCIHI_SIZE 0x20000000 |
80 | d0f7453d | Huacai Chen | #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) |
81 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_BASE 0x1fd00000 |
82 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_BASE_VA 0xbfd00000 |
83 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_SIZE 0x00010000 |
84 | d0f7453d | Huacai Chen | #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) |
85 | d0f7453d | Huacai Chen | #define BONITO_PCICFG_BASE 0x1fe80000 |
86 | d0f7453d | Huacai Chen | #define BONITO_PCICFG_SIZE 0x00080000 |
87 | d0f7453d | Huacai Chen | #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) |
88 | d0f7453d | Huacai Chen | |
89 | d0f7453d | Huacai Chen | |
90 | d0f7453d | Huacai Chen | #define BONITO_PCICONFIGBASE 0x00 |
91 | d0f7453d | Huacai Chen | #define BONITO_REGBASE 0x100 |
92 | d0f7453d | Huacai Chen | |
93 | d0f7453d | Huacai Chen | #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
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94 | d0f7453d | Huacai Chen | #define BONITO_PCICONFIG_SIZE (0x100) |
95 | d0f7453d | Huacai Chen | |
96 | d0f7453d | Huacai Chen | #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE)
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97 | d0f7453d | Huacai Chen | #define BONITO_INTERNAL_REG_SIZE (0x70) |
98 | d0f7453d | Huacai Chen | |
99 | d0f7453d | Huacai Chen | #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
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100 | d0f7453d | Huacai Chen | #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
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101 | d0f7453d | Huacai Chen | |
102 | d0f7453d | Huacai Chen | |
103 | d0f7453d | Huacai Chen | |
104 | d0f7453d | Huacai Chen | /* 1. Bonito h/w Configuration */
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105 | d0f7453d | Huacai Chen | /* Power on register */
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106 | d0f7453d | Huacai Chen | |
107 | d0f7453d | Huacai Chen | #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ |
108 | d0f7453d | Huacai Chen | #define BONITO_BONGENCFG_OFFSET 0x4 |
109 | d0f7453d | Huacai Chen | #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ |
110 | d0f7453d | Huacai Chen | |
111 | d0f7453d | Huacai Chen | /* 2. IO & IDE configuration */
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112 | d0f7453d | Huacai Chen | #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ |
113 | d0f7453d | Huacai Chen | |
114 | d0f7453d | Huacai Chen | /* 3. IO & IDE configuration */
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115 | d0f7453d | Huacai Chen | #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ |
116 | d0f7453d | Huacai Chen | |
117 | d0f7453d | Huacai Chen | /* 4. PCI address map control */
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118 | d0f7453d | Huacai Chen | #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ |
119 | d0f7453d | Huacai Chen | #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ |
120 | d0f7453d | Huacai Chen | #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ |
121 | d0f7453d | Huacai Chen | |
122 | d0f7453d | Huacai Chen | /* 5. ICU & GPIO regs */
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123 | d0f7453d | Huacai Chen | /* GPIO Regs - r/w */
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124 | d0f7453d | Huacai Chen | #define BONITO_GPIODATA_OFFSET 0x1c |
125 | d0f7453d | Huacai Chen | #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ |
126 | d0f7453d | Huacai Chen | #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ |
127 | d0f7453d | Huacai Chen | |
128 | d0f7453d | Huacai Chen | /* ICU Configuration Regs - r/w */
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129 | d0f7453d | Huacai Chen | #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ |
130 | d0f7453d | Huacai Chen | #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ |
131 | d0f7453d | Huacai Chen | #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ |
132 | d0f7453d | Huacai Chen | |
133 | d0f7453d | Huacai Chen | /* ICU Enable Regs - IntEn & IntISR are r/o. */
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134 | d0f7453d | Huacai Chen | #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ |
135 | d0f7453d | Huacai Chen | #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ |
136 | d0f7453d | Huacai Chen | #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ |
137 | d0f7453d | Huacai Chen | #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ |
138 | d0f7453d | Huacai Chen | |
139 | d0f7453d | Huacai Chen | /* PCI mail boxes */
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140 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL0_OFFSET 0x40 |
141 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL1_OFFSET 0x44 |
142 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL2_OFFSET 0x48 |
143 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL3_OFFSET 0x4c |
144 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ |
145 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ |
146 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ |
147 | d0f7453d | Huacai Chen | #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ |
148 | d0f7453d | Huacai Chen | |
149 | d0f7453d | Huacai Chen | /* 6. PCI cache */
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150 | d0f7453d | Huacai Chen | #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ |
151 | d0f7453d | Huacai Chen | #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ |
152 | d0f7453d | Huacai Chen | #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ |
153 | d0f7453d | Huacai Chen | #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ |
154 | d0f7453d | Huacai Chen | |
155 | d0f7453d | Huacai Chen | /* 7. other*/
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156 | d0f7453d | Huacai Chen | #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ |
157 | d0f7453d | Huacai Chen | #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ |
158 | d0f7453d | Huacai Chen | #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ |
159 | d0f7453d | Huacai Chen | #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ |
160 | d0f7453d | Huacai Chen | |
161 | d0f7453d | Huacai Chen | #define BONITO_REGS (0x70 >> 2) |
162 | d0f7453d | Huacai Chen | |
163 | d0f7453d | Huacai Chen | /* PCI config for south bridge. type 0 */
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164 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ |
165 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_IDSEL_OFFSET 11 |
166 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ |
167 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_FUN_OFFSET 8 |
168 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_REG_MASK 0xFC |
169 | d0f7453d | Huacai Chen | #define BONITO_PCICONF_REG_OFFSET 0 |
170 | d0f7453d | Huacai Chen | |
171 | d0f7453d | Huacai Chen | |
172 | d0f7453d | Huacai Chen | /* idsel BIT = pci slot number +12 */
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173 | d0f7453d | Huacai Chen | #define PCI_SLOT_BASE 12 |
174 | d0f7453d | Huacai Chen | #define PCI_IDSEL_VIA686B_BIT (17) |
175 | d0f7453d | Huacai Chen | #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) |
176 | d0f7453d | Huacai Chen | |
177 | d0f7453d | Huacai Chen | #define PCI_ADDR(busno,devno,funno,regno) \
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178 | d0f7453d | Huacai Chen | ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) |
179 | d0f7453d | Huacai Chen | |
180 | d0f7453d | Huacai Chen | typedef PCIHostState BonitoState;
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181 | d0f7453d | Huacai Chen | |
182 | d0f7453d | Huacai Chen | typedef struct PCIBonitoState |
183 | d0f7453d | Huacai Chen | { |
184 | d0f7453d | Huacai Chen | PCIDevice dev; |
185 | d0f7453d | Huacai Chen | BonitoState *pcihost; |
186 | d0f7453d | Huacai Chen | uint32_t regs[BONITO_REGS]; |
187 | d0f7453d | Huacai Chen | |
188 | d0f7453d | Huacai Chen | struct bonldma {
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189 | d0f7453d | Huacai Chen | uint32_t ldmactrl; |
190 | d0f7453d | Huacai Chen | uint32_t ldmastat; |
191 | d0f7453d | Huacai Chen | uint32_t ldmaaddr; |
192 | d0f7453d | Huacai Chen | uint32_t ldmago; |
193 | d0f7453d | Huacai Chen | } bonldma; |
194 | d0f7453d | Huacai Chen | |
195 | d0f7453d | Huacai Chen | /* Based at 1fe00300, bonito Copier */
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196 | d0f7453d | Huacai Chen | struct boncop {
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197 | d0f7453d | Huacai Chen | uint32_t copctrl; |
198 | d0f7453d | Huacai Chen | uint32_t copstat; |
199 | d0f7453d | Huacai Chen | uint32_t coppaddr; |
200 | d0f7453d | Huacai Chen | uint32_t copgo; |
201 | d0f7453d | Huacai Chen | } boncop; |
202 | d0f7453d | Huacai Chen | |
203 | d0f7453d | Huacai Chen | /* Bonito registers */
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204 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_reg_start; |
205 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_reg_length; |
206 | d0f7453d | Huacai Chen | int bonito_reg_handle;
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207 | d0f7453d | Huacai Chen | |
208 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_pciconf_start; |
209 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_pciconf_length; |
210 | d0f7453d | Huacai Chen | int bonito_pciconf_handle;
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211 | d0f7453d | Huacai Chen | |
212 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_spciconf_start; |
213 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_spciconf_length; |
214 | d0f7453d | Huacai Chen | int bonito_spciconf_handle;
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215 | d0f7453d | Huacai Chen | |
216 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_pciio_start; |
217 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_pciio_length; |
218 | d0f7453d | Huacai Chen | int bonito_pciio_handle;
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219 | d0f7453d | Huacai Chen | |
220 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_localio_start; |
221 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_localio_length; |
222 | d0f7453d | Huacai Chen | int bonito_localio_handle;
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223 | d0f7453d | Huacai Chen | |
224 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_ldma_start; |
225 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_ldma_length; |
226 | d0f7453d | Huacai Chen | int bonito_ldma_handle;
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227 | d0f7453d | Huacai Chen | |
228 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_cop_start; |
229 | d0f7453d | Huacai Chen | target_phys_addr_t bonito_cop_length; |
230 | d0f7453d | Huacai Chen | int bonito_cop_handle;
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231 | d0f7453d | Huacai Chen | |
232 | d0f7453d | Huacai Chen | } PCIBonitoState; |
233 | d0f7453d | Huacai Chen | |
234 | d0f7453d | Huacai Chen | PCIBonitoState * bonito_state; |
235 | d0f7453d | Huacai Chen | |
236 | d0f7453d | Huacai Chen | static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
237 | d0f7453d | Huacai Chen | { |
238 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
239 | d0f7453d | Huacai Chen | uint32_t saddr; |
240 | d0f7453d | Huacai Chen | int reset = 0; |
241 | d0f7453d | Huacai Chen | |
242 | d0f7453d | Huacai Chen | saddr = (addr - BONITO_REGBASE) >> 2;
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243 | d0f7453d | Huacai Chen | |
244 | b2bedb21 | Stefan Weil | DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); |
245 | d0f7453d | Huacai Chen | switch (saddr) {
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246 | d0f7453d | Huacai Chen | case BONITO_BONPONCFG:
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247 | d0f7453d | Huacai Chen | case BONITO_IODEVCFG:
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248 | d0f7453d | Huacai Chen | case BONITO_SDCFG:
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249 | d0f7453d | Huacai Chen | case BONITO_PCIMAP:
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250 | d0f7453d | Huacai Chen | case BONITO_PCIMEMBASECFG:
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251 | d0f7453d | Huacai Chen | case BONITO_PCIMAP_CFG:
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252 | d0f7453d | Huacai Chen | case BONITO_GPIODATA:
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253 | d0f7453d | Huacai Chen | case BONITO_GPIOIE:
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254 | d0f7453d | Huacai Chen | case BONITO_INTEDGE:
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255 | d0f7453d | Huacai Chen | case BONITO_INTSTEER:
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256 | d0f7453d | Huacai Chen | case BONITO_INTPOL:
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257 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL0:
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258 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL1:
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259 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL2:
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260 | d0f7453d | Huacai Chen | case BONITO_PCIMAIL3:
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261 | d0f7453d | Huacai Chen | case BONITO_PCICACHECTRL:
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262 | d0f7453d | Huacai Chen | case BONITO_PCICACHETAG:
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263 | d0f7453d | Huacai Chen | case BONITO_PCIBADADDR:
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264 | d0f7453d | Huacai Chen | case BONITO_PCIMSTAT:
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265 | d0f7453d | Huacai Chen | case BONITO_TIMECFG:
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266 | d0f7453d | Huacai Chen | case BONITO_CPUCFG:
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267 | d0f7453d | Huacai Chen | case BONITO_DQCFG:
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268 | d0f7453d | Huacai Chen | case BONITO_MEMSIZE:
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269 | d0f7453d | Huacai Chen | s->regs[saddr] = val; |
270 | d0f7453d | Huacai Chen | break;
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271 | d0f7453d | Huacai Chen | case BONITO_BONGENCFG:
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272 | d0f7453d | Huacai Chen | if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { |
273 | d0f7453d | Huacai Chen | reset = 1; /* bit 2 jump from 0 to 1 cause reset */ |
274 | d0f7453d | Huacai Chen | } |
275 | d0f7453d | Huacai Chen | s->regs[saddr] = val; |
276 | d0f7453d | Huacai Chen | if (reset) {
|
277 | d0f7453d | Huacai Chen | qemu_system_reset_request(); |
278 | d0f7453d | Huacai Chen | } |
279 | d0f7453d | Huacai Chen | break;
|
280 | d0f7453d | Huacai Chen | case BONITO_INTENSET:
|
281 | d0f7453d | Huacai Chen | s->regs[BONITO_INTENSET] = val; |
282 | d0f7453d | Huacai Chen | s->regs[BONITO_INTEN] |= val; |
283 | d0f7453d | Huacai Chen | break;
|
284 | d0f7453d | Huacai Chen | case BONITO_INTENCLR:
|
285 | d0f7453d | Huacai Chen | s->regs[BONITO_INTENCLR] = val; |
286 | d0f7453d | Huacai Chen | s->regs[BONITO_INTEN] &= ~val; |
287 | d0f7453d | Huacai Chen | break;
|
288 | d0f7453d | Huacai Chen | case BONITO_INTEN:
|
289 | d0f7453d | Huacai Chen | case BONITO_INTISR:
|
290 | b2bedb21 | Stefan Weil | DPRINTF("write to readonly bonito register %x\n", saddr);
|
291 | d0f7453d | Huacai Chen | break;
|
292 | d0f7453d | Huacai Chen | default:
|
293 | b2bedb21 | Stefan Weil | DPRINTF("write to unknown bonito register %x\n", saddr);
|
294 | d0f7453d | Huacai Chen | break;
|
295 | d0f7453d | Huacai Chen | } |
296 | d0f7453d | Huacai Chen | } |
297 | d0f7453d | Huacai Chen | |
298 | d0f7453d | Huacai Chen | static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr) |
299 | d0f7453d | Huacai Chen | { |
300 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
301 | d0f7453d | Huacai Chen | uint32_t saddr; |
302 | d0f7453d | Huacai Chen | |
303 | d0f7453d | Huacai Chen | saddr = (addr - BONITO_REGBASE) >> 2;
|
304 | d0f7453d | Huacai Chen | |
305 | b2bedb21 | Stefan Weil | DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); |
306 | d0f7453d | Huacai Chen | switch (saddr) {
|
307 | d0f7453d | Huacai Chen | case BONITO_INTISR:
|
308 | d0f7453d | Huacai Chen | return s->regs[saddr];
|
309 | d0f7453d | Huacai Chen | default:
|
310 | d0f7453d | Huacai Chen | return s->regs[saddr];
|
311 | d0f7453d | Huacai Chen | } |
312 | d0f7453d | Huacai Chen | } |
313 | d0f7453d | Huacai Chen | |
314 | d0f7453d | Huacai Chen | static CPUWriteMemoryFunc * const bonito_write[] = { |
315 | d0f7453d | Huacai Chen | NULL,
|
316 | d0f7453d | Huacai Chen | NULL,
|
317 | d0f7453d | Huacai Chen | bonito_writel, |
318 | d0f7453d | Huacai Chen | }; |
319 | d0f7453d | Huacai Chen | |
320 | d0f7453d | Huacai Chen | static CPUReadMemoryFunc * const bonito_read[] = { |
321 | d0f7453d | Huacai Chen | NULL,
|
322 | d0f7453d | Huacai Chen | NULL,
|
323 | d0f7453d | Huacai Chen | bonito_readl, |
324 | d0f7453d | Huacai Chen | }; |
325 | d0f7453d | Huacai Chen | |
326 | d0f7453d | Huacai Chen | static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr, |
327 | d0f7453d | Huacai Chen | uint32_t val) |
328 | d0f7453d | Huacai Chen | { |
329 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
330 | d0f7453d | Huacai Chen | |
331 | b2bedb21 | Stefan Weil | DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); |
332 | d0f7453d | Huacai Chen | s->dev.config_write(&s->dev, addr, val, 4);
|
333 | d0f7453d | Huacai Chen | } |
334 | d0f7453d | Huacai Chen | |
335 | d0f7453d | Huacai Chen | static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr) |
336 | d0f7453d | Huacai Chen | { |
337 | d0f7453d | Huacai Chen | |
338 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
339 | d0f7453d | Huacai Chen | |
340 | d0f7453d | Huacai Chen | DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); |
341 | d0f7453d | Huacai Chen | return s->dev.config_read(&s->dev, addr, 4); |
342 | d0f7453d | Huacai Chen | } |
343 | d0f7453d | Huacai Chen | |
344 | d0f7453d | Huacai Chen | /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
|
345 | d0f7453d | Huacai Chen | static CPUWriteMemoryFunc * const bonito_pciconf_write[] = { |
346 | d0f7453d | Huacai Chen | NULL,
|
347 | d0f7453d | Huacai Chen | NULL,
|
348 | d0f7453d | Huacai Chen | bonito_pciconf_writel, |
349 | d0f7453d | Huacai Chen | }; |
350 | d0f7453d | Huacai Chen | |
351 | d0f7453d | Huacai Chen | static CPUReadMemoryFunc * const bonito_pciconf_read[] = { |
352 | d0f7453d | Huacai Chen | NULL,
|
353 | d0f7453d | Huacai Chen | NULL,
|
354 | d0f7453d | Huacai Chen | bonito_pciconf_readl, |
355 | d0f7453d | Huacai Chen | }; |
356 | d0f7453d | Huacai Chen | |
357 | d0f7453d | Huacai Chen | static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr) |
358 | d0f7453d | Huacai Chen | { |
359 | d0f7453d | Huacai Chen | uint32_t val; |
360 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
361 | d0f7453d | Huacai Chen | |
362 | d0f7453d | Huacai Chen | val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
|
363 | d0f7453d | Huacai Chen | |
364 | d0f7453d | Huacai Chen | return val;
|
365 | d0f7453d | Huacai Chen | } |
366 | d0f7453d | Huacai Chen | |
367 | d0f7453d | Huacai Chen | static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr, |
368 | d0f7453d | Huacai Chen | uint32_t val) |
369 | d0f7453d | Huacai Chen | { |
370 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
371 | d0f7453d | Huacai Chen | |
372 | d0f7453d | Huacai Chen | ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; |
373 | d0f7453d | Huacai Chen | } |
374 | d0f7453d | Huacai Chen | |
375 | d0f7453d | Huacai Chen | static CPUWriteMemoryFunc * const bonito_ldma_write[] = { |
376 | d0f7453d | Huacai Chen | NULL,
|
377 | d0f7453d | Huacai Chen | NULL,
|
378 | d0f7453d | Huacai Chen | bonito_ldma_writel, |
379 | d0f7453d | Huacai Chen | }; |
380 | d0f7453d | Huacai Chen | |
381 | d0f7453d | Huacai Chen | static CPUReadMemoryFunc * const bonito_ldma_read[] = { |
382 | d0f7453d | Huacai Chen | NULL,
|
383 | d0f7453d | Huacai Chen | NULL,
|
384 | d0f7453d | Huacai Chen | bonito_ldma_readl, |
385 | d0f7453d | Huacai Chen | }; |
386 | d0f7453d | Huacai Chen | |
387 | d0f7453d | Huacai Chen | static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr) |
388 | d0f7453d | Huacai Chen | { |
389 | d0f7453d | Huacai Chen | uint32_t val; |
390 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
391 | d0f7453d | Huacai Chen | |
392 | d0f7453d | Huacai Chen | val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
|
393 | d0f7453d | Huacai Chen | |
394 | d0f7453d | Huacai Chen | return val;
|
395 | d0f7453d | Huacai Chen | } |
396 | d0f7453d | Huacai Chen | |
397 | d0f7453d | Huacai Chen | static void bonito_cop_writel(void *opaque, target_phys_addr_t addr, |
398 | d0f7453d | Huacai Chen | uint32_t val) |
399 | d0f7453d | Huacai Chen | { |
400 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
401 | d0f7453d | Huacai Chen | |
402 | d0f7453d | Huacai Chen | ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; |
403 | d0f7453d | Huacai Chen | } |
404 | d0f7453d | Huacai Chen | |
405 | d0f7453d | Huacai Chen | static CPUWriteMemoryFunc * const bonito_cop_write[] = { |
406 | d0f7453d | Huacai Chen | NULL,
|
407 | d0f7453d | Huacai Chen | NULL,
|
408 | d0f7453d | Huacai Chen | bonito_cop_writel, |
409 | d0f7453d | Huacai Chen | }; |
410 | d0f7453d | Huacai Chen | |
411 | d0f7453d | Huacai Chen | static CPUReadMemoryFunc * const bonito_cop_read[] = { |
412 | d0f7453d | Huacai Chen | NULL,
|
413 | d0f7453d | Huacai Chen | NULL,
|
414 | d0f7453d | Huacai Chen | bonito_cop_readl, |
415 | d0f7453d | Huacai Chen | }; |
416 | d0f7453d | Huacai Chen | |
417 | d0f7453d | Huacai Chen | static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr) |
418 | d0f7453d | Huacai Chen | { |
419 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
420 | d0f7453d | Huacai Chen | uint32_t cfgaddr; |
421 | d0f7453d | Huacai Chen | uint32_t idsel; |
422 | d0f7453d | Huacai Chen | uint32_t devno; |
423 | d0f7453d | Huacai Chen | uint32_t funno; |
424 | d0f7453d | Huacai Chen | uint32_t regno; |
425 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
426 | d0f7453d | Huacai Chen | |
427 | d0f7453d | Huacai Chen | /* support type0 pci config */
|
428 | d0f7453d | Huacai Chen | if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { |
429 | d0f7453d | Huacai Chen | return 0xffffffff; |
430 | d0f7453d | Huacai Chen | } |
431 | d0f7453d | Huacai Chen | |
432 | d0f7453d | Huacai Chen | cfgaddr = addr & 0xffff;
|
433 | d0f7453d | Huacai Chen | cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; |
434 | d0f7453d | Huacai Chen | |
435 | d0f7453d | Huacai Chen | idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; |
436 | d0f7453d | Huacai Chen | devno = ffs(idsel) - 1;
|
437 | d0f7453d | Huacai Chen | funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; |
438 | d0f7453d | Huacai Chen | regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; |
439 | d0f7453d | Huacai Chen | |
440 | d0f7453d | Huacai Chen | if (idsel == 0) { |
441 | d0f7453d | Huacai Chen | fprintf(stderr, "error in bonito pci config address" TARGET_FMT_plx
|
442 | d0f7453d | Huacai Chen | ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]);
|
443 | d0f7453d | Huacai Chen | exit(1);
|
444 | d0f7453d | Huacai Chen | } |
445 | d0f7453d | Huacai Chen | pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno); |
446 | b2bedb21 | Stefan Weil | DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
|
447 | d0f7453d | Huacai Chen | cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno); |
448 | d0f7453d | Huacai Chen | |
449 | d0f7453d | Huacai Chen | return pciaddr;
|
450 | d0f7453d | Huacai Chen | } |
451 | d0f7453d | Huacai Chen | |
452 | d0f7453d | Huacai Chen | static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr, |
453 | d0f7453d | Huacai Chen | uint32_t val) |
454 | d0f7453d | Huacai Chen | { |
455 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
456 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
457 | d0f7453d | Huacai Chen | uint16_t status; |
458 | d0f7453d | Huacai Chen | |
459 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val); |
460 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
461 | d0f7453d | Huacai Chen | |
462 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
463 | d0f7453d | Huacai Chen | return;
|
464 | d0f7453d | Huacai Chen | } |
465 | d0f7453d | Huacai Chen | |
466 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
467 | d0f7453d | Huacai Chen | s->pcihost->config_reg = (pciaddr) | (1u << 31); |
468 | d0f7453d | Huacai Chen | pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, 1); |
469 | d0f7453d | Huacai Chen | |
470 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
471 | d0f7453d | Huacai Chen | status = pci_get_word(s->dev.config + PCI_STATUS); |
472 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
473 | d0f7453d | Huacai Chen | pci_set_word(s->dev.config + PCI_STATUS, status); |
474 | d0f7453d | Huacai Chen | } |
475 | d0f7453d | Huacai Chen | |
476 | d0f7453d | Huacai Chen | static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr, |
477 | d0f7453d | Huacai Chen | uint32_t val) |
478 | d0f7453d | Huacai Chen | { |
479 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
480 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
481 | d0f7453d | Huacai Chen | uint16_t status; |
482 | d0f7453d | Huacai Chen | |
483 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val); |
484 | d0f7453d | Huacai Chen | assert((addr&0x1)==0); |
485 | d0f7453d | Huacai Chen | |
486 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
487 | d0f7453d | Huacai Chen | |
488 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
489 | d0f7453d | Huacai Chen | return;
|
490 | d0f7453d | Huacai Chen | } |
491 | d0f7453d | Huacai Chen | |
492 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
493 | d0f7453d | Huacai Chen | s->pcihost->config_reg = (pciaddr) | (1u << 31); |
494 | d0f7453d | Huacai Chen | pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2);
|
495 | d0f7453d | Huacai Chen | |
496 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
497 | d0f7453d | Huacai Chen | status = pci_get_word(s->dev.config + PCI_STATUS); |
498 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
499 | d0f7453d | Huacai Chen | pci_set_word(s->dev.config + PCI_STATUS, status); |
500 | d0f7453d | Huacai Chen | } |
501 | d0f7453d | Huacai Chen | |
502 | d0f7453d | Huacai Chen | static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr, |
503 | d0f7453d | Huacai Chen | uint32_t val) |
504 | d0f7453d | Huacai Chen | { |
505 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
506 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
507 | d0f7453d | Huacai Chen | uint16_t status; |
508 | d0f7453d | Huacai Chen | |
509 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); |
510 | d0f7453d | Huacai Chen | assert((addr&0x3)==0); |
511 | d0f7453d | Huacai Chen | |
512 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
513 | d0f7453d | Huacai Chen | |
514 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
515 | d0f7453d | Huacai Chen | return;
|
516 | d0f7453d | Huacai Chen | } |
517 | d0f7453d | Huacai Chen | |
518 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
519 | d0f7453d | Huacai Chen | s->pcihost->config_reg = (pciaddr) | (1u << 31); |
520 | d0f7453d | Huacai Chen | pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4);
|
521 | d0f7453d | Huacai Chen | |
522 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
523 | d0f7453d | Huacai Chen | status = pci_get_word(s->dev.config + PCI_STATUS); |
524 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
525 | d0f7453d | Huacai Chen | pci_set_word(s->dev.config + PCI_STATUS, status); |
526 | d0f7453d | Huacai Chen | } |
527 | d0f7453d | Huacai Chen | |
528 | d0f7453d | Huacai Chen | static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr) |
529 | d0f7453d | Huacai Chen | { |
530 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
531 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
532 | d0f7453d | Huacai Chen | uint16_t status; |
533 | d0f7453d | Huacai Chen | |
534 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr); |
535 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
536 | d0f7453d | Huacai Chen | |
537 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
538 | d0f7453d | Huacai Chen | return 0xff; |
539 | d0f7453d | Huacai Chen | } |
540 | d0f7453d | Huacai Chen | |
541 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
542 | d0f7453d | Huacai Chen | s->pcihost->config_reg = (pciaddr) | (1u << 31); |
543 | d0f7453d | Huacai Chen | |
544 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
545 | d0f7453d | Huacai Chen | status = pci_get_word(s->dev.config + PCI_STATUS); |
546 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
547 | d0f7453d | Huacai Chen | pci_set_word(s->dev.config + PCI_STATUS, status); |
548 | d0f7453d | Huacai Chen | |
549 | d0f7453d | Huacai Chen | return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1); |
550 | d0f7453d | Huacai Chen | } |
551 | d0f7453d | Huacai Chen | |
552 | d0f7453d | Huacai Chen | static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr) |
553 | d0f7453d | Huacai Chen | { |
554 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
555 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
556 | d0f7453d | Huacai Chen | uint16_t status; |
557 | d0f7453d | Huacai Chen | |
558 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); |
559 | d0f7453d | Huacai Chen | assert((addr&0x1)==0); |
560 | d0f7453d | Huacai Chen | |
561 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
562 | d0f7453d | Huacai Chen | |
563 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
564 | d0f7453d | Huacai Chen | return 0xffff; |
565 | d0f7453d | Huacai Chen | } |
566 | d0f7453d | Huacai Chen | |
567 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
568 | d0f7453d | Huacai Chen | s->pcihost->config_reg = (pciaddr) | (1u << 31); |
569 | d0f7453d | Huacai Chen | |
570 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
571 | d0f7453d | Huacai Chen | status = pci_get_word(s->dev.config + PCI_STATUS); |
572 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
573 | d0f7453d | Huacai Chen | pci_set_word(s->dev.config + PCI_STATUS, status); |
574 | d0f7453d | Huacai Chen | |
575 | d0f7453d | Huacai Chen | return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2); |
576 | d0f7453d | Huacai Chen | } |
577 | d0f7453d | Huacai Chen | |
578 | d0f7453d | Huacai Chen | static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr) |
579 | d0f7453d | Huacai Chen | { |
580 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
581 | d0f7453d | Huacai Chen | uint32_t pciaddr; |
582 | d0f7453d | Huacai Chen | uint16_t status; |
583 | d0f7453d | Huacai Chen | |
584 | b2bedb21 | Stefan Weil | DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); |
585 | d0f7453d | Huacai Chen | assert((addr&0x3) == 0); |
586 | d0f7453d | Huacai Chen | |
587 | d0f7453d | Huacai Chen | pciaddr = bonito_sbridge_pciaddr(s, addr); |
588 | d0f7453d | Huacai Chen | |
589 | d0f7453d | Huacai Chen | if (pciaddr == 0xffffffff) { |
590 | d0f7453d | Huacai Chen | return 0xffffffff; |
591 | d0f7453d | Huacai Chen | } |
592 | d0f7453d | Huacai Chen | |
593 | d0f7453d | Huacai Chen | /* set the pci address in s->config_reg */
|
594 | d0f7453d | Huacai Chen | s->pcihost->config_reg = (pciaddr) | (1u << 31); |
595 | d0f7453d | Huacai Chen | |
596 | d0f7453d | Huacai Chen | /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
|
597 | d0f7453d | Huacai Chen | status = pci_get_word(s->dev.config + PCI_STATUS); |
598 | d0f7453d | Huacai Chen | status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); |
599 | d0f7453d | Huacai Chen | pci_set_word(s->dev.config + PCI_STATUS, status); |
600 | d0f7453d | Huacai Chen | |
601 | d0f7453d | Huacai Chen | return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4); |
602 | d0f7453d | Huacai Chen | } |
603 | d0f7453d | Huacai Chen | |
604 | d0f7453d | Huacai Chen | /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
|
605 | d0f7453d | Huacai Chen | static CPUWriteMemoryFunc * const bonito_spciconf_write[] = { |
606 | d0f7453d | Huacai Chen | bonito_spciconf_writeb, |
607 | d0f7453d | Huacai Chen | bonito_spciconf_writew, |
608 | d0f7453d | Huacai Chen | bonito_spciconf_writel, |
609 | d0f7453d | Huacai Chen | }; |
610 | d0f7453d | Huacai Chen | |
611 | d0f7453d | Huacai Chen | static CPUReadMemoryFunc * const bonito_spciconf_read[] = { |
612 | d0f7453d | Huacai Chen | bonito_spciconf_readb, |
613 | d0f7453d | Huacai Chen | bonito_spciconf_readw, |
614 | d0f7453d | Huacai Chen | bonito_spciconf_readl, |
615 | d0f7453d | Huacai Chen | }; |
616 | d0f7453d | Huacai Chen | |
617 | d0f7453d | Huacai Chen | #define BONITO_IRQ_BASE 32 |
618 | d0f7453d | Huacai Chen | |
619 | d0f7453d | Huacai Chen | static void pci_bonito_set_irq(void *opaque, int irq_num, int level) |
620 | d0f7453d | Huacai Chen | { |
621 | d0f7453d | Huacai Chen | qemu_irq *pic = opaque; |
622 | d0f7453d | Huacai Chen | int internal_irq = irq_num - BONITO_IRQ_BASE;
|
623 | d0f7453d | Huacai Chen | |
624 | d0f7453d | Huacai Chen | if (bonito_state->regs[BONITO_INTEDGE] & (1<<internal_irq)) { |
625 | d0f7453d | Huacai Chen | qemu_irq_pulse(*pic); |
626 | d0f7453d | Huacai Chen | } else { /* level triggered */ |
627 | d0f7453d | Huacai Chen | if (bonito_state->regs[BONITO_INTPOL] & (1<<internal_irq)) { |
628 | d0f7453d | Huacai Chen | qemu_irq_raise(*pic); |
629 | d0f7453d | Huacai Chen | } else {
|
630 | d0f7453d | Huacai Chen | qemu_irq_lower(*pic); |
631 | d0f7453d | Huacai Chen | } |
632 | d0f7453d | Huacai Chen | } |
633 | d0f7453d | Huacai Chen | } |
634 | d0f7453d | Huacai Chen | |
635 | d0f7453d | Huacai Chen | /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
|
636 | d0f7453d | Huacai Chen | static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) |
637 | d0f7453d | Huacai Chen | { |
638 | d0f7453d | Huacai Chen | int slot;
|
639 | d0f7453d | Huacai Chen | |
640 | d0f7453d | Huacai Chen | slot = (pci_dev->devfn >> 3);
|
641 | d0f7453d | Huacai Chen | |
642 | d0f7453d | Huacai Chen | switch (slot) {
|
643 | d0f7453d | Huacai Chen | case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ |
644 | d0f7453d | Huacai Chen | return irq_num % 4 + BONITO_IRQ_BASE; |
645 | d0f7453d | Huacai Chen | case 6: /* FULONG2E_ATI_SLOT, VGA */ |
646 | d0f7453d | Huacai Chen | return 4 + BONITO_IRQ_BASE; |
647 | d0f7453d | Huacai Chen | case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ |
648 | d0f7453d | Huacai Chen | return 5 + BONITO_IRQ_BASE; |
649 | d0f7453d | Huacai Chen | case 8 ... 12: /* PCI slot 1 to 4 */ |
650 | d0f7453d | Huacai Chen | return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; |
651 | d0f7453d | Huacai Chen | default: /* Unknown device, don't do any translation */ |
652 | d0f7453d | Huacai Chen | return irq_num;
|
653 | d0f7453d | Huacai Chen | } |
654 | d0f7453d | Huacai Chen | } |
655 | d0f7453d | Huacai Chen | |
656 | d0f7453d | Huacai Chen | static void bonito_reset(void *opaque) |
657 | d0f7453d | Huacai Chen | { |
658 | d0f7453d | Huacai Chen | PCIBonitoState *s = opaque; |
659 | d0f7453d | Huacai Chen | |
660 | d0f7453d | Huacai Chen | /* set the default value of north bridge registers */
|
661 | d0f7453d | Huacai Chen | |
662 | d0f7453d | Huacai Chen | s->regs[BONITO_BONPONCFG] = 0xc40;
|
663 | d0f7453d | Huacai Chen | s->regs[BONITO_BONGENCFG] = 0x1384;
|
664 | d0f7453d | Huacai Chen | s->regs[BONITO_IODEVCFG] = 0x2bff8010;
|
665 | d0f7453d | Huacai Chen | s->regs[BONITO_SDCFG] = 0x255e0091;
|
666 | d0f7453d | Huacai Chen | |
667 | d0f7453d | Huacai Chen | s->regs[BONITO_GPIODATA] = 0x1ff;
|
668 | d0f7453d | Huacai Chen | s->regs[BONITO_GPIOIE] = 0x1ff;
|
669 | d0f7453d | Huacai Chen | s->regs[BONITO_DQCFG] = 0x8;
|
670 | d0f7453d | Huacai Chen | s->regs[BONITO_MEMSIZE] = 0x10000000;
|
671 | d0f7453d | Huacai Chen | s->regs[BONITO_PCIMAP] = 0x6140;
|
672 | d0f7453d | Huacai Chen | } |
673 | d0f7453d | Huacai Chen | |
674 | d0f7453d | Huacai Chen | static const VMStateDescription vmstate_bonito = { |
675 | d0f7453d | Huacai Chen | .name = "Bonito",
|
676 | d0f7453d | Huacai Chen | .version_id = 1,
|
677 | d0f7453d | Huacai Chen | .minimum_version_id = 1,
|
678 | d0f7453d | Huacai Chen | .minimum_version_id_old = 1,
|
679 | d0f7453d | Huacai Chen | .fields = (VMStateField []) { |
680 | d0f7453d | Huacai Chen | VMSTATE_PCI_DEVICE(dev, PCIBonitoState), |
681 | d0f7453d | Huacai Chen | VMSTATE_END_OF_LIST() |
682 | d0f7453d | Huacai Chen | } |
683 | d0f7453d | Huacai Chen | }; |
684 | d0f7453d | Huacai Chen | |
685 | d0f7453d | Huacai Chen | static int bonito_pcihost_initfn(SysBusDevice *dev) |
686 | d0f7453d | Huacai Chen | { |
687 | d0f7453d | Huacai Chen | return 0; |
688 | d0f7453d | Huacai Chen | } |
689 | d0f7453d | Huacai Chen | |
690 | d0f7453d | Huacai Chen | static int bonito_initfn(PCIDevice *dev) |
691 | d0f7453d | Huacai Chen | { |
692 | d0f7453d | Huacai Chen | PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); |
693 | d0f7453d | Huacai Chen | |
694 | d0f7453d | Huacai Chen | /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
|
695 | d0f7453d | Huacai Chen | pci_config_set_prog_interface(dev->config, 0x00);
|
696 | d0f7453d | Huacai Chen | |
697 | d0f7453d | Huacai Chen | /* set the north bridge register mapping */
|
698 | 2507c12a | Alexander Graf | s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s, |
699 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
700 | d0f7453d | Huacai Chen | s->bonito_reg_start = BONITO_INTERNAL_REG_BASE; |
701 | d0f7453d | Huacai Chen | s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE; |
702 | d0f7453d | Huacai Chen | cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length, |
703 | d0f7453d | Huacai Chen | s->bonito_reg_handle); |
704 | d0f7453d | Huacai Chen | |
705 | d0f7453d | Huacai Chen | /* set the north bridge pci configure mapping */
|
706 | d0f7453d | Huacai Chen | s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read, |
707 | 2507c12a | Alexander Graf | bonito_pciconf_write, s, |
708 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
709 | d0f7453d | Huacai Chen | s->bonito_pciconf_start = BONITO_PCICONFIG_BASE; |
710 | d0f7453d | Huacai Chen | s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE; |
711 | d0f7453d | Huacai Chen | cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length, |
712 | d0f7453d | Huacai Chen | s->bonito_pciconf_handle); |
713 | d0f7453d | Huacai Chen | |
714 | d0f7453d | Huacai Chen | /* set the south bridge pci configure mapping */
|
715 | d0f7453d | Huacai Chen | s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read, |
716 | 2507c12a | Alexander Graf | bonito_spciconf_write, s, |
717 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
718 | d0f7453d | Huacai Chen | s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE; |
719 | d0f7453d | Huacai Chen | s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE; |
720 | d0f7453d | Huacai Chen | cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length, |
721 | d0f7453d | Huacai Chen | s->bonito_spciconf_handle); |
722 | d0f7453d | Huacai Chen | |
723 | d0f7453d | Huacai Chen | s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read, |
724 | 2507c12a | Alexander Graf | bonito_ldma_write, s, |
725 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
726 | d0f7453d | Huacai Chen | s->bonito_ldma_start = 0xbfe00200;
|
727 | d0f7453d | Huacai Chen | s->bonito_ldma_length = 0x100;
|
728 | d0f7453d | Huacai Chen | cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length, |
729 | d0f7453d | Huacai Chen | s->bonito_ldma_handle); |
730 | d0f7453d | Huacai Chen | |
731 | d0f7453d | Huacai Chen | s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read, |
732 | 2507c12a | Alexander Graf | bonito_cop_write, s, |
733 | 2507c12a | Alexander Graf | DEVICE_NATIVE_ENDIAN); |
734 | d0f7453d | Huacai Chen | s->bonito_cop_start = 0xbfe00300;
|
735 | d0f7453d | Huacai Chen | s->bonito_cop_length = 0x100;
|
736 | d0f7453d | Huacai Chen | cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length, |
737 | d0f7453d | Huacai Chen | s->bonito_cop_handle); |
738 | d0f7453d | Huacai Chen | |
739 | d0f7453d | Huacai Chen | /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
|
740 | d0f7453d | Huacai Chen | s->bonito_pciio_start = BONITO_PCIIO_BASE; |
741 | d0f7453d | Huacai Chen | s->bonito_pciio_length = BONITO_PCIIO_SIZE; |
742 | d0f7453d | Huacai Chen | isa_mem_base = s->bonito_pciio_start; |
743 | 968d683c | Alexander Graf | isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length); |
744 | d0f7453d | Huacai Chen | |
745 | d0f7453d | Huacai Chen | /* add pci local io mapping */
|
746 | d0f7453d | Huacai Chen | s->bonito_localio_start = BONITO_DEV_BASE; |
747 | d0f7453d | Huacai Chen | s->bonito_localio_length = BONITO_DEV_SIZE; |
748 | 968d683c | Alexander Graf | isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length); |
749 | d0f7453d | Huacai Chen | |
750 | d0f7453d | Huacai Chen | /* set the default value of north bridge pci config */
|
751 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_COMMAND, 0x0000);
|
752 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_STATUS, 0x0000);
|
753 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
|
754 | d0f7453d | Huacai Chen | pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
|
755 | d0f7453d | Huacai Chen | |
756 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
|
757 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
|
758 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
|
759 | d0f7453d | Huacai Chen | pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
|
760 | d0f7453d | Huacai Chen | |
761 | d0f7453d | Huacai Chen | qemu_register_reset(bonito_reset, s); |
762 | d0f7453d | Huacai Chen | |
763 | d0f7453d | Huacai Chen | return 0; |
764 | d0f7453d | Huacai Chen | } |
765 | d0f7453d | Huacai Chen | |
766 | d0f7453d | Huacai Chen | PCIBus *bonito_init(qemu_irq *pic) |
767 | d0f7453d | Huacai Chen | { |
768 | d0f7453d | Huacai Chen | DeviceState *dev; |
769 | d0f7453d | Huacai Chen | PCIBus *b; |
770 | d0f7453d | Huacai Chen | BonitoState *pcihost; |
771 | d0f7453d | Huacai Chen | PCIBonitoState *s; |
772 | d0f7453d | Huacai Chen | PCIDevice *d; |
773 | d0f7453d | Huacai Chen | |
774 | d0f7453d | Huacai Chen | dev = qdev_create(NULL, "Bonito-pcihost"); |
775 | d0f7453d | Huacai Chen | pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev)); |
776 | d0f7453d | Huacai Chen | b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq,
|
777 | 1e39101c | Avi Kivity | pci_bonito_map_irq, pic, get_system_memory(), |
778 | aee97b84 | Avi Kivity | get_system_io(), |
779 | 1e39101c | Avi Kivity | 0x28, 32); |
780 | d0f7453d | Huacai Chen | pcihost->bus = b; |
781 | d0f7453d | Huacai Chen | qdev_init_nofail(dev); |
782 | d0f7453d | Huacai Chen | |
783 | d0f7453d | Huacai Chen | d = pci_create_simple(b, PCI_DEVFN(0, 0), "Bonito"); |
784 | d0f7453d | Huacai Chen | s = DO_UPCAST(PCIBonitoState, dev, d); |
785 | d0f7453d | Huacai Chen | s->pcihost = pcihost; |
786 | d0f7453d | Huacai Chen | bonito_state = s; |
787 | d0f7453d | Huacai Chen | |
788 | d0f7453d | Huacai Chen | return b;
|
789 | d0f7453d | Huacai Chen | } |
790 | d0f7453d | Huacai Chen | |
791 | d0f7453d | Huacai Chen | static PCIDeviceInfo bonito_info = {
|
792 | d0f7453d | Huacai Chen | .qdev.name = "Bonito",
|
793 | d0f7453d | Huacai Chen | .qdev.desc = "Host bridge",
|
794 | d0f7453d | Huacai Chen | .qdev.size = sizeof(PCIBonitoState),
|
795 | d0f7453d | Huacai Chen | .qdev.vmsd = &vmstate_bonito, |
796 | d0f7453d | Huacai Chen | .qdev.no_user = 1,
|
797 | d0f7453d | Huacai Chen | .init = bonito_initfn, |
798 | 51387f86 | Isaku Yamahata | /*Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"*/
|
799 | 51387f86 | Isaku Yamahata | .vendor_id = 0xdf53,
|
800 | 51387f86 | Isaku Yamahata | .device_id = 0x00d5,
|
801 | 51387f86 | Isaku Yamahata | .revision = 0x01,
|
802 | 51387f86 | Isaku Yamahata | .class_id = PCI_CLASS_BRIDGE_HOST, |
803 | d0f7453d | Huacai Chen | }; |
804 | d0f7453d | Huacai Chen | |
805 | d0f7453d | Huacai Chen | static SysBusDeviceInfo bonito_pcihost_info = {
|
806 | d0f7453d | Huacai Chen | .init = bonito_pcihost_initfn, |
807 | d0f7453d | Huacai Chen | .qdev.name = "Bonito-pcihost",
|
808 | d0f7453d | Huacai Chen | .qdev.size = sizeof(BonitoState),
|
809 | d0f7453d | Huacai Chen | .qdev.no_user = 1,
|
810 | d0f7453d | Huacai Chen | }; |
811 | d0f7453d | Huacai Chen | |
812 | d0f7453d | Huacai Chen | static void bonito_register(void) |
813 | d0f7453d | Huacai Chen | { |
814 | d0f7453d | Huacai Chen | sysbus_register_withprop(&bonito_pcihost_info); |
815 | d0f7453d | Huacai Chen | pci_qdev_register(&bonito_info); |
816 | d0f7453d | Huacai Chen | } |
817 | d0f7453d | Huacai Chen | device_init(bonito_register); |