Revision da726e5e hw/ppc4xx_pci.c
b/hw/ppc4xx_pci.c | ||
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54 | 54 |
|
55 | 55 |
PCIHostState pci_state; |
56 | 56 |
PCIDevice *pci_dev; |
57 |
MemoryRegion iomem_addr; |
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MemoryRegion iomem_regs; |
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57 | 59 |
}; |
58 | 60 |
typedef struct PPC4xxPCIState PPC4xxPCIState; |
59 | 61 |
|
... | ... | |
84 | 86 |
#define PCI_REG_SIZE 0x40 |
85 | 87 |
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86 | 88 |
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static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr) |
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static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr, |
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unsigned size) |
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88 | 91 |
{ |
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PPC4xxPCIState *ppc4xx_pci = opaque; |
90 | 93 |
|
91 | 94 |
return ppc4xx_pci->pci_state.config_reg; |
92 | 95 |
} |
93 | 96 |
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static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = { |
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&pci4xx_cfgaddr_readl, |
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&pci4xx_cfgaddr_readl, |
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&pci4xx_cfgaddr_readl, |
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}; |
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99 |
|
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static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr, |
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uint64_t value, unsigned size) |
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102 | 99 |
{ |
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PPC4xxPCIState *ppc4xx_pci = opaque; |
104 | 101 |
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105 | 102 |
ppc4xx_pci->pci_state.config_reg = value & ~0x3; |
106 | 103 |
} |
107 | 104 |
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static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
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&pci4xx_cfgaddr_writel,
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&pci4xx_cfgaddr_writel,
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&pci4xx_cfgaddr_writel,
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static const MemoryRegionOps pci4xx_cfgaddr_ops = {
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.read = pci4xx_cfgaddr_read,
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.write = pci4xx_cfgaddr_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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112 | 109 |
}; |
113 | 110 |
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114 | 111 |
static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, |
115 |
uint32_t value)
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uint64_t value, unsigned size)
|
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116 | 113 |
{ |
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struct PPC4xxPCIState *pci = opaque; |
118 | 115 |
|
... | ... | |
179 | 176 |
} |
180 | 177 |
} |
181 | 178 |
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static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset) |
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static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset, |
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unsigned size) |
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183 | 181 |
{ |
184 | 182 |
struct PPC4xxPCIState *pci = opaque; |
185 | 183 |
uint32_t value; |
... | ... | |
246 | 244 |
return value; |
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} |
248 | 246 |
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static CPUReadMemoryFunc * const pci_reg_read[] = { |
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&ppc4xx_pci_reg_read4, |
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&ppc4xx_pci_reg_read4, |
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&ppc4xx_pci_reg_read4, |
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}; |
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254 |
|
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static CPUWriteMemoryFunc * const pci_reg_write[] = { |
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&ppc4xx_pci_reg_write4, |
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&ppc4xx_pci_reg_write4, |
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&ppc4xx_pci_reg_write4, |
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static const MemoryRegionOps pci_reg_ops = { |
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.read = ppc4xx_pci_reg_read4, |
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.write = ppc4xx_pci_reg_write4, |
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.endianness = DEVICE_LITTLE_ENDIAN, |
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259 | 251 |
}; |
260 | 252 |
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261 | 253 |
static void ppc4xx_pci_reset(void *opaque) |
... | ... | |
337 | 329 |
target_phys_addr_t registers) |
338 | 330 |
{ |
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PPC4xxPCIState *controller; |
340 |
int index; |
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341 | 332 |
static int ppc4xx_pci_id; |
342 | 333 |
uint8_t *pci_conf; |
343 | 334 |
|
... | ... | |
360 | 351 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
361 | 352 |
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362 | 353 |
/* CFGADDR */ |
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index = cpu_register_io_memory(pci4xx_cfgaddr_read, |
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pci4xx_cfgaddr_write, controller, |
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DEVICE_LITTLE_ENDIAN); |
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if (index < 0) |
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goto free; |
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cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); |
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memory_region_init_io(&controller->iomem_addr, &pci4xx_cfgaddr_ops, |
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controller, "pci.cfgaddr", 4); |
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memory_region_add_subregion(get_system_memory(), |
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config_space + PCIC0_CFGADDR, |
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&controller->iomem_addr); |
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369 | 359 |
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370 | 360 |
/* CFGDATA */ |
371 | 361 |
memory_region_init_io(&controller->pci_state.data_mem, |
... | ... | |
376 | 366 |
&controller->pci_state.data_mem); |
377 | 367 |
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378 | 368 |
/* Internal registers */ |
379 |
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, |
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DEVICE_LITTLE_ENDIAN); |
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if (index < 0) |
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goto free; |
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cpu_register_physical_memory(registers, PCI_REG_SIZE, index); |
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memory_region_init_io(&controller->iomem_regs, &pci_reg_ops, controller, |
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"pci.regs", PCI_REG_SIZE); |
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memory_region_add_subregion(get_system_memory(), registers, |
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&controller->iomem_regs); |
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384 | 373 |
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385 | 374 |
qemu_register_reset(ppc4xx_pci_reset, controller); |
386 | 375 |
|
... | ... | |
389 | 378 |
&vmstate_ppc4xx_pci, controller); |
390 | 379 |
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391 | 380 |
return controller->pci_state.bus; |
392 |
|
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free: |
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printf("%s error\n", __func__); |
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g_free(controller); |
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return NULL; |
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397 | 381 |
} |
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