Revision da726e5e hw/ppc4xx_pci.c

b/hw/ppc4xx_pci.c
54 54

  
55 55
    PCIHostState pci_state;
56 56
    PCIDevice *pci_dev;
57
    MemoryRegion iomem_addr;
58
    MemoryRegion iomem_regs;
57 59
};
58 60
typedef struct PPC4xxPCIState PPC4xxPCIState;
59 61

  
......
84 86
#define PCI_REG_SIZE        0x40
85 87

  
86 88

  
87
static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
89
static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
90
                                    unsigned size)
88 91
{
89 92
    PPC4xxPCIState *ppc4xx_pci = opaque;
90 93

  
91 94
    return ppc4xx_pci->pci_state.config_reg;
92 95
}
93 96

  
94
static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
95
    &pci4xx_cfgaddr_readl,
96
    &pci4xx_cfgaddr_readl,
97
    &pci4xx_cfgaddr_readl,
98
};
99

  
100
static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
101
                                  uint32_t value)
97
static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
98
                                  uint64_t value, unsigned size)
102 99
{
103 100
    PPC4xxPCIState *ppc4xx_pci = opaque;
104 101

  
105 102
    ppc4xx_pci->pci_state.config_reg = value & ~0x3;
106 103
}
107 104

  
108
static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
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    &pci4xx_cfgaddr_writel,
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    &pci4xx_cfgaddr_writel,
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    &pci4xx_cfgaddr_writel,
105
static const MemoryRegionOps pci4xx_cfgaddr_ops = {
106
    .read = pci4xx_cfgaddr_read,
107
    .write = pci4xx_cfgaddr_write,
108
    .endianness = DEVICE_LITTLE_ENDIAN,
112 109
};
113 110

  
114 111
static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
115
                                  uint32_t value)
112
                                  uint64_t value, unsigned size)
116 113
{
117 114
    struct PPC4xxPCIState *pci = opaque;
118 115

  
......
179 176
    }
180 177
}
181 178

  
182
static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
179
static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
180
                                     unsigned size)
183 181
{
184 182
    struct PPC4xxPCIState *pci = opaque;
185 183
    uint32_t value;
......
246 244
    return value;
247 245
}
248 246

  
249
static CPUReadMemoryFunc * const pci_reg_read[] = {
250
    &ppc4xx_pci_reg_read4,
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    &ppc4xx_pci_reg_read4,
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    &ppc4xx_pci_reg_read4,
253
};
254

  
255
static CPUWriteMemoryFunc * const pci_reg_write[] = {
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    &ppc4xx_pci_reg_write4,
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    &ppc4xx_pci_reg_write4,
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    &ppc4xx_pci_reg_write4,
247
static const MemoryRegionOps pci_reg_ops = {
248
    .read = ppc4xx_pci_reg_read4,
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    .write = ppc4xx_pci_reg_write4,
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    .endianness = DEVICE_LITTLE_ENDIAN,
259 251
};
260 252

  
261 253
static void ppc4xx_pci_reset(void *opaque)
......
337 329
                        target_phys_addr_t registers)
338 330
{
339 331
    PPC4xxPCIState *controller;
340
    int index;
341 332
    static int ppc4xx_pci_id;
342 333
    uint8_t *pci_conf;
343 334

  
......
360 351
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
361 352

  
362 353
    /* CFGADDR */
363
    index = cpu_register_io_memory(pci4xx_cfgaddr_read,
364
                                   pci4xx_cfgaddr_write, controller,
365
                                   DEVICE_LITTLE_ENDIAN);
366
    if (index < 0)
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        goto free;
368
    cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
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    memory_region_init_io(&controller->iomem_addr, &pci4xx_cfgaddr_ops,
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                          controller, "pci.cfgaddr", 4);
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    memory_region_add_subregion(get_system_memory(),
357
                                config_space + PCIC0_CFGADDR,
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                                &controller->iomem_addr);
369 359

  
370 360
    /* CFGDATA */
371 361
    memory_region_init_io(&controller->pci_state.data_mem,
......
376 366
                                &controller->pci_state.data_mem);
377 367

  
378 368
    /* Internal registers */
379
    index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
380
                                   DEVICE_LITTLE_ENDIAN);
381
    if (index < 0)
382
        goto free;
383
    cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
369
    memory_region_init_io(&controller->iomem_regs, &pci_reg_ops, controller,
370
                          "pci.regs", PCI_REG_SIZE);
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    memory_region_add_subregion(get_system_memory(), registers,
372
                                &controller->iomem_regs);
384 373

  
385 374
    qemu_register_reset(ppc4xx_pci_reset, controller);
386 375

  
......
389 378
                     &vmstate_ppc4xx_pci, controller);
390 379

  
391 380
    return controller->pci_state.bus;
392

  
393
free:
394
    printf("%s error\n", __func__);
395
    g_free(controller);
396
    return NULL;
397 381
}

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