root / hw / etraxfs_dma.c @ da726e5e
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/*
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* QEMU ETRAX DMA Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <stdio.h> |
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#include <sys/time.h> |
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#include "hw.h" |
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#include "exec-memory.h" |
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#include "qemu-common.h" |
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#include "sysemu.h" |
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#include "etraxfs_dma.h" |
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#define D(x)
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#define RW_DATA (0x0 / 4) |
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#define RW_SAVED_DATA (0x58 / 4) |
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#define RW_SAVED_DATA_BUF (0x5c / 4) |
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#define RW_GROUP (0x60 / 4) |
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#define RW_GROUP_DOWN (0x7c / 4) |
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#define RW_CMD (0x80 / 4) |
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#define RW_CFG (0x84 / 4) |
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#define RW_STAT (0x88 / 4) |
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#define RW_INTR_MASK (0x8c / 4) |
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#define RW_ACK_INTR (0x90 / 4) |
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#define R_INTR (0x94 / 4) |
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#define R_MASKED_INTR (0x98 / 4) |
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#define RW_STREAM_CMD (0x9c / 4) |
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#define DMA_REG_MAX (0x100 / 4) |
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/* descriptors */
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// ------------------------------------------------------------ dma_descr_group
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typedef struct dma_descr_group { |
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uint32_t next; |
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unsigned eol : 1; |
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unsigned tol : 1; |
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unsigned bol : 1; |
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unsigned : 1; |
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unsigned intr : 1; |
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unsigned : 2; |
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unsigned en : 1; |
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unsigned : 7; |
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unsigned dis : 1; |
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unsigned md : 16; |
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struct dma_descr_group *up;
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union {
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struct dma_descr_context *context;
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struct dma_descr_group *group;
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} down; |
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} dma_descr_group; |
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// ---------------------------------------------------------- dma_descr_context
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typedef struct dma_descr_context { |
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uint32_t next; |
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unsigned eol : 1; |
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unsigned : 3; |
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unsigned intr : 1; |
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unsigned : 1; |
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unsigned store_mode : 1; |
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unsigned en : 1; |
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unsigned : 7; |
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unsigned dis : 1; |
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unsigned md0 : 16; |
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unsigned md1;
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unsigned md2;
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unsigned md3;
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unsigned md4;
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uint32_t saved_data; |
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uint32_t saved_data_buf; |
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} dma_descr_context; |
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// ------------------------------------------------------------- dma_descr_data
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typedef struct dma_descr_data { |
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uint32_t next; |
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uint32_t buf; |
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unsigned eol : 1; |
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unsigned : 2; |
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unsigned out_eop : 1; |
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unsigned intr : 1; |
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unsigned wait : 1; |
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unsigned : 2; |
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unsigned : 3; |
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unsigned in_eop : 1; |
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unsigned : 4; |
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unsigned md : 16; |
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uint32_t after; |
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} dma_descr_data; |
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/* Constants */
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enum {
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regk_dma_ack_pkt = 0x00000100,
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regk_dma_anytime = 0x00000001,
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regk_dma_array = 0x00000008,
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regk_dma_burst = 0x00000020,
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regk_dma_client = 0x00000002,
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regk_dma_copy_next = 0x00000010,
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regk_dma_copy_up = 0x00000020,
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regk_dma_data_at_eol = 0x00000001,
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regk_dma_dis_c = 0x00000010,
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regk_dma_dis_g = 0x00000020,
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regk_dma_idle = 0x00000001,
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regk_dma_intern = 0x00000004,
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regk_dma_load_c = 0x00000200,
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regk_dma_load_c_n = 0x00000280,
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regk_dma_load_c_next = 0x00000240,
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regk_dma_load_d = 0x00000140,
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regk_dma_load_g = 0x00000300,
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regk_dma_load_g_down = 0x000003c0,
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regk_dma_load_g_next = 0x00000340,
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regk_dma_load_g_up = 0x00000380,
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regk_dma_next_en = 0x00000010,
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regk_dma_next_pkt = 0x00000010,
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regk_dma_no = 0x00000000,
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regk_dma_only_at_wait = 0x00000000,
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regk_dma_restore = 0x00000020,
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regk_dma_rst = 0x00000001,
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regk_dma_running = 0x00000004,
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regk_dma_rw_cfg_default = 0x00000000,
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regk_dma_rw_cmd_default = 0x00000000,
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regk_dma_rw_intr_mask_default = 0x00000000,
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regk_dma_rw_stat_default = 0x00000101,
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regk_dma_rw_stream_cmd_default = 0x00000000,
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regk_dma_save_down = 0x00000020,
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regk_dma_save_up = 0x00000020,
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regk_dma_set_reg = 0x00000050,
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regk_dma_set_w_size1 = 0x00000190,
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regk_dma_set_w_size2 = 0x000001a0,
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regk_dma_set_w_size4 = 0x000001c0,
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regk_dma_stopped = 0x00000002,
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regk_dma_store_c = 0x00000002,
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regk_dma_store_descr = 0x00000000,
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regk_dma_store_g = 0x00000004,
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regk_dma_store_md = 0x00000001,
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regk_dma_sw = 0x00000008,
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regk_dma_update_down = 0x00000020,
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regk_dma_yes = 0x00000001
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}; |
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enum dma_ch_state
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{ |
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RST = 1,
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STOPPED = 2,
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RUNNING = 4
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}; |
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struct fs_dma_channel
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{ |
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qemu_irq irq; |
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struct etraxfs_dma_client *client;
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/* Internal status. */
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int stream_cmd_src;
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enum dma_ch_state state;
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unsigned int input : 1; |
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unsigned int eol : 1; |
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struct dma_descr_group current_g;
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struct dma_descr_context current_c;
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struct dma_descr_data current_d;
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/* Controll registers. */
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uint32_t regs[DMA_REG_MAX]; |
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}; |
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struct fs_dma_ctrl
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{ |
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MemoryRegion mmio; |
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int nr_channels;
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struct fs_dma_channel *channels;
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QEMUBH *bh; |
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}; |
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static void DMA_run(void *opaque); |
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static int channel_out_run(struct fs_dma_ctrl *ctrl, int c); |
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static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) |
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{ |
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return ctrl->channels[c].regs[reg];
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} |
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static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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return channel_reg(ctrl, c, RW_CFG) & 2; |
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} |
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static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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return (channel_reg(ctrl, c, RW_CFG) & 1) |
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&& ctrl->channels[c].client; |
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} |
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static inline int fs_channel(target_phys_addr_t addr) |
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{ |
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/* Every channel has a 0x2000 ctrl register map. */
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return addr >> 13; |
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} |
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#ifdef USE_THIS_DEAD_CODE
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static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); |
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_g,
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sizeof ctrl->channels[c].current_g);
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} |
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static void dump_c(int ch, struct dma_descr_context *c) |
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{ |
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%x\n", c->next);
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printf("saved_data=%x\n", c->saved_data);
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printf("saved_data_buf=%x\n", c->saved_data_buf);
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printf("eol=%x\n", (uint32_t) c->eol);
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} |
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static void dump_d(int ch, struct dma_descr_data *d) |
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{ |
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printf("%s ch=%d\n", __func__, ch);
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printf("next=%x\n", d->next);
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printf("buf=%x\n", d->buf);
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printf("after=%x\n", d->after);
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printf("intr=%x\n", (uint32_t) d->intr);
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printf("out_eop=%x\n", (uint32_t) d->out_eop);
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printf("in_eop=%x\n", (uint32_t) d->in_eop);
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printf("eol=%x\n", (uint32_t) d->eol);
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} |
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#endif
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static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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/* Load and decode. FIXME: handle endianness. */
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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D(dump_c(c, &ctrl->channels[c].current_c)); |
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/* I guess this should update the current pos. */
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ctrl->channels[c].regs[RW_SAVED_DATA] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
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} |
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static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); |
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cpu_physical_memory_read (addr, |
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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ctrl->channels[c].regs[RW_DATA] = addr; |
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} |
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static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); |
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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cpu_physical_memory_write (addr, |
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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} |
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); |
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cpu_physical_memory_write (addr, |
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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} |
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static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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/* FIXME: */
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} |
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static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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if (ctrl->channels[c].client)
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{ |
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ctrl->channels[c].eol = 0;
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ctrl->channels[c].state = RUNNING; |
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if (!ctrl->channels[c].input)
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channel_out_run(ctrl, c); |
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} else
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printf("WARNING: starting DMA ch %d with no client\n", c);
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qemu_bh_schedule_idle(ctrl->bh); |
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} |
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static void channel_continue(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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if (!channel_en(ctrl, c)
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|| channel_stopped(ctrl, c) |
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|| ctrl->channels[c].state != RUNNING |
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/* Only reload the current data descriptor if it has eol set. */
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|| !ctrl->channels[c].current_d.eol) { |
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D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
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c, ctrl->channels[c].state, |
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channel_stopped(ctrl, c), |
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channel_en(ctrl,c), |
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ctrl->channels[c].eol)); |
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D(dump_d(c, &ctrl->channels[c].current_d)); |
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return;
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} |
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/* Reload the current descriptor. */
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channel_load_d(ctrl, c); |
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/* If the current descriptor cleared the eol flag and we had already
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reached eol state, do the continue. */
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if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
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D(printf("continue %d ok %x\n", c,
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ctrl->channels[c].current_d.next)); |
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ctrl->channels[c].regs[RW_SAVED_DATA] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
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channel_load_d(ctrl, c); |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
356 |
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channel_start(ctrl, c); |
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} |
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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(uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
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} |
362 |
|
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static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) |
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{ |
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unsigned int cmd = v & ((1 << 10) - 1); |
366 |
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D(printf("%s ch=%d cmd=%x\n",
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__func__, c, cmd)); |
369 |
if (cmd & regk_dma_load_d) {
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channel_load_d(ctrl, c); |
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if (cmd & regk_dma_burst)
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channel_start(ctrl, c); |
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} |
374 |
|
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if (cmd & regk_dma_load_c) {
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channel_load_c(ctrl, c); |
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} |
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} |
379 |
|
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static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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D(printf("%s %d\n", __func__, c));
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ctrl->channels[c].regs[R_INTR] &= |
384 |
~(ctrl->channels[c].regs[RW_ACK_INTR]); |
385 |
|
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ctrl->channels[c].regs[R_MASKED_INTR] = |
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ctrl->channels[c].regs[R_INTR] |
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& ctrl->channels[c].regs[RW_INTR_MASK]; |
389 |
|
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D(printf("%s: chan=%d masked_intr=%x\n", __func__,
|
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c, |
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ctrl->channels[c].regs[R_MASKED_INTR])); |
393 |
|
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qemu_set_irq(ctrl->channels[c].irq, |
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!!ctrl->channels[c].regs[R_MASKED_INTR]); |
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} |
397 |
|
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static int channel_out_run(struct fs_dma_ctrl *ctrl, int c) |
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{ |
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uint32_t len; |
401 |
uint32_t saved_data_buf; |
402 |
unsigned char buf[2 * 1024]; |
403 |
|
404 |
if (ctrl->channels[c].eol)
|
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return 0; |
406 |
|
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do {
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D(printf("ch=%d buf=%x after=%x\n",
|
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c, |
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(uint32_t)ctrl->channels[c].current_d.buf, |
411 |
(uint32_t)ctrl->channels[c].current_d.after)); |
412 |
|
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channel_load_d(ctrl, c); |
414 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
415 |
len = (uint32_t)(unsigned long) |
416 |
ctrl->channels[c].current_d.after; |
417 |
len -= saved_data_buf; |
418 |
|
419 |
if (len > sizeof buf) |
420 |
len = sizeof buf;
|
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cpu_physical_memory_read (saved_data_buf, buf, len); |
422 |
|
423 |
D(printf("channel %d pushes %x %u bytes\n", c,
|
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saved_data_buf, len)); |
425 |
|
426 |
if (ctrl->channels[c].client->client.push)
|
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ctrl->channels[c].client->client.push( |
428 |
ctrl->channels[c].client->client.opaque, |
429 |
buf, len); |
430 |
else
|
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printf("WARNING: DMA ch%d dataloss,"
|
432 |
" no attached client.\n", c);
|
433 |
|
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saved_data_buf += len; |
435 |
|
436 |
if (saved_data_buf == (uint32_t)(unsigned long) |
437 |
ctrl->channels[c].current_d.after) { |
438 |
/* Done. Step to next. */
|
439 |
if (ctrl->channels[c].current_d.out_eop) {
|
440 |
/* TODO: signal eop to the client. */
|
441 |
D(printf("signal eop\n"));
|
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} |
443 |
if (ctrl->channels[c].current_d.intr) {
|
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/* TODO: signal eop to the client. */
|
445 |
/* data intr. */
|
446 |
D(printf("signal intr %d eol=%d\n",
|
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len, ctrl->channels[c].current_d.eol)); |
448 |
ctrl->channels[c].regs[R_INTR] |= (1 << 2); |
449 |
channel_update_irq(ctrl, c); |
450 |
} |
451 |
channel_store_d(ctrl, c); |
452 |
if (ctrl->channels[c].current_d.eol) {
|
453 |
D(printf("channel %d EOL\n", c));
|
454 |
ctrl->channels[c].eol = 1;
|
455 |
|
456 |
/* Mark the context as disabled. */
|
457 |
ctrl->channels[c].current_c.dis = 1;
|
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channel_store_c(ctrl, c); |
459 |
|
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channel_stop(ctrl, c); |
461 |
} else {
|
462 |
ctrl->channels[c].regs[RW_SAVED_DATA] = |
463 |
(uint32_t)(unsigned long)ctrl-> |
464 |
channels[c].current_d.next; |
465 |
/* Load new descriptor. */
|
466 |
channel_load_d(ctrl, c); |
467 |
saved_data_buf = (uint32_t)(unsigned long) |
468 |
ctrl->channels[c].current_d.buf; |
469 |
} |
470 |
|
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
472 |
saved_data_buf; |
473 |
D(dump_d(c, &ctrl->channels[c].current_d)); |
474 |
} |
475 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
476 |
} while (!ctrl->channels[c].eol);
|
477 |
return 1; |
478 |
} |
479 |
|
480 |
static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, |
481 |
unsigned char *buf, int buflen, int eop) |
482 |
{ |
483 |
uint32_t len; |
484 |
uint32_t saved_data_buf; |
485 |
|
486 |
if (ctrl->channels[c].eol == 1) |
487 |
return 0; |
488 |
|
489 |
channel_load_d(ctrl, c); |
490 |
saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
491 |
len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after; |
492 |
len -= saved_data_buf; |
493 |
|
494 |
if (len > buflen)
|
495 |
len = buflen; |
496 |
|
497 |
cpu_physical_memory_write (saved_data_buf, buf, len); |
498 |
saved_data_buf += len; |
499 |
|
500 |
if (saved_data_buf ==
|
501 |
(uint32_t)(unsigned long)ctrl->channels[c].current_d.after |
502 |
|| eop) { |
503 |
uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; |
504 |
|
505 |
D(printf("in dscr end len=%d\n",
|
506 |
ctrl->channels[c].current_d.after |
507 |
- ctrl->channels[c].current_d.buf)); |
508 |
ctrl->channels[c].current_d.after = saved_data_buf; |
509 |
|
510 |
/* Done. Step to next. */
|
511 |
if (ctrl->channels[c].current_d.intr) {
|
512 |
/* TODO: signal eop to the client. */
|
513 |
/* data intr. */
|
514 |
ctrl->channels[c].regs[R_INTR] |= 3;
|
515 |
} |
516 |
if (eop) {
|
517 |
ctrl->channels[c].current_d.in_eop = 1;
|
518 |
ctrl->channels[c].regs[R_INTR] |= 8;
|
519 |
} |
520 |
if (r_intr != ctrl->channels[c].regs[R_INTR])
|
521 |
channel_update_irq(ctrl, c); |
522 |
|
523 |
channel_store_d(ctrl, c); |
524 |
D(dump_d(c, &ctrl->channels[c].current_d)); |
525 |
|
526 |
if (ctrl->channels[c].current_d.eol) {
|
527 |
D(printf("channel %d EOL\n", c));
|
528 |
ctrl->channels[c].eol = 1;
|
529 |
|
530 |
/* Mark the context as disabled. */
|
531 |
ctrl->channels[c].current_c.dis = 1;
|
532 |
channel_store_c(ctrl, c); |
533 |
|
534 |
channel_stop(ctrl, c); |
535 |
} else {
|
536 |
ctrl->channels[c].regs[RW_SAVED_DATA] = |
537 |
(uint32_t)(unsigned long)ctrl-> |
538 |
channels[c].current_d.next; |
539 |
/* Load new descriptor. */
|
540 |
channel_load_d(ctrl, c); |
541 |
saved_data_buf = (uint32_t)(unsigned long) |
542 |
ctrl->channels[c].current_d.buf; |
543 |
} |
544 |
} |
545 |
|
546 |
ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
547 |
return len;
|
548 |
} |
549 |
|
550 |
static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) |
551 |
{ |
552 |
if (ctrl->channels[c].client->client.pull) {
|
553 |
ctrl->channels[c].client->client.pull( |
554 |
ctrl->channels[c].client->client.opaque); |
555 |
return 1; |
556 |
} else
|
557 |
return 0; |
558 |
} |
559 |
|
560 |
static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) |
561 |
{ |
562 |
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); |
563 |
return 0; |
564 |
} |
565 |
|
566 |
static uint64_t
|
567 |
dma_read(void *opaque, target_phys_addr_t addr, unsigned int size) |
568 |
{ |
569 |
struct fs_dma_ctrl *ctrl = opaque;
|
570 |
int c;
|
571 |
uint32_t r = 0;
|
572 |
|
573 |
if (size != 4) { |
574 |
dma_rinvalid(opaque, addr); |
575 |
} |
576 |
|
577 |
/* Make addr relative to this channel and bounded to nr regs. */
|
578 |
c = fs_channel(addr); |
579 |
addr &= 0xff;
|
580 |
addr >>= 2;
|
581 |
switch (addr)
|
582 |
{ |
583 |
case RW_STAT:
|
584 |
r = ctrl->channels[c].state & 7;
|
585 |
r |= ctrl->channels[c].eol << 5;
|
586 |
r |= ctrl->channels[c].stream_cmd_src << 8;
|
587 |
break;
|
588 |
|
589 |
default:
|
590 |
r = ctrl->channels[c].regs[addr]; |
591 |
D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n", |
592 |
__func__, c, addr)); |
593 |
break;
|
594 |
} |
595 |
return r;
|
596 |
} |
597 |
|
598 |
static void |
599 |
dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
|
600 |
{ |
601 |
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); |
602 |
} |
603 |
|
604 |
static void |
605 |
dma_update_state(struct fs_dma_ctrl *ctrl, int c) |
606 |
{ |
607 |
if (ctrl->channels[c].regs[RW_CFG] & 2) |
608 |
ctrl->channels[c].state = STOPPED; |
609 |
if (!(ctrl->channels[c].regs[RW_CFG] & 1)) |
610 |
ctrl->channels[c].state = RST; |
611 |
} |
612 |
|
613 |
static void |
614 |
dma_write(void *opaque, target_phys_addr_t addr,
|
615 |
uint64_t val64, unsigned int size) |
616 |
{ |
617 |
struct fs_dma_ctrl *ctrl = opaque;
|
618 |
uint32_t value = val64; |
619 |
int c;
|
620 |
|
621 |
if (size != 4) { |
622 |
dma_winvalid(opaque, addr, value); |
623 |
} |
624 |
|
625 |
/* Make addr relative to this channel and bounded to nr regs. */
|
626 |
c = fs_channel(addr); |
627 |
addr &= 0xff;
|
628 |
addr >>= 2;
|
629 |
switch (addr)
|
630 |
{ |
631 |
case RW_DATA:
|
632 |
ctrl->channels[c].regs[addr] = value; |
633 |
break;
|
634 |
|
635 |
case RW_CFG:
|
636 |
ctrl->channels[c].regs[addr] = value; |
637 |
dma_update_state(ctrl, c); |
638 |
break;
|
639 |
case RW_CMD:
|
640 |
/* continue. */
|
641 |
if (value & ~1) |
642 |
printf("Invalid store to ch=%d RW_CMD %x\n",
|
643 |
c, value); |
644 |
ctrl->channels[c].regs[addr] = value; |
645 |
channel_continue(ctrl, c); |
646 |
break;
|
647 |
|
648 |
case RW_SAVED_DATA:
|
649 |
case RW_SAVED_DATA_BUF:
|
650 |
case RW_GROUP:
|
651 |
case RW_GROUP_DOWN:
|
652 |
ctrl->channels[c].regs[addr] = value; |
653 |
break;
|
654 |
|
655 |
case RW_ACK_INTR:
|
656 |
case RW_INTR_MASK:
|
657 |
ctrl->channels[c].regs[addr] = value; |
658 |
channel_update_irq(ctrl, c); |
659 |
if (addr == RW_ACK_INTR)
|
660 |
ctrl->channels[c].regs[RW_ACK_INTR] = 0;
|
661 |
break;
|
662 |
|
663 |
case RW_STREAM_CMD:
|
664 |
if (value & ~1023) |
665 |
printf("Invalid store to ch=%d "
|
666 |
"RW_STREAMCMD %x\n",
|
667 |
c, value); |
668 |
ctrl->channels[c].regs[addr] = value; |
669 |
D(printf("stream_cmd ch=%d\n", c));
|
670 |
channel_stream_cmd(ctrl, c, value); |
671 |
break;
|
672 |
|
673 |
default:
|
674 |
D(printf ("%s c=%d " TARGET_FMT_plx "\n", |
675 |
__func__, c, addr)); |
676 |
break;
|
677 |
} |
678 |
} |
679 |
|
680 |
static const MemoryRegionOps dma_ops = { |
681 |
.read = dma_read, |
682 |
.write = dma_write, |
683 |
.endianness = DEVICE_NATIVE_ENDIAN, |
684 |
.valid = { |
685 |
.min_access_size = 1,
|
686 |
.max_access_size = 4
|
687 |
} |
688 |
}; |
689 |
|
690 |
static int etraxfs_dmac_run(void *opaque) |
691 |
{ |
692 |
struct fs_dma_ctrl *ctrl = opaque;
|
693 |
int i;
|
694 |
int p = 0; |
695 |
|
696 |
for (i = 0; |
697 |
i < ctrl->nr_channels; |
698 |
i++) |
699 |
{ |
700 |
if (ctrl->channels[i].state == RUNNING)
|
701 |
{ |
702 |
if (ctrl->channels[i].input) {
|
703 |
p += channel_in_run(ctrl, i); |
704 |
} else {
|
705 |
p += channel_out_run(ctrl, i); |
706 |
} |
707 |
} |
708 |
} |
709 |
return p;
|
710 |
} |
711 |
|
712 |
int etraxfs_dmac_input(struct etraxfs_dma_client *client, |
713 |
void *buf, int len, int eop) |
714 |
{ |
715 |
return channel_in_process(client->ctrl, client->channel,
|
716 |
buf, len, eop); |
717 |
} |
718 |
|
719 |
/* Connect an IRQ line with a channel. */
|
720 |
void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) |
721 |
{ |
722 |
struct fs_dma_ctrl *ctrl = opaque;
|
723 |
ctrl->channels[c].irq = *line; |
724 |
ctrl->channels[c].input = input; |
725 |
} |
726 |
|
727 |
void etraxfs_dmac_connect_client(void *opaque, int c, |
728 |
struct etraxfs_dma_client *cl)
|
729 |
{ |
730 |
struct fs_dma_ctrl *ctrl = opaque;
|
731 |
cl->ctrl = ctrl; |
732 |
cl->channel = c; |
733 |
ctrl->channels[c].client = cl; |
734 |
} |
735 |
|
736 |
|
737 |
static void DMA_run(void *opaque) |
738 |
{ |
739 |
struct fs_dma_ctrl *etraxfs_dmac = opaque;
|
740 |
int p = 1; |
741 |
|
742 |
if (runstate_is_running())
|
743 |
p = etraxfs_dmac_run(etraxfs_dmac); |
744 |
|
745 |
if (p)
|
746 |
qemu_bh_schedule_idle(etraxfs_dmac->bh); |
747 |
} |
748 |
|
749 |
void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels) |
750 |
{ |
751 |
struct fs_dma_ctrl *ctrl = NULL; |
752 |
|
753 |
ctrl = g_malloc0(sizeof *ctrl);
|
754 |
|
755 |
ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
756 |
|
757 |
ctrl->nr_channels = nr_channels; |
758 |
ctrl->channels = g_malloc0(sizeof ctrl->channels[0] * nr_channels); |
759 |
|
760 |
memory_region_init_io(&ctrl->mmio, &dma_ops, ctrl, "etraxfs-dma",
|
761 |
nr_channels * 0x2000);
|
762 |
memory_region_add_subregion(get_system_memory(), base, &ctrl->mmio); |
763 |
|
764 |
return ctrl;
|
765 |
} |