root / target-microblaze / translate.c @ dadc1064
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/*
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* Xilinx MicroBlaze emulation for qemu: main translation routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias.
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "disas.h" |
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#include "tcg-op.h" |
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#include "helper.h" |
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#include "microblaze-decode.h" |
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#define GEN_HELPER 1 |
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#include "helper.h" |
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#define SIM_COMPAT 0 |
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#define DISAS_GNU 1 |
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#define DISAS_MB 1 |
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#if DISAS_MB && !SIM_COMPAT
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# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
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#else
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# define LOG_DIS(...) do { } while (0) |
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#endif
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#define D(x)
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#define EXTRACT_FIELD(src, start, end) \
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(((src) >> start) & ((1 << (end - start + 1)) - 1)) |
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static TCGv env_debug;
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static TCGv_ptr cpu_env;
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static TCGv cpu_R[32]; |
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static TCGv cpu_SR[18]; |
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static TCGv env_imm;
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static TCGv env_btaken;
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static TCGv env_btarget;
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static TCGv env_iflags;
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#include "gen-icount.h" |
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/* This is the state at translation time. */
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typedef struct DisasContext { |
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CPUMBState *env; |
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target_ulong pc; |
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/* Decoder. */
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int type_b;
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uint32_t ir; |
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uint8_t opcode; |
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uint8_t rd, ra, rb; |
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uint16_t imm; |
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unsigned int cpustate_changed; |
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unsigned int delayed_branch; |
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unsigned int tb_flags, synced_flags; /* tb dependent flags. */ |
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unsigned int clear_imm; |
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int is_jmp;
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#define JMP_NOJMP 0 |
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#define JMP_DIRECT 1 |
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#define JMP_DIRECT_CC 2 |
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#define JMP_INDIRECT 3 |
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unsigned int jmp; |
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uint32_t jmp_pc; |
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int abort_at_next_insn;
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int nr_nops;
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struct TranslationBlock *tb;
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int singlestep_enabled;
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} DisasContext; |
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static const char *regnames[] = |
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{ |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", |
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}; |
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static const char *special_regnames[] = |
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{ |
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"rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", |
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"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", |
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"sr16", "sr17", "sr18" |
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}; |
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/* Sign extend at translation time. */
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static inline int sign_extend(unsigned int val, unsigned int width) |
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{ |
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int sval;
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/* LSL. */
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val <<= 31 - width;
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sval = val; |
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/* ASR. */
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sval >>= 31 - width;
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return sval;
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} |
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static inline void t_sync_flags(DisasContext *dc) |
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{ |
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/* Synch the tb dependent flags between translator and runtime. */
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if (dc->tb_flags != dc->synced_flags) {
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tcg_gen_movi_tl(env_iflags, dc->tb_flags); |
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dc->synced_flags = dc->tb_flags; |
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} |
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} |
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static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) |
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{ |
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TCGv_i32 tmp = tcg_const_i32(index); |
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t_sync_flags(dc); |
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tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
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gen_helper_raise_exception(tmp); |
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tcg_temp_free_i32(tmp); |
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dc->is_jmp = DISAS_UPDATE; |
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} |
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static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
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{ |
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TranslationBlock *tb; |
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tb = dc->tb; |
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if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
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tcg_gen_goto_tb(n); |
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tcg_gen_movi_tl(cpu_SR[SR_PC], dest); |
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tcg_gen_exit_tb((tcg_target_long)tb + n); |
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} else {
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tcg_gen_movi_tl(cpu_SR[SR_PC], dest); |
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tcg_gen_exit_tb(0);
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} |
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} |
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static void read_carry(DisasContext *dc, TCGv d) |
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{ |
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tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
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} |
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static void write_carry(DisasContext *dc, TCGv v) |
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{ |
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TCGv t0 = tcg_temp_new(); |
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tcg_gen_shli_tl(t0, v, 31);
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tcg_gen_sari_tl(t0, t0, 31);
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tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC)); |
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tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], |
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~(MSR_C | MSR_CC)); |
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tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0); |
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tcg_temp_free(t0); |
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} |
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/* True if ALU operand b is a small immediate that may deserve
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faster treatment. */
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static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) |
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{ |
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/* Immediate insn without the imm prefix ? */
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return dc->type_b && !(dc->tb_flags & IMM_FLAG);
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} |
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static inline TCGv *dec_alu_op_b(DisasContext *dc) |
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{ |
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if (dc->type_b) {
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if (dc->tb_flags & IMM_FLAG)
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tcg_gen_ori_tl(env_imm, env_imm, dc->imm); |
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else
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tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm)); |
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return &env_imm;
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} else
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return &cpu_R[dc->rb];
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} |
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static void dec_add(DisasContext *dc) |
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{ |
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unsigned int k, c; |
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TCGv cf; |
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k = dc->opcode & 4;
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c = dc->opcode & 2;
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LOG_DIS("add%s%s%s r%d r%d r%d\n",
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dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", |
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dc->rd, dc->ra, dc->rb); |
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/* Take care of the easy cases first. */
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if (k) {
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/* k - keep carry, no need to update MSR. */
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/* If rd == r0, it's a nop. */
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if (dc->rd) {
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
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if (c) {
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/* c - Add carry into the result. */
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cf = tcg_temp_new(); |
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read_carry(dc, cf); |
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
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tcg_temp_free(cf); |
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} |
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} |
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return;
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} |
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/* From now on, we can assume k is zero. So we need to update MSR. */
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/* Extract carry. */
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cf = tcg_temp_new(); |
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if (c) {
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read_carry(dc, cf); |
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} else {
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tcg_gen_movi_tl(cf, 0);
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} |
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if (dc->rd) {
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TCGv ncf = tcg_temp_new(); |
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gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); |
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
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tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
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write_carry(dc, ncf); |
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tcg_temp_free(ncf); |
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} else {
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gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); |
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write_carry(dc, cf); |
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} |
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tcg_temp_free(cf); |
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} |
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static void dec_sub(DisasContext *dc) |
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{ |
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unsigned int u, cmp, k, c; |
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TCGv cf, na; |
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u = dc->imm & 2;
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k = dc->opcode & 4;
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c = dc->opcode & 2;
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cmp = (dc->imm & 1) && (!dc->type_b) && k;
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if (cmp) {
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LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); |
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if (dc->rd) {
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if (u)
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gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
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else
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gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
256 |
} |
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return;
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} |
259 |
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LOG_DIS("sub%s%s r%d, r%d r%d\n",
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k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); |
262 |
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/* Take care of the easy cases first. */
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if (k) {
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/* k - keep carry, no need to update MSR. */
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/* If rd == r0, it's a nop. */
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if (dc->rd) {
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tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); |
269 |
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if (c) {
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/* c - Add carry into the result. */
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cf = tcg_temp_new(); |
273 |
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read_carry(dc, cf); |
275 |
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
276 |
tcg_temp_free(cf); |
277 |
} |
278 |
} |
279 |
return;
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} |
281 |
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/* From now on, we can assume k is zero. So we need to update MSR. */
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/* Extract carry. And complement a into na. */
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cf = tcg_temp_new(); |
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na = tcg_temp_new(); |
286 |
if (c) {
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read_carry(dc, cf); |
288 |
} else {
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tcg_gen_movi_tl(cf, 1);
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} |
291 |
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/* d = b + ~a + c. carry defaults to 1. */
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tcg_gen_not_tl(na, cpu_R[dc->ra]); |
294 |
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if (dc->rd) {
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TCGv ncf = tcg_temp_new(); |
297 |
gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); |
298 |
tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); |
299 |
tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf); |
300 |
write_carry(dc, ncf); |
301 |
tcg_temp_free(ncf); |
302 |
} else {
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gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); |
304 |
write_carry(dc, cf); |
305 |
} |
306 |
tcg_temp_free(cf); |
307 |
tcg_temp_free(na); |
308 |
} |
309 |
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static void dec_pattern(DisasContext *dc) |
311 |
{ |
312 |
unsigned int mode; |
313 |
int l1;
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if ((dc->tb_flags & MSR_EE_FLAG)
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&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
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&& !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
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318 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
319 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
320 |
} |
321 |
|
322 |
mode = dc->opcode & 3;
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323 |
switch (mode) {
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324 |
case 0: |
325 |
/* pcmpbf. */
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LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
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if (dc->rd)
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gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
329 |
break;
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330 |
case 2: |
331 |
LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
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332 |
if (dc->rd) {
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333 |
TCGv t0 = tcg_temp_local_new(); |
334 |
l1 = gen_new_label(); |
335 |
tcg_gen_movi_tl(t0, 1);
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336 |
tcg_gen_brcond_tl(TCG_COND_EQ, |
337 |
cpu_R[dc->ra], cpu_R[dc->rb], l1); |
338 |
tcg_gen_movi_tl(t0, 0);
|
339 |
gen_set_label(l1); |
340 |
tcg_gen_mov_tl(cpu_R[dc->rd], t0); |
341 |
tcg_temp_free(t0); |
342 |
} |
343 |
break;
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344 |
case 3: |
345 |
LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
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346 |
l1 = gen_new_label(); |
347 |
if (dc->rd) {
|
348 |
TCGv t0 = tcg_temp_local_new(); |
349 |
tcg_gen_movi_tl(t0, 1);
|
350 |
tcg_gen_brcond_tl(TCG_COND_NE, |
351 |
cpu_R[dc->ra], cpu_R[dc->rb], l1); |
352 |
tcg_gen_movi_tl(t0, 0);
|
353 |
gen_set_label(l1); |
354 |
tcg_gen_mov_tl(cpu_R[dc->rd], t0); |
355 |
tcg_temp_free(t0); |
356 |
} |
357 |
break;
|
358 |
default:
|
359 |
cpu_abort(dc->env, |
360 |
"unsupported pattern insn opcode=%x\n", dc->opcode);
|
361 |
break;
|
362 |
} |
363 |
} |
364 |
|
365 |
static void dec_and(DisasContext *dc) |
366 |
{ |
367 |
unsigned int not; |
368 |
|
369 |
if (!dc->type_b && (dc->imm & (1 << 10))) { |
370 |
dec_pattern(dc); |
371 |
return;
|
372 |
} |
373 |
|
374 |
not = dc->opcode & (1 << 1); |
375 |
LOG_DIS("and%s\n", not ? "n" : ""); |
376 |
|
377 |
if (!dc->rd)
|
378 |
return;
|
379 |
|
380 |
if (not) {
|
381 |
TCGv t = tcg_temp_new(); |
382 |
tcg_gen_not_tl(t, *(dec_alu_op_b(dc))); |
383 |
tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t); |
384 |
tcg_temp_free(t); |
385 |
} else
|
386 |
tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
387 |
} |
388 |
|
389 |
static void dec_or(DisasContext *dc) |
390 |
{ |
391 |
if (!dc->type_b && (dc->imm & (1 << 10))) { |
392 |
dec_pattern(dc); |
393 |
return;
|
394 |
} |
395 |
|
396 |
LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
|
397 |
if (dc->rd)
|
398 |
tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
399 |
} |
400 |
|
401 |
static void dec_xor(DisasContext *dc) |
402 |
{ |
403 |
if (!dc->type_b && (dc->imm & (1 << 10))) { |
404 |
dec_pattern(dc); |
405 |
return;
|
406 |
} |
407 |
|
408 |
LOG_DIS("xor r%d\n", dc->rd);
|
409 |
if (dc->rd)
|
410 |
tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
411 |
} |
412 |
|
413 |
static inline void msr_read(DisasContext *dc, TCGv d) |
414 |
{ |
415 |
tcg_gen_mov_tl(d, cpu_SR[SR_MSR]); |
416 |
} |
417 |
|
418 |
static inline void msr_write(DisasContext *dc, TCGv v) |
419 |
{ |
420 |
TCGv t; |
421 |
|
422 |
t = tcg_temp_new(); |
423 |
dc->cpustate_changed = 1;
|
424 |
/* PVR bit is not writable. */
|
425 |
tcg_gen_andi_tl(t, v, ~MSR_PVR); |
426 |
tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); |
427 |
tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v); |
428 |
tcg_temp_free(t); |
429 |
} |
430 |
|
431 |
static void dec_msr(DisasContext *dc) |
432 |
{ |
433 |
TCGv t0, t1; |
434 |
unsigned int sr, to, rn; |
435 |
int mem_index = cpu_mmu_index(dc->env);
|
436 |
|
437 |
sr = dc->imm & ((1 << 14) - 1); |
438 |
to = dc->imm & (1 << 14); |
439 |
dc->type_b = 1;
|
440 |
if (to)
|
441 |
dc->cpustate_changed = 1;
|
442 |
|
443 |
/* msrclr and msrset. */
|
444 |
if (!(dc->imm & (1 << 15))) { |
445 |
unsigned int clr = dc->ir & (1 << 16); |
446 |
|
447 |
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", |
448 |
dc->rd, dc->imm); |
449 |
|
450 |
if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) { |
451 |
/* nop??? */
|
452 |
return;
|
453 |
} |
454 |
|
455 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
456 |
&& mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) { |
457 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
458 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
459 |
return;
|
460 |
} |
461 |
|
462 |
if (dc->rd)
|
463 |
msr_read(dc, cpu_R[dc->rd]); |
464 |
|
465 |
t0 = tcg_temp_new(); |
466 |
t1 = tcg_temp_new(); |
467 |
msr_read(dc, t0); |
468 |
tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc))); |
469 |
|
470 |
if (clr) {
|
471 |
tcg_gen_not_tl(t1, t1); |
472 |
tcg_gen_and_tl(t0, t0, t1); |
473 |
} else
|
474 |
tcg_gen_or_tl(t0, t0, t1); |
475 |
msr_write(dc, t0); |
476 |
tcg_temp_free(t0); |
477 |
tcg_temp_free(t1); |
478 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
|
479 |
dc->is_jmp = DISAS_UPDATE; |
480 |
return;
|
481 |
} |
482 |
|
483 |
if (to) {
|
484 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
485 |
&& mem_index == MMU_USER_IDX) { |
486 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
487 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
488 |
return;
|
489 |
} |
490 |
} |
491 |
|
492 |
#if !defined(CONFIG_USER_ONLY)
|
493 |
/* Catch read/writes to the mmu block. */
|
494 |
if ((sr & ~0xff) == 0x1000) { |
495 |
sr &= 7;
|
496 |
LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); |
497 |
if (to)
|
498 |
gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]); |
499 |
else
|
500 |
gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr)); |
501 |
return;
|
502 |
} |
503 |
#endif
|
504 |
|
505 |
if (to) {
|
506 |
LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); |
507 |
switch (sr) {
|
508 |
case 0: |
509 |
break;
|
510 |
case 1: |
511 |
msr_write(dc, cpu_R[dc->ra]); |
512 |
break;
|
513 |
case 0x3: |
514 |
tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]); |
515 |
break;
|
516 |
case 0x5: |
517 |
tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]); |
518 |
break;
|
519 |
case 0x7: |
520 |
tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
|
521 |
break;
|
522 |
case 0x800: |
523 |
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr)); |
524 |
break;
|
525 |
case 0x802: |
526 |
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr)); |
527 |
break;
|
528 |
default:
|
529 |
cpu_abort(dc->env, "unknown mts reg %x\n", sr);
|
530 |
break;
|
531 |
} |
532 |
} else {
|
533 |
LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); |
534 |
|
535 |
switch (sr) {
|
536 |
case 0: |
537 |
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); |
538 |
break;
|
539 |
case 1: |
540 |
msr_read(dc, cpu_R[dc->rd]); |
541 |
break;
|
542 |
case 0x3: |
543 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]); |
544 |
break;
|
545 |
case 0x5: |
546 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]); |
547 |
break;
|
548 |
case 0x7: |
549 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]); |
550 |
break;
|
551 |
case 0xb: |
552 |
tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]); |
553 |
break;
|
554 |
case 0x800: |
555 |
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr)); |
556 |
break;
|
557 |
case 0x802: |
558 |
tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr)); |
559 |
break;
|
560 |
case 0x2000: |
561 |
case 0x2001: |
562 |
case 0x2002: |
563 |
case 0x2003: |
564 |
case 0x2004: |
565 |
case 0x2005: |
566 |
case 0x2006: |
567 |
case 0x2007: |
568 |
case 0x2008: |
569 |
case 0x2009: |
570 |
case 0x200a: |
571 |
case 0x200b: |
572 |
case 0x200c: |
573 |
rn = sr & 0xf;
|
574 |
tcg_gen_ld_tl(cpu_R[dc->rd], |
575 |
cpu_env, offsetof(CPUMBState, pvr.regs[rn])); |
576 |
break;
|
577 |
default:
|
578 |
cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
|
579 |
break;
|
580 |
} |
581 |
} |
582 |
|
583 |
if (dc->rd == 0) { |
584 |
tcg_gen_movi_tl(cpu_R[0], 0); |
585 |
} |
586 |
} |
587 |
|
588 |
/* 64-bit signed mul, lower result in d and upper in d2. */
|
589 |
static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b) |
590 |
{ |
591 |
TCGv_i64 t0, t1; |
592 |
|
593 |
t0 = tcg_temp_new_i64(); |
594 |
t1 = tcg_temp_new_i64(); |
595 |
|
596 |
tcg_gen_ext_i32_i64(t0, a); |
597 |
tcg_gen_ext_i32_i64(t1, b); |
598 |
tcg_gen_mul_i64(t0, t0, t1); |
599 |
|
600 |
tcg_gen_trunc_i64_i32(d, t0); |
601 |
tcg_gen_shri_i64(t0, t0, 32);
|
602 |
tcg_gen_trunc_i64_i32(d2, t0); |
603 |
|
604 |
tcg_temp_free_i64(t0); |
605 |
tcg_temp_free_i64(t1); |
606 |
} |
607 |
|
608 |
/* 64-bit unsigned muls, lower result in d and upper in d2. */
|
609 |
static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b) |
610 |
{ |
611 |
TCGv_i64 t0, t1; |
612 |
|
613 |
t0 = tcg_temp_new_i64(); |
614 |
t1 = tcg_temp_new_i64(); |
615 |
|
616 |
tcg_gen_extu_i32_i64(t0, a); |
617 |
tcg_gen_extu_i32_i64(t1, b); |
618 |
tcg_gen_mul_i64(t0, t0, t1); |
619 |
|
620 |
tcg_gen_trunc_i64_i32(d, t0); |
621 |
tcg_gen_shri_i64(t0, t0, 32);
|
622 |
tcg_gen_trunc_i64_i32(d2, t0); |
623 |
|
624 |
tcg_temp_free_i64(t0); |
625 |
tcg_temp_free_i64(t1); |
626 |
} |
627 |
|
628 |
/* Multiplier unit. */
|
629 |
static void dec_mul(DisasContext *dc) |
630 |
{ |
631 |
TCGv d[2];
|
632 |
unsigned int subcode; |
633 |
|
634 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
635 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
636 |
&& !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
|
637 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
638 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
639 |
return;
|
640 |
} |
641 |
|
642 |
subcode = dc->imm & 3;
|
643 |
d[0] = tcg_temp_new();
|
644 |
d[1] = tcg_temp_new();
|
645 |
|
646 |
if (dc->type_b) {
|
647 |
LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
|
648 |
t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
|
649 |
goto done;
|
650 |
} |
651 |
|
652 |
/* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
|
653 |
if (subcode >= 1 && subcode <= 3 |
654 |
&& !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
|
655 |
/* nop??? */
|
656 |
} |
657 |
|
658 |
switch (subcode) {
|
659 |
case 0: |
660 |
LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
661 |
t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
|
662 |
break;
|
663 |
case 1: |
664 |
LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
665 |
t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
|
666 |
break;
|
667 |
case 2: |
668 |
LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
669 |
t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
|
670 |
break;
|
671 |
case 3: |
672 |
LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
|
673 |
t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
|
674 |
break;
|
675 |
default:
|
676 |
cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
|
677 |
break;
|
678 |
} |
679 |
done:
|
680 |
tcg_temp_free(d[0]);
|
681 |
tcg_temp_free(d[1]);
|
682 |
} |
683 |
|
684 |
/* Div unit. */
|
685 |
static void dec_div(DisasContext *dc) |
686 |
{ |
687 |
unsigned int u; |
688 |
|
689 |
u = dc->imm & 2;
|
690 |
LOG_DIS("div\n");
|
691 |
|
692 |
if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) |
693 |
&& !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
|
694 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
695 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
696 |
} |
697 |
|
698 |
if (u)
|
699 |
gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); |
700 |
else
|
701 |
gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); |
702 |
if (!dc->rd)
|
703 |
tcg_gen_movi_tl(cpu_R[dc->rd], 0);
|
704 |
} |
705 |
|
706 |
static void dec_barrel(DisasContext *dc) |
707 |
{ |
708 |
TCGv t0; |
709 |
unsigned int s, t; |
710 |
|
711 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
712 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
713 |
&& !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
|
714 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
715 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
716 |
return;
|
717 |
} |
718 |
|
719 |
s = dc->imm & (1 << 10); |
720 |
t = dc->imm & (1 << 9); |
721 |
|
722 |
LOG_DIS("bs%s%s r%d r%d r%d\n",
|
723 |
s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); |
724 |
|
725 |
t0 = tcg_temp_new(); |
726 |
|
727 |
tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc))); |
728 |
tcg_gen_andi_tl(t0, t0, 31);
|
729 |
|
730 |
if (s)
|
731 |
tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); |
732 |
else {
|
733 |
if (t)
|
734 |
tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); |
735 |
else
|
736 |
tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0); |
737 |
} |
738 |
} |
739 |
|
740 |
static void dec_bit(DisasContext *dc) |
741 |
{ |
742 |
TCGv t0, t1; |
743 |
unsigned int op; |
744 |
int mem_index = cpu_mmu_index(dc->env);
|
745 |
|
746 |
op = dc->ir & ((1 << 8) - 1); |
747 |
switch (op) {
|
748 |
case 0x21: |
749 |
/* src. */
|
750 |
t0 = tcg_temp_new(); |
751 |
|
752 |
LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
|
753 |
tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
|
754 |
if (dc->rd) {
|
755 |
t1 = tcg_temp_new(); |
756 |
read_carry(dc, t1); |
757 |
tcg_gen_shli_tl(t1, t1, 31);
|
758 |
|
759 |
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
|
760 |
tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1); |
761 |
tcg_temp_free(t1); |
762 |
} |
763 |
|
764 |
/* Update carry. */
|
765 |
write_carry(dc, t0); |
766 |
tcg_temp_free(t0); |
767 |
break;
|
768 |
|
769 |
case 0x1: |
770 |
case 0x41: |
771 |
/* srl. */
|
772 |
t0 = tcg_temp_new(); |
773 |
LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
|
774 |
|
775 |
/* Update carry. */
|
776 |
tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
|
777 |
write_carry(dc, t0); |
778 |
tcg_temp_free(t0); |
779 |
if (dc->rd) {
|
780 |
if (op == 0x41) |
781 |
tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
|
782 |
else
|
783 |
tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
|
784 |
} |
785 |
break;
|
786 |
case 0x60: |
787 |
LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
|
788 |
tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); |
789 |
break;
|
790 |
case 0x61: |
791 |
LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
|
792 |
tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); |
793 |
break;
|
794 |
case 0x64: |
795 |
case 0x66: |
796 |
case 0x74: |
797 |
case 0x76: |
798 |
/* wdc. */
|
799 |
LOG_DIS("wdc r%d\n", dc->ra);
|
800 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
801 |
&& mem_index == MMU_USER_IDX) { |
802 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
803 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
804 |
return;
|
805 |
} |
806 |
break;
|
807 |
case 0x68: |
808 |
/* wic. */
|
809 |
LOG_DIS("wic r%d\n", dc->ra);
|
810 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
811 |
&& mem_index == MMU_USER_IDX) { |
812 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
813 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
814 |
return;
|
815 |
} |
816 |
break;
|
817 |
case 0xe0: |
818 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
819 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
820 |
&& !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
|
821 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
822 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
823 |
} |
824 |
if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) { |
825 |
gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]); |
826 |
} |
827 |
break;
|
828 |
default:
|
829 |
cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
|
830 |
dc->pc, op, dc->rd, dc->ra, dc->rb); |
831 |
break;
|
832 |
} |
833 |
} |
834 |
|
835 |
static inline void sync_jmpstate(DisasContext *dc) |
836 |
{ |
837 |
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
|
838 |
if (dc->jmp == JMP_DIRECT) {
|
839 |
tcg_gen_movi_tl(env_btaken, 1);
|
840 |
} |
841 |
dc->jmp = JMP_INDIRECT; |
842 |
tcg_gen_movi_tl(env_btarget, dc->jmp_pc); |
843 |
} |
844 |
} |
845 |
|
846 |
static void dec_imm(DisasContext *dc) |
847 |
{ |
848 |
LOG_DIS("imm %x\n", dc->imm << 16); |
849 |
tcg_gen_movi_tl(env_imm, (dc->imm << 16));
|
850 |
dc->tb_flags |= IMM_FLAG; |
851 |
dc->clear_imm = 0;
|
852 |
} |
853 |
|
854 |
static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, |
855 |
unsigned int size) |
856 |
{ |
857 |
int mem_index = cpu_mmu_index(dc->env);
|
858 |
|
859 |
if (size == 1) { |
860 |
tcg_gen_qemu_ld8u(dst, addr, mem_index); |
861 |
} else if (size == 2) { |
862 |
tcg_gen_qemu_ld16u(dst, addr, mem_index); |
863 |
} else if (size == 4) { |
864 |
tcg_gen_qemu_ld32u(dst, addr, mem_index); |
865 |
} else
|
866 |
cpu_abort(dc->env, "Incorrect load size %d\n", size);
|
867 |
} |
868 |
|
869 |
static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) |
870 |
{ |
871 |
unsigned int extimm = dc->tb_flags & IMM_FLAG; |
872 |
/* Should be set to one if r1 is used by loadstores. */
|
873 |
int stackprot = 0; |
874 |
|
875 |
/* All load/stores use ra. */
|
876 |
if (dc->ra == 1) { |
877 |
stackprot = 1;
|
878 |
} |
879 |
|
880 |
/* Treat the common cases first. */
|
881 |
if (!dc->type_b) {
|
882 |
/* If any of the regs is r0, return a ptr to the other. */
|
883 |
if (dc->ra == 0) { |
884 |
return &cpu_R[dc->rb];
|
885 |
} else if (dc->rb == 0) { |
886 |
return &cpu_R[dc->ra];
|
887 |
} |
888 |
|
889 |
if (dc->rb == 1) { |
890 |
stackprot = 1;
|
891 |
} |
892 |
|
893 |
*t = tcg_temp_new(); |
894 |
tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]); |
895 |
|
896 |
if (stackprot) {
|
897 |
gen_helper_stackprot(*t); |
898 |
} |
899 |
return t;
|
900 |
} |
901 |
/* Immediate. */
|
902 |
if (!extimm) {
|
903 |
if (dc->imm == 0) { |
904 |
return &cpu_R[dc->ra];
|
905 |
} |
906 |
*t = tcg_temp_new(); |
907 |
tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm)); |
908 |
tcg_gen_add_tl(*t, cpu_R[dc->ra], *t); |
909 |
} else {
|
910 |
*t = tcg_temp_new(); |
911 |
tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
912 |
} |
913 |
|
914 |
if (stackprot) {
|
915 |
gen_helper_stackprot(*t); |
916 |
} |
917 |
return t;
|
918 |
} |
919 |
|
920 |
static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size) |
921 |
{ |
922 |
if (size == 4) { |
923 |
tcg_gen_bswap32_tl(dst, src); |
924 |
} else if (size == 2) { |
925 |
TCGv t = tcg_temp_new(); |
926 |
|
927 |
/* bswap16 assumes the high bits are zero. */
|
928 |
tcg_gen_andi_tl(t, src, 0xffff);
|
929 |
tcg_gen_bswap16_tl(dst, t); |
930 |
tcg_temp_free(t); |
931 |
} else {
|
932 |
/* Ignore.
|
933 |
cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
|
934 |
*/
|
935 |
} |
936 |
} |
937 |
|
938 |
static void dec_load(DisasContext *dc) |
939 |
{ |
940 |
TCGv t, *addr; |
941 |
unsigned int size, rev = 0; |
942 |
|
943 |
size = 1 << (dc->opcode & 3); |
944 |
|
945 |
if (!dc->type_b) {
|
946 |
rev = (dc->ir >> 9) & 1; |
947 |
} |
948 |
|
949 |
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) |
950 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
|
951 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
952 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
953 |
return;
|
954 |
} |
955 |
|
956 |
LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : ""); |
957 |
|
958 |
t_sync_flags(dc); |
959 |
addr = compute_ldst_addr(dc, &t); |
960 |
|
961 |
/*
|
962 |
* When doing reverse accesses we need to do two things.
|
963 |
*
|
964 |
* 1. Reverse the address wrt endianness.
|
965 |
* 2. Byteswap the data lanes on the way back into the CPU core.
|
966 |
*/
|
967 |
if (rev && size != 4) { |
968 |
/* Endian reverse the address. t is addr. */
|
969 |
switch (size) {
|
970 |
case 1: |
971 |
{ |
972 |
/* 00 -> 11
|
973 |
01 -> 10
|
974 |
10 -> 10
|
975 |
11 -> 00 */
|
976 |
TCGv low = tcg_temp_new(); |
977 |
|
978 |
/* Force addr into the temp. */
|
979 |
if (addr != &t) {
|
980 |
t = tcg_temp_new(); |
981 |
tcg_gen_mov_tl(t, *addr); |
982 |
addr = &t; |
983 |
} |
984 |
|
985 |
tcg_gen_andi_tl(low, t, 3);
|
986 |
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
|
987 |
tcg_gen_andi_tl(t, t, ~3);
|
988 |
tcg_gen_or_tl(t, t, low); |
989 |
tcg_gen_mov_tl(env_imm, t); |
990 |
tcg_temp_free(low); |
991 |
break;
|
992 |
} |
993 |
|
994 |
case 2: |
995 |
/* 00 -> 10
|
996 |
10 -> 00. */
|
997 |
/* Force addr into the temp. */
|
998 |
if (addr != &t) {
|
999 |
t = tcg_temp_new(); |
1000 |
tcg_gen_xori_tl(t, *addr, 2);
|
1001 |
addr = &t; |
1002 |
} else {
|
1003 |
tcg_gen_xori_tl(t, t, 2);
|
1004 |
} |
1005 |
break;
|
1006 |
default:
|
1007 |
cpu_abort(dc->env, "Invalid reverse size\n");
|
1008 |
break;
|
1009 |
} |
1010 |
} |
1011 |
|
1012 |
/* If we get a fault on a dslot, the jmpstate better be in sync. */
|
1013 |
sync_jmpstate(dc); |
1014 |
|
1015 |
/* Verify alignment if needed. */
|
1016 |
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { |
1017 |
TCGv v = tcg_temp_new(); |
1018 |
|
1019 |
/*
|
1020 |
* Microblaze gives MMU faults priority over faults due to
|
1021 |
* unaligned addresses. That's why we speculatively do the load
|
1022 |
* into v. If the load succeeds, we verify alignment of the
|
1023 |
* address and if that succeeds we write into the destination reg.
|
1024 |
*/
|
1025 |
gen_load(dc, v, *addr, size); |
1026 |
|
1027 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
1028 |
gen_helper_memalign(*addr, tcg_const_tl(dc->rd), |
1029 |
tcg_const_tl(0), tcg_const_tl(size - 1)); |
1030 |
if (dc->rd) {
|
1031 |
if (rev) {
|
1032 |
dec_byteswap(dc, cpu_R[dc->rd], v, size); |
1033 |
} else {
|
1034 |
tcg_gen_mov_tl(cpu_R[dc->rd], v); |
1035 |
} |
1036 |
} |
1037 |
tcg_temp_free(v); |
1038 |
} else {
|
1039 |
if (dc->rd) {
|
1040 |
gen_load(dc, cpu_R[dc->rd], *addr, size); |
1041 |
if (rev) {
|
1042 |
dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size); |
1043 |
} |
1044 |
} else {
|
1045 |
/* We are loading into r0, no need to reverse. */
|
1046 |
gen_load(dc, env_imm, *addr, size); |
1047 |
} |
1048 |
} |
1049 |
|
1050 |
if (addr == &t)
|
1051 |
tcg_temp_free(t); |
1052 |
} |
1053 |
|
1054 |
static void gen_store(DisasContext *dc, TCGv addr, TCGv val, |
1055 |
unsigned int size) |
1056 |
{ |
1057 |
int mem_index = cpu_mmu_index(dc->env);
|
1058 |
|
1059 |
if (size == 1) |
1060 |
tcg_gen_qemu_st8(val, addr, mem_index); |
1061 |
else if (size == 2) { |
1062 |
tcg_gen_qemu_st16(val, addr, mem_index); |
1063 |
} else if (size == 4) { |
1064 |
tcg_gen_qemu_st32(val, addr, mem_index); |
1065 |
} else
|
1066 |
cpu_abort(dc->env, "Incorrect store size %d\n", size);
|
1067 |
} |
1068 |
|
1069 |
static void dec_store(DisasContext *dc) |
1070 |
{ |
1071 |
TCGv t, *addr; |
1072 |
unsigned int size, rev = 0; |
1073 |
|
1074 |
size = 1 << (dc->opcode & 3); |
1075 |
if (!dc->type_b) {
|
1076 |
rev = (dc->ir >> 9) & 1; |
1077 |
} |
1078 |
|
1079 |
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) |
1080 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
|
1081 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1082 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1083 |
return;
|
1084 |
} |
1085 |
|
1086 |
LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : ""); |
1087 |
t_sync_flags(dc); |
1088 |
/* If we get a fault on a dslot, the jmpstate better be in sync. */
|
1089 |
sync_jmpstate(dc); |
1090 |
addr = compute_ldst_addr(dc, &t); |
1091 |
|
1092 |
if (rev && size != 4) { |
1093 |
/* Endian reverse the address. t is addr. */
|
1094 |
switch (size) {
|
1095 |
case 1: |
1096 |
{ |
1097 |
/* 00 -> 11
|
1098 |
01 -> 10
|
1099 |
10 -> 10
|
1100 |
11 -> 00 */
|
1101 |
TCGv low = tcg_temp_new(); |
1102 |
|
1103 |
/* Force addr into the temp. */
|
1104 |
if (addr != &t) {
|
1105 |
t = tcg_temp_new(); |
1106 |
tcg_gen_mov_tl(t, *addr); |
1107 |
addr = &t; |
1108 |
} |
1109 |
|
1110 |
tcg_gen_andi_tl(low, t, 3);
|
1111 |
tcg_gen_sub_tl(low, tcg_const_tl(3), low);
|
1112 |
tcg_gen_andi_tl(t, t, ~3);
|
1113 |
tcg_gen_or_tl(t, t, low); |
1114 |
tcg_gen_mov_tl(env_imm, t); |
1115 |
tcg_temp_free(low); |
1116 |
break;
|
1117 |
} |
1118 |
|
1119 |
case 2: |
1120 |
/* 00 -> 10
|
1121 |
10 -> 00. */
|
1122 |
/* Force addr into the temp. */
|
1123 |
if (addr != &t) {
|
1124 |
t = tcg_temp_new(); |
1125 |
tcg_gen_xori_tl(t, *addr, 2);
|
1126 |
addr = &t; |
1127 |
} else {
|
1128 |
tcg_gen_xori_tl(t, t, 2);
|
1129 |
} |
1130 |
break;
|
1131 |
default:
|
1132 |
cpu_abort(dc->env, "Invalid reverse size\n");
|
1133 |
break;
|
1134 |
} |
1135 |
|
1136 |
if (size != 1) { |
1137 |
TCGv bs_data = tcg_temp_new(); |
1138 |
dec_byteswap(dc, bs_data, cpu_R[dc->rd], size); |
1139 |
gen_store(dc, *addr, bs_data, size); |
1140 |
tcg_temp_free(bs_data); |
1141 |
} else {
|
1142 |
gen_store(dc, *addr, cpu_R[dc->rd], size); |
1143 |
} |
1144 |
} else {
|
1145 |
if (rev) {
|
1146 |
TCGv bs_data = tcg_temp_new(); |
1147 |
dec_byteswap(dc, bs_data, cpu_R[dc->rd], size); |
1148 |
gen_store(dc, *addr, bs_data, size); |
1149 |
tcg_temp_free(bs_data); |
1150 |
} else {
|
1151 |
gen_store(dc, *addr, cpu_R[dc->rd], size); |
1152 |
} |
1153 |
} |
1154 |
|
1155 |
/* Verify alignment if needed. */
|
1156 |
if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { |
1157 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
1158 |
/* FIXME: if the alignment is wrong, we should restore the value
|
1159 |
* in memory. One possible way to achieve this is to probe
|
1160 |
* the MMU prior to the memaccess, thay way we could put
|
1161 |
* the alignment checks in between the probe and the mem
|
1162 |
* access.
|
1163 |
*/
|
1164 |
gen_helper_memalign(*addr, tcg_const_tl(dc->rd), |
1165 |
tcg_const_tl(1), tcg_const_tl(size - 1)); |
1166 |
} |
1167 |
|
1168 |
if (addr == &t)
|
1169 |
tcg_temp_free(t); |
1170 |
} |
1171 |
|
1172 |
static inline void eval_cc(DisasContext *dc, unsigned int cc, |
1173 |
TCGv d, TCGv a, TCGv b) |
1174 |
{ |
1175 |
switch (cc) {
|
1176 |
case CC_EQ:
|
1177 |
tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b); |
1178 |
break;
|
1179 |
case CC_NE:
|
1180 |
tcg_gen_setcond_tl(TCG_COND_NE, d, a, b); |
1181 |
break;
|
1182 |
case CC_LT:
|
1183 |
tcg_gen_setcond_tl(TCG_COND_LT, d, a, b); |
1184 |
break;
|
1185 |
case CC_LE:
|
1186 |
tcg_gen_setcond_tl(TCG_COND_LE, d, a, b); |
1187 |
break;
|
1188 |
case CC_GE:
|
1189 |
tcg_gen_setcond_tl(TCG_COND_GE, d, a, b); |
1190 |
break;
|
1191 |
case CC_GT:
|
1192 |
tcg_gen_setcond_tl(TCG_COND_GT, d, a, b); |
1193 |
break;
|
1194 |
default:
|
1195 |
cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
|
1196 |
break;
|
1197 |
} |
1198 |
} |
1199 |
|
1200 |
static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false) |
1201 |
{ |
1202 |
int l1;
|
1203 |
|
1204 |
l1 = gen_new_label(); |
1205 |
/* Conditional jmp. */
|
1206 |
tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false); |
1207 |
tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
|
1208 |
tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true); |
1209 |
gen_set_label(l1); |
1210 |
} |
1211 |
|
1212 |
static void dec_bcc(DisasContext *dc) |
1213 |
{ |
1214 |
unsigned int cc; |
1215 |
unsigned int dslot; |
1216 |
|
1217 |
cc = EXTRACT_FIELD(dc->ir, 21, 23); |
1218 |
dslot = dc->ir & (1 << 25); |
1219 |
LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); |
1220 |
|
1221 |
dc->delayed_branch = 1;
|
1222 |
if (dslot) {
|
1223 |
dc->delayed_branch = 2;
|
1224 |
dc->tb_flags |= D_FLAG; |
1225 |
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), |
1226 |
cpu_env, offsetof(CPUMBState, bimm)); |
1227 |
} |
1228 |
|
1229 |
if (dec_alu_op_b_is_small_imm(dc)) {
|
1230 |
int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
|
1231 |
|
1232 |
tcg_gen_movi_tl(env_btarget, dc->pc + offset); |
1233 |
dc->jmp = JMP_DIRECT_CC; |
1234 |
dc->jmp_pc = dc->pc + offset; |
1235 |
} else {
|
1236 |
dc->jmp = JMP_INDIRECT; |
1237 |
tcg_gen_movi_tl(env_btarget, dc->pc); |
1238 |
tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); |
1239 |
} |
1240 |
eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
|
1241 |
} |
1242 |
|
1243 |
static void dec_br(DisasContext *dc) |
1244 |
{ |
1245 |
unsigned int dslot, link, abs, mbar; |
1246 |
int mem_index = cpu_mmu_index(dc->env);
|
1247 |
|
1248 |
dslot = dc->ir & (1 << 20); |
1249 |
abs = dc->ir & (1 << 19); |
1250 |
link = dc->ir & (1 << 18); |
1251 |
|
1252 |
/* Memory barrier. */
|
1253 |
mbar = (dc->ir >> 16) & 31; |
1254 |
if (mbar == 2 && dc->imm == 4) { |
1255 |
LOG_DIS("mbar %d\n", dc->rd);
|
1256 |
/* Break the TB. */
|
1257 |
dc->cpustate_changed = 1;
|
1258 |
return;
|
1259 |
} |
1260 |
|
1261 |
LOG_DIS("br%s%s%s%s imm=%x\n",
|
1262 |
abs ? "a" : "", link ? "l" : "", |
1263 |
dc->type_b ? "i" : "", dslot ? "d" : "", |
1264 |
dc->imm); |
1265 |
|
1266 |
dc->delayed_branch = 1;
|
1267 |
if (dslot) {
|
1268 |
dc->delayed_branch = 2;
|
1269 |
dc->tb_flags |= D_FLAG; |
1270 |
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), |
1271 |
cpu_env, offsetof(CPUMBState, bimm)); |
1272 |
} |
1273 |
if (link && dc->rd)
|
1274 |
tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc); |
1275 |
|
1276 |
dc->jmp = JMP_INDIRECT; |
1277 |
if (abs) {
|
1278 |
tcg_gen_movi_tl(env_btaken, 1);
|
1279 |
tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc))); |
1280 |
if (link && !dslot) {
|
1281 |
if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) |
1282 |
t_gen_raise_exception(dc, EXCP_BREAK); |
1283 |
if (dc->imm == 0) { |
1284 |
if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
|
1285 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1286 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1287 |
return;
|
1288 |
} |
1289 |
|
1290 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
1291 |
} |
1292 |
} |
1293 |
} else {
|
1294 |
if (dec_alu_op_b_is_small_imm(dc)) {
|
1295 |
dc->jmp = JMP_DIRECT; |
1296 |
dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); |
1297 |
} else {
|
1298 |
tcg_gen_movi_tl(env_btaken, 1);
|
1299 |
tcg_gen_movi_tl(env_btarget, dc->pc); |
1300 |
tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc))); |
1301 |
} |
1302 |
} |
1303 |
} |
1304 |
|
1305 |
static inline void do_rti(DisasContext *dc) |
1306 |
{ |
1307 |
TCGv t0, t1; |
1308 |
t0 = tcg_temp_new(); |
1309 |
t1 = tcg_temp_new(); |
1310 |
tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
|
1311 |
tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE); |
1312 |
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); |
1313 |
|
1314 |
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); |
1315 |
tcg_gen_or_tl(t1, t1, t0); |
1316 |
msr_write(dc, t1); |
1317 |
tcg_temp_free(t1); |
1318 |
tcg_temp_free(t0); |
1319 |
dc->tb_flags &= ~DRTI_FLAG; |
1320 |
} |
1321 |
|
1322 |
static inline void do_rtb(DisasContext *dc) |
1323 |
{ |
1324 |
TCGv t0, t1; |
1325 |
t0 = tcg_temp_new(); |
1326 |
t1 = tcg_temp_new(); |
1327 |
tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP); |
1328 |
tcg_gen_shri_tl(t0, t1, 1);
|
1329 |
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); |
1330 |
|
1331 |
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); |
1332 |
tcg_gen_or_tl(t1, t1, t0); |
1333 |
msr_write(dc, t1); |
1334 |
tcg_temp_free(t1); |
1335 |
tcg_temp_free(t0); |
1336 |
dc->tb_flags &= ~DRTB_FLAG; |
1337 |
} |
1338 |
|
1339 |
static inline void do_rte(DisasContext *dc) |
1340 |
{ |
1341 |
TCGv t0, t1; |
1342 |
t0 = tcg_temp_new(); |
1343 |
t1 = tcg_temp_new(); |
1344 |
|
1345 |
tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE); |
1346 |
tcg_gen_andi_tl(t1, t1, ~MSR_EIP); |
1347 |
tcg_gen_shri_tl(t0, t1, 1);
|
1348 |
tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM)); |
1349 |
|
1350 |
tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM)); |
1351 |
tcg_gen_or_tl(t1, t1, t0); |
1352 |
msr_write(dc, t1); |
1353 |
tcg_temp_free(t1); |
1354 |
tcg_temp_free(t0); |
1355 |
dc->tb_flags &= ~DRTE_FLAG; |
1356 |
} |
1357 |
|
1358 |
static void dec_rts(DisasContext *dc) |
1359 |
{ |
1360 |
unsigned int b_bit, i_bit, e_bit; |
1361 |
int mem_index = cpu_mmu_index(dc->env);
|
1362 |
|
1363 |
i_bit = dc->ir & (1 << 21); |
1364 |
b_bit = dc->ir & (1 << 22); |
1365 |
e_bit = dc->ir & (1 << 23); |
1366 |
|
1367 |
dc->delayed_branch = 2;
|
1368 |
dc->tb_flags |= D_FLAG; |
1369 |
tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)), |
1370 |
cpu_env, offsetof(CPUMBState, bimm)); |
1371 |
|
1372 |
if (i_bit) {
|
1373 |
LOG_DIS("rtid ir=%x\n", dc->ir);
|
1374 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1375 |
&& mem_index == MMU_USER_IDX) { |
1376 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1377 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1378 |
} |
1379 |
dc->tb_flags |= DRTI_FLAG; |
1380 |
} else if (b_bit) { |
1381 |
LOG_DIS("rtbd ir=%x\n", dc->ir);
|
1382 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1383 |
&& mem_index == MMU_USER_IDX) { |
1384 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1385 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1386 |
} |
1387 |
dc->tb_flags |= DRTB_FLAG; |
1388 |
} else if (e_bit) { |
1389 |
LOG_DIS("rted ir=%x\n", dc->ir);
|
1390 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1391 |
&& mem_index == MMU_USER_IDX) { |
1392 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1393 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1394 |
} |
1395 |
dc->tb_flags |= DRTE_FLAG; |
1396 |
} else
|
1397 |
LOG_DIS("rts ir=%x\n", dc->ir);
|
1398 |
|
1399 |
dc->jmp = JMP_INDIRECT; |
1400 |
tcg_gen_movi_tl(env_btaken, 1);
|
1401 |
tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc))); |
1402 |
} |
1403 |
|
1404 |
static int dec_check_fpuv2(DisasContext *dc) |
1405 |
{ |
1406 |
int r;
|
1407 |
|
1408 |
r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
|
1409 |
|
1410 |
if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
|
1411 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); |
1412 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1413 |
} |
1414 |
return r;
|
1415 |
} |
1416 |
|
1417 |
static void dec_fpu(DisasContext *dc) |
1418 |
{ |
1419 |
unsigned int fpu_insn; |
1420 |
|
1421 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1422 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
1423 |
&& !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
|
1424 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1425 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1426 |
return;
|
1427 |
} |
1428 |
|
1429 |
fpu_insn = (dc->ir >> 7) & 7; |
1430 |
|
1431 |
switch (fpu_insn) {
|
1432 |
case 0: |
1433 |
gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
1434 |
break;
|
1435 |
|
1436 |
case 1: |
1437 |
gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
1438 |
break;
|
1439 |
|
1440 |
case 2: |
1441 |
gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
1442 |
break;
|
1443 |
|
1444 |
case 3: |
1445 |
gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); |
1446 |
break;
|
1447 |
|
1448 |
case 4: |
1449 |
switch ((dc->ir >> 4) & 7) { |
1450 |
case 0: |
1451 |
gen_helper_fcmp_un(cpu_R[dc->rd], |
1452 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1453 |
break;
|
1454 |
case 1: |
1455 |
gen_helper_fcmp_lt(cpu_R[dc->rd], |
1456 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1457 |
break;
|
1458 |
case 2: |
1459 |
gen_helper_fcmp_eq(cpu_R[dc->rd], |
1460 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1461 |
break;
|
1462 |
case 3: |
1463 |
gen_helper_fcmp_le(cpu_R[dc->rd], |
1464 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1465 |
break;
|
1466 |
case 4: |
1467 |
gen_helper_fcmp_gt(cpu_R[dc->rd], |
1468 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1469 |
break;
|
1470 |
case 5: |
1471 |
gen_helper_fcmp_ne(cpu_R[dc->rd], |
1472 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1473 |
break;
|
1474 |
case 6: |
1475 |
gen_helper_fcmp_ge(cpu_R[dc->rd], |
1476 |
cpu_R[dc->ra], cpu_R[dc->rb]); |
1477 |
break;
|
1478 |
default:
|
1479 |
qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
|
1480 |
fpu_insn, dc->pc, dc->opcode); |
1481 |
dc->abort_at_next_insn = 1;
|
1482 |
break;
|
1483 |
} |
1484 |
break;
|
1485 |
|
1486 |
case 5: |
1487 |
if (!dec_check_fpuv2(dc)) {
|
1488 |
return;
|
1489 |
} |
1490 |
gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]); |
1491 |
break;
|
1492 |
|
1493 |
case 6: |
1494 |
if (!dec_check_fpuv2(dc)) {
|
1495 |
return;
|
1496 |
} |
1497 |
gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]); |
1498 |
break;
|
1499 |
|
1500 |
case 7: |
1501 |
if (!dec_check_fpuv2(dc)) {
|
1502 |
return;
|
1503 |
} |
1504 |
gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]); |
1505 |
break;
|
1506 |
|
1507 |
default:
|
1508 |
qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
|
1509 |
fpu_insn, dc->pc, dc->opcode); |
1510 |
dc->abort_at_next_insn = 1;
|
1511 |
break;
|
1512 |
} |
1513 |
} |
1514 |
|
1515 |
static void dec_null(DisasContext *dc) |
1516 |
{ |
1517 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1518 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
|
1519 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1520 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1521 |
return;
|
1522 |
} |
1523 |
qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
|
1524 |
dc->abort_at_next_insn = 1;
|
1525 |
} |
1526 |
|
1527 |
/* Insns connected to FSL or AXI stream attached devices. */
|
1528 |
static void dec_stream(DisasContext *dc) |
1529 |
{ |
1530 |
int mem_index = cpu_mmu_index(dc->env);
|
1531 |
TCGv_i32 t_id, t_ctrl; |
1532 |
int ctrl;
|
1533 |
|
1534 |
LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", |
1535 |
dc->type_b ? "" : "d", dc->imm); |
1536 |
|
1537 |
if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
|
1538 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); |
1539 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1540 |
return;
|
1541 |
} |
1542 |
|
1543 |
t_id = tcg_temp_new(); |
1544 |
if (dc->type_b) {
|
1545 |
tcg_gen_movi_tl(t_id, dc->imm & 0xf);
|
1546 |
ctrl = dc->imm >> 10;
|
1547 |
} else {
|
1548 |
tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
|
1549 |
ctrl = dc->imm >> 5;
|
1550 |
} |
1551 |
|
1552 |
t_ctrl = tcg_const_tl(ctrl); |
1553 |
|
1554 |
if (dc->rd == 0) { |
1555 |
gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); |
1556 |
} else {
|
1557 |
gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); |
1558 |
} |
1559 |
tcg_temp_free(t_id); |
1560 |
tcg_temp_free(t_ctrl); |
1561 |
} |
1562 |
|
1563 |
static struct decoder_info { |
1564 |
struct {
|
1565 |
uint32_t bits; |
1566 |
uint32_t mask; |
1567 |
}; |
1568 |
void (*dec)(DisasContext *dc);
|
1569 |
} decinfo[] = { |
1570 |
{DEC_ADD, dec_add}, |
1571 |
{DEC_SUB, dec_sub}, |
1572 |
{DEC_AND, dec_and}, |
1573 |
{DEC_XOR, dec_xor}, |
1574 |
{DEC_OR, dec_or}, |
1575 |
{DEC_BIT, dec_bit}, |
1576 |
{DEC_BARREL, dec_barrel}, |
1577 |
{DEC_LD, dec_load}, |
1578 |
{DEC_ST, dec_store}, |
1579 |
{DEC_IMM, dec_imm}, |
1580 |
{DEC_BR, dec_br}, |
1581 |
{DEC_BCC, dec_bcc}, |
1582 |
{DEC_RTS, dec_rts}, |
1583 |
{DEC_FPU, dec_fpu}, |
1584 |
{DEC_MUL, dec_mul}, |
1585 |
{DEC_DIV, dec_div}, |
1586 |
{DEC_MSR, dec_msr}, |
1587 |
{DEC_STREAM, dec_stream}, |
1588 |
{{0, 0}, dec_null} |
1589 |
}; |
1590 |
|
1591 |
static inline void decode(DisasContext *dc) |
1592 |
{ |
1593 |
uint32_t ir; |
1594 |
int i;
|
1595 |
|
1596 |
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
|
1597 |
tcg_gen_debug_insn_start(dc->pc); |
1598 |
|
1599 |
dc->ir = ir = ldl_code(dc->pc); |
1600 |
LOG_DIS("%8.8x\t", dc->ir);
|
1601 |
|
1602 |
if (dc->ir)
|
1603 |
dc->nr_nops = 0;
|
1604 |
else {
|
1605 |
if ((dc->tb_flags & MSR_EE_FLAG)
|
1606 |
&& (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
|
1607 |
&& (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
|
1608 |
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); |
1609 |
t_gen_raise_exception(dc, EXCP_HW_EXCP); |
1610 |
return;
|
1611 |
} |
1612 |
|
1613 |
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
|
1614 |
dc->nr_nops++; |
1615 |
if (dc->nr_nops > 4) |
1616 |
cpu_abort(dc->env, "fetching nop sequence\n");
|
1617 |
} |
1618 |
/* bit 2 seems to indicate insn type. */
|
1619 |
dc->type_b = ir & (1 << 29); |
1620 |
|
1621 |
dc->opcode = EXTRACT_FIELD(ir, 26, 31); |
1622 |
dc->rd = EXTRACT_FIELD(ir, 21, 25); |
1623 |
dc->ra = EXTRACT_FIELD(ir, 16, 20); |
1624 |
dc->rb = EXTRACT_FIELD(ir, 11, 15); |
1625 |
dc->imm = EXTRACT_FIELD(ir, 0, 15); |
1626 |
|
1627 |
/* Large switch for all insns. */
|
1628 |
for (i = 0; i < ARRAY_SIZE(decinfo); i++) { |
1629 |
if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
|
1630 |
decinfo[i].dec(dc); |
1631 |
break;
|
1632 |
} |
1633 |
} |
1634 |
} |
1635 |
|
1636 |
static void check_breakpoint(CPUMBState *env, DisasContext *dc) |
1637 |
{ |
1638 |
CPUBreakpoint *bp; |
1639 |
|
1640 |
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
1641 |
QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
1642 |
if (bp->pc == dc->pc) {
|
1643 |
t_gen_raise_exception(dc, EXCP_DEBUG); |
1644 |
dc->is_jmp = DISAS_UPDATE; |
1645 |
} |
1646 |
} |
1647 |
} |
1648 |
} |
1649 |
|
1650 |
/* generate intermediate code for basic block 'tb'. */
|
1651 |
static void |
1652 |
gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, |
1653 |
int search_pc)
|
1654 |
{ |
1655 |
uint16_t *gen_opc_end; |
1656 |
uint32_t pc_start; |
1657 |
int j, lj;
|
1658 |
struct DisasContext ctx;
|
1659 |
struct DisasContext *dc = &ctx;
|
1660 |
uint32_t next_page_start, org_flags; |
1661 |
target_ulong npc; |
1662 |
int num_insns;
|
1663 |
int max_insns;
|
1664 |
|
1665 |
qemu_log_try_set_file(stderr); |
1666 |
|
1667 |
pc_start = tb->pc; |
1668 |
dc->env = env; |
1669 |
dc->tb = tb; |
1670 |
org_flags = dc->synced_flags = dc->tb_flags = tb->flags; |
1671 |
|
1672 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1673 |
|
1674 |
dc->is_jmp = DISAS_NEXT; |
1675 |
dc->jmp = 0;
|
1676 |
dc->delayed_branch = !!(dc->tb_flags & D_FLAG); |
1677 |
if (dc->delayed_branch) {
|
1678 |
dc->jmp = JMP_INDIRECT; |
1679 |
} |
1680 |
dc->pc = pc_start; |
1681 |
dc->singlestep_enabled = env->singlestep_enabled; |
1682 |
dc->cpustate_changed = 0;
|
1683 |
dc->abort_at_next_insn = 0;
|
1684 |
dc->nr_nops = 0;
|
1685 |
|
1686 |
if (pc_start & 3) |
1687 |
cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
|
1688 |
|
1689 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1690 |
#if !SIM_COMPAT
|
1691 |
qemu_log("--------------\n");
|
1692 |
log_cpu_state(env, 0);
|
1693 |
#endif
|
1694 |
} |
1695 |
|
1696 |
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
1697 |
lj = -1;
|
1698 |
num_insns = 0;
|
1699 |
max_insns = tb->cflags & CF_COUNT_MASK; |
1700 |
if (max_insns == 0) |
1701 |
max_insns = CF_COUNT_MASK; |
1702 |
|
1703 |
gen_icount_start(); |
1704 |
do
|
1705 |
{ |
1706 |
#if SIM_COMPAT
|
1707 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1708 |
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); |
1709 |
gen_helper_debug(); |
1710 |
} |
1711 |
#endif
|
1712 |
check_breakpoint(env, dc); |
1713 |
|
1714 |
if (search_pc) {
|
1715 |
j = gen_opc_ptr - gen_opc_buf; |
1716 |
if (lj < j) {
|
1717 |
lj++; |
1718 |
while (lj < j)
|
1719 |
gen_opc_instr_start[lj++] = 0;
|
1720 |
} |
1721 |
gen_opc_pc[lj] = dc->pc; |
1722 |
gen_opc_instr_start[lj] = 1;
|
1723 |
gen_opc_icount[lj] = num_insns; |
1724 |
} |
1725 |
|
1726 |
/* Pretty disas. */
|
1727 |
LOG_DIS("%8.8x:\t", dc->pc);
|
1728 |
|
1729 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1730 |
gen_io_start(); |
1731 |
|
1732 |
dc->clear_imm = 1;
|
1733 |
decode(dc); |
1734 |
if (dc->clear_imm)
|
1735 |
dc->tb_flags &= ~IMM_FLAG; |
1736 |
dc->pc += 4;
|
1737 |
num_insns++; |
1738 |
|
1739 |
if (dc->delayed_branch) {
|
1740 |
dc->delayed_branch--; |
1741 |
if (!dc->delayed_branch) {
|
1742 |
if (dc->tb_flags & DRTI_FLAG)
|
1743 |
do_rti(dc); |
1744 |
if (dc->tb_flags & DRTB_FLAG)
|
1745 |
do_rtb(dc); |
1746 |
if (dc->tb_flags & DRTE_FLAG)
|
1747 |
do_rte(dc); |
1748 |
/* Clear the delay slot flag. */
|
1749 |
dc->tb_flags &= ~D_FLAG; |
1750 |
/* If it is a direct jump, try direct chaining. */
|
1751 |
if (dc->jmp == JMP_INDIRECT) {
|
1752 |
eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc)); |
1753 |
dc->is_jmp = DISAS_JUMP; |
1754 |
} else if (dc->jmp == JMP_DIRECT) { |
1755 |
t_sync_flags(dc); |
1756 |
gen_goto_tb(dc, 0, dc->jmp_pc);
|
1757 |
dc->is_jmp = DISAS_TB_JUMP; |
1758 |
} else if (dc->jmp == JMP_DIRECT_CC) { |
1759 |
int l1;
|
1760 |
|
1761 |
t_sync_flags(dc); |
1762 |
l1 = gen_new_label(); |
1763 |
/* Conditional jmp. */
|
1764 |
tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
|
1765 |
gen_goto_tb(dc, 1, dc->pc);
|
1766 |
gen_set_label(l1); |
1767 |
gen_goto_tb(dc, 0, dc->jmp_pc);
|
1768 |
|
1769 |
dc->is_jmp = DISAS_TB_JUMP; |
1770 |
} |
1771 |
break;
|
1772 |
} |
1773 |
} |
1774 |
if (env->singlestep_enabled)
|
1775 |
break;
|
1776 |
} while (!dc->is_jmp && !dc->cpustate_changed
|
1777 |
&& gen_opc_ptr < gen_opc_end |
1778 |
&& !singlestep |
1779 |
&& (dc->pc < next_page_start) |
1780 |
&& num_insns < max_insns); |
1781 |
|
1782 |
npc = dc->pc; |
1783 |
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
|
1784 |
if (dc->tb_flags & D_FLAG) {
|
1785 |
dc->is_jmp = DISAS_UPDATE; |
1786 |
tcg_gen_movi_tl(cpu_SR[SR_PC], npc); |
1787 |
sync_jmpstate(dc); |
1788 |
} else
|
1789 |
npc = dc->jmp_pc; |
1790 |
} |
1791 |
|
1792 |
if (tb->cflags & CF_LAST_IO)
|
1793 |
gen_io_end(); |
1794 |
/* Force an update if the per-tb cpu state has changed. */
|
1795 |
if (dc->is_jmp == DISAS_NEXT
|
1796 |
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) { |
1797 |
dc->is_jmp = DISAS_UPDATE; |
1798 |
tcg_gen_movi_tl(cpu_SR[SR_PC], npc); |
1799 |
} |
1800 |
t_sync_flags(dc); |
1801 |
|
1802 |
if (unlikely(env->singlestep_enabled)) {
|
1803 |
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); |
1804 |
|
1805 |
if (dc->is_jmp != DISAS_JUMP) {
|
1806 |
tcg_gen_movi_tl(cpu_SR[SR_PC], npc); |
1807 |
} |
1808 |
gen_helper_raise_exception(tmp); |
1809 |
tcg_temp_free_i32(tmp); |
1810 |
} else {
|
1811 |
switch(dc->is_jmp) {
|
1812 |
case DISAS_NEXT:
|
1813 |
gen_goto_tb(dc, 1, npc);
|
1814 |
break;
|
1815 |
default:
|
1816 |
case DISAS_JUMP:
|
1817 |
case DISAS_UPDATE:
|
1818 |
/* indicate that the hash table must be used
|
1819 |
to find the next TB */
|
1820 |
tcg_gen_exit_tb(0);
|
1821 |
break;
|
1822 |
case DISAS_TB_JUMP:
|
1823 |
/* nothing more to generate */
|
1824 |
break;
|
1825 |
} |
1826 |
} |
1827 |
gen_icount_end(tb, num_insns); |
1828 |
*gen_opc_ptr = INDEX_op_end; |
1829 |
if (search_pc) {
|
1830 |
j = gen_opc_ptr - gen_opc_buf; |
1831 |
lj++; |
1832 |
while (lj <= j)
|
1833 |
gen_opc_instr_start[lj++] = 0;
|
1834 |
} else {
|
1835 |
tb->size = dc->pc - pc_start; |
1836 |
tb->icount = num_insns; |
1837 |
} |
1838 |
|
1839 |
#ifdef DEBUG_DISAS
|
1840 |
#if !SIM_COMPAT
|
1841 |
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
1842 |
qemu_log("\n");
|
1843 |
#if DISAS_GNU
|
1844 |
log_target_disas(pc_start, dc->pc - pc_start, 0);
|
1845 |
#endif
|
1846 |
qemu_log("\nisize=%d osize=%td\n",
|
1847 |
dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); |
1848 |
} |
1849 |
#endif
|
1850 |
#endif
|
1851 |
assert(!dc->abort_at_next_insn); |
1852 |
} |
1853 |
|
1854 |
void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb) |
1855 |
{ |
1856 |
gen_intermediate_code_internal(env, tb, 0);
|
1857 |
} |
1858 |
|
1859 |
void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb) |
1860 |
{ |
1861 |
gen_intermediate_code_internal(env, tb, 1);
|
1862 |
} |
1863 |
|
1864 |
void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf,
|
1865 |
int flags)
|
1866 |
{ |
1867 |
int i;
|
1868 |
|
1869 |
if (!env || !f)
|
1870 |
return;
|
1871 |
|
1872 |
cpu_fprintf(f, "IN: PC=%x %s\n",
|
1873 |
env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); |
1874 |
cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
|
1875 |
env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], |
1876 |
env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); |
1877 |
cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
|
1878 |
env->btaken, env->btarget, |
1879 |
(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", |
1880 |
(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", |
1881 |
(env->sregs[SR_MSR] & MSR_EIP), |
1882 |
(env->sregs[SR_MSR] & MSR_IE)); |
1883 |
|
1884 |
for (i = 0; i < 32; i++) { |
1885 |
cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
|
1886 |
if ((i + 1) % 4 == 0) |
1887 |
cpu_fprintf(f, "\n");
|
1888 |
} |
1889 |
cpu_fprintf(f, "\n\n");
|
1890 |
} |
1891 |
|
1892 |
CPUMBState *cpu_mb_init (const char *cpu_model) |
1893 |
{ |
1894 |
CPUMBState *env; |
1895 |
static int tcg_initialized = 0; |
1896 |
int i;
|
1897 |
|
1898 |
env = g_malloc0(sizeof(CPUMBState));
|
1899 |
|
1900 |
cpu_exec_init(env); |
1901 |
cpu_state_reset(env); |
1902 |
qemu_init_vcpu(env); |
1903 |
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); |
1904 |
|
1905 |
if (tcg_initialized)
|
1906 |
return env;
|
1907 |
|
1908 |
tcg_initialized = 1;
|
1909 |
|
1910 |
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
1911 |
|
1912 |
env_debug = tcg_global_mem_new(TCG_AREG0, |
1913 |
offsetof(CPUMBState, debug), |
1914 |
"debug0");
|
1915 |
env_iflags = tcg_global_mem_new(TCG_AREG0, |
1916 |
offsetof(CPUMBState, iflags), |
1917 |
"iflags");
|
1918 |
env_imm = tcg_global_mem_new(TCG_AREG0, |
1919 |
offsetof(CPUMBState, imm), |
1920 |
"imm");
|
1921 |
env_btarget = tcg_global_mem_new(TCG_AREG0, |
1922 |
offsetof(CPUMBState, btarget), |
1923 |
"btarget");
|
1924 |
env_btaken = tcg_global_mem_new(TCG_AREG0, |
1925 |
offsetof(CPUMBState, btaken), |
1926 |
"btaken");
|
1927 |
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { |
1928 |
cpu_R[i] = tcg_global_mem_new(TCG_AREG0, |
1929 |
offsetof(CPUMBState, regs[i]), |
1930 |
regnames[i]); |
1931 |
} |
1932 |
for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { |
1933 |
cpu_SR[i] = tcg_global_mem_new(TCG_AREG0, |
1934 |
offsetof(CPUMBState, sregs[i]), |
1935 |
special_regnames[i]); |
1936 |
} |
1937 |
#define GEN_HELPER 2 |
1938 |
#include "helper.h" |
1939 |
|
1940 |
return env;
|
1941 |
} |
1942 |
|
1943 |
void cpu_state_reset(CPUMBState *env)
|
1944 |
{ |
1945 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
1946 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
1947 |
log_cpu_state(env, 0);
|
1948 |
} |
1949 |
|
1950 |
memset(env, 0, offsetof(CPUMBState, breakpoints));
|
1951 |
tlb_flush(env, 1);
|
1952 |
|
1953 |
/* Disable stack protector. */
|
1954 |
env->shr = ~0;
|
1955 |
|
1956 |
env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
|
1957 |
| PVR0_USE_BARREL_MASK \ |
1958 |
| PVR0_USE_DIV_MASK \ |
1959 |
| PVR0_USE_HW_MUL_MASK \ |
1960 |
| PVR0_USE_EXC_MASK \ |
1961 |
| PVR0_USE_ICACHE_MASK \ |
1962 |
| PVR0_USE_DCACHE_MASK \ |
1963 |
| PVR0_USE_MMU \ |
1964 |
| (0xb << 8); |
1965 |
env->pvr.regs[2] = PVR2_D_OPB_MASK \
|
1966 |
| PVR2_D_LMB_MASK \ |
1967 |
| PVR2_I_OPB_MASK \ |
1968 |
| PVR2_I_LMB_MASK \ |
1969 |
| PVR2_USE_MSR_INSTR \ |
1970 |
| PVR2_USE_PCMP_INSTR \ |
1971 |
| PVR2_USE_BARREL_MASK \ |
1972 |
| PVR2_USE_DIV_MASK \ |
1973 |
| PVR2_USE_HW_MUL_MASK \ |
1974 |
| PVR2_USE_MUL64_MASK \ |
1975 |
| PVR2_USE_FPU_MASK \ |
1976 |
| PVR2_USE_FPU2_MASK \ |
1977 |
| PVR2_FPU_EXC_MASK \ |
1978 |
| 0;
|
1979 |
env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ |
1980 |
env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); |
1981 |
|
1982 |
#if defined(CONFIG_USER_ONLY)
|
1983 |
/* start in user mode with interrupts enabled. */
|
1984 |
env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; |
1985 |
env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ |
1986 |
#else
|
1987 |
env->sregs[SR_MSR] = 0;
|
1988 |
mmu_init(&env->mmu); |
1989 |
env->mmu.c_mmu = 3;
|
1990 |
env->mmu.c_mmu_tlb_access = 3;
|
1991 |
env->mmu.c_mmu_zones = 16;
|
1992 |
#endif
|
1993 |
} |
1994 |
|
1995 |
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) |
1996 |
{ |
1997 |
env->sregs[SR_PC] = gen_opc_pc[pc_pos]; |
1998 |
} |