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1
/*
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   SPARC translation
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   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   Copyright (C) 2003-2005 Fabrice Bellard
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   This library is free software; you can redistribute it and/or
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   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "helper.h"
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#include "tcg-op.h"
33

    
34
#define DEBUG_DISAS
35

    
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#define DYNAMIC_PC  1 /* dynamic pc value */
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#define JUMP_PC     2 /* dynamic pc value which takes only two values
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                         according to jump_pc[T2] */
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/* global register indexes */
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static TCGv cpu_env, cpu_regwptr;
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static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
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static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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#ifdef TARGET_SPARC64
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static TCGv cpu_xcc;
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#endif
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/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50

    
51
#include "gen-icount.h"
52

    
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typedef struct DisasContext {
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    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
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    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
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    int is_br;
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    int mem_idx;
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    int fpu_enabled;
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    int address_mask_32bit;
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    struct TranslationBlock *tb;
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    uint32_t features;
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} DisasContext;
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// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
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  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
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// This function uses the order in the manuals, i.e. bit 0 is 2^0
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#define GET_FIELD_SP(X, FROM, TO) \
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    GET_FIELD(X, 31 - (TO), 31 - (FROM))
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73
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
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#ifdef TARGET_SPARC64
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#define FFPREG(r) (r)
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#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
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#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
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#else
81
#define FFPREG(r) (r)
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#define DFPREG(r) (r & 0x1e)
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#define QFPREG(r) (r & 0x1c)
84
#endif
85

    
86
static int sign_extend(int x, int len)
87
{
88
    len = 32 - len;
89
    return (x << len) >> len;
90
}
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92
#define IS_IMM (insn & (1<<13))
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94
/* floating point registers moves */
95
static void gen_op_load_fpr_FT0(unsigned int src)
96
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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}
100

    
101
static void gen_op_load_fpr_FT1(unsigned int src)
102
{
103
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
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}
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static void gen_op_store_FT0_fpr(unsigned int dst)
108
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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}
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static void gen_op_load_fpr_DT0(unsigned int src)
114
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.lower));
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}
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static void gen_op_load_fpr_DT1(unsigned int src)
124
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
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                   offsetof(CPU_DoubleU, l.lower));
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}
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133
static void gen_op_store_DT0_fpr(unsigned int dst)
134
{
135
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.lower));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
141
}
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143
static void gen_op_load_fpr_QT0(unsigned int src)
144
{
145
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
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                   offsetof(CPU_QuadU, l.upmost));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
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                   offsetof(CPU_QuadU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
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                   offsetof(CPU_QuadU, l.lower));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
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                   offsetof(CPU_QuadU, l.lowest));
157
}
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159
static void gen_op_load_fpr_QT1(unsigned int src)
160
{
161
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
162
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upmost));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
168
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.lower));
170
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
171
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.lowest));
173
}
174

    
175
static void gen_op_store_QT0_fpr(unsigned int dst)
176
{
177
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178
                   offsetof(CPU_QuadU, l.upmost));
179
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
180
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
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                   offsetof(CPU_QuadU, l.upper));
182
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
183
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184
                   offsetof(CPU_QuadU, l.lower));
185
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
186
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
187
                   offsetof(CPU_QuadU, l.lowest));
188
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
189
}
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191
/* moves */
192
#ifdef CONFIG_USER_ONLY
193
#define supervisor(dc) 0
194
#ifdef TARGET_SPARC64
195
#define hypervisor(dc) 0
196
#endif
197
#else
198
#define supervisor(dc) (dc->mem_idx >= 1)
199
#ifdef TARGET_SPARC64
200
#define hypervisor(dc) (dc->mem_idx == 2)
201
#else
202
#endif
203
#endif
204

    
205
#ifdef TARGET_SPARC64
206
#ifndef TARGET_ABI32
207
#define AM_CHECK(dc) ((dc)->address_mask_32bit)
208
#else
209
#define AM_CHECK(dc) (1)
210
#endif
211
#endif
212

    
213
static inline void gen_address_mask(DisasContext *dc, TCGv addr)
214
{
215
#ifdef TARGET_SPARC64
216
    if (AM_CHECK(dc))
217
        tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
218
#endif
219
}
220

    
221
static inline void gen_movl_reg_TN(int reg, TCGv tn)
222
{
223
    if (reg == 0)
224
        tcg_gen_movi_tl(tn, 0);
225
    else if (reg < 8)
226
        tcg_gen_mov_tl(tn, cpu_gregs[reg]);
227
    else {
228
        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
229
    }
230
}
231

    
232
static inline void gen_movl_TN_reg(int reg, TCGv tn)
233
{
234
    if (reg == 0)
235
        return;
236
    else if (reg < 8)
237
        tcg_gen_mov_tl(cpu_gregs[reg], tn);
238
    else {
239
        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
240
    }
241
}
242

    
243
static inline void gen_goto_tb(DisasContext *s, int tb_num,
244
                               target_ulong pc, target_ulong npc)
245
{
246
    TranslationBlock *tb;
247

    
248
    tb = s->tb;
249
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
250
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
251
        /* jump to same page: we can use a direct jump */
252
        tcg_gen_goto_tb(tb_num);
253
        tcg_gen_movi_tl(cpu_pc, pc);
254
        tcg_gen_movi_tl(cpu_npc, npc);
255
        tcg_gen_exit_tb((long)tb + tb_num);
256
    } else {
257
        /* jump to another page: currently not optimized */
258
        tcg_gen_movi_tl(cpu_pc, pc);
259
        tcg_gen_movi_tl(cpu_npc, npc);
260
        tcg_gen_exit_tb(0);
261
    }
262
}
263

    
264
// XXX suboptimal
265
static inline void gen_mov_reg_N(TCGv reg, TCGv src)
266
{
267
    tcg_gen_extu_i32_tl(reg, src);
268
    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
269
    tcg_gen_andi_tl(reg, reg, 0x1);
270
}
271

    
272
static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
273
{
274
    tcg_gen_extu_i32_tl(reg, src);
275
    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
276
    tcg_gen_andi_tl(reg, reg, 0x1);
277
}
278

    
279
static inline void gen_mov_reg_V(TCGv reg, TCGv src)
280
{
281
    tcg_gen_extu_i32_tl(reg, src);
282
    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
283
    tcg_gen_andi_tl(reg, reg, 0x1);
284
}
285

    
286
static inline void gen_mov_reg_C(TCGv reg, TCGv src)
287
{
288
    tcg_gen_extu_i32_tl(reg, src);
289
    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
290
    tcg_gen_andi_tl(reg, reg, 0x1);
291
}
292

    
293
static inline void gen_cc_clear_icc(void)
294
{
295
    tcg_gen_movi_i32(cpu_psr, 0);
296
}
297

    
298
#ifdef TARGET_SPARC64
299
static inline void gen_cc_clear_xcc(void)
300
{
301
    tcg_gen_movi_i32(cpu_xcc, 0);
302
}
303
#endif
304

    
305
/* old op:
306
    if (!T0)
307
        env->psr |= PSR_ZERO;
308
    if ((int32_t) T0 < 0)
309
        env->psr |= PSR_NEG;
310
*/
311
static inline void gen_cc_NZ_icc(TCGv dst)
312
{
313
    TCGv r_temp;
314
    int l1, l2;
315

    
316
    l1 = gen_new_label();
317
    l2 = gen_new_label();
318
    r_temp = tcg_temp_new(TCG_TYPE_TL);
319
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
320
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
321
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
322
    gen_set_label(l1);
323
    tcg_gen_ext_i32_tl(r_temp, dst);
324
    tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
325
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
326
    gen_set_label(l2);
327
    tcg_temp_free(r_temp);
328
}
329

    
330
#ifdef TARGET_SPARC64
331
static inline void gen_cc_NZ_xcc(TCGv dst)
332
{
333
    int l1, l2;
334

    
335
    l1 = gen_new_label();
336
    l2 = gen_new_label();
337
    tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
338
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
339
    gen_set_label(l1);
340
    tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
341
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
342
    gen_set_label(l2);
343
}
344
#endif
345

    
346
/* old op:
347
    if (T0 < src1)
348
        env->psr |= PSR_CARRY;
349
*/
350
static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
351
{
352
    TCGv r_temp;
353
    int l1;
354

    
355
    l1 = gen_new_label();
356
    r_temp = tcg_temp_new(TCG_TYPE_TL);
357
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
358
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
359
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
360
    gen_set_label(l1);
361
    tcg_temp_free(r_temp);
362
}
363

    
364
#ifdef TARGET_SPARC64
365
static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
366
{
367
    int l1;
368

    
369
    l1 = gen_new_label();
370
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
371
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
372
    gen_set_label(l1);
373
}
374
#endif
375

    
376
/* old op:
377
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
378
        env->psr |= PSR_OVF;
379
*/
380
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
381
{
382
    TCGv r_temp;
383

    
384
    r_temp = tcg_temp_new(TCG_TYPE_TL);
385
    tcg_gen_xor_tl(r_temp, src1, src2);
386
    tcg_gen_xori_tl(r_temp, r_temp, -1);
387
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
388
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
389
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
390
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
391
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
392
    tcg_temp_free(r_temp);
393
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
394
}
395

    
396
#ifdef TARGET_SPARC64
397
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
398
{
399
    TCGv r_temp;
400

    
401
    r_temp = tcg_temp_new(TCG_TYPE_TL);
402
    tcg_gen_xor_tl(r_temp, src1, src2);
403
    tcg_gen_xori_tl(r_temp, r_temp, -1);
404
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
405
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
406
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
407
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
408
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
409
    tcg_temp_free(r_temp);
410
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
411
}
412
#endif
413

    
414
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
415
{
416
    TCGv r_temp, r_const;
417
    int l1;
418

    
419
    l1 = gen_new_label();
420

    
421
    r_temp = tcg_temp_new(TCG_TYPE_TL);
422
    tcg_gen_xor_tl(r_temp, src1, src2);
423
    tcg_gen_xori_tl(r_temp, r_temp, -1);
424
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
425
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
426
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
427
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
428
    r_const = tcg_const_i32(TT_TOVF);
429
    tcg_gen_helper_0_1(raise_exception, r_const);
430
    tcg_temp_free(r_const);
431
    gen_set_label(l1);
432
    tcg_temp_free(r_temp);
433
}
434

    
435
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
436
{
437
    int l1;
438

    
439
    l1 = gen_new_label();
440
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
441
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
442
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
443
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
444
    gen_set_label(l1);
445
}
446

    
447
static inline void gen_tag_tv(TCGv src1, TCGv src2)
448
{
449
    int l1;
450
    TCGv r_const;
451

    
452
    l1 = gen_new_label();
453
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
454
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
455
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
456
    r_const = tcg_const_i32(TT_TOVF);
457
    tcg_gen_helper_0_1(raise_exception, r_const);
458
    tcg_temp_free(r_const);
459
    gen_set_label(l1);
460
}
461

    
462
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
463
{
464
    tcg_gen_mov_tl(cpu_cc_src, src1);
465
    tcg_gen_mov_tl(cpu_cc_src2, src2);
466
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
467
    gen_cc_clear_icc();
468
    gen_cc_NZ_icc(cpu_cc_dst);
469
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
470
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
471
#ifdef TARGET_SPARC64
472
    gen_cc_clear_xcc();
473
    gen_cc_NZ_xcc(cpu_cc_dst);
474
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
475
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
476
#endif
477
    tcg_gen_mov_tl(dst, cpu_cc_dst);
478
}
479

    
480
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
481
{
482
    tcg_gen_mov_tl(cpu_cc_src, src1);
483
    tcg_gen_mov_tl(cpu_cc_src2, src2);
484
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
485
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
486
    gen_cc_clear_icc();
487
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
488
#ifdef TARGET_SPARC64
489
    gen_cc_clear_xcc();
490
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
491
#endif
492
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
493
    gen_cc_NZ_icc(cpu_cc_dst);
494
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
495
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
496
#ifdef TARGET_SPARC64
497
    gen_cc_NZ_xcc(cpu_cc_dst);
498
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
499
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
500
#endif
501
    tcg_gen_mov_tl(dst, cpu_cc_dst);
502
}
503

    
504
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
505
{
506
    tcg_gen_mov_tl(cpu_cc_src, src1);
507
    tcg_gen_mov_tl(cpu_cc_src2, src2);
508
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
509
    gen_cc_clear_icc();
510
    gen_cc_NZ_icc(cpu_cc_dst);
511
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
512
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
513
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
514
#ifdef TARGET_SPARC64
515
    gen_cc_clear_xcc();
516
    gen_cc_NZ_xcc(cpu_cc_dst);
517
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
518
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
519
#endif
520
    tcg_gen_mov_tl(dst, cpu_cc_dst);
521
}
522

    
523
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
524
{
525
    tcg_gen_mov_tl(cpu_cc_src, src1);
526
    tcg_gen_mov_tl(cpu_cc_src2, src2);
527
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
528
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
529
    gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
530
    gen_cc_clear_icc();
531
    gen_cc_NZ_icc(cpu_cc_dst);
532
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
533
#ifdef TARGET_SPARC64
534
    gen_cc_clear_xcc();
535
    gen_cc_NZ_xcc(cpu_cc_dst);
536
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
537
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
538
#endif
539
    tcg_gen_mov_tl(dst, cpu_cc_dst);
540
}
541

    
542
/* old op:
543
    if (src1 < T1)
544
        env->psr |= PSR_CARRY;
545
*/
546
static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
547
{
548
    TCGv r_temp1, r_temp2;
549
    int l1;
550

    
551
    l1 = gen_new_label();
552
    r_temp1 = tcg_temp_new(TCG_TYPE_TL);
553
    r_temp2 = tcg_temp_new(TCG_TYPE_TL);
554
    tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
555
    tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
556
    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
557
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
558
    gen_set_label(l1);
559
    tcg_temp_free(r_temp1);
560
    tcg_temp_free(r_temp2);
561
}
562

    
563
#ifdef TARGET_SPARC64
564
static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
565
{
566
    int l1;
567

    
568
    l1 = gen_new_label();
569
    tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
570
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
571
    gen_set_label(l1);
572
}
573
#endif
574

    
575
/* old op:
576
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
577
        env->psr |= PSR_OVF;
578
*/
579
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
580
{
581
    TCGv r_temp;
582

    
583
    r_temp = tcg_temp_new(TCG_TYPE_TL);
584
    tcg_gen_xor_tl(r_temp, src1, src2);
585
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
586
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
587
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
588
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
589
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
590
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
591
    tcg_temp_free(r_temp);
592
}
593

    
594
#ifdef TARGET_SPARC64
595
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
596
{
597
    TCGv r_temp;
598

    
599
    r_temp = tcg_temp_new(TCG_TYPE_TL);
600
    tcg_gen_xor_tl(r_temp, src1, src2);
601
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
602
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
603
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
604
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
605
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
606
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
607
    tcg_temp_free(r_temp);
608
}
609
#endif
610

    
611
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
612
{
613
    TCGv r_temp, r_const;
614
    int l1;
615

    
616
    l1 = gen_new_label();
617

    
618
    r_temp = tcg_temp_new(TCG_TYPE_TL);
619
    tcg_gen_xor_tl(r_temp, src1, src2);
620
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
621
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
622
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
623
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
624
    r_const = tcg_const_i32(TT_TOVF);
625
    tcg_gen_helper_0_1(raise_exception, r_const);
626
    tcg_temp_free(r_const);
627
    gen_set_label(l1);
628
    tcg_temp_free(r_temp);
629
}
630

    
631
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
632
{
633
    tcg_gen_mov_tl(cpu_cc_src, src1);
634
    tcg_gen_mov_tl(cpu_cc_src2, src2);
635
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
636
    gen_cc_clear_icc();
637
    gen_cc_NZ_icc(cpu_cc_dst);
638
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
639
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
640
#ifdef TARGET_SPARC64
641
    gen_cc_clear_xcc();
642
    gen_cc_NZ_xcc(cpu_cc_dst);
643
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
644
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
645
#endif
646
    tcg_gen_mov_tl(dst, cpu_cc_dst);
647
}
648

    
649
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
650
{
651
    tcg_gen_mov_tl(cpu_cc_src, src1);
652
    tcg_gen_mov_tl(cpu_cc_src2, src2);
653
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
654
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
655
    gen_cc_clear_icc();
656
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
657
#ifdef TARGET_SPARC64
658
    gen_cc_clear_xcc();
659
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
660
#endif
661
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
662
    gen_cc_NZ_icc(cpu_cc_dst);
663
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
664
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
665
#ifdef TARGET_SPARC64
666
    gen_cc_NZ_xcc(cpu_cc_dst);
667
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
668
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
669
#endif
670
    tcg_gen_mov_tl(dst, cpu_cc_dst);
671
}
672

    
673
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
674
{
675
    tcg_gen_mov_tl(cpu_cc_src, src1);
676
    tcg_gen_mov_tl(cpu_cc_src2, src2);
677
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
678
    gen_cc_clear_icc();
679
    gen_cc_NZ_icc(cpu_cc_dst);
680
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
681
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
682
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
683
#ifdef TARGET_SPARC64
684
    gen_cc_clear_xcc();
685
    gen_cc_NZ_xcc(cpu_cc_dst);
686
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
687
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
688
#endif
689
    tcg_gen_mov_tl(dst, cpu_cc_dst);
690
}
691

    
692
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
693
{
694
    tcg_gen_mov_tl(cpu_cc_src, src1);
695
    tcg_gen_mov_tl(cpu_cc_src2, src2);
696
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
697
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
698
    gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
699
    gen_cc_clear_icc();
700
    gen_cc_NZ_icc(cpu_cc_dst);
701
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
702
#ifdef TARGET_SPARC64
703
    gen_cc_clear_xcc();
704
    gen_cc_NZ_xcc(cpu_cc_dst);
705
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
706
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
707
#endif
708
    tcg_gen_mov_tl(dst, cpu_cc_dst);
709
}
710

    
711
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
712
{
713
    TCGv r_temp, r_temp2;
714
    int l1;
715

    
716
    l1 = gen_new_label();
717
    r_temp = tcg_temp_new(TCG_TYPE_TL);
718
    r_temp2 = tcg_temp_new(TCG_TYPE_I32);
719

    
720
    /* old op:
721
    if (!(env->y & 1))
722
        T1 = 0;
723
    */
724
    tcg_gen_mov_tl(cpu_cc_src, src1);
725
    tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
726
    tcg_gen_trunc_tl_i32(r_temp2, r_temp);
727
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
728
    tcg_gen_mov_tl(cpu_cc_src2, src2);
729
    tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
730
    tcg_gen_movi_tl(cpu_cc_src2, 0);
731
    gen_set_label(l1);
732

    
733
    // b2 = T0 & 1;
734
    // env->y = (b2 << 31) | (env->y >> 1);
735
    tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
736
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
737
    tcg_gen_shli_i32(r_temp2, r_temp2, 31);
738
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
739
    tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
740
    tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
741
    tcg_temp_free(r_temp2);
742
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
743

    
744
    // b1 = N ^ V;
745
    gen_mov_reg_N(cpu_tmp0, cpu_psr);
746
    gen_mov_reg_V(r_temp, cpu_psr);
747
    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
748
    tcg_temp_free(r_temp);
749

    
750
    // T0 = (b1 << 31) | (T0 >> 1);
751
    // src1 = T0;
752
    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
753
    tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
754
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
755

    
756
    /* do addition and update flags */
757
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
758

    
759
    gen_cc_clear_icc();
760
    gen_cc_NZ_icc(cpu_cc_dst);
761
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
762
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
763
    tcg_gen_mov_tl(dst, cpu_cc_dst);
764
}
765

    
766
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
767
{
768
    TCGv r_temp, r_temp2;
769

    
770
    r_temp = tcg_temp_new(TCG_TYPE_I64);
771
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
772

    
773
    tcg_gen_extu_tl_i64(r_temp, src2);
774
    tcg_gen_extu_tl_i64(r_temp2, src1);
775
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
776

    
777
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
778
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
779
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
780
    tcg_temp_free(r_temp);
781
#ifdef TARGET_SPARC64
782
    tcg_gen_mov_i64(dst, r_temp2);
783
#else
784
    tcg_gen_trunc_i64_tl(dst, r_temp2);
785
#endif
786
    tcg_temp_free(r_temp2);
787
}
788

    
789
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
790
{
791
    TCGv r_temp, r_temp2;
792

    
793
    r_temp = tcg_temp_new(TCG_TYPE_I64);
794
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
795

    
796
    tcg_gen_ext_tl_i64(r_temp, src2);
797
    tcg_gen_ext_tl_i64(r_temp2, src1);
798
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
799

    
800
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
801
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
802
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
803
    tcg_temp_free(r_temp);
804
#ifdef TARGET_SPARC64
805
    tcg_gen_mov_i64(dst, r_temp2);
806
#else
807
    tcg_gen_trunc_i64_tl(dst, r_temp2);
808
#endif
809
    tcg_temp_free(r_temp2);
810
}
811

    
812
#ifdef TARGET_SPARC64
813
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
814
{
815
    TCGv r_const;
816
    int l1;
817

    
818
    l1 = gen_new_label();
819
    tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
820
    r_const = tcg_const_i32(TT_DIV_ZERO);
821
    tcg_gen_helper_0_1(raise_exception, r_const);
822
    tcg_temp_free(r_const);
823
    gen_set_label(l1);
824
}
825

    
826
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
827
{
828
    int l1, l2;
829

    
830
    l1 = gen_new_label();
831
    l2 = gen_new_label();
832
    tcg_gen_mov_tl(cpu_cc_src, src1);
833
    tcg_gen_mov_tl(cpu_cc_src2, src2);
834
    gen_trap_ifdivzero_tl(cpu_cc_src2);
835
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
836
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
837
    tcg_gen_movi_i64(dst, INT64_MIN);
838
    tcg_gen_br(l2);
839
    gen_set_label(l1);
840
    tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
841
    gen_set_label(l2);
842
}
843
#endif
844

    
845
static inline void gen_op_div_cc(TCGv dst)
846
{
847
    int l1;
848

    
849
    tcg_gen_mov_tl(cpu_cc_dst, dst);
850
    gen_cc_clear_icc();
851
    gen_cc_NZ_icc(cpu_cc_dst);
852
    l1 = gen_new_label();
853
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
854
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
855
    gen_set_label(l1);
856
}
857

    
858
static inline void gen_op_logic_cc(TCGv dst)
859
{
860
    tcg_gen_mov_tl(cpu_cc_dst, dst);
861

    
862
    gen_cc_clear_icc();
863
    gen_cc_NZ_icc(cpu_cc_dst);
864
#ifdef TARGET_SPARC64
865
    gen_cc_clear_xcc();
866
    gen_cc_NZ_xcc(cpu_cc_dst);
867
#endif
868
}
869

    
870
// 1
871
static inline void gen_op_eval_ba(TCGv dst)
872
{
873
    tcg_gen_movi_tl(dst, 1);
874
}
875

    
876
// Z
877
static inline void gen_op_eval_be(TCGv dst, TCGv src)
878
{
879
    gen_mov_reg_Z(dst, src);
880
}
881

    
882
// Z | (N ^ V)
883
static inline void gen_op_eval_ble(TCGv dst, TCGv src)
884
{
885
    gen_mov_reg_N(cpu_tmp0, src);
886
    gen_mov_reg_V(dst, src);
887
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
888
    gen_mov_reg_Z(cpu_tmp0, src);
889
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
890
}
891

    
892
// N ^ V
893
static inline void gen_op_eval_bl(TCGv dst, TCGv src)
894
{
895
    gen_mov_reg_V(cpu_tmp0, src);
896
    gen_mov_reg_N(dst, src);
897
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
898
}
899

    
900
// C | Z
901
static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
902
{
903
    gen_mov_reg_Z(cpu_tmp0, src);
904
    gen_mov_reg_C(dst, src);
905
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
906
}
907

    
908
// C
909
static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
910
{
911
    gen_mov_reg_C(dst, src);
912
}
913

    
914
// V
915
static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
916
{
917
    gen_mov_reg_V(dst, src);
918
}
919

    
920
// 0
921
static inline void gen_op_eval_bn(TCGv dst)
922
{
923
    tcg_gen_movi_tl(dst, 0);
924
}
925

    
926
// N
927
static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
928
{
929
    gen_mov_reg_N(dst, src);
930
}
931

    
932
// !Z
933
static inline void gen_op_eval_bne(TCGv dst, TCGv src)
934
{
935
    gen_mov_reg_Z(dst, src);
936
    tcg_gen_xori_tl(dst, dst, 0x1);
937
}
938

    
939
// !(Z | (N ^ V))
940
static inline void gen_op_eval_bg(TCGv dst, TCGv src)
941
{
942
    gen_mov_reg_N(cpu_tmp0, src);
943
    gen_mov_reg_V(dst, src);
944
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
945
    gen_mov_reg_Z(cpu_tmp0, src);
946
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
947
    tcg_gen_xori_tl(dst, dst, 0x1);
948
}
949

    
950
// !(N ^ V)
951
static inline void gen_op_eval_bge(TCGv dst, TCGv src)
952
{
953
    gen_mov_reg_V(cpu_tmp0, src);
954
    gen_mov_reg_N(dst, src);
955
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
956
    tcg_gen_xori_tl(dst, dst, 0x1);
957
}
958

    
959
// !(C | Z)
960
static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
961
{
962
    gen_mov_reg_Z(cpu_tmp0, src);
963
    gen_mov_reg_C(dst, src);
964
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
965
    tcg_gen_xori_tl(dst, dst, 0x1);
966
}
967

    
968
// !C
969
static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
970
{
971
    gen_mov_reg_C(dst, src);
972
    tcg_gen_xori_tl(dst, dst, 0x1);
973
}
974

    
975
// !N
976
static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
977
{
978
    gen_mov_reg_N(dst, src);
979
    tcg_gen_xori_tl(dst, dst, 0x1);
980
}
981

    
982
// !V
983
static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
984
{
985
    gen_mov_reg_V(dst, src);
986
    tcg_gen_xori_tl(dst, dst, 0x1);
987
}
988

    
989
/*
990
  FPSR bit field FCC1 | FCC0:
991
   0 =
992
   1 <
993
   2 >
994
   3 unordered
995
*/
996
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
997
                                    unsigned int fcc_offset)
998
{
999
    tcg_gen_extu_i32_tl(reg, src);
1000
    tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
1001
    tcg_gen_andi_tl(reg, reg, 0x1);
1002
}
1003

    
1004
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
1005
                                    unsigned int fcc_offset)
1006
{
1007
    tcg_gen_extu_i32_tl(reg, src);
1008
    tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
1009
    tcg_gen_andi_tl(reg, reg, 0x1);
1010
}
1011

    
1012
// !0: FCC0 | FCC1
1013
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1014
                                    unsigned int fcc_offset)
1015
{
1016
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1017
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1018
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1019
}
1020

    
1021
// 1 or 2: FCC0 ^ FCC1
1022
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1023
                                    unsigned int fcc_offset)
1024
{
1025
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1026
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1027
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1028
}
1029

    
1030
// 1 or 3: FCC0
1031
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1032
                                    unsigned int fcc_offset)
1033
{
1034
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1035
}
1036

    
1037
// 1: FCC0 & !FCC1
1038
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1039
                                    unsigned int fcc_offset)
1040
{
1041
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1042
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1043
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1044
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1045
}
1046

    
1047
// 2 or 3: FCC1
1048
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1049
                                    unsigned int fcc_offset)
1050
{
1051
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1052
}
1053

    
1054
// 2: !FCC0 & FCC1
1055
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1056
                                    unsigned int fcc_offset)
1057
{
1058
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1059
    tcg_gen_xori_tl(dst, dst, 0x1);
1060
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1061
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1062
}
1063

    
1064
// 3: FCC0 & FCC1
1065
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1066
                                    unsigned int fcc_offset)
1067
{
1068
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1069
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1070
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1071
}
1072

    
1073
// 0: !(FCC0 | FCC1)
1074
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1075
                                    unsigned int fcc_offset)
1076
{
1077
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1078
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1079
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1080
    tcg_gen_xori_tl(dst, dst, 0x1);
1081
}
1082

    
1083
// 0 or 3: !(FCC0 ^ FCC1)
1084
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1085
                                    unsigned int fcc_offset)
1086
{
1087
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1088
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1089
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1090
    tcg_gen_xori_tl(dst, dst, 0x1);
1091
}
1092

    
1093
// 0 or 2: !FCC0
1094
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1095
                                    unsigned int fcc_offset)
1096
{
1097
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1098
    tcg_gen_xori_tl(dst, dst, 0x1);
1099
}
1100

    
1101
// !1: !(FCC0 & !FCC1)
1102
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1103
                                    unsigned int fcc_offset)
1104
{
1105
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1106
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1107
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1108
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1109
    tcg_gen_xori_tl(dst, dst, 0x1);
1110
}
1111

    
1112
// 0 or 1: !FCC1
1113
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1114
                                    unsigned int fcc_offset)
1115
{
1116
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1117
    tcg_gen_xori_tl(dst, dst, 0x1);
1118
}
1119

    
1120
// !2: !(!FCC0 & FCC1)
1121
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1122
                                    unsigned int fcc_offset)
1123
{
1124
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1125
    tcg_gen_xori_tl(dst, dst, 0x1);
1126
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1127
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1128
    tcg_gen_xori_tl(dst, dst, 0x1);
1129
}
1130

    
1131
// !3: !(FCC0 & FCC1)
1132
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1133
                                    unsigned int fcc_offset)
1134
{
1135
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1136
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1137
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1138
    tcg_gen_xori_tl(dst, dst, 0x1);
1139
}
1140

    
1141
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1142
                               target_ulong pc2, TCGv r_cond)
1143
{
1144
    int l1;
1145

    
1146
    l1 = gen_new_label();
1147

    
1148
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1149

    
1150
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
1151

    
1152
    gen_set_label(l1);
1153
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
1154
}
1155

    
1156
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1157
                                target_ulong pc2, TCGv r_cond)
1158
{
1159
    int l1;
1160

    
1161
    l1 = gen_new_label();
1162

    
1163
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1164

    
1165
    gen_goto_tb(dc, 0, pc2, pc1);
1166

    
1167
    gen_set_label(l1);
1168
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1169
}
1170

    
1171
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1172
                                      TCGv r_cond)
1173
{
1174
    int l1, l2;
1175

    
1176
    l1 = gen_new_label();
1177
    l2 = gen_new_label();
1178

    
1179
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1180

    
1181
    tcg_gen_movi_tl(cpu_npc, npc1);
1182
    tcg_gen_br(l2);
1183

    
1184
    gen_set_label(l1);
1185
    tcg_gen_movi_tl(cpu_npc, npc2);
1186
    gen_set_label(l2);
1187
}
1188

    
1189
/* call this function before using the condition register as it may
1190
   have been set for a jump */
1191
static inline void flush_cond(DisasContext *dc, TCGv cond)
1192
{
1193
    if (dc->npc == JUMP_PC) {
1194
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1195
        dc->npc = DYNAMIC_PC;
1196
    }
1197
}
1198

    
1199
static inline void save_npc(DisasContext *dc, TCGv cond)
1200
{
1201
    if (dc->npc == JUMP_PC) {
1202
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1203
        dc->npc = DYNAMIC_PC;
1204
    } else if (dc->npc != DYNAMIC_PC) {
1205
        tcg_gen_movi_tl(cpu_npc, dc->npc);
1206
    }
1207
}
1208

    
1209
static inline void save_state(DisasContext *dc, TCGv cond)
1210
{
1211
    tcg_gen_movi_tl(cpu_pc, dc->pc);
1212
    save_npc(dc, cond);
1213
}
1214

    
1215
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1216
{
1217
    if (dc->npc == JUMP_PC) {
1218
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1219
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1220
        dc->pc = DYNAMIC_PC;
1221
    } else if (dc->npc == DYNAMIC_PC) {
1222
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1223
        dc->pc = DYNAMIC_PC;
1224
    } else {
1225
        dc->pc = dc->npc;
1226
    }
1227
}
1228

    
1229
static inline void gen_op_next_insn(void)
1230
{
1231
    tcg_gen_mov_tl(cpu_pc, cpu_npc);
1232
    tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1233
}
1234

    
1235
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1236
{
1237
    TCGv r_src;
1238

    
1239
#ifdef TARGET_SPARC64
1240
    if (cc)
1241
        r_src = cpu_xcc;
1242
    else
1243
        r_src = cpu_psr;
1244
#else
1245
    r_src = cpu_psr;
1246
#endif
1247
    switch (cond) {
1248
    case 0x0:
1249
        gen_op_eval_bn(r_dst);
1250
        break;
1251
    case 0x1:
1252
        gen_op_eval_be(r_dst, r_src);
1253
        break;
1254
    case 0x2:
1255
        gen_op_eval_ble(r_dst, r_src);
1256
        break;
1257
    case 0x3:
1258
        gen_op_eval_bl(r_dst, r_src);
1259
        break;
1260
    case 0x4:
1261
        gen_op_eval_bleu(r_dst, r_src);
1262
        break;
1263
    case 0x5:
1264
        gen_op_eval_bcs(r_dst, r_src);
1265
        break;
1266
    case 0x6:
1267
        gen_op_eval_bneg(r_dst, r_src);
1268
        break;
1269
    case 0x7:
1270
        gen_op_eval_bvs(r_dst, r_src);
1271
        break;
1272
    case 0x8:
1273
        gen_op_eval_ba(r_dst);
1274
        break;
1275
    case 0x9:
1276
        gen_op_eval_bne(r_dst, r_src);
1277
        break;
1278
    case 0xa:
1279
        gen_op_eval_bg(r_dst, r_src);
1280
        break;
1281
    case 0xb:
1282
        gen_op_eval_bge(r_dst, r_src);
1283
        break;
1284
    case 0xc:
1285
        gen_op_eval_bgu(r_dst, r_src);
1286
        break;
1287
    case 0xd:
1288
        gen_op_eval_bcc(r_dst, r_src);
1289
        break;
1290
    case 0xe:
1291
        gen_op_eval_bpos(r_dst, r_src);
1292
        break;
1293
    case 0xf:
1294
        gen_op_eval_bvc(r_dst, r_src);
1295
        break;
1296
    }
1297
}
1298

    
1299
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1300
{
1301
    unsigned int offset;
1302

    
1303
    switch (cc) {
1304
    default:
1305
    case 0x0:
1306
        offset = 0;
1307
        break;
1308
    case 0x1:
1309
        offset = 32 - 10;
1310
        break;
1311
    case 0x2:
1312
        offset = 34 - 10;
1313
        break;
1314
    case 0x3:
1315
        offset = 36 - 10;
1316
        break;
1317
    }
1318

    
1319
    switch (cond) {
1320
    case 0x0:
1321
        gen_op_eval_bn(r_dst);
1322
        break;
1323
    case 0x1:
1324
        gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1325
        break;
1326
    case 0x2:
1327
        gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1328
        break;
1329
    case 0x3:
1330
        gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1331
        break;
1332
    case 0x4:
1333
        gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1334
        break;
1335
    case 0x5:
1336
        gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1337
        break;
1338
    case 0x6:
1339
        gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1340
        break;
1341
    case 0x7:
1342
        gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1343
        break;
1344
    case 0x8:
1345
        gen_op_eval_ba(r_dst);
1346
        break;
1347
    case 0x9:
1348
        gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1349
        break;
1350
    case 0xa:
1351
        gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1352
        break;
1353
    case 0xb:
1354
        gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1355
        break;
1356
    case 0xc:
1357
        gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1358
        break;
1359
    case 0xd:
1360
        gen_op_eval_fble(r_dst, cpu_fsr, offset);
1361
        break;
1362
    case 0xe:
1363
        gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1364
        break;
1365
    case 0xf:
1366
        gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1367
        break;
1368
    }
1369
}
1370

    
1371
#ifdef TARGET_SPARC64
1372
// Inverted logic
1373
static const int gen_tcg_cond_reg[8] = {
1374
    -1,
1375
    TCG_COND_NE,
1376
    TCG_COND_GT,
1377
    TCG_COND_GE,
1378
    -1,
1379
    TCG_COND_EQ,
1380
    TCG_COND_LE,
1381
    TCG_COND_LT,
1382
};
1383

    
1384
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1385
{
1386
    int l1;
1387

    
1388
    l1 = gen_new_label();
1389
    tcg_gen_movi_tl(r_dst, 0);
1390
    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1391
    tcg_gen_movi_tl(r_dst, 1);
1392
    gen_set_label(l1);
1393
}
1394
#endif
1395

    
1396
/* XXX: potentially incorrect if dynamic npc */
1397
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1398
                      TCGv r_cond)
1399
{
1400
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1401
    target_ulong target = dc->pc + offset;
1402

    
1403
    if (cond == 0x0) {
1404
        /* unconditional not taken */
1405
        if (a) {
1406
            dc->pc = dc->npc + 4;
1407
            dc->npc = dc->pc + 4;
1408
        } else {
1409
            dc->pc = dc->npc;
1410
            dc->npc = dc->pc + 4;
1411
        }
1412
    } else if (cond == 0x8) {
1413
        /* unconditional taken */
1414
        if (a) {
1415
            dc->pc = target;
1416
            dc->npc = dc->pc + 4;
1417
        } else {
1418
            dc->pc = dc->npc;
1419
            dc->npc = target;
1420
        }
1421
    } else {
1422
        flush_cond(dc, r_cond);
1423
        gen_cond(r_cond, cc, cond);
1424
        if (a) {
1425
            gen_branch_a(dc, target, dc->npc, r_cond);
1426
            dc->is_br = 1;
1427
        } else {
1428
            dc->pc = dc->npc;
1429
            dc->jump_pc[0] = target;
1430
            dc->jump_pc[1] = dc->npc + 4;
1431
            dc->npc = JUMP_PC;
1432
        }
1433
    }
1434
}
1435

    
1436
/* XXX: potentially incorrect if dynamic npc */
1437
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1438
                      TCGv r_cond)
1439
{
1440
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1441
    target_ulong target = dc->pc + offset;
1442

    
1443
    if (cond == 0x0) {
1444
        /* unconditional not taken */
1445
        if (a) {
1446
            dc->pc = dc->npc + 4;
1447
            dc->npc = dc->pc + 4;
1448
        } else {
1449
            dc->pc = dc->npc;
1450
            dc->npc = dc->pc + 4;
1451
        }
1452
    } else if (cond == 0x8) {
1453
        /* unconditional taken */
1454
        if (a) {
1455
            dc->pc = target;
1456
            dc->npc = dc->pc + 4;
1457
        } else {
1458
            dc->pc = dc->npc;
1459
            dc->npc = target;
1460
        }
1461
    } else {
1462
        flush_cond(dc, r_cond);
1463
        gen_fcond(r_cond, cc, cond);
1464
        if (a) {
1465
            gen_branch_a(dc, target, dc->npc, r_cond);
1466
            dc->is_br = 1;
1467
        } else {
1468
            dc->pc = dc->npc;
1469
            dc->jump_pc[0] = target;
1470
            dc->jump_pc[1] = dc->npc + 4;
1471
            dc->npc = JUMP_PC;
1472
        }
1473
    }
1474
}
1475

    
1476
#ifdef TARGET_SPARC64
1477
/* XXX: potentially incorrect if dynamic npc */
1478
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1479
                          TCGv r_cond, TCGv r_reg)
1480
{
1481
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1482
    target_ulong target = dc->pc + offset;
1483

    
1484
    flush_cond(dc, r_cond);
1485
    gen_cond_reg(r_cond, cond, r_reg);
1486
    if (a) {
1487
        gen_branch_a(dc, target, dc->npc, r_cond);
1488
        dc->is_br = 1;
1489
    } else {
1490
        dc->pc = dc->npc;
1491
        dc->jump_pc[0] = target;
1492
        dc->jump_pc[1] = dc->npc + 4;
1493
        dc->npc = JUMP_PC;
1494
    }
1495
}
1496

    
1497
static GenOpFunc * const gen_fcmps[4] = {
1498
    helper_fcmps,
1499
    helper_fcmps_fcc1,
1500
    helper_fcmps_fcc2,
1501
    helper_fcmps_fcc3,
1502
};
1503

    
1504
static GenOpFunc * const gen_fcmpd[4] = {
1505
    helper_fcmpd,
1506
    helper_fcmpd_fcc1,
1507
    helper_fcmpd_fcc2,
1508
    helper_fcmpd_fcc3,
1509
};
1510

    
1511
static GenOpFunc * const gen_fcmpq[4] = {
1512
    helper_fcmpq,
1513
    helper_fcmpq_fcc1,
1514
    helper_fcmpq_fcc2,
1515
    helper_fcmpq_fcc3,
1516
};
1517

    
1518
static GenOpFunc * const gen_fcmpes[4] = {
1519
    helper_fcmpes,
1520
    helper_fcmpes_fcc1,
1521
    helper_fcmpes_fcc2,
1522
    helper_fcmpes_fcc3,
1523
};
1524

    
1525
static GenOpFunc * const gen_fcmped[4] = {
1526
    helper_fcmped,
1527
    helper_fcmped_fcc1,
1528
    helper_fcmped_fcc2,
1529
    helper_fcmped_fcc3,
1530
};
1531

    
1532
static GenOpFunc * const gen_fcmpeq[4] = {
1533
    helper_fcmpeq,
1534
    helper_fcmpeq_fcc1,
1535
    helper_fcmpeq_fcc2,
1536
    helper_fcmpeq_fcc3,
1537
};
1538

    
1539
static inline void gen_op_fcmps(int fccno)
1540
{
1541
    tcg_gen_helper_0_0(gen_fcmps[fccno]);
1542
}
1543

    
1544
static inline void gen_op_fcmpd(int fccno)
1545
{
1546
    tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1547
}
1548

    
1549
static inline void gen_op_fcmpq(int fccno)
1550
{
1551
    tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1552
}
1553

    
1554
static inline void gen_op_fcmpes(int fccno)
1555
{
1556
    tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1557
}
1558

    
1559
static inline void gen_op_fcmped(int fccno)
1560
{
1561
    tcg_gen_helper_0_0(gen_fcmped[fccno]);
1562
}
1563

    
1564
static inline void gen_op_fcmpeq(int fccno)
1565
{
1566
    tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1567
}
1568

    
1569
#else
1570

    
1571
static inline void gen_op_fcmps(int fccno)
1572
{
1573
    tcg_gen_helper_0_0(helper_fcmps);
1574
}
1575

    
1576
static inline void gen_op_fcmpd(int fccno)
1577
{
1578
    tcg_gen_helper_0_0(helper_fcmpd);
1579
}
1580

    
1581
static inline void gen_op_fcmpq(int fccno)
1582
{
1583
    tcg_gen_helper_0_0(helper_fcmpq);
1584
}
1585

    
1586
static inline void gen_op_fcmpes(int fccno)
1587
{
1588
    tcg_gen_helper_0_0(helper_fcmpes);
1589
}
1590

    
1591
static inline void gen_op_fcmped(int fccno)
1592
{
1593
    tcg_gen_helper_0_0(helper_fcmped);
1594
}
1595

    
1596
static inline void gen_op_fcmpeq(int fccno)
1597
{
1598
    tcg_gen_helper_0_0(helper_fcmpeq);
1599
}
1600
#endif
1601

    
1602
static inline void gen_op_fpexception_im(int fsr_flags)
1603
{
1604
    TCGv r_const;
1605

    
1606
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1607
    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1608
    r_const = tcg_const_i32(TT_FP_EXCP);
1609
    tcg_gen_helper_0_1(raise_exception, r_const);
1610
    tcg_temp_free(r_const);
1611
}
1612

    
1613
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1614
{
1615
#if !defined(CONFIG_USER_ONLY)
1616
    if (!dc->fpu_enabled) {
1617
        TCGv r_const;
1618

    
1619
        save_state(dc, r_cond);
1620
        r_const = tcg_const_i32(TT_NFPU_INSN);
1621
        tcg_gen_helper_0_1(raise_exception, r_const);
1622
        tcg_temp_free(r_const);
1623
        dc->is_br = 1;
1624
        return 1;
1625
    }
1626
#endif
1627
    return 0;
1628
}
1629

    
1630
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1631
{
1632
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1633
}
1634

    
1635
static inline void gen_clear_float_exceptions(void)
1636
{
1637
    tcg_gen_helper_0_0(helper_clear_float_exceptions);
1638
}
1639

    
1640
/* asi moves */
1641
#ifdef TARGET_SPARC64
1642
static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1643
{
1644
    int asi, offset;
1645
    TCGv r_asi;
1646

    
1647
    if (IS_IMM) {
1648
        r_asi = tcg_temp_new(TCG_TYPE_I32);
1649
        offset = GET_FIELD(insn, 25, 31);
1650
        tcg_gen_addi_tl(r_addr, r_addr, offset);
1651
        tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1652
    } else {
1653
        asi = GET_FIELD(insn, 19, 26);
1654
        r_asi = tcg_const_i32(asi);
1655
    }
1656
    return r_asi;
1657
}
1658

    
1659
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1660
                              int sign)
1661
{
1662
    TCGv r_asi, r_size, r_sign;
1663

    
1664
    r_asi = gen_get_asi(insn, addr);
1665
    r_size = tcg_const_i32(size);
1666
    r_sign = tcg_const_i32(sign);
1667
    tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1668
    tcg_temp_free(r_sign);
1669
    tcg_temp_free(r_size);
1670
    tcg_temp_free(r_asi);
1671
}
1672

    
1673
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1674
{
1675
    TCGv r_asi, r_size;
1676

    
1677
    r_asi = gen_get_asi(insn, addr);
1678
    r_size = tcg_const_i32(size);
1679
    tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1680
    tcg_temp_free(r_size);
1681
    tcg_temp_free(r_asi);
1682
}
1683

    
1684
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1685
{
1686
    TCGv r_asi, r_size, r_rd;
1687

    
1688
    r_asi = gen_get_asi(insn, addr);
1689
    r_size = tcg_const_i32(size);
1690
    r_rd = tcg_const_i32(rd);
1691
    tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1692
    tcg_temp_free(r_rd);
1693
    tcg_temp_free(r_size);
1694
    tcg_temp_free(r_asi);
1695
}
1696

    
1697
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1698
{
1699
    TCGv r_asi, r_size, r_rd;
1700

    
1701
    r_asi = gen_get_asi(insn, addr);
1702
    r_size = tcg_const_i32(size);
1703
    r_rd = tcg_const_i32(rd);
1704
    tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1705
    tcg_temp_free(r_rd);
1706
    tcg_temp_free(r_size);
1707
    tcg_temp_free(r_asi);
1708
}
1709

    
1710
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1711
{
1712
    TCGv r_asi, r_size, r_sign;
1713

    
1714
    r_asi = gen_get_asi(insn, addr);
1715
    r_size = tcg_const_i32(4);
1716
    r_sign = tcg_const_i32(0);
1717
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1718
    tcg_temp_free(r_sign);
1719
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1720
    tcg_temp_free(r_size);
1721
    tcg_temp_free(r_asi);
1722
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1723
}
1724

    
1725
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1726
{
1727
    TCGv r_asi, r_rd;
1728

    
1729
    r_asi = gen_get_asi(insn, addr);
1730
    r_rd = tcg_const_i32(rd);
1731
    tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd);
1732
    tcg_temp_free(r_rd);
1733
    tcg_temp_free(r_asi);
1734
}
1735

    
1736
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1737
{
1738
    TCGv r_temp, r_asi, r_size;
1739

    
1740
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1741
    gen_movl_reg_TN(rd + 1, r_temp);
1742
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1743
                       r_temp);
1744
    tcg_temp_free(r_temp);
1745
    r_asi = gen_get_asi(insn, addr);
1746
    r_size = tcg_const_i32(8);
1747
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1748
    tcg_temp_free(r_size);
1749
    tcg_temp_free(r_asi);
1750
}
1751

    
1752
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1753
                               int rd)
1754
{
1755
    TCGv r_val1, r_asi;
1756

    
1757
    r_val1 = tcg_temp_new(TCG_TYPE_TL);
1758
    gen_movl_reg_TN(rd, r_val1);
1759
    r_asi = gen_get_asi(insn, addr);
1760
    tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1761
    tcg_temp_free(r_asi);
1762
    tcg_temp_free(r_val1);
1763
}
1764

    
1765
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1766
                                int rd)
1767
{
1768
    TCGv r_asi;
1769

    
1770
    gen_movl_reg_TN(rd, cpu_tmp64);
1771
    r_asi = gen_get_asi(insn, addr);
1772
    tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1773
    tcg_temp_free(r_asi);
1774
}
1775

    
1776
#elif !defined(CONFIG_USER_ONLY)
1777

    
1778
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1779
                              int sign)
1780
{
1781
    TCGv r_asi, r_size, r_sign;
1782

    
1783
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1784
    r_size = tcg_const_i32(size);
1785
    r_sign = tcg_const_i32(sign);
1786
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1787
    tcg_temp_free(r_sign);
1788
    tcg_temp_free(r_size);
1789
    tcg_temp_free(r_asi);
1790
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1791
}
1792

    
1793
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1794
{
1795
    TCGv r_asi, r_size;
1796

    
1797
    tcg_gen_extu_tl_i64(cpu_tmp64, src);
1798
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1799
    r_size = tcg_const_i32(size);
1800
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1801
    tcg_temp_free(r_size);
1802
    tcg_temp_free(r_asi);
1803
}
1804

    
1805
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1806
{
1807
    TCGv r_asi, r_size, r_sign;
1808

    
1809
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1810
    r_size = tcg_const_i32(4);
1811
    r_sign = tcg_const_i32(0);
1812
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1813
    tcg_temp_free(r_sign);
1814
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1815
    tcg_temp_free(r_size);
1816
    tcg_temp_free(r_asi);
1817
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1818
}
1819

    
1820
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1821
{
1822
    TCGv r_asi, r_size, r_sign;
1823

    
1824
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1825
    r_size = tcg_const_i32(8);
1826
    r_sign = tcg_const_i32(0);
1827
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1828
    tcg_temp_free(r_sign);
1829
    tcg_temp_free(r_size);
1830
    tcg_temp_free(r_asi);
1831
    tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1832
    gen_movl_TN_reg(rd + 1, cpu_tmp0);
1833
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1834
    tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1835
    gen_movl_TN_reg(rd, hi);
1836
}
1837

    
1838
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1839
{
1840
    TCGv r_temp, r_asi, r_size;
1841

    
1842
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1843
    gen_movl_reg_TN(rd + 1, r_temp);
1844
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1845
    tcg_temp_free(r_temp);
1846
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1847
    r_size = tcg_const_i32(8);
1848
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1849
    tcg_temp_free(r_size);
1850
    tcg_temp_free(r_asi);
1851
}
1852
#endif
1853

    
1854
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1855
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1856
{
1857
    TCGv r_val, r_asi, r_size;
1858

    
1859
    gen_ld_asi(dst, addr, insn, 1, 0);
1860

    
1861
    r_val = tcg_const_i64(0xffULL);
1862
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1863
    r_size = tcg_const_i32(1);
1864
    tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1865
    tcg_temp_free(r_size);
1866
    tcg_temp_free(r_asi);
1867
    tcg_temp_free(r_val);
1868
}
1869
#endif
1870

    
1871
static inline TCGv get_src1(unsigned int insn, TCGv def)
1872
{
1873
    TCGv r_rs1 = def;
1874
    unsigned int rs1;
1875

    
1876
    rs1 = GET_FIELD(insn, 13, 17);
1877
    if (rs1 == 0)
1878
        r_rs1 = tcg_const_tl(0); // XXX how to free?
1879
    else if (rs1 < 8)
1880
        r_rs1 = cpu_gregs[rs1];
1881
    else
1882
        tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1883
    return r_rs1;
1884
}
1885

    
1886
static inline TCGv get_src2(unsigned int insn, TCGv def)
1887
{
1888
    TCGv r_rs2 = def;
1889
    unsigned int rs2;
1890

    
1891
    if (IS_IMM) { /* immediate */
1892
        rs2 = GET_FIELDs(insn, 19, 31);
1893
        r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1894
    } else { /* register */
1895
        rs2 = GET_FIELD(insn, 27, 31);
1896
        if (rs2 == 0)
1897
            r_rs2 = tcg_const_tl(0); // XXX how to free?
1898
        else if (rs2 < 8)
1899
            r_rs2 = cpu_gregs[rs2];
1900
        else
1901
            tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1902
    }
1903
    return r_rs2;
1904
}
1905

    
1906
#define CHECK_IU_FEATURE(dc, FEATURE)                      \
1907
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1908
        goto illegal_insn;
1909
#define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1910
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1911
        goto nfpu_insn;
1912

    
1913
/* before an instruction, dc->pc must be static */
1914
static void disas_sparc_insn(DisasContext * dc)
1915
{
1916
    unsigned int insn, opc, rs1, rs2, rd;
1917

    
1918
    if (unlikely(loglevel & CPU_LOG_TB_OP))
1919
        tcg_gen_debug_insn_start(dc->pc);
1920
    insn = ldl_code(dc->pc);
1921
    opc = GET_FIELD(insn, 0, 1);
1922

    
1923
    rd = GET_FIELD(insn, 2, 6);
1924

    
1925
    cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1926
    cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1927

    
1928
    switch (opc) {
1929
    case 0:                     /* branches/sethi */
1930
        {
1931
            unsigned int xop = GET_FIELD(insn, 7, 9);
1932
            int32_t target;
1933
            switch (xop) {
1934
#ifdef TARGET_SPARC64
1935
            case 0x1:           /* V9 BPcc */
1936
                {
1937
                    int cc;
1938

    
1939
                    target = GET_FIELD_SP(insn, 0, 18);
1940
                    target = sign_extend(target, 18);
1941
                    target <<= 2;
1942
                    cc = GET_FIELD_SP(insn, 20, 21);
1943
                    if (cc == 0)
1944
                        do_branch(dc, target, insn, 0, cpu_cond);
1945
                    else if (cc == 2)
1946
                        do_branch(dc, target, insn, 1, cpu_cond);
1947
                    else
1948
                        goto illegal_insn;
1949
                    goto jmp_insn;
1950
                }
1951
            case 0x3:           /* V9 BPr */
1952
                {
1953
                    target = GET_FIELD_SP(insn, 0, 13) |
1954
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1955
                    target = sign_extend(target, 16);
1956
                    target <<= 2;
1957
                    cpu_src1 = get_src1(insn, cpu_src1);
1958
                    do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1959
                    goto jmp_insn;
1960
                }
1961
            case 0x5:           /* V9 FBPcc */
1962
                {
1963
                    int cc = GET_FIELD_SP(insn, 20, 21);
1964
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1965
                        goto jmp_insn;
1966
                    target = GET_FIELD_SP(insn, 0, 18);
1967
                    target = sign_extend(target, 19);
1968
                    target <<= 2;
1969
                    do_fbranch(dc, target, insn, cc, cpu_cond);
1970
                    goto jmp_insn;
1971
                }
1972
#else
1973
            case 0x7:           /* CBN+x */
1974
                {
1975
                    goto ncp_insn;
1976
                }
1977
#endif
1978
            case 0x2:           /* BN+x */
1979
                {
1980
                    target = GET_FIELD(insn, 10, 31);
1981
                    target = sign_extend(target, 22);
1982
                    target <<= 2;
1983
                    do_branch(dc, target, insn, 0, cpu_cond);
1984
                    goto jmp_insn;
1985
                }
1986
            case 0x6:           /* FBN+x */
1987
                {
1988
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1989
                        goto jmp_insn;
1990
                    target = GET_FIELD(insn, 10, 31);
1991
                    target = sign_extend(target, 22);
1992
                    target <<= 2;
1993
                    do_fbranch(dc, target, insn, 0, cpu_cond);
1994
                    goto jmp_insn;
1995
                }
1996
            case 0x4:           /* SETHI */
1997
                if (rd) { // nop
1998
                    uint32_t value = GET_FIELD(insn, 10, 31);
1999
                    TCGv r_const;
2000

    
2001
                    r_const = tcg_const_tl(value << 10);
2002
                    gen_movl_TN_reg(rd, r_const);
2003
                    tcg_temp_free(r_const);
2004
                }
2005
                break;
2006
            case 0x0:           /* UNIMPL */
2007
            default:
2008
                goto illegal_insn;
2009
            }
2010
            break;
2011
        }
2012
        break;
2013
    case 1:
2014
        /*CALL*/ {
2015
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
2016
            TCGv r_const;
2017

    
2018
            r_const = tcg_const_tl(dc->pc);
2019
            gen_movl_TN_reg(15, r_const);
2020
            tcg_temp_free(r_const);
2021
            target += dc->pc;
2022
            gen_mov_pc_npc(dc, cpu_cond);
2023
            dc->npc = target;
2024
        }
2025
        goto jmp_insn;
2026
    case 2:                     /* FPU & Logical Operations */
2027
        {
2028
            unsigned int xop = GET_FIELD(insn, 7, 12);
2029
            if (xop == 0x3a) {  /* generate trap */
2030
                int cond;
2031

    
2032
                cpu_src1 = get_src1(insn, cpu_src1);
2033
                if (IS_IMM) {
2034
                    rs2 = GET_FIELD(insn, 25, 31);
2035
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2036
                } else {
2037
                    rs2 = GET_FIELD(insn, 27, 31);
2038
                    if (rs2 != 0) {
2039
                        gen_movl_reg_TN(rs2, cpu_src2);
2040
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2041
                    } else
2042
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
2043
                }
2044
                cond = GET_FIELD(insn, 3, 6);
2045
                if (cond == 0x8) {
2046
                    save_state(dc, cpu_cond);
2047
                    tcg_gen_helper_0_1(helper_trap, cpu_dst);
2048
                } else if (cond != 0) {
2049
                    TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2050
#ifdef TARGET_SPARC64
2051
                    /* V9 icc/xcc */
2052
                    int cc = GET_FIELD_SP(insn, 11, 12);
2053

    
2054
                    save_state(dc, cpu_cond);
2055
                    if (cc == 0)
2056
                        gen_cond(r_cond, 0, cond);
2057
                    else if (cc == 2)
2058
                        gen_cond(r_cond, 1, cond);
2059
                    else
2060
                        goto illegal_insn;
2061
#else
2062
                    save_state(dc, cpu_cond);
2063
                    gen_cond(r_cond, 0, cond);
2064
#endif
2065
                    tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2066
                    tcg_temp_free(r_cond);
2067
                }
2068
                gen_op_next_insn();
2069
                tcg_gen_exit_tb(0);
2070
                dc->is_br = 1;
2071
                goto jmp_insn;
2072
            } else if (xop == 0x28) {
2073
                rs1 = GET_FIELD(insn, 13, 17);
2074
                switch(rs1) {
2075
                case 0: /* rdy */
2076
#ifndef TARGET_SPARC64
2077
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
2078
                                       manual, rdy on the microSPARC
2079
                                       II */
2080
                case 0x0f:          /* stbar in the SPARCv8 manual,
2081
                                       rdy on the microSPARC II */
2082
                case 0x10 ... 0x1f: /* implementation-dependent in the
2083
                                       SPARCv8 manual, rdy on the
2084
                                       microSPARC II */
2085
#endif
2086
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2087
                                  offsetof(CPUSPARCState, y));
2088
                    gen_movl_TN_reg(rd, cpu_tmp0);
2089
                    break;
2090
#ifdef TARGET_SPARC64
2091
                case 0x2: /* V9 rdccr */
2092
                    tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2093
                    gen_movl_TN_reg(rd, cpu_dst);
2094
                    break;
2095
                case 0x3: /* V9 rdasi */
2096
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2097
                                   offsetof(CPUSPARCState, asi));
2098
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2099
                    gen_movl_TN_reg(rd, cpu_dst);
2100
                    break;
2101
                case 0x4: /* V9 rdtick */
2102
                    {
2103
                        TCGv r_tickptr;
2104

    
2105
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2106
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2107
                                       offsetof(CPUState, tick));
2108
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2109
                                           r_tickptr);
2110
                        tcg_temp_free(r_tickptr);
2111
                        gen_movl_TN_reg(rd, cpu_dst);
2112
                    }
2113
                    break;
2114
                case 0x5: /* V9 rdpc */
2115
                    {
2116
                        TCGv r_const;
2117

    
2118
                        r_const = tcg_const_tl(dc->pc);
2119
                        gen_movl_TN_reg(rd, r_const);
2120
                        tcg_temp_free(r_const);
2121
                    }
2122
                    break;
2123
                case 0x6: /* V9 rdfprs */
2124
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2125
                                   offsetof(CPUSPARCState, fprs));
2126
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2127
                    gen_movl_TN_reg(rd, cpu_dst);
2128
                    break;
2129
                case 0xf: /* V9 membar */
2130
                    break; /* no effect */
2131
                case 0x13: /* Graphics Status */
2132
                    if (gen_trap_ifnofpu(dc, cpu_cond))
2133
                        goto jmp_insn;
2134
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2135
                                  offsetof(CPUSPARCState, gsr));
2136
                    gen_movl_TN_reg(rd, cpu_tmp0);
2137
                    break;
2138
                case 0x17: /* Tick compare */
2139
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2140
                                  offsetof(CPUSPARCState, tick_cmpr));
2141
                    gen_movl_TN_reg(rd, cpu_tmp0);
2142
                    break;
2143
                case 0x18: /* System tick */
2144
                    {
2145
                        TCGv r_tickptr;
2146

    
2147
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2148
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2149
                                       offsetof(CPUState, stick));
2150
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2151
                                           r_tickptr);
2152
                        tcg_temp_free(r_tickptr);
2153
                        gen_movl_TN_reg(rd, cpu_dst);
2154
                    }
2155
                    break;
2156
                case 0x19: /* System tick compare */
2157
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2158
                                  offsetof(CPUSPARCState, stick_cmpr));
2159
                    gen_movl_TN_reg(rd, cpu_tmp0);
2160
                    break;
2161
                case 0x10: /* Performance Control */
2162
                case 0x11: /* Performance Instrumentation Counter */
2163
                case 0x12: /* Dispatch Control */
2164
                case 0x14: /* Softint set, WO */
2165
                case 0x15: /* Softint clear, WO */
2166
                case 0x16: /* Softint write */
2167
#endif
2168
                default:
2169
                    goto illegal_insn;
2170
                }
2171
#if !defined(CONFIG_USER_ONLY)
2172
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2173
#ifndef TARGET_SPARC64
2174
                if (!supervisor(dc))
2175
                    goto priv_insn;
2176
                tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2177
#else
2178
                if (!hypervisor(dc))
2179
                    goto priv_insn;
2180
                rs1 = GET_FIELD(insn, 13, 17);
2181
                switch (rs1) {
2182
                case 0: // hpstate
2183
                    // gen_op_rdhpstate();
2184
                    break;
2185
                case 1: // htstate
2186
                    // gen_op_rdhtstate();
2187
                    break;
2188
                case 3: // hintp
2189
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2190
                                   offsetof(CPUSPARCState, hintp));
2191
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2192
                    break;
2193
                case 5: // htba
2194
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2195
                                   offsetof(CPUSPARCState, htba));
2196
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2197
                    break;
2198
                case 6: // hver
2199
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2200
                                   offsetof(CPUSPARCState, hver));
2201
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2202
                    break;
2203
                case 31: // hstick_cmpr
2204
                    tcg_gen_ld_tl(cpu_dst, cpu_env,
2205
                                  offsetof(CPUSPARCState, hstick_cmpr));
2206
                    break;
2207
                default:
2208
                    goto illegal_insn;
2209
                }
2210
#endif
2211
                gen_movl_TN_reg(rd, cpu_dst);
2212
                break;
2213
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2214
                if (!supervisor(dc))
2215
                    goto priv_insn;
2216
#ifdef TARGET_SPARC64
2217
                rs1 = GET_FIELD(insn, 13, 17);
2218
                switch (rs1) {
2219
                case 0: // tpc
2220
                    {
2221
                        TCGv r_tsptr;
2222

    
2223
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2224
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2225
                                       offsetof(CPUState, tsptr));
2226
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2227
                                      offsetof(trap_state, tpc));
2228
                        tcg_temp_free(r_tsptr);
2229
                    }
2230
                    break;
2231
                case 1: // tnpc
2232
                    {
2233
                        TCGv r_tsptr;
2234

    
2235
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2236
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2237
                                       offsetof(CPUState, tsptr));
2238
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2239
                                      offsetof(trap_state, tnpc));
2240
                        tcg_temp_free(r_tsptr);
2241
                    }
2242
                    break;
2243
                case 2: // tstate
2244
                    {
2245
                        TCGv r_tsptr;
2246

    
2247
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2248
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2249
                                       offsetof(CPUState, tsptr));
2250
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2251
                                      offsetof(trap_state, tstate));
2252
                        tcg_temp_free(r_tsptr);
2253
                    }
2254
                    break;
2255
                case 3: // tt
2256
                    {
2257
                        TCGv r_tsptr;
2258

    
2259
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2260
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2261
                                       offsetof(CPUState, tsptr));
2262
                        tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2263
                                       offsetof(trap_state, tt));
2264
                        tcg_temp_free(r_tsptr);
2265
                    }
2266
                    break;
2267
                case 4: // tick
2268
                    {
2269
                        TCGv r_tickptr;
2270

    
2271
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2272
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2273
                                       offsetof(CPUState, tick));
2274
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2275
                                           r_tickptr);
2276
                        gen_movl_TN_reg(rd, cpu_tmp0);
2277
                        tcg_temp_free(r_tickptr);
2278
                    }
2279
                    break;
2280
                case 5: // tba
2281
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2282
                                  offsetof(CPUSPARCState, tbr));
2283
                    break;
2284
                case 6: // pstate
2285
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2286
                                   offsetof(CPUSPARCState, pstate));
2287
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2288
                    break;
2289
                case 7: // tl
2290
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2291
                                   offsetof(CPUSPARCState, tl));
2292
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2293
                    break;
2294
                case 8: // pil
2295
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2296
                                   offsetof(CPUSPARCState, psrpil));
2297
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2298
                    break;
2299
                case 9: // cwp
2300
                    tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2301
                    break;
2302
                case 10: // cansave
2303
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2304
                                   offsetof(CPUSPARCState, cansave));
2305
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2306
                    break;
2307
                case 11: // canrestore
2308
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2309
                                   offsetof(CPUSPARCState, canrestore));
2310
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2311
                    break;
2312
                case 12: // cleanwin
2313
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2314
                                   offsetof(CPUSPARCState, cleanwin));
2315
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2316
                    break;
2317
                case 13: // otherwin
2318
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2319
                                   offsetof(CPUSPARCState, otherwin));
2320
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2321
                    break;
2322
                case 14: // wstate
2323
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2324
                                   offsetof(CPUSPARCState, wstate));
2325
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2326
                    break;
2327
                case 16: // UA2005 gl
2328
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2329
                                   offsetof(CPUSPARCState, gl));
2330
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2331
                    break;
2332
                case 26: // UA2005 strand status
2333
                    if (!hypervisor(dc))
2334
                        goto priv_insn;
2335
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2336
                                   offsetof(CPUSPARCState, ssr));
2337
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2338
                    break;
2339
                case 31: // ver
2340
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2341
                                  offsetof(CPUSPARCState, version));
2342
                    break;
2343
                case 15: // fq
2344
                default:
2345
                    goto illegal_insn;
2346
                }
2347
#else
2348
                tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2349
                               offsetof(CPUSPARCState, wim));
2350
                tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2351
#endif
2352
                gen_movl_TN_reg(rd, cpu_tmp0);
2353
                break;
2354
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2355
#ifdef TARGET_SPARC64
2356
                save_state(dc, cpu_cond);
2357
                tcg_gen_helper_0_0(helper_flushw);
2358
#else
2359
                if (!supervisor(dc))
2360
                    goto priv_insn;
2361
                tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2362
                gen_movl_TN_reg(rd, cpu_tmp0);
2363
#endif
2364
                break;
2365
#endif
2366
            } else if (xop == 0x34) {   /* FPU Operations */
2367
                if (gen_trap_ifnofpu(dc, cpu_cond))
2368
                    goto jmp_insn;
2369
                gen_op_clear_ieee_excp_and_FTT();
2370
                rs1 = GET_FIELD(insn, 13, 17);
2371
                rs2 = GET_FIELD(insn, 27, 31);
2372
                xop = GET_FIELD(insn, 18, 26);
2373
                switch (xop) {
2374
                    case 0x1: /* fmovs */
2375
                        gen_op_load_fpr_FT0(rs2);
2376
                        gen_op_store_FT0_fpr(rd);
2377
                        break;
2378
                    case 0x5: /* fnegs */
2379
                        gen_op_load_fpr_FT1(rs2);
2380
                        tcg_gen_helper_0_0(helper_fnegs);
2381
                        gen_op_store_FT0_fpr(rd);
2382
                        break;
2383
                    case 0x9: /* fabss */
2384
                        gen_op_load_fpr_FT1(rs2);
2385
                        tcg_gen_helper_0_0(helper_fabss);
2386
                        gen_op_store_FT0_fpr(rd);
2387
                        break;
2388
                    case 0x29: /* fsqrts */
2389
                        CHECK_FPU_FEATURE(dc, FSQRT);
2390
                        gen_op_load_fpr_FT1(rs2);
2391
                        gen_clear_float_exceptions();
2392
                        tcg_gen_helper_0_0(helper_fsqrts);
2393
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2394
                        gen_op_store_FT0_fpr(rd);
2395
                        break;
2396
                    case 0x2a: /* fsqrtd */
2397
                        CHECK_FPU_FEATURE(dc, FSQRT);
2398
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2399
                        gen_clear_float_exceptions();
2400
                        tcg_gen_helper_0_0(helper_fsqrtd);
2401
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2402
                        gen_op_store_DT0_fpr(DFPREG(rd));
2403
                        break;
2404
                    case 0x2b: /* fsqrtq */
2405
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2406
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2407
                        gen_clear_float_exceptions();
2408
                        tcg_gen_helper_0_0(helper_fsqrtq);
2409
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2410
                        gen_op_store_QT0_fpr(QFPREG(rd));
2411
                        break;
2412
                    case 0x41:
2413
                        gen_op_load_fpr_FT0(rs1);
2414
                        gen_op_load_fpr_FT1(rs2);
2415
                        gen_clear_float_exceptions();
2416
                        tcg_gen_helper_0_0(helper_fadds);
2417
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2418
                        gen_op_store_FT0_fpr(rd);
2419
                        break;
2420
                    case 0x42:
2421
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2422
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2423
                        gen_clear_float_exceptions();
2424
                        tcg_gen_helper_0_0(helper_faddd);
2425
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2426
                        gen_op_store_DT0_fpr(DFPREG(rd));
2427
                        break;
2428
                    case 0x43: /* faddq */
2429
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2430
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2431
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2432
                        gen_clear_float_exceptions();
2433
                        tcg_gen_helper_0_0(helper_faddq);
2434
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2435
                        gen_op_store_QT0_fpr(QFPREG(rd));
2436
                        break;
2437
                    case 0x45:
2438
                        gen_op_load_fpr_FT0(rs1);
2439
                        gen_op_load_fpr_FT1(rs2);
2440
                        gen_clear_float_exceptions();
2441
                        tcg_gen_helper_0_0(helper_fsubs);
2442
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2443
                        gen_op_store_FT0_fpr(rd);
2444
                        break;
2445
                    case 0x46:
2446
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2447
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2448
                        gen_clear_float_exceptions();
2449
                        tcg_gen_helper_0_0(helper_fsubd);
2450
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2451
                        gen_op_store_DT0_fpr(DFPREG(rd));
2452
                        break;
2453
                    case 0x47: /* fsubq */
2454
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2455
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2456
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2457
                        gen_clear_float_exceptions();
2458
                        tcg_gen_helper_0_0(helper_fsubq);
2459
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2460
                        gen_op_store_QT0_fpr(QFPREG(rd));
2461
                        break;
2462
                    case 0x49: /* fmuls */
2463
                        CHECK_FPU_FEATURE(dc, FMUL);
2464
                        gen_op_load_fpr_FT0(rs1);
2465
                        gen_op_load_fpr_FT1(rs2);
2466
                        gen_clear_float_exceptions();
2467
                        tcg_gen_helper_0_0(helper_fmuls);
2468
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2469
                        gen_op_store_FT0_fpr(rd);
2470
                        break;
2471
                    case 0x4a: /* fmuld */
2472
                        CHECK_FPU_FEATURE(dc, FMUL);
2473
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2474
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2475
                        gen_clear_float_exceptions();
2476
                        tcg_gen_helper_0_0(helper_fmuld);
2477
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2478
                        gen_op_store_DT0_fpr(DFPREG(rd));
2479
                        break;
2480
                    case 0x4b: /* fmulq */
2481
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2482
                        CHECK_FPU_FEATURE(dc, FMUL);
2483
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2484
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2485
                        gen_clear_float_exceptions();
2486
                        tcg_gen_helper_0_0(helper_fmulq);
2487
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2488
                        gen_op_store_QT0_fpr(QFPREG(rd));
2489
                        break;
2490
                    case 0x4d:
2491
                        gen_op_load_fpr_FT0(rs1);
2492
                        gen_op_load_fpr_FT1(rs2);
2493
                        gen_clear_float_exceptions();
2494
                        tcg_gen_helper_0_0(helper_fdivs);
2495
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2496
                        gen_op_store_FT0_fpr(rd);
2497
                        break;
2498
                    case 0x4e:
2499
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2500
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2501
                        gen_clear_float_exceptions();
2502
                        tcg_gen_helper_0_0(helper_fdivd);
2503
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2504
                        gen_op_store_DT0_fpr(DFPREG(rd));
2505
                        break;
2506
                    case 0x4f: /* fdivq */
2507
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2508
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2509
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2510
                        gen_clear_float_exceptions();
2511
                        tcg_gen_helper_0_0(helper_fdivq);
2512
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2513
                        gen_op_store_QT0_fpr(QFPREG(rd));
2514
                        break;
2515
                    case 0x69:
2516
                        CHECK_FPU_FEATURE(dc, FSMULD);
2517
                        gen_op_load_fpr_FT0(rs1);
2518
                        gen_op_load_fpr_FT1(rs2);
2519
                        gen_clear_float_exceptions();
2520
                        tcg_gen_helper_0_0(helper_fsmuld);
2521
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2522
                        gen_op_store_DT0_fpr(DFPREG(rd));
2523
                        break;
2524
                    case 0x6e: /* fdmulq */
2525
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2526
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2527
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2528
                        gen_clear_float_exceptions();
2529
                        tcg_gen_helper_0_0(helper_fdmulq);
2530
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2531
                        gen_op_store_QT0_fpr(QFPREG(rd));
2532
                        break;
2533
                    case 0xc4:
2534
                        gen_op_load_fpr_FT1(rs2);
2535
                        gen_clear_float_exceptions();
2536
                        tcg_gen_helper_0_0(helper_fitos);
2537
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2538
                        gen_op_store_FT0_fpr(rd);
2539
                        break;
2540
                    case 0xc6:
2541
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2542
                        gen_clear_float_exceptions();
2543
                        tcg_gen_helper_0_0(helper_fdtos);
2544
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2545
                        gen_op_store_FT0_fpr(rd);
2546
                        break;
2547
                    case 0xc7: /* fqtos */
2548
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2549
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2550
                        gen_clear_float_exceptions();
2551
                        tcg_gen_helper_0_0(helper_fqtos);
2552
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2553
                        gen_op_store_FT0_fpr(rd);
2554
                        break;
2555
                    case 0xc8:
2556
                        gen_op_load_fpr_FT1(rs2);
2557
                        tcg_gen_helper_0_0(helper_fitod);
2558
                        gen_op_store_DT0_fpr(DFPREG(rd));
2559
                        break;
2560
                    case 0xc9:
2561
                        gen_op_load_fpr_FT1(rs2);
2562
                        tcg_gen_helper_0_0(helper_fstod);
2563
                        gen_op_store_DT0_fpr(DFPREG(rd));
2564
                        break;
2565
                    case 0xcb: /* fqtod */
2566
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2567
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2568
                        gen_clear_float_exceptions();
2569
                        tcg_gen_helper_0_0(helper_fqtod);
2570
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2571
                        gen_op_store_DT0_fpr(DFPREG(rd));
2572
                        break;
2573
                    case 0xcc: /* fitoq */
2574
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2575
                        gen_op_load_fpr_FT1(rs2);
2576
                        tcg_gen_helper_0_0(helper_fitoq);
2577
                        gen_op_store_QT0_fpr(QFPREG(rd));
2578
                        break;
2579
                    case 0xcd: /* fstoq */
2580
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2581
                        gen_op_load_fpr_FT1(rs2);
2582
                        tcg_gen_helper_0_0(helper_fstoq);
2583
                        gen_op_store_QT0_fpr(QFPREG(rd));
2584
                        break;
2585
                    case 0xce: /* fdtoq */
2586
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2587
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2588
                        tcg_gen_helper_0_0(helper_fdtoq);
2589
                        gen_op_store_QT0_fpr(QFPREG(rd));
2590
                        break;
2591
                    case 0xd1:
2592
                        gen_op_load_fpr_FT1(rs2);
2593
                        gen_clear_float_exceptions();
2594
                        tcg_gen_helper_0_0(helper_fstoi);
2595
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2596
                        gen_op_store_FT0_fpr(rd);
2597
                        break;
2598
                    case 0xd2:
2599
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2600
                        gen_clear_float_exceptions();
2601
                        tcg_gen_helper_0_0(helper_fdtoi);
2602
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2603
                        gen_op_store_FT0_fpr(rd);
2604
                        break;
2605
                    case 0xd3: /* fqtoi */
2606
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2607
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2608
                        gen_clear_float_exceptions();
2609
                        tcg_gen_helper_0_0(helper_fqtoi);
2610
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2611
                        gen_op_store_FT0_fpr(rd);
2612
                        break;
2613
#ifdef TARGET_SPARC64
2614
                    case 0x2: /* V9 fmovd */
2615
                        gen_op_load_fpr_DT0(DFPREG(rs2));
2616
                        gen_op_store_DT0_fpr(DFPREG(rd));
2617
                        break;
2618
                    case 0x3: /* V9 fmovq */
2619
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2620
                        gen_op_load_fpr_QT0(QFPREG(rs2));
2621
                        gen_op_store_QT0_fpr(QFPREG(rd));
2622
                        break;
2623
                    case 0x6: /* V9 fnegd */
2624
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2625
                        tcg_gen_helper_0_0(helper_fnegd);
2626
                        gen_op_store_DT0_fpr(DFPREG(rd));
2627
                        break;
2628
                    case 0x7: /* V9 fnegq */
2629
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2630
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2631
                        tcg_gen_helper_0_0(helper_fnegq);
2632
                        gen_op_store_QT0_fpr(QFPREG(rd));
2633
                        break;
2634
                    case 0xa: /* V9 fabsd */
2635
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2636
                        tcg_gen_helper_0_0(helper_fabsd);
2637
                        gen_op_store_DT0_fpr(DFPREG(rd));
2638
                        break;
2639
                    case 0xb: /* V9 fabsq */
2640
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2641
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2642
                        tcg_gen_helper_0_0(helper_fabsq);
2643
                        gen_op_store_QT0_fpr(QFPREG(rd));
2644
                        break;
2645
                    case 0x81: /* V9 fstox */
2646
                        gen_op_load_fpr_FT1(rs2);
2647
                        gen_clear_float_exceptions();
2648
                        tcg_gen_helper_0_0(helper_fstox);
2649
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2650
                        gen_op_store_DT0_fpr(DFPREG(rd));
2651
                        break;
2652
                    case 0x82: /* V9 fdtox */
2653
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2654
                        gen_clear_float_exceptions();
2655
                        tcg_gen_helper_0_0(helper_fdtox);
2656
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2657
                        gen_op_store_DT0_fpr(DFPREG(rd));
2658
                        break;
2659
                    case 0x83: /* V9 fqtox */
2660
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2661
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2662
                        gen_clear_float_exceptions();
2663
                        tcg_gen_helper_0_0(helper_fqtox);
2664
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2665
                        gen_op_store_DT0_fpr(DFPREG(rd));
2666
                        break;
2667
                    case 0x84: /* V9 fxtos */
2668
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2669
                        gen_clear_float_exceptions();
2670
                        tcg_gen_helper_0_0(helper_fxtos);
2671
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2672
                        gen_op_store_FT0_fpr(rd);
2673
                        break;
2674
                    case 0x88: /* V9 fxtod */
2675
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2676
                        gen_clear_float_exceptions();
2677
                        tcg_gen_helper_0_0(helper_fxtod);
2678
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2679
                        gen_op_store_DT0_fpr(DFPREG(rd));
2680
                        break;
2681
                    case 0x8c: /* V9 fxtoq */
2682
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2683
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2684
                        gen_clear_float_exceptions();
2685
                        tcg_gen_helper_0_0(helper_fxtoq);
2686
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2687
                        gen_op_store_QT0_fpr(QFPREG(rd));
2688
                        break;
2689
#endif
2690
                    default:
2691
                        goto illegal_insn;
2692
                }
2693
            } else if (xop == 0x35) {   /* FPU Operations */
2694
#ifdef TARGET_SPARC64
2695
                int cond;
2696
#endif
2697
                if (gen_trap_ifnofpu(dc, cpu_cond))
2698
                    goto jmp_insn;
2699
                gen_op_clear_ieee_excp_and_FTT();
2700
                rs1 = GET_FIELD(insn, 13, 17);
2701
                rs2 = GET_FIELD(insn, 27, 31);
2702
                xop = GET_FIELD(insn, 18, 26);
2703
#ifdef TARGET_SPARC64
2704
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2705
                    int l1;
2706

    
2707
                    l1 = gen_new_label();
2708
                    cond = GET_FIELD_SP(insn, 14, 17);
2709
                    cpu_src1 = get_src1(insn, cpu_src1);
2710
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2711
                                       0, l1);
2712
                    gen_op_load_fpr_FT0(rs2);
2713
                    gen_op_store_FT0_fpr(rd);
2714
                    gen_set_label(l1);
2715
                    break;
2716
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2717
                    int l1;
2718

    
2719
                    l1 = gen_new_label();
2720
                    cond = GET_FIELD_SP(insn, 14, 17);
2721
                    cpu_src1 = get_src1(insn, cpu_src1);
2722
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2723
                                       0, l1);
2724
                    gen_op_load_fpr_DT0(DFPREG(rs2));
2725
                    gen_op_store_DT0_fpr(DFPREG(rd));
2726
                    gen_set_label(l1);
2727
                    break;
2728
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2729
                    int l1;
2730

    
2731
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2732
                    l1 = gen_new_label();
2733
                    cond = GET_FIELD_SP(insn, 14, 17);
2734
                    cpu_src1 = get_src1(insn, cpu_src1);
2735
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2736
                                       0, l1);
2737
                    gen_op_load_fpr_QT0(QFPREG(rs2));
2738
                    gen_op_store_QT0_fpr(QFPREG(rd));
2739
                    gen_set_label(l1);
2740
                    break;
2741
                }
2742
#endif
2743
                switch (xop) {
2744
#ifdef TARGET_SPARC64
2745
#define FMOVCC(size_FDQ, fcc)                                           \
2746
                    {                                                   \
2747
                        TCGv r_cond;                                    \
2748
                        int l1;                                         \
2749
                                                                        \
2750
                        l1 = gen_new_label();                           \
2751
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2752
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2753
                        gen_fcond(r_cond, fcc, cond);                   \
2754
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2755
                                           0, l1);                      \
2756
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2757
                            (glue(size_FDQ, FPREG(rs2)));               \
2758
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2759
                            (glue(size_FDQ, FPREG(rd)));                \
2760
                        gen_set_label(l1);                              \
2761
                        tcg_temp_free(r_cond);                          \
2762
                    }
2763
                    case 0x001: /* V9 fmovscc %fcc0 */
2764
                        FMOVCC(F, 0);
2765
                        break;
2766
                    case 0x002: /* V9 fmovdcc %fcc0 */
2767
                        FMOVCC(D, 0);
2768
                        break;
2769
                    case 0x003: /* V9 fmovqcc %fcc0 */
2770
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2771
                        FMOVCC(Q, 0);
2772
                        break;
2773
                    case 0x041: /* V9 fmovscc %fcc1 */
2774
                        FMOVCC(F, 1);
2775
                        break;
2776
                    case 0x042: /* V9 fmovdcc %fcc1 */
2777
                        FMOVCC(D, 1);
2778
                        break;
2779
                    case 0x043: /* V9 fmovqcc %fcc1 */
2780
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2781
                        FMOVCC(Q, 1);
2782
                        break;
2783
                    case 0x081: /* V9 fmovscc %fcc2 */
2784
                        FMOVCC(F, 2);
2785
                        break;
2786
                    case 0x082: /* V9 fmovdcc %fcc2 */
2787
                        FMOVCC(D, 2);
2788
                        break;
2789
                    case 0x083: /* V9 fmovqcc %fcc2 */
2790
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2791
                        FMOVCC(Q, 2);
2792
                        break;
2793
                    case 0x0c1: /* V9 fmovscc %fcc3 */
2794
                        FMOVCC(F, 3);
2795
                        break;
2796
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
2797
                        FMOVCC(D, 3);
2798
                        break;
2799
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
2800
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2801
                        FMOVCC(Q, 3);
2802
                        break;
2803
#undef FMOVCC
2804
#define FMOVCC(size_FDQ, icc)                                           \
2805
                    {                                                   \
2806
                        TCGv r_cond;                                    \
2807
                        int l1;                                         \
2808
                                                                        \
2809
                        l1 = gen_new_label();                           \
2810
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2811
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2812
                        gen_cond(r_cond, icc, cond);                    \
2813
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2814
                                           0, l1);                      \
2815
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2816
                            (glue(size_FDQ, FPREG(rs2)));               \
2817
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2818
                            (glue(size_FDQ, FPREG(rd)));                \
2819
                        gen_set_label(l1);                              \
2820
                        tcg_temp_free(r_cond);                          \
2821
                    }
2822

    
2823
                    case 0x101: /* V9 fmovscc %icc */
2824
                        FMOVCC(F, 0);
2825
                        break;
2826
                    case 0x102: /* V9 fmovdcc %icc */
2827
                        FMOVCC(D, 0);
2828
                    case 0x103: /* V9 fmovqcc %icc */
2829
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2830
                        FMOVCC(Q, 0);
2831
                        break;
2832
                    case 0x181: /* V9 fmovscc %xcc */
2833
                        FMOVCC(F, 1);
2834
                        break;
2835
                    case 0x182: /* V9 fmovdcc %xcc */
2836
                        FMOVCC(D, 1);
2837
                        break;
2838
                    case 0x183: /* V9 fmovqcc %xcc */
2839
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2840
                        FMOVCC(Q, 1);
2841
                        break;
2842
#undef FMOVCC
2843
#endif
2844
                    case 0x51: /* fcmps, V9 %fcc */
2845
                        gen_op_load_fpr_FT0(rs1);
2846
                        gen_op_load_fpr_FT1(rs2);
2847
                        gen_op_fcmps(rd & 3);
2848
                        break;
2849
                    case 0x52: /* fcmpd, V9 %fcc */
2850
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2851
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2852
                        gen_op_fcmpd(rd & 3);
2853
                        break;
2854
                    case 0x53: /* fcmpq, V9 %fcc */
2855
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2856
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2857
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2858
                        gen_op_fcmpq(rd & 3);
2859
                        break;
2860
                    case 0x55: /* fcmpes, V9 %fcc */
2861
                        gen_op_load_fpr_FT0(rs1);
2862
                        gen_op_load_fpr_FT1(rs2);
2863
                        gen_op_fcmpes(rd & 3);
2864
                        break;
2865
                    case 0x56: /* fcmped, V9 %fcc */
2866
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2867
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2868
                        gen_op_fcmped(rd & 3);
2869
                        break;
2870
                    case 0x57: /* fcmpeq, V9 %fcc */
2871
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2872
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2873
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2874
                        gen_op_fcmpeq(rd & 3);
2875
                        break;
2876
                    default:
2877
                        goto illegal_insn;
2878
                }
2879
            } else if (xop == 0x2) {
2880
                // clr/mov shortcut
2881

    
2882
                rs1 = GET_FIELD(insn, 13, 17);
2883
                if (rs1 == 0) {
2884
                    // or %g0, x, y -> mov T0, x; mov y, T0
2885
                    if (IS_IMM) {       /* immediate */
2886
                        TCGv r_const;
2887

    
2888
                        rs2 = GET_FIELDs(insn, 19, 31);
2889
                        r_const = tcg_const_tl((int)rs2);
2890
                        gen_movl_TN_reg(rd, r_const);
2891
                        tcg_temp_free(r_const);
2892
                    } else {            /* register */
2893
                        rs2 = GET_FIELD(insn, 27, 31);
2894
                        gen_movl_reg_TN(rs2, cpu_dst);
2895
                        gen_movl_TN_reg(rd, cpu_dst);
2896
                    }
2897
                } else {
2898
                    cpu_src1 = get_src1(insn, cpu_src1);
2899
                    if (IS_IMM) {       /* immediate */
2900
                        rs2 = GET_FIELDs(insn, 19, 31);
2901
                        tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2902
                        gen_movl_TN_reg(rd, cpu_dst);
2903
                    } else {            /* register */
2904
                        // or x, %g0, y -> mov T1, x; mov y, T1
2905
                        rs2 = GET_FIELD(insn, 27, 31);
2906
                        if (rs2 != 0) {
2907
                            gen_movl_reg_TN(rs2, cpu_src2);
2908
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2909
                            gen_movl_TN_reg(rd, cpu_dst);
2910
                        } else
2911
                            gen_movl_TN_reg(rd, cpu_src1);
2912
                    }
2913
                }
2914
#ifdef TARGET_SPARC64
2915
            } else if (xop == 0x25) { /* sll, V9 sllx */
2916
                cpu_src1 = get_src1(insn, cpu_src1);
2917
                if (IS_IMM) {   /* immediate */
2918
                    rs2 = GET_FIELDs(insn, 20, 31);
2919
                    if (insn & (1 << 12)) {
2920
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2921
                    } else {
2922
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2923
                        tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2924
                    }
2925
                } else {                /* register */
2926
                    rs2 = GET_FIELD(insn, 27, 31);
2927
                    gen_movl_reg_TN(rs2, cpu_src2);
2928
                    if (insn & (1 << 12)) {
2929
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2930
                        tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2931
                    } else {
2932
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2933
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2934
                        tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2935
                    }
2936
                }
2937
                gen_movl_TN_reg(rd, cpu_dst);
2938
            } else if (xop == 0x26) { /* srl, V9 srlx */
2939
                cpu_src1 = get_src1(insn, cpu_src1);
2940
                if (IS_IMM) {   /* immediate */
2941
                    rs2 = GET_FIELDs(insn, 20, 31);
2942
                    if (insn & (1 << 12)) {
2943
                        tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2944
                    } else {
2945
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2946
                        tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2947
                    }
2948
                } else {                /* register */
2949
                    rs2 = GET_FIELD(insn, 27, 31);
2950
                    gen_movl_reg_TN(rs2, cpu_src2);
2951
                    if (insn & (1 << 12)) {
2952
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2953
                        tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2954
                    } else {
2955
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2956
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2957
                        tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2958
                    }
2959
                }
2960
                gen_movl_TN_reg(rd, cpu_dst);
2961
            } else if (xop == 0x27) { /* sra, V9 srax */
2962
                cpu_src1 = get_src1(insn, cpu_src1);
2963
                if (IS_IMM) {   /* immediate */
2964
                    rs2 = GET_FIELDs(insn, 20, 31);
2965
                    if (insn & (1 << 12)) {
2966
                        tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2967
                    } else {
2968
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2969
                        tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2970
                        tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2971
                    }
2972
                } else {                /* register */
2973
                    rs2 = GET_FIELD(insn, 27, 31);
2974
                    gen_movl_reg_TN(rs2, cpu_src2);
2975
                    if (insn & (1 << 12)) {
2976
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2977
                        tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2978
                    } else {
2979
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2980
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2981
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2982
                    }
2983
                }
2984
                gen_movl_TN_reg(rd, cpu_dst);
2985
#endif
2986
            } else if (xop < 0x36) {
2987
                cpu_src1 = get_src1(insn, cpu_src1);
2988
                cpu_src2 = get_src2(insn, cpu_src2);
2989
                if (xop < 0x20) {
2990
                    switch (xop & ~0x10) {
2991
                    case 0x0:
2992
                        if (xop & 0x10)
2993
                            gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2994
                        else
2995
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2996
                        break;
2997
                    case 0x1:
2998
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2999
                        if (xop & 0x10)
3000
                            gen_op_logic_cc(cpu_dst);
3001
                        break;
3002
                    case 0x2:
3003
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3004
                        if (xop & 0x10)
3005
                            gen_op_logic_cc(cpu_dst);
3006
                        break;
3007
                    case 0x3:
3008
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3009
                        if (xop & 0x10)
3010
                            gen_op_logic_cc(cpu_dst);
3011
                        break;
3012
                    case 0x4:
3013
                        if (xop & 0x10)
3014
                            gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3015
                        else
3016
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3017
                        break;
3018
                    case 0x5:
3019
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3020
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3021
                        if (xop & 0x10)
3022
                            gen_op_logic_cc(cpu_dst);
3023
                        break;
3024
                    case 0x6:
3025
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3026
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3027
                        if (xop & 0x10)
3028
                            gen_op_logic_cc(cpu_dst);
3029
                        break;
3030
                    case 0x7:
3031
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3032
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3033
                        if (xop & 0x10)
3034
                            gen_op_logic_cc(cpu_dst);
3035
                        break;
3036
                    case 0x8:
3037
                        if (xop & 0x10)
3038
                            gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3039
                        else {
3040
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3041
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3042
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3043
                        }
3044
                        break;
3045
#ifdef TARGET_SPARC64
3046
                    case 0x9: /* V9 mulx */
3047
                        tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3048
                        break;
3049
#endif
3050
                    case 0xa:
3051
                        CHECK_IU_FEATURE(dc, MUL);
3052
                        gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3053
                        if (xop & 0x10)
3054
                            gen_op_logic_cc(cpu_dst);
3055
                        break;
3056
                    case 0xb:
3057
                        CHECK_IU_FEATURE(dc, MUL);
3058
                        gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3059
                        if (xop & 0x10)
3060
                            gen_op_logic_cc(cpu_dst);
3061
                        break;
3062
                    case 0xc:
3063
                        if (xop & 0x10)
3064
                            gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3065
                        else {
3066
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3067
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3068
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3069
                        }
3070
                        break;
3071
#ifdef TARGET_SPARC64
3072
                    case 0xd: /* V9 udivx */
3073
                        tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3074
                        tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3075
                        gen_trap_ifdivzero_tl(cpu_cc_src2);
3076
                        tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3077
                        break;
3078
#endif
3079
                    case 0xe:
3080
                        CHECK_IU_FEATURE(dc, DIV);
3081
                        tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3082
                                           cpu_src2);
3083
                        if (xop & 0x10)
3084
                            gen_op_div_cc(cpu_dst);
3085
                        break;
3086
                    case 0xf:
3087
                        CHECK_IU_FEATURE(dc, DIV);
3088
                        tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3089
                                           cpu_src2);
3090
                        if (xop & 0x10)
3091
                            gen_op_div_cc(cpu_dst);
3092
                        break;
3093
                    default:
3094
                        goto illegal_insn;
3095
                    }
3096
                    gen_movl_TN_reg(rd, cpu_dst);
3097
                } else {
3098
                    switch (xop) {
3099
                    case 0x20: /* taddcc */
3100
                        gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3101
                        gen_movl_TN_reg(rd, cpu_dst);
3102
                        break;
3103
                    case 0x21: /* tsubcc */
3104
                        gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3105
                        gen_movl_TN_reg(rd, cpu_dst);
3106
                        break;
3107
                    case 0x22: /* taddcctv */
3108
                        save_state(dc, cpu_cond);
3109
                        gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3110
                        gen_movl_TN_reg(rd, cpu_dst);
3111
                        break;
3112
                    case 0x23: /* tsubcctv */
3113
                        save_state(dc, cpu_cond);
3114
                        gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3115
                        gen_movl_TN_reg(rd, cpu_dst);
3116
                        break;
3117
                    case 0x24: /* mulscc */
3118
                        gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3119
                        gen_movl_TN_reg(rd, cpu_dst);
3120
                        break;
3121
#ifndef TARGET_SPARC64
3122
                    case 0x25:  /* sll */
3123
                        if (IS_IMM) { /* immediate */
3124
                            rs2 = GET_FIELDs(insn, 20, 31);
3125
                            tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3126
                        } else { /* register */
3127
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3128
                            tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3129
                        }
3130
                        gen_movl_TN_reg(rd, cpu_dst);
3131
                        break;
3132
                    case 0x26:  /* srl */
3133
                        if (IS_IMM) { /* immediate */
3134
                            rs2 = GET_FIELDs(insn, 20, 31);
3135
                            tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3136
                        } else { /* register */
3137
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3138
                            tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3139
                        }
3140
                        gen_movl_TN_reg(rd, cpu_dst);
3141
                        break;
3142
                    case 0x27:  /* sra */
3143
                        if (IS_IMM) { /* immediate */
3144
                            rs2 = GET_FIELDs(insn, 20, 31);
3145
                            tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3146
                        } else { /* register */
3147
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3148
                            tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3149
                        }
3150
                        gen_movl_TN_reg(rd, cpu_dst);
3151
                        break;
3152
#endif
3153
                    case 0x30:
3154
                        {
3155
                            switch(rd) {
3156
                            case 0: /* wry */
3157
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3158
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3159
                                              offsetof(CPUSPARCState, y));
3160
                                break;
3161
#ifndef TARGET_SPARC64
3162
                            case 0x01 ... 0x0f: /* undefined in the
3163
                                                   SPARCv8 manual, nop
3164
                                                   on the microSPARC
3165
                                                   II */
3166
                            case 0x10 ... 0x1f: /* implementation-dependent
3167
                                                   in the SPARCv8
3168
                                                   manual, nop on the
3169
                                                   microSPARC II */
3170
                                break;
3171
#else
3172
                            case 0x2: /* V9 wrccr */
3173
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3174
                                tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3175
                                break;
3176
                            case 0x3: /* V9 wrasi */
3177
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3178
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3179
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3180
                                               offsetof(CPUSPARCState, asi));
3181
                                break;
3182
                            case 0x6: /* V9 wrfprs */
3183
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3184
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3185
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3186
                                               offsetof(CPUSPARCState, fprs));
3187
                                save_state(dc, cpu_cond);
3188
                                gen_op_next_insn();
3189
                                tcg_gen_exit_tb(0);
3190
                                dc->is_br = 1;
3191
                                break;
3192
                            case 0xf: /* V9 sir, nop if user */
3193
#if !defined(CONFIG_USER_ONLY)
3194
                                if (supervisor(dc))
3195
                                    ; // XXX
3196
#endif
3197
                                break;
3198
                            case 0x13: /* Graphics Status */
3199
                                if (gen_trap_ifnofpu(dc, cpu_cond))
3200
                                    goto jmp_insn;
3201
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3202
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3203
                                              offsetof(CPUSPARCState, gsr));
3204
                                break;
3205
                            case 0x17: /* Tick compare */
3206
#if !defined(CONFIG_USER_ONLY)
3207
                                if (!supervisor(dc))
3208
                                    goto illegal_insn;
3209
#endif
3210
                                {
3211
                                    TCGv r_tickptr;
3212

    
3213
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3214
                                                   cpu_src2);
3215
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3216
                                                  offsetof(CPUSPARCState,
3217
                                                           tick_cmpr));
3218
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3219
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3220
                                                   offsetof(CPUState, tick));
3221
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3222
                                                       r_tickptr, cpu_tmp0);
3223
                                    tcg_temp_free(r_tickptr);
3224
                                }
3225
                                break;
3226
                            case 0x18: /* System tick */
3227
#if !defined(CONFIG_USER_ONLY)
3228
                                if (!supervisor(dc))
3229
                                    goto illegal_insn;
3230
#endif
3231
                                {
3232
                                    TCGv r_tickptr;
3233

    
3234
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3235
                                                   cpu_src2);
3236
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3237
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3238
                                                   offsetof(CPUState, stick));
3239
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3240
                                                       r_tickptr, cpu_dst);
3241
                                    tcg_temp_free(r_tickptr);
3242
                                }
3243
                                break;
3244
                            case 0x19: /* System tick compare */
3245
#if !defined(CONFIG_USER_ONLY)
3246
                                if (!supervisor(dc))
3247
                                    goto illegal_insn;
3248
#endif
3249
                                {
3250
                                    TCGv r_tickptr;
3251

    
3252
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3253
                                                   cpu_src2);
3254
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3255
                                                  offsetof(CPUSPARCState,
3256
                                                           stick_cmpr));
3257
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3258
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3259
                                                   offsetof(CPUState, stick));
3260
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3261
                                                       r_tickptr, cpu_tmp0);
3262
                                    tcg_temp_free(r_tickptr);
3263
                                }
3264
                                break;
3265

    
3266
                            case 0x10: /* Performance Control */
3267
                            case 0x11: /* Performance Instrumentation
3268
                                          Counter */
3269
                            case 0x12: /* Dispatch Control */
3270
                            case 0x14: /* Softint set */
3271
                            case 0x15: /* Softint clear */
3272
                            case 0x16: /* Softint write */
3273
#endif
3274
                            default:
3275
                                goto illegal_insn;
3276
                            }
3277
                        }
3278
                        break;
3279
#if !defined(CONFIG_USER_ONLY)
3280
                    case 0x31: /* wrpsr, V9 saved, restored */
3281
                        {
3282
                            if (!supervisor(dc))
3283
                                goto priv_insn;
3284
#ifdef TARGET_SPARC64
3285
                            switch (rd) {
3286
                            case 0:
3287
                                tcg_gen_helper_0_0(helper_saved);
3288
                                break;
3289
                            case 1:
3290
                                tcg_gen_helper_0_0(helper_restored);
3291
                                break;
3292
                            case 2: /* UA2005 allclean */
3293
                            case 3: /* UA2005 otherw */
3294
                            case 4: /* UA2005 normalw */
3295
                            case 5: /* UA2005 invalw */
3296
                                // XXX
3297
                            default:
3298
                                goto illegal_insn;
3299
                            }
3300
#else
3301
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3302
                            tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3303
                            save_state(dc, cpu_cond);
3304
                            gen_op_next_insn();
3305
                            tcg_gen_exit_tb(0);
3306
                            dc->is_br = 1;
3307
#endif
3308
                        }
3309
                        break;
3310
                    case 0x32: /* wrwim, V9 wrpr */
3311
                        {
3312
                            if (!supervisor(dc))
3313
                                goto priv_insn;
3314
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3315
#ifdef TARGET_SPARC64
3316
                            switch (rd) {
3317
                            case 0: // tpc
3318
                                {
3319
                                    TCGv r_tsptr;
3320

    
3321
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3322
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3323
                                                   offsetof(CPUState, tsptr));
3324
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3325
                                                  offsetof(trap_state, tpc));
3326
                                    tcg_temp_free(r_tsptr);
3327
                                }
3328
                                break;
3329
                            case 1: // tnpc
3330
                                {
3331
                                    TCGv r_tsptr;
3332

    
3333
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3334
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3335
                                                   offsetof(CPUState, tsptr));
3336
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3337
                                                  offsetof(trap_state, tnpc));
3338
                                    tcg_temp_free(r_tsptr);
3339
                                }
3340
                                break;
3341
                            case 2: // tstate
3342
                                {
3343
                                    TCGv r_tsptr;
3344

    
3345
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3346
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3347
                                                   offsetof(CPUState, tsptr));
3348
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3349
                                                  offsetof(trap_state,
3350
                                                           tstate));
3351
                                    tcg_temp_free(r_tsptr);
3352
                                }
3353
                                break;
3354
                            case 3: // tt
3355
                                {
3356
                                    TCGv r_tsptr;
3357

    
3358
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3359
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3360
                                                   offsetof(CPUState, tsptr));
3361
                                    tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3362
                                                   offsetof(trap_state, tt));
3363
                                    tcg_temp_free(r_tsptr);
3364
                                }
3365
                                break;
3366
                            case 4: // tick
3367
                                {
3368
                                    TCGv r_tickptr;
3369

    
3370
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3371
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3372
                                                   offsetof(CPUState, tick));
3373
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3374
                                                       r_tickptr, cpu_tmp0);
3375
                                    tcg_temp_free(r_tickptr);
3376
                                }
3377
                                break;
3378
                            case 5: // tba
3379
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3380
                                              offsetof(CPUSPARCState, tbr));
3381
                                break;
3382
                            case 6: // pstate
3383
                                save_state(dc, cpu_cond);
3384
                                tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3385
                                gen_op_next_insn();
3386
                                tcg_gen_exit_tb(0);
3387
                                dc->is_br = 1;
3388
                                break;
3389
                            case 7: // tl
3390
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3391
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3392
                                               offsetof(CPUSPARCState, tl));
3393
                                break;
3394
                            case 8: // pil
3395
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3396
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3397
                                               offsetof(CPUSPARCState,
3398
                                                        psrpil));
3399
                                break;
3400
                            case 9: // cwp
3401
                                tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3402
                                break;
3403
                            case 10: // cansave
3404
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3405
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3406
                                               offsetof(CPUSPARCState,
3407
                                                        cansave));
3408
                                break;
3409
                            case 11: // canrestore
3410
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3411
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3412
                                               offsetof(CPUSPARCState,
3413
                                                        canrestore));
3414
                                break;
3415
                            case 12: // cleanwin
3416
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3417
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3418
                                               offsetof(CPUSPARCState,
3419
                                                        cleanwin));
3420
                                break;
3421
                            case 13: // otherwin
3422
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3423
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3424
                                               offsetof(CPUSPARCState,
3425
                                                        otherwin));
3426
                                break;
3427
                            case 14: // wstate
3428
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3429
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3430
                                               offsetof(CPUSPARCState,
3431
                                                        wstate));
3432
                                break;
3433
                            case 16: // UA2005 gl
3434
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3435
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3436
                                               offsetof(CPUSPARCState, gl));
3437
                                break;
3438
                            case 26: // UA2005 strand status
3439
                                if (!hypervisor(dc))
3440
                                    goto priv_insn;
3441
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3442
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3443
                                               offsetof(CPUSPARCState, ssr));
3444
                                break;
3445
                            default:
3446
                                goto illegal_insn;
3447
                            }
3448
#else
3449
                            tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3450
                            tcg_gen_st_i32(cpu_tmp32, cpu_env,
3451
                                           offsetof(CPUSPARCState, wim));
3452
#endif
3453
                        }
3454
                        break;
3455
                    case 0x33: /* wrtbr, UA2005 wrhpr */
3456
                        {
3457
#ifndef TARGET_SPARC64
3458
                            if (!supervisor(dc))
3459
                                goto priv_insn;
3460
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3461
                            tcg_gen_st_tl(cpu_tmp0, cpu_env,
3462
                                          offsetof(CPUSPARCState, tbr));
3463
#else
3464
                            if (!hypervisor(dc))
3465
                                goto priv_insn;
3466
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3467
                            switch (rd) {
3468
                            case 0: // hpstate
3469
                                // XXX gen_op_wrhpstate();
3470
                                save_state(dc, cpu_cond);
3471
                                gen_op_next_insn();
3472
                                tcg_gen_exit_tb(0);
3473
                                dc->is_br = 1;
3474
                                break;
3475
                            case 1: // htstate
3476
                                // XXX gen_op_wrhtstate();
3477
                                break;
3478
                            case 3: // hintp
3479
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3480
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3481
                                               offsetof(CPUSPARCState, hintp));
3482
                                break;
3483
                            case 5: // htba
3484
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3485
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3486
                                               offsetof(CPUSPARCState, htba));
3487
                                break;
3488
                            case 31: // hstick_cmpr
3489
                                {
3490
                                    TCGv r_tickptr;
3491

    
3492
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3493
                                                  offsetof(CPUSPARCState,
3494
                                                           hstick_cmpr));
3495
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3496
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3497
                                                   offsetof(CPUState, hstick));
3498
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3499
                                                       r_tickptr, cpu_tmp0);
3500
                                    tcg_temp_free(r_tickptr);
3501
                                }
3502
                                break;
3503
                            case 6: // hver readonly
3504
                            default:
3505
                                goto illegal_insn;
3506
                            }
3507
#endif
3508
                        }
3509
                        break;
3510
#endif
3511
#ifdef TARGET_SPARC64
3512
                    case 0x2c: /* V9 movcc */
3513
                        {
3514
                            int cc = GET_FIELD_SP(insn, 11, 12);
3515
                            int cond = GET_FIELD_SP(insn, 14, 17);
3516
                            TCGv r_cond;
3517
                            int l1;
3518

    
3519
                            r_cond = tcg_temp_new(TCG_TYPE_TL);
3520
                            if (insn & (1 << 18)) {
3521
                                if (cc == 0)
3522
                                    gen_cond(r_cond, 0, cond);
3523
                                else if (cc == 2)
3524
                                    gen_cond(r_cond, 1, cond);
3525
                                else
3526
                                    goto illegal_insn;
3527
                            } else {
3528
                                gen_fcond(r_cond, cc, cond);
3529
                            }
3530

    
3531
                            l1 = gen_new_label();
3532

    
3533
                            tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3534
                            if (IS_IMM) {       /* immediate */
3535
                                TCGv r_const;
3536

    
3537
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
3538
                                r_const = tcg_const_tl((int)rs2);
3539
                                gen_movl_TN_reg(rd, r_const);
3540
                                tcg_temp_free(r_const);
3541
                            } else {
3542
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3543
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3544
                                gen_movl_TN_reg(rd, cpu_tmp0);
3545
                            }
3546
                            gen_set_label(l1);
3547
                            tcg_temp_free(r_cond);
3548
                            break;
3549
                        }
3550
                    case 0x2d: /* V9 sdivx */
3551
                        gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3552
                        gen_movl_TN_reg(rd, cpu_dst);
3553
                        break;
3554
                    case 0x2e: /* V9 popc */
3555
                        {
3556
                            cpu_src2 = get_src2(insn, cpu_src2);
3557
                            tcg_gen_helper_1_1(helper_popc, cpu_dst,
3558
                                               cpu_src2);
3559
                            gen_movl_TN_reg(rd, cpu_dst);
3560
                        }
3561
                    case 0x2f: /* V9 movr */
3562
                        {
3563
                            int cond = GET_FIELD_SP(insn, 10, 12);
3564
                            int l1;
3565

    
3566
                            cpu_src1 = get_src1(insn, cpu_src1);
3567

    
3568
                            l1 = gen_new_label();
3569

    
3570
                            tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3571
                                              cpu_src1, 0, l1);
3572
                            if (IS_IMM) {       /* immediate */
3573
                                TCGv r_const;
3574

    
3575
                                rs2 = GET_FIELD_SPs(insn, 0, 9);
3576
                                r_const = tcg_const_tl((int)rs2);
3577
                                gen_movl_TN_reg(rd, r_const);
3578
                                tcg_temp_free(r_const);
3579
                            } else {
3580
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3581
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3582
                                gen_movl_TN_reg(rd, cpu_tmp0);
3583
                            }
3584
                            gen_set_label(l1);
3585
                            break;
3586
                        }
3587
#endif
3588
                    default:
3589
                        goto illegal_insn;
3590
                    }
3591
                }
3592
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3593
#ifdef TARGET_SPARC64
3594
                int opf = GET_FIELD_SP(insn, 5, 13);
3595
                rs1 = GET_FIELD(insn, 13, 17);
3596
                rs2 = GET_FIELD(insn, 27, 31);
3597
                if (gen_trap_ifnofpu(dc, cpu_cond))
3598
                    goto jmp_insn;
3599

    
3600
                switch (opf) {
3601
                case 0x000: /* VIS I edge8cc */
3602
                case 0x001: /* VIS II edge8n */
3603
                case 0x002: /* VIS I edge8lcc */
3604
                case 0x003: /* VIS II edge8ln */
3605
                case 0x004: /* VIS I edge16cc */
3606
                case 0x005: /* VIS II edge16n */
3607
                case 0x006: /* VIS I edge16lcc */
3608
                case 0x007: /* VIS II edge16ln */
3609
                case 0x008: /* VIS I edge32cc */
3610
                case 0x009: /* VIS II edge32n */
3611
                case 0x00a: /* VIS I edge32lcc */
3612
                case 0x00b: /* VIS II edge32ln */
3613
                    // XXX
3614
                    goto illegal_insn;
3615
                case 0x010: /* VIS I array8 */
3616
                    CHECK_FPU_FEATURE(dc, VIS1);
3617
                    cpu_src1 = get_src1(insn, cpu_src1);
3618
                    gen_movl_reg_TN(rs2, cpu_src2);
3619
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3620
                                       cpu_src2);
3621
                    gen_movl_TN_reg(rd, cpu_dst);
3622
                    break;
3623
                case 0x012: /* VIS I array16 */
3624
                    CHECK_FPU_FEATURE(dc, VIS1);
3625
                    cpu_src1 = get_src1(insn, cpu_src1);
3626
                    gen_movl_reg_TN(rs2, cpu_src2);
3627
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3628
                                       cpu_src2);
3629
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3630
                    gen_movl_TN_reg(rd, cpu_dst);
3631
                    break;
3632
                case 0x014: /* VIS I array32 */
3633
                    CHECK_FPU_FEATURE(dc, VIS1);
3634
                    cpu_src1 = get_src1(insn, cpu_src1);
3635
                    gen_movl_reg_TN(rs2, cpu_src2);
3636
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3637
                                       cpu_src2);
3638
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3639
                    gen_movl_TN_reg(rd, cpu_dst);
3640
                    break;
3641
                case 0x018: /* VIS I alignaddr */
3642
                    CHECK_FPU_FEATURE(dc, VIS1);
3643
                    cpu_src1 = get_src1(insn, cpu_src1);
3644
                    gen_movl_reg_TN(rs2, cpu_src2);
3645
                    tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3646
                                       cpu_src2);
3647
                    gen_movl_TN_reg(rd, cpu_dst);
3648
                    break;
3649
                case 0x019: /* VIS II bmask */
3650
                case 0x01a: /* VIS I alignaddrl */
3651
                    // XXX
3652
                    goto illegal_insn;
3653
                case 0x020: /* VIS I fcmple16 */
3654
                    CHECK_FPU_FEATURE(dc, VIS1);
3655
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3656
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3657
                    tcg_gen_helper_0_0(helper_fcmple16);
3658
                    gen_op_store_DT0_fpr(DFPREG(rd));
3659
                    break;
3660
                case 0x022: /* VIS I fcmpne16 */
3661
                    CHECK_FPU_FEATURE(dc, VIS1);
3662
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3663
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3664
                    tcg_gen_helper_0_0(helper_fcmpne16);
3665
                    gen_op_store_DT0_fpr(DFPREG(rd));
3666
                    break;
3667
                case 0x024: /* VIS I fcmple32 */
3668
                    CHECK_FPU_FEATURE(dc, VIS1);
3669
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3670
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3671
                    tcg_gen_helper_0_0(helper_fcmple32);
3672
                    gen_op_store_DT0_fpr(DFPREG(rd));
3673
                    break;
3674
                case 0x026: /* VIS I fcmpne32 */
3675
                    CHECK_FPU_FEATURE(dc, VIS1);
3676
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3677
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3678
                    tcg_gen_helper_0_0(helper_fcmpne32);
3679
                    gen_op_store_DT0_fpr(DFPREG(rd));
3680
                    break;
3681
                case 0x028: /* VIS I fcmpgt16 */
3682
                    CHECK_FPU_FEATURE(dc, VIS1);
3683
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3684
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3685
                    tcg_gen_helper_0_0(helper_fcmpgt16);
3686
                    gen_op_store_DT0_fpr(DFPREG(rd));
3687
                    break;
3688
                case 0x02a: /* VIS I fcmpeq16 */
3689
                    CHECK_FPU_FEATURE(dc, VIS1);
3690
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3691
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3692
                    tcg_gen_helper_0_0(helper_fcmpeq16);
3693
                    gen_op_store_DT0_fpr(DFPREG(rd));
3694
                    break;
3695
                case 0x02c: /* VIS I fcmpgt32 */
3696
                    CHECK_FPU_FEATURE(dc, VIS1);
3697
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3698
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3699
                    tcg_gen_helper_0_0(helper_fcmpgt32);
3700
                    gen_op_store_DT0_fpr(DFPREG(rd));
3701
                    break;
3702
                case 0x02e: /* VIS I fcmpeq32 */
3703
                    CHECK_FPU_FEATURE(dc, VIS1);
3704
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3705
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3706
                    tcg_gen_helper_0_0(helper_fcmpeq32);
3707
                    gen_op_store_DT0_fpr(DFPREG(rd));
3708
                    break;
3709
                case 0x031: /* VIS I fmul8x16 */
3710
                    CHECK_FPU_FEATURE(dc, VIS1);
3711
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3712
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3713
                    tcg_gen_helper_0_0(helper_fmul8x16);
3714
                    gen_op_store_DT0_fpr(DFPREG(rd));
3715
                    break;
3716
                case 0x033: /* VIS I fmul8x16au */
3717
                    CHECK_FPU_FEATURE(dc, VIS1);
3718
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3719
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3720
                    tcg_gen_helper_0_0(helper_fmul8x16au);
3721
                    gen_op_store_DT0_fpr(DFPREG(rd));
3722
                    break;
3723
                case 0x035: /* VIS I fmul8x16al */
3724
                    CHECK_FPU_FEATURE(dc, VIS1);
3725
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3726
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3727
                    tcg_gen_helper_0_0(helper_fmul8x16al);
3728
                    gen_op_store_DT0_fpr(DFPREG(rd));
3729
                    break;
3730
                case 0x036: /* VIS I fmul8sux16 */
3731
                    CHECK_FPU_FEATURE(dc, VIS1);
3732
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3733
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3734
                    tcg_gen_helper_0_0(helper_fmul8sux16);
3735
                    gen_op_store_DT0_fpr(DFPREG(rd));
3736
                    break;
3737
                case 0x037: /* VIS I fmul8ulx16 */
3738
                    CHECK_FPU_FEATURE(dc, VIS1);
3739
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3740
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3741
                    tcg_gen_helper_0_0(helper_fmul8ulx16);
3742
                    gen_op_store_DT0_fpr(DFPREG(rd));
3743
                    break;
3744
                case 0x038: /* VIS I fmuld8sux16 */
3745
                    CHECK_FPU_FEATURE(dc, VIS1);
3746
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3747
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3748
                    tcg_gen_helper_0_0(helper_fmuld8sux16);
3749
                    gen_op_store_DT0_fpr(DFPREG(rd));
3750
                    break;
3751
                case 0x039: /* VIS I fmuld8ulx16 */
3752
                    CHECK_FPU_FEATURE(dc, VIS1);
3753
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3754
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3755
                    tcg_gen_helper_0_0(helper_fmuld8ulx16);
3756
                    gen_op_store_DT0_fpr(DFPREG(rd));
3757
                    break;
3758
                case 0x03a: /* VIS I fpack32 */
3759
                case 0x03b: /* VIS I fpack16 */
3760
                case 0x03d: /* VIS I fpackfix */
3761
                case 0x03e: /* VIS I pdist */
3762
                    // XXX
3763
                    goto illegal_insn;
3764
                case 0x048: /* VIS I faligndata */
3765
                    CHECK_FPU_FEATURE(dc, VIS1);
3766
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3767
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3768
                    tcg_gen_helper_0_0(helper_faligndata);
3769
                    gen_op_store_DT0_fpr(DFPREG(rd));
3770
                    break;
3771
                case 0x04b: /* VIS I fpmerge */
3772
                    CHECK_FPU_FEATURE(dc, VIS1);
3773
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3774
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3775
                    tcg_gen_helper_0_0(helper_fpmerge);
3776
                    gen_op_store_DT0_fpr(DFPREG(rd));
3777
                    break;
3778
                case 0x04c: /* VIS II bshuffle */
3779
                    // XXX
3780
                    goto illegal_insn;
3781
                case 0x04d: /* VIS I fexpand */
3782
                    CHECK_FPU_FEATURE(dc, VIS1);
3783
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3784
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3785
                    tcg_gen_helper_0_0(helper_fexpand);
3786
                    gen_op_store_DT0_fpr(DFPREG(rd));
3787
                    break;
3788
                case 0x050: /* VIS I fpadd16 */
3789
                    CHECK_FPU_FEATURE(dc, VIS1);
3790
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3791
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3792
                    tcg_gen_helper_0_0(helper_fpadd16);
3793
                    gen_op_store_DT0_fpr(DFPREG(rd));
3794
                    break;
3795
                case 0x051: /* VIS I fpadd16s */
3796
                    CHECK_FPU_FEATURE(dc, VIS1);
3797
                    gen_op_load_fpr_FT0(rs1);
3798
                    gen_op_load_fpr_FT1(rs2);
3799
                    tcg_gen_helper_0_0(helper_fpadd16s);
3800
                    gen_op_store_FT0_fpr(rd);
3801
                    break;
3802
                case 0x052: /* VIS I fpadd32 */
3803
                    CHECK_FPU_FEATURE(dc, VIS1);
3804
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3805
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3806
                    tcg_gen_helper_0_0(helper_fpadd32);
3807
                    gen_op_store_DT0_fpr(DFPREG(rd));
3808
                    break;
3809
                case 0x053: /* VIS I fpadd32s */
3810
                    CHECK_FPU_FEATURE(dc, VIS1);
3811
                    gen_op_load_fpr_FT0(rs1);
3812
                    gen_op_load_fpr_FT1(rs2);
3813
                    tcg_gen_helper_0_0(helper_fpadd32s);
3814
                    gen_op_store_FT0_fpr(rd);
3815
                    break;
3816
                case 0x054: /* VIS I fpsub16 */
3817
                    CHECK_FPU_FEATURE(dc, VIS1);
3818
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3819
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3820
                    tcg_gen_helper_0_0(helper_fpsub16);
3821
                    gen_op_store_DT0_fpr(DFPREG(rd));
3822
                    break;
3823
                case 0x055: /* VIS I fpsub16s */
3824
                    CHECK_FPU_FEATURE(dc, VIS1);
3825
                    gen_op_load_fpr_FT0(rs1);
3826
                    gen_op_load_fpr_FT1(rs2);
3827
                    tcg_gen_helper_0_0(helper_fpsub16s);
3828
                    gen_op_store_FT0_fpr(rd);
3829
                    break;
3830
                case 0x056: /* VIS I fpsub32 */
3831
                    CHECK_FPU_FEATURE(dc, VIS1);
3832
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3833
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3834
                    tcg_gen_helper_0_0(helper_fpadd32);
3835
                    gen_op_store_DT0_fpr(DFPREG(rd));
3836
                    break;
3837
                case 0x057: /* VIS I fpsub32s */
3838
                    CHECK_FPU_FEATURE(dc, VIS1);
3839
                    gen_op_load_fpr_FT0(rs1);
3840
                    gen_op_load_fpr_FT1(rs2);
3841
                    tcg_gen_helper_0_0(helper_fpsub32s);
3842
                    gen_op_store_FT0_fpr(rd);
3843
                    break;
3844
                case 0x060: /* VIS I fzero */
3845
                    CHECK_FPU_FEATURE(dc, VIS1);
3846
                    tcg_gen_helper_0_0(helper_movl_DT0_0);
3847
                    gen_op_store_DT0_fpr(DFPREG(rd));
3848
                    break;
3849
                case 0x061: /* VIS I fzeros */
3850
                    CHECK_FPU_FEATURE(dc, VIS1);
3851
                    tcg_gen_helper_0_0(helper_movl_FT0_0);
3852
                    gen_op_store_FT0_fpr(rd);
3853
                    break;
3854
                case 0x062: /* VIS I fnor */
3855
                    CHECK_FPU_FEATURE(dc, VIS1);
3856
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3857
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3858
                    tcg_gen_helper_0_0(helper_fnor);
3859
                    gen_op_store_DT0_fpr(DFPREG(rd));
3860
                    break;
3861
                case 0x063: /* VIS I fnors */
3862
                    CHECK_FPU_FEATURE(dc, VIS1);
3863
                    gen_op_load_fpr_FT0(rs1);
3864
                    gen_op_load_fpr_FT1(rs2);
3865
                    tcg_gen_helper_0_0(helper_fnors);
3866
                    gen_op_store_FT0_fpr(rd);
3867
                    break;
3868
                case 0x064: /* VIS I fandnot2 */
3869
                    CHECK_FPU_FEATURE(dc, VIS1);
3870
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3871
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3872
                    tcg_gen_helper_0_0(helper_fandnot);
3873
                    gen_op_store_DT0_fpr(DFPREG(rd));
3874
                    break;
3875
                case 0x065: /* VIS I fandnot2s */
3876
                    CHECK_FPU_FEATURE(dc, VIS1);
3877
                    gen_op_load_fpr_FT1(rs1);
3878
                    gen_op_load_fpr_FT0(rs2);
3879
                    tcg_gen_helper_0_0(helper_fandnots);
3880
                    gen_op_store_FT0_fpr(rd);
3881
                    break;
3882
                case 0x066: /* VIS I fnot2 */
3883
                    CHECK_FPU_FEATURE(dc, VIS1);
3884
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3885
                    tcg_gen_helper_0_0(helper_fnot);
3886
                    gen_op_store_DT0_fpr(DFPREG(rd));
3887
                    break;
3888
                case 0x067: /* VIS I fnot2s */
3889
                    CHECK_FPU_FEATURE(dc, VIS1);
3890
                    gen_op_load_fpr_FT1(rs2);
3891
                    tcg_gen_helper_0_0(helper_fnot);
3892
                    gen_op_store_FT0_fpr(rd);
3893
                    break;
3894
                case 0x068: /* VIS I fandnot1 */
3895
                    CHECK_FPU_FEATURE(dc, VIS1);
3896
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3897
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3898
                    tcg_gen_helper_0_0(helper_fandnot);
3899
                    gen_op_store_DT0_fpr(DFPREG(rd));
3900
                    break;
3901
                case 0x069: /* VIS I fandnot1s */
3902
                    CHECK_FPU_FEATURE(dc, VIS1);
3903
                    gen_op_load_fpr_FT0(rs1);
3904
                    gen_op_load_fpr_FT1(rs2);
3905
                    tcg_gen_helper_0_0(helper_fandnots);
3906
                    gen_op_store_FT0_fpr(rd);
3907
                    break;
3908
                case 0x06a: /* VIS I fnot1 */
3909
                    CHECK_FPU_FEATURE(dc, VIS1);
3910
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3911
                    tcg_gen_helper_0_0(helper_fnot);
3912
                    gen_op_store_DT0_fpr(DFPREG(rd));
3913
                    break;
3914
                case 0x06b: /* VIS I fnot1s */
3915
                    CHECK_FPU_FEATURE(dc, VIS1);
3916
                    gen_op_load_fpr_FT1(rs1);
3917
                    tcg_gen_helper_0_0(helper_fnot);
3918
                    gen_op_store_FT0_fpr(rd);
3919
                    break;
3920
                case 0x06c: /* VIS I fxor */
3921
                    CHECK_FPU_FEATURE(dc, VIS1);
3922
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3923
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3924
                    tcg_gen_helper_0_0(helper_fxor);
3925
                    gen_op_store_DT0_fpr(DFPREG(rd));
3926
                    break;
3927
                case 0x06d: /* VIS I fxors */
3928
                    CHECK_FPU_FEATURE(dc, VIS1);
3929
                    gen_op_load_fpr_FT0(rs1);
3930
                    gen_op_load_fpr_FT1(rs2);
3931
                    tcg_gen_helper_0_0(helper_fxors);
3932
                    gen_op_store_FT0_fpr(rd);
3933
                    break;
3934
                case 0x06e: /* VIS I fnand */
3935
                    CHECK_FPU_FEATURE(dc, VIS1);
3936
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3937
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3938
                    tcg_gen_helper_0_0(helper_fnand);
3939
                    gen_op_store_DT0_fpr(DFPREG(rd));
3940
                    break;
3941
                case 0x06f: /* VIS I fnands */
3942
                    CHECK_FPU_FEATURE(dc, VIS1);
3943
                    gen_op_load_fpr_FT0(rs1);
3944
                    gen_op_load_fpr_FT1(rs2);
3945
                    tcg_gen_helper_0_0(helper_fnands);
3946
                    gen_op_store_FT0_fpr(rd);
3947
                    break;
3948
                case 0x070: /* VIS I fand */
3949
                    CHECK_FPU_FEATURE(dc, VIS1);
3950
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3951
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3952
                    tcg_gen_helper_0_0(helper_fand);
3953
                    gen_op_store_DT0_fpr(DFPREG(rd));
3954
                    break;
3955
                case 0x071: /* VIS I fands */
3956
                    CHECK_FPU_FEATURE(dc, VIS1);
3957
                    gen_op_load_fpr_FT0(rs1);
3958
                    gen_op_load_fpr_FT1(rs2);
3959
                    tcg_gen_helper_0_0(helper_fands);
3960
                    gen_op_store_FT0_fpr(rd);
3961
                    break;
3962
                case 0x072: /* VIS I fxnor */
3963
                    CHECK_FPU_FEATURE(dc, VIS1);
3964
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3965
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3966
                    tcg_gen_helper_0_0(helper_fxnor);
3967
                    gen_op_store_DT0_fpr(DFPREG(rd));
3968
                    break;
3969
                case 0x073: /* VIS I fxnors */
3970
                    CHECK_FPU_FEATURE(dc, VIS1);
3971
                    gen_op_load_fpr_FT0(rs1);
3972
                    gen_op_load_fpr_FT1(rs2);
3973
                    tcg_gen_helper_0_0(helper_fxnors);
3974
                    gen_op_store_FT0_fpr(rd);
3975
                    break;
3976
                case 0x074: /* VIS I fsrc1 */
3977
                    CHECK_FPU_FEATURE(dc, VIS1);
3978
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3979
                    gen_op_store_DT0_fpr(DFPREG(rd));
3980
                    break;
3981
                case 0x075: /* VIS I fsrc1s */
3982
                    CHECK_FPU_FEATURE(dc, VIS1);
3983
                    gen_op_load_fpr_FT0(rs1);
3984
                    gen_op_store_FT0_fpr(rd);
3985
                    break;
3986
                case 0x076: /* VIS I fornot2 */
3987
                    CHECK_FPU_FEATURE(dc, VIS1);
3988
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3989
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3990
                    tcg_gen_helper_0_0(helper_fornot);
3991
                    gen_op_store_DT0_fpr(DFPREG(rd));
3992
                    break;
3993
                case 0x077: /* VIS I fornot2s */
3994
                    CHECK_FPU_FEATURE(dc, VIS1);
3995
                    gen_op_load_fpr_FT1(rs1);
3996
                    gen_op_load_fpr_FT0(rs2);
3997
                    tcg_gen_helper_0_0(helper_fornots);
3998
                    gen_op_store_FT0_fpr(rd);
3999
                    break;
4000
                case 0x078: /* VIS I fsrc2 */
4001
                    CHECK_FPU_FEATURE(dc, VIS1);
4002
                    gen_op_load_fpr_DT0(DFPREG(rs2));
4003
                    gen_op_store_DT0_fpr(DFPREG(rd));
4004
                    break;
4005
                case 0x079: /* VIS I fsrc2s */
4006
                    CHECK_FPU_FEATURE(dc, VIS1);
4007
                    gen_op_load_fpr_FT0(rs2);
4008
                    gen_op_store_FT0_fpr(rd);
4009
                    break;
4010
                case 0x07a: /* VIS I fornot1 */
4011
                    CHECK_FPU_FEATURE(dc, VIS1);
4012
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4013
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4014
                    tcg_gen_helper_0_0(helper_fornot);
4015
                    gen_op_store_DT0_fpr(DFPREG(rd));
4016
                    break;
4017
                case 0x07b: /* VIS I fornot1s */
4018
                    CHECK_FPU_FEATURE(dc, VIS1);
4019
                    gen_op_load_fpr_FT0(rs1);
4020
                    gen_op_load_fpr_FT1(rs2);
4021
                    tcg_gen_helper_0_0(helper_fornots);
4022
                    gen_op_store_FT0_fpr(rd);
4023
                    break;
4024
                case 0x07c: /* VIS I for */
4025
                    CHECK_FPU_FEATURE(dc, VIS1);
4026
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4027
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4028
                    tcg_gen_helper_0_0(helper_for);
4029
                    gen_op_store_DT0_fpr(DFPREG(rd));
4030
                    break;
4031
                case 0x07d: /* VIS I fors */
4032
                    CHECK_FPU_FEATURE(dc, VIS1);
4033
                    gen_op_load_fpr_FT0(rs1);
4034
                    gen_op_load_fpr_FT1(rs2);
4035
                    tcg_gen_helper_0_0(helper_fors);
4036
                    gen_op_store_FT0_fpr(rd);
4037
                    break;
4038
                case 0x07e: /* VIS I fone */
4039
                    CHECK_FPU_FEATURE(dc, VIS1);
4040
                    tcg_gen_helper_0_0(helper_movl_DT0_1);
4041
                    gen_op_store_DT0_fpr(DFPREG(rd));
4042
                    break;
4043
                case 0x07f: /* VIS I fones */
4044
                    CHECK_FPU_FEATURE(dc, VIS1);
4045
                    tcg_gen_helper_0_0(helper_movl_FT0_1);
4046
                    gen_op_store_FT0_fpr(rd);
4047
                    break;
4048
                case 0x080: /* VIS I shutdown */
4049
                case 0x081: /* VIS II siam */
4050
                    // XXX
4051
                    goto illegal_insn;
4052
                default:
4053
                    goto illegal_insn;
4054
                }
4055
#else
4056
                goto ncp_insn;
4057
#endif
4058
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4059
#ifdef TARGET_SPARC64
4060
                goto illegal_insn;
4061
#else
4062
                goto ncp_insn;
4063
#endif
4064
#ifdef TARGET_SPARC64
4065
            } else if (xop == 0x39) { /* V9 return */
4066
                TCGv r_const;
4067

    
4068
                save_state(dc, cpu_cond);
4069
                cpu_src1 = get_src1(insn, cpu_src1);
4070
                if (IS_IMM) {   /* immediate */
4071
                    rs2 = GET_FIELDs(insn, 19, 31);
4072
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4073
                } else {                /* register */
4074
                    rs2 = GET_FIELD(insn, 27, 31);
4075
                    if (rs2) {
4076
                        gen_movl_reg_TN(rs2, cpu_src2);
4077
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4078
                    } else
4079
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4080
                }
4081
                tcg_gen_helper_0_0(helper_restore);
4082
                gen_mov_pc_npc(dc, cpu_cond);
4083
                r_const = tcg_const_i32(3);
4084
                tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4085
                tcg_temp_free(r_const);
4086
                tcg_gen_mov_tl(cpu_npc, cpu_dst);
4087
                dc->npc = DYNAMIC_PC;
4088
                goto jmp_insn;
4089
#endif
4090
            } else {
4091
                cpu_src1 = get_src1(insn, cpu_src1);
4092
                if (IS_IMM) {   /* immediate */
4093
                    rs2 = GET_FIELDs(insn, 19, 31);
4094
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4095
                } else {                /* register */
4096
                    rs2 = GET_FIELD(insn, 27, 31);
4097
                    if (rs2) {
4098
                        gen_movl_reg_TN(rs2, cpu_src2);
4099
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4100
                    } else
4101
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4102
                }
4103
                switch (xop) {
4104
                case 0x38:      /* jmpl */
4105
                    {
4106
                        TCGv r_const;
4107

    
4108
                        r_const = tcg_const_tl(dc->pc);
4109
                        gen_movl_TN_reg(rd, r_const);
4110
                        tcg_temp_free(r_const);
4111
                        gen_mov_pc_npc(dc, cpu_cond);
4112
                        r_const = tcg_const_i32(3);
4113
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4114
                                           r_const);
4115
                        tcg_temp_free(r_const);
4116
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4117
                        dc->npc = DYNAMIC_PC;
4118
                    }
4119
                    goto jmp_insn;
4120
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4121
                case 0x39:      /* rett, V9 return */
4122
                    {
4123
                        TCGv r_const;
4124

    
4125
                        if (!supervisor(dc))
4126
                            goto priv_insn;
4127
                        gen_mov_pc_npc(dc, cpu_cond);
4128
                        r_const = tcg_const_i32(3);
4129
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4130
                                           r_const);
4131
                        tcg_temp_free(r_const);
4132
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4133
                        dc->npc = DYNAMIC_PC;
4134
                        tcg_gen_helper_0_0(helper_rett);
4135
                    }
4136
                    goto jmp_insn;
4137
#endif
4138
                case 0x3b: /* flush */
4139
                    if (!((dc)->features & CPU_FEATURE_FLUSH))
4140
                        goto unimp_flush;
4141
                    tcg_gen_helper_0_1(helper_flush, cpu_dst);
4142
                    break;
4143
                case 0x3c:      /* save */
4144
                    save_state(dc, cpu_cond);
4145
                    tcg_gen_helper_0_0(helper_save);
4146
                    gen_movl_TN_reg(rd, cpu_dst);
4147
                    break;
4148
                case 0x3d:      /* restore */
4149
                    save_state(dc, cpu_cond);
4150
                    tcg_gen_helper_0_0(helper_restore);
4151
                    gen_movl_TN_reg(rd, cpu_dst);
4152
                    break;
4153
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4154
                case 0x3e:      /* V9 done/retry */
4155
                    {
4156
                        switch (rd) {
4157
                        case 0:
4158
                            if (!supervisor(dc))
4159
                                goto priv_insn;
4160
                            dc->npc = DYNAMIC_PC;
4161
                            dc->pc = DYNAMIC_PC;
4162
                            tcg_gen_helper_0_0(helper_done);
4163
                            goto jmp_insn;
4164
                        case 1:
4165
                            if (!supervisor(dc))
4166
                                goto priv_insn;
4167
                            dc->npc = DYNAMIC_PC;
4168
                            dc->pc = DYNAMIC_PC;
4169
                            tcg_gen_helper_0_0(helper_retry);
4170
                            goto jmp_insn;
4171
                        default:
4172
                            goto illegal_insn;
4173
                        }
4174
                    }
4175
                    break;
4176
#endif
4177
                default:
4178
                    goto illegal_insn;
4179
                }
4180
            }
4181
            break;
4182
        }
4183
        break;
4184
    case 3:                     /* load/store instructions */
4185
        {
4186
            unsigned int xop = GET_FIELD(insn, 7, 12);
4187

    
4188
            cpu_src1 = get_src1(insn, cpu_src1);
4189
            if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
4190
                rs2 = GET_FIELD(insn, 27, 31);
4191
                gen_movl_reg_TN(rs2, cpu_src2);
4192
                tcg_gen_mov_tl(cpu_addr, cpu_src1);
4193
            } else if (IS_IMM) {     /* immediate */
4194
                rs2 = GET_FIELDs(insn, 19, 31);
4195
                tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4196
            } else {            /* register */
4197
                rs2 = GET_FIELD(insn, 27, 31);
4198
                if (rs2 != 0) {
4199
                    gen_movl_reg_TN(rs2, cpu_src2);
4200
                    tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4201
                } else
4202
                    tcg_gen_mov_tl(cpu_addr, cpu_src1);
4203
            }
4204
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4205
                (xop > 0x17 && xop <= 0x1d ) ||
4206
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4207
                switch (xop) {
4208
                case 0x0:       /* load unsigned word */
4209
                    gen_address_mask(dc, cpu_addr);
4210
                    tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4211
                    break;
4212
                case 0x1:       /* load unsigned byte */
4213
                    gen_address_mask(dc, cpu_addr);
4214
                    tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4215
                    break;
4216
                case 0x2:       /* load unsigned halfword */
4217
                    gen_address_mask(dc, cpu_addr);
4218
                    tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4219
                    break;
4220
                case 0x3:       /* load double word */
4221
                    if (rd & 1)
4222
                        goto illegal_insn;
4223
                    else {
4224
                        TCGv r_const;
4225

    
4226
                        save_state(dc, cpu_cond);
4227
                        r_const = tcg_const_i32(7);
4228
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4229
                                           r_const); // XXX remove
4230
                        tcg_temp_free(r_const);
4231
                        gen_address_mask(dc, cpu_addr);
4232
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4233
                        tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4234
                        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4235
                        gen_movl_TN_reg(rd + 1, cpu_tmp0);
4236
                        tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4237
                        tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4238
                        tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4239
                    }
4240
                    break;
4241
                case 0x9:       /* load signed byte */
4242
                    gen_address_mask(dc, cpu_addr);
4243
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4244
                    break;
4245
                case 0xa:       /* load signed halfword */
4246
                    gen_address_mask(dc, cpu_addr);
4247
                    tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4248
                    break;
4249
                case 0xd:       /* ldstub -- XXX: should be atomically */
4250
                    {
4251
                        TCGv r_const;
4252

    
4253
                        gen_address_mask(dc, cpu_addr);
4254
                        tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4255
                        r_const = tcg_const_tl(0xff);
4256
                        tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4257
                        tcg_temp_free(r_const);
4258
                    }
4259
                    break;
4260
                case 0x0f:      /* swap register with memory. Also
4261
                                   atomically */
4262
                    CHECK_IU_FEATURE(dc, SWAP);
4263
                    gen_movl_reg_TN(rd, cpu_val);
4264
                    gen_address_mask(dc, cpu_addr);
4265
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4266
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4267
                    tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4268
                    break;
4269
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4270
                case 0x10:      /* load word alternate */
4271
#ifndef TARGET_SPARC64
4272
                    if (IS_IMM)
4273
                        goto illegal_insn;
4274
                    if (!supervisor(dc))
4275
                        goto priv_insn;
4276
#endif
4277
                    save_state(dc, cpu_cond);
4278
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4279
                    break;
4280
                case 0x11:      /* load unsigned byte alternate */
4281
#ifndef TARGET_SPARC64
4282
                    if (IS_IMM)
4283
                        goto illegal_insn;
4284
                    if (!supervisor(dc))
4285
                        goto priv_insn;
4286
#endif
4287
                    save_state(dc, cpu_cond);
4288
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4289
                    break;
4290
                case 0x12:      /* load unsigned halfword alternate */
4291
#ifndef TARGET_SPARC64
4292
                    if (IS_IMM)
4293
                        goto illegal_insn;
4294
                    if (!supervisor(dc))
4295
                        goto priv_insn;
4296
#endif
4297
                    save_state(dc, cpu_cond);
4298
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4299
                    break;
4300
                case 0x13:      /* load double word alternate */
4301
#ifndef TARGET_SPARC64
4302
                    if (IS_IMM)
4303
                        goto illegal_insn;
4304
                    if (!supervisor(dc))
4305
                        goto priv_insn;
4306
#endif
4307
                    if (rd & 1)
4308
                        goto illegal_insn;
4309
                    save_state(dc, cpu_cond);
4310
                    gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4311
                    goto skip_move;
4312
                case 0x19:      /* load signed byte alternate */
4313
#ifndef TARGET_SPARC64
4314
                    if (IS_IMM)
4315
                        goto illegal_insn;
4316
                    if (!supervisor(dc))
4317
                        goto priv_insn;
4318
#endif
4319
                    save_state(dc, cpu_cond);
4320
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4321
                    break;
4322
                case 0x1a:      /* load signed halfword alternate */
4323
#ifndef TARGET_SPARC64
4324
                    if (IS_IMM)
4325
                        goto illegal_insn;
4326
                    if (!supervisor(dc))
4327
                        goto priv_insn;
4328
#endif
4329
                    save_state(dc, cpu_cond);
4330
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4331
                    break;
4332
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
4333
#ifndef TARGET_SPARC64
4334
                    if (IS_IMM)
4335
                        goto illegal_insn;
4336
                    if (!supervisor(dc))
4337
                        goto priv_insn;
4338
#endif
4339
                    save_state(dc, cpu_cond);
4340
                    gen_ldstub_asi(cpu_val, cpu_addr, insn);
4341
                    break;
4342
                case 0x1f:      /* swap reg with alt. memory. Also
4343
                                   atomically */
4344
                    CHECK_IU_FEATURE(dc, SWAP);
4345
#ifndef TARGET_SPARC64
4346
                    if (IS_IMM)
4347
                        goto illegal_insn;
4348
                    if (!supervisor(dc))
4349
                        goto priv_insn;
4350
#endif
4351
                    save_state(dc, cpu_cond);
4352
                    gen_movl_reg_TN(rd, cpu_val);
4353
                    gen_swap_asi(cpu_val, cpu_addr, insn);
4354
                    break;
4355

    
4356
#ifndef TARGET_SPARC64
4357
                case 0x30: /* ldc */
4358
                case 0x31: /* ldcsr */
4359
                case 0x33: /* lddc */
4360
                    goto ncp_insn;
4361
#endif
4362
#endif
4363
#ifdef TARGET_SPARC64
4364
                case 0x08: /* V9 ldsw */
4365
                    gen_address_mask(dc, cpu_addr);
4366
                    tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4367
                    break;
4368
                case 0x0b: /* V9 ldx */
4369
                    gen_address_mask(dc, cpu_addr);
4370
                    tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4371
                    break;
4372
                case 0x18: /* V9 ldswa */
4373
                    save_state(dc, cpu_cond);
4374
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4375
                    break;
4376
                case 0x1b: /* V9 ldxa */
4377
                    save_state(dc, cpu_cond);
4378
                    gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4379
                    break;
4380
                case 0x2d: /* V9 prefetch, no effect */
4381
                    goto skip_move;
4382
                case 0x30: /* V9 ldfa */
4383
                    save_state(dc, cpu_cond);
4384
                    gen_ldf_asi(cpu_addr, insn, 4, rd);
4385
                    goto skip_move;
4386
                case 0x33: /* V9 lddfa */
4387
                    save_state(dc, cpu_cond);
4388
                    gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4389
                    goto skip_move;
4390
                case 0x3d: /* V9 prefetcha, no effect */
4391
                    goto skip_move;
4392
                case 0x32: /* V9 ldqfa */
4393
                    CHECK_FPU_FEATURE(dc, FLOAT128);
4394
                    save_state(dc, cpu_cond);
4395
                    gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4396
                    goto skip_move;
4397
#endif
4398
                default:
4399
                    goto illegal_insn;
4400
                }
4401
                gen_movl_TN_reg(rd, cpu_val);
4402
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4403
            skip_move: ;
4404
#endif
4405
            } else if (xop >= 0x20 && xop < 0x24) {
4406
                if (gen_trap_ifnofpu(dc, cpu_cond))
4407
                    goto jmp_insn;
4408
                save_state(dc, cpu_cond);
4409
                switch (xop) {
4410
                case 0x20:      /* load fpreg */
4411
                    gen_address_mask(dc, cpu_addr);
4412
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4413
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4414
                                   offsetof(CPUState, fpr[rd]));
4415
                    break;
4416
                case 0x21:      /* load fsr */
4417
                    gen_address_mask(dc, cpu_addr);
4418
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4419
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4420
                                   offsetof(CPUState, ft0));
4421
                    tcg_gen_helper_0_0(helper_ldfsr);
4422
                    break;
4423
                case 0x22:      /* load quad fpreg */
4424
                    {
4425
                        TCGv r_const;
4426

    
4427
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4428
                        r_const = tcg_const_i32(dc->mem_idx);
4429
                        tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4430
                        tcg_temp_free(r_const);
4431
                        gen_op_store_QT0_fpr(QFPREG(rd));
4432
                    }
4433
                    break;
4434
                case 0x23:      /* load double fpreg */
4435
                    {
4436
                        TCGv r_const;
4437

    
4438
                        r_const = tcg_const_i32(dc->mem_idx);
4439
                        tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4440
                        tcg_temp_free(r_const);
4441
                        gen_op_store_DT0_fpr(DFPREG(rd));
4442
                    }
4443
                    break;
4444
                default:
4445
                    goto illegal_insn;
4446
                }
4447
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4448
                       xop == 0xe || xop == 0x1e) {
4449
                gen_movl_reg_TN(rd, cpu_val);
4450
                switch (xop) {
4451
                case 0x4: /* store word */
4452
                    gen_address_mask(dc, cpu_addr);
4453
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4454
                    break;
4455
                case 0x5: /* store byte */
4456
                    gen_address_mask(dc, cpu_addr);
4457
                    tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4458
                    break;
4459
                case 0x6: /* store halfword */
4460
                    gen_address_mask(dc, cpu_addr);
4461
                    tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4462
                    break;
4463
                case 0x7: /* store double word */
4464
                    if (rd & 1)
4465
                        goto illegal_insn;
4466
                    else {
4467
                        TCGv r_low, r_const;
4468

    
4469
                        save_state(dc, cpu_cond);
4470
                        gen_address_mask(dc, cpu_addr);
4471
                        r_const = tcg_const_i32(7);
4472
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4473
                                           r_const); // XXX remove
4474
                        tcg_temp_free(r_const);
4475
                        r_low = tcg_temp_new(TCG_TYPE_TL);
4476
                        gen_movl_reg_TN(rd + 1, r_low);
4477
                        tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4478
                                           r_low);
4479
                        tcg_temp_free(r_low);
4480
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4481
                    }
4482
                    break;
4483
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4484
                case 0x14: /* store word alternate */
4485
#ifndef TARGET_SPARC64
4486
                    if (IS_IMM)
4487
                        goto illegal_insn;
4488
                    if (!supervisor(dc))
4489
                        goto priv_insn;
4490
#endif
4491
                    save_state(dc, cpu_cond);
4492
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4493
                    break;
4494
                case 0x15: /* store byte alternate */
4495
#ifndef TARGET_SPARC64
4496
                    if (IS_IMM)
4497
                        goto illegal_insn;
4498
                    if (!supervisor(dc))
4499
                        goto priv_insn;
4500
#endif
4501
                    save_state(dc, cpu_cond);
4502
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4503
                    break;
4504
                case 0x16: /* store halfword alternate */
4505
#ifndef TARGET_SPARC64
4506
                    if (IS_IMM)
4507
                        goto illegal_insn;
4508
                    if (!supervisor(dc))
4509
                        goto priv_insn;
4510
#endif
4511
                    save_state(dc, cpu_cond);
4512
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4513
                    break;
4514
                case 0x17: /* store double word alternate */
4515
#ifndef TARGET_SPARC64
4516
                    if (IS_IMM)
4517
                        goto illegal_insn;
4518
                    if (!supervisor(dc))
4519
                        goto priv_insn;
4520
#endif
4521
                    if (rd & 1)
4522
                        goto illegal_insn;
4523
                    else {
4524
                        save_state(dc, cpu_cond);
4525
                        gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4526
                    }
4527
                    break;
4528
#endif
4529
#ifdef TARGET_SPARC64
4530
                case 0x0e: /* V9 stx */
4531
                    gen_address_mask(dc, cpu_addr);
4532
                    tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4533
                    break;
4534
                case 0x1e: /* V9 stxa */
4535
                    save_state(dc, cpu_cond);
4536
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4537
                    break;
4538
#endif
4539
                default:
4540
                    goto illegal_insn;
4541
                }
4542
            } else if (xop > 0x23 && xop < 0x28) {
4543
                if (gen_trap_ifnofpu(dc, cpu_cond))
4544
                    goto jmp_insn;
4545
                save_state(dc, cpu_cond);
4546
                switch (xop) {
4547
                case 0x24: /* store fpreg */
4548
                    gen_address_mask(dc, cpu_addr);
4549
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4550
                                   offsetof(CPUState, fpr[rd]));
4551
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4552
                    break;
4553
                case 0x25: /* stfsr, V9 stxfsr */
4554
                    gen_address_mask(dc, cpu_addr);
4555
                    tcg_gen_helper_0_0(helper_stfsr);
4556
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4557
                                   offsetof(CPUState, ft0));
4558
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4559
                    break;
4560
                case 0x26:
4561
#ifdef TARGET_SPARC64
4562
                    /* V9 stqf, store quad fpreg */
4563
                    {
4564
                        TCGv r_const;
4565

    
4566
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4567
                        gen_op_load_fpr_QT0(QFPREG(rd));
4568
                        r_const = tcg_const_i32(dc->mem_idx);
4569
                        tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4570
                        tcg_temp_free(r_const);
4571
                    }
4572
                    break;
4573
#else /* !TARGET_SPARC64 */
4574
                    /* stdfq, store floating point queue */
4575
#if defined(CONFIG_USER_ONLY)
4576
                    goto illegal_insn;
4577
#else
4578
                    if (!supervisor(dc))
4579
                        goto priv_insn;
4580
                    if (gen_trap_ifnofpu(dc, cpu_cond))
4581
                        goto jmp_insn;
4582
                    goto nfq_insn;
4583
#endif
4584
#endif
4585
                case 0x27: /* store double fpreg */
4586
                    {
4587
                        TCGv r_const;
4588

    
4589
                        gen_op_load_fpr_DT0(DFPREG(rd));
4590
                        r_const = tcg_const_i32(dc->mem_idx);
4591
                        tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4592
                        tcg_temp_free(r_const);
4593
                    }
4594
                    break;
4595
                default:
4596
                    goto illegal_insn;
4597
                }
4598
            } else if (xop > 0x33 && xop < 0x3f) {
4599
                save_state(dc, cpu_cond);
4600
                switch (xop) {
4601
#ifdef TARGET_SPARC64
4602
                case 0x34: /* V9 stfa */
4603
                    gen_op_load_fpr_FT0(rd);
4604
                    gen_stf_asi(cpu_addr, insn, 4, rd);
4605
                    break;
4606
                case 0x36: /* V9 stqfa */
4607
                    {
4608
                        TCGv r_const;
4609

    
4610
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4611
                        r_const = tcg_const_i32(7);
4612
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4613
                                           r_const);
4614
                        tcg_temp_free(r_const);
4615
                        gen_op_load_fpr_QT0(QFPREG(rd));
4616
                        gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4617
                    }
4618
                    break;
4619
                case 0x37: /* V9 stdfa */
4620
                    gen_op_load_fpr_DT0(DFPREG(rd));
4621
                    gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4622
                    break;
4623
                case 0x3c: /* V9 casa */
4624
                    gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4625
                    gen_movl_TN_reg(rd, cpu_val);
4626
                    break;
4627
                case 0x3e: /* V9 casxa */
4628
                    gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4629
                    gen_movl_TN_reg(rd, cpu_val);
4630
                    break;
4631
#else
4632
                case 0x34: /* stc */
4633
                case 0x35: /* stcsr */
4634
                case 0x36: /* stdcq */
4635
                case 0x37: /* stdc */
4636
                    goto ncp_insn;
4637
#endif
4638
                default:
4639
                    goto illegal_insn;
4640
                }
4641
            }
4642
            else
4643
                goto illegal_insn;
4644
        }
4645
        break;
4646
    }
4647
    /* default case for non jump instructions */
4648
    if (dc->npc == DYNAMIC_PC) {
4649
        dc->pc = DYNAMIC_PC;
4650
        gen_op_next_insn();
4651
    } else if (dc->npc == JUMP_PC) {
4652
        /* we can do a static jump */
4653
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4654
        dc->is_br = 1;
4655
    } else {
4656
        dc->pc = dc->npc;
4657
        dc->npc = dc->npc + 4;
4658
    }
4659
 jmp_insn:
4660
    return;
4661
 illegal_insn:
4662
    {
4663
        TCGv r_const;
4664

    
4665
        save_state(dc, cpu_cond);
4666
        r_const = tcg_const_i32(TT_ILL_INSN);
4667
        tcg_gen_helper_0_1(raise_exception, r_const);
4668
        tcg_temp_free(r_const);
4669
        dc->is_br = 1;
4670
    }
4671
    return;
4672
 unimp_flush:
4673
    {
4674
        TCGv r_const;
4675

    
4676
        save_state(dc, cpu_cond);
4677
        r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4678
        tcg_gen_helper_0_1(raise_exception, r_const);
4679
        tcg_temp_free(r_const);
4680
        dc->is_br = 1;
4681
    }
4682
    return;
4683
#if !defined(CONFIG_USER_ONLY)
4684
 priv_insn:
4685
    {
4686
        TCGv r_const;
4687

    
4688
        save_state(dc, cpu_cond);
4689
        r_const = tcg_const_i32(TT_PRIV_INSN);
4690
        tcg_gen_helper_0_1(raise_exception, r_const);
4691
        tcg_temp_free(r_const);
4692
        dc->is_br = 1;
4693
    }
4694
    return;
4695
#endif
4696
 nfpu_insn:
4697
    save_state(dc, cpu_cond);
4698
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4699
    dc->is_br = 1;
4700
    return;
4701
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4702
 nfq_insn:
4703
    save_state(dc, cpu_cond);
4704
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4705
    dc->is_br = 1;
4706
    return;
4707
#endif
4708
#ifndef TARGET_SPARC64
4709
 ncp_insn:
4710
    {
4711
        TCGv r_const;
4712

    
4713
        save_state(dc, cpu_cond);
4714
        r_const = tcg_const_i32(TT_NCP_INSN);
4715
        tcg_gen_helper_0_1(raise_exception, r_const);
4716
        tcg_temp_free(r_const);
4717
        dc->is_br = 1;
4718
    }
4719
    return;
4720
#endif
4721
}
4722

    
4723
static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4724
                                                  int spc, CPUSPARCState *env)
4725
{
4726
    target_ulong pc_start, last_pc;
4727
    uint16_t *gen_opc_end;
4728
    DisasContext dc1, *dc = &dc1;
4729
    int j, lj = -1;
4730
    int num_insns;
4731
    int max_insns;
4732

    
4733
    memset(dc, 0, sizeof(DisasContext));
4734
    dc->tb = tb;
4735
    pc_start = tb->pc;
4736
    dc->pc = pc_start;
4737
    last_pc = dc->pc;
4738
    dc->npc = (target_ulong) tb->cs_base;
4739
    dc->mem_idx = cpu_mmu_index(env);
4740
    dc->features = env->features;
4741
    if ((dc->features & CPU_FEATURE_FLOAT)) {
4742
        dc->fpu_enabled = cpu_fpu_enabled(env);
4743
#if defined(CONFIG_USER_ONLY)
4744
        dc->features |= CPU_FEATURE_FLOAT128;
4745
#endif
4746
    } else
4747
        dc->fpu_enabled = 0;
4748
#ifdef TARGET_SPARC64
4749
    dc->address_mask_32bit = env->pstate & PS_AM;
4750
#endif
4751
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4752

    
4753
    cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4754
    cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4755
    cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4756

    
4757
    cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4758

    
4759
    // loads and stores
4760
    cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4761
    cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4762

    
4763
    num_insns = 0;
4764
    max_insns = tb->cflags & CF_COUNT_MASK;
4765
    if (max_insns == 0)
4766
        max_insns = CF_COUNT_MASK;
4767
    gen_icount_start();
4768
    do {
4769
        if (env->nb_breakpoints > 0) {
4770
            for(j = 0; j < env->nb_breakpoints; j++) {
4771
                if (env->breakpoints[j] == dc->pc) {
4772
                    if (dc->pc != pc_start)
4773
                        save_state(dc, cpu_cond);
4774
                    tcg_gen_helper_0_0(helper_debug);
4775
                    tcg_gen_exit_tb(0);
4776
                    dc->is_br = 1;
4777
                    goto exit_gen_loop;
4778
                }
4779
            }
4780
        }
4781
        if (spc) {
4782
            if (loglevel > 0)
4783
                fprintf(logfile, "Search PC...\n");
4784
            j = gen_opc_ptr - gen_opc_buf;
4785
            if (lj < j) {
4786
                lj++;
4787
                while (lj < j)
4788
                    gen_opc_instr_start[lj++] = 0;
4789
                gen_opc_pc[lj] = dc->pc;
4790
                gen_opc_npc[lj] = dc->npc;
4791
                gen_opc_instr_start[lj] = 1;
4792
                gen_opc_icount[lj] = num_insns;
4793
            }
4794
        }
4795
        if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4796
            gen_io_start();
4797
        last_pc = dc->pc;
4798
        disas_sparc_insn(dc);
4799
        num_insns++;
4800

    
4801
        if (dc->is_br)
4802
            break;
4803
        /* if the next PC is different, we abort now */
4804
        if (dc->pc != (last_pc + 4))
4805
            break;
4806
        /* if we reach a page boundary, we stop generation so that the
4807
           PC of a TT_TFAULT exception is always in the right page */
4808
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4809
            break;
4810
        /* if single step mode, we generate only one instruction and
4811
           generate an exception */
4812
        if (env->singlestep_enabled) {
4813
            tcg_gen_movi_tl(cpu_pc, dc->pc);
4814
            tcg_gen_exit_tb(0);
4815
            break;
4816
        }
4817
    } while ((gen_opc_ptr < gen_opc_end) &&
4818
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4819
             num_insns < max_insns);
4820

    
4821
 exit_gen_loop:
4822
    tcg_temp_free(cpu_addr);
4823
    tcg_temp_free(cpu_val);
4824
    tcg_temp_free(cpu_dst);
4825
    tcg_temp_free(cpu_tmp64);
4826
    tcg_temp_free(cpu_tmp32);
4827
    tcg_temp_free(cpu_tmp0);
4828
    if (tb->cflags & CF_LAST_IO)
4829
        gen_io_end();
4830
    if (!dc->is_br) {
4831
        if (dc->pc != DYNAMIC_PC &&
4832
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4833
            /* static PC and NPC: we can use direct chaining */
4834
            gen_goto_tb(dc, 0, dc->pc, dc->npc);
4835
        } else {
4836
            if (dc->pc != DYNAMIC_PC)
4837
                tcg_gen_movi_tl(cpu_pc, dc->pc);
4838
            save_npc(dc, cpu_cond);
4839
            tcg_gen_exit_tb(0);
4840
        }
4841
    }
4842
    gen_icount_end(tb, num_insns);
4843
    *gen_opc_ptr = INDEX_op_end;
4844
    if (spc) {
4845
        j = gen_opc_ptr - gen_opc_buf;
4846
        lj++;
4847
        while (lj <= j)
4848
            gen_opc_instr_start[lj++] = 0;
4849
#if 0
4850
        if (loglevel > 0) {
4851
            page_dump(logfile);
4852
        }
4853
#endif
4854
        gen_opc_jump_pc[0] = dc->jump_pc[0];
4855
        gen_opc_jump_pc[1] = dc->jump_pc[1];
4856
    } else {
4857
        tb->size = last_pc + 4 - pc_start;
4858
        tb->icount = num_insns;
4859
    }
4860
#ifdef DEBUG_DISAS
4861
    if (loglevel & CPU_LOG_TB_IN_ASM) {
4862
        fprintf(logfile, "--------------\n");
4863
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4864
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4865
        fprintf(logfile, "\n");
4866
    }
4867
#endif
4868
}
4869

    
4870
void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4871
{
4872
    gen_intermediate_code_internal(tb, 0, env);
4873
}
4874

    
4875
void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4876
{
4877
    gen_intermediate_code_internal(tb, 1, env);
4878
}
4879

    
4880
void gen_intermediate_code_init(CPUSPARCState *env)
4881
{
4882
    unsigned int i;
4883
    static int inited;
4884
    static const char * const gregnames[8] = {
4885
        NULL, // g0 not used
4886
        "g1",
4887
        "g2",
4888
        "g3",
4889
        "g4",
4890
        "g5",
4891
        "g6",
4892
        "g7",
4893
    };
4894

    
4895
    /* init various static tables */
4896
    if (!inited) {
4897
        inited = 1;
4898

    
4899
        cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4900
        cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4901
                                         offsetof(CPUState, regwptr),
4902
                                         "regwptr");
4903
#ifdef TARGET_SPARC64
4904
        cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4905
                                     TCG_AREG0, offsetof(CPU