root / hw / display / cirrus_vga.c @ db895a1e
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1 | e6e5ad80 | bellard | /*
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2 | aeb3c85f | bellard | * QEMU Cirrus CLGD 54xx VGA Emulator.
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3 | 5fafdf24 | ths | *
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4 | e6e5ad80 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | aeb3c85f | bellard | * Copyright (c) 2004 Makoto Suzuki (suzu)
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6 | 5fafdf24 | ths | *
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7 | e6e5ad80 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | e6e5ad80 | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | e6e5ad80 | bellard | * in the Software without restriction, including without limitation the rights
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10 | e6e5ad80 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | e6e5ad80 | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | e6e5ad80 | bellard | * furnished to do so, subject to the following conditions:
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13 | e6e5ad80 | bellard | *
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14 | e6e5ad80 | bellard | * The above copyright notice and this permission notice shall be included in
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15 | e6e5ad80 | bellard | * all copies or substantial portions of the Software.
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16 | e6e5ad80 | bellard | *
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17 | e6e5ad80 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | e6e5ad80 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | e6e5ad80 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | e6e5ad80 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | e6e5ad80 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | e6e5ad80 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | e6e5ad80 | bellard | * THE SOFTWARE.
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24 | e6e5ad80 | bellard | */
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25 | aeb3c85f | bellard | /*
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26 | aeb3c85f | bellard | * Reference: Finn Thogersons' VGADOC4b
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27 | aeb3c85f | bellard | * available at http://home.worldonline.dk/~finth/
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28 | aeb3c85f | bellard | */
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29 | 83c9f4ca | Paolo Bonzini | #include "hw/hw.h" |
30 | 83c9f4ca | Paolo Bonzini | #include "hw/pci/pci.h" |
31 | 28ecbaee | Paolo Bonzini | #include "ui/console.h" |
32 | 47b43a1f | Paolo Bonzini | #include "vga_int.h" |
33 | 83c9f4ca | Paolo Bonzini | #include "hw/loader.h" |
34 | e6e5ad80 | bellard | |
35 | a5082316 | bellard | /*
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36 | a5082316 | bellard | * TODO:
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37 | ad81218e | bellard | * - destination write mask support not complete (bits 5..7)
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38 | a5082316 | bellard | * - optimize linear mappings
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39 | a5082316 | bellard | * - optimize bitblt functions
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40 | a5082316 | bellard | */
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41 | a5082316 | bellard | |
42 | e36f36e1 | bellard | //#define DEBUG_CIRRUS
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43 | a21ae81d | bellard | //#define DEBUG_BITBLT
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44 | e36f36e1 | bellard | |
45 | e6e5ad80 | bellard | /***************************************
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46 | e6e5ad80 | bellard | *
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47 | e6e5ad80 | bellard | * definitions
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48 | e6e5ad80 | bellard | *
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49 | e6e5ad80 | bellard | ***************************************/
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50 | e6e5ad80 | bellard | |
51 | e6e5ad80 | bellard | // ID
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52 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5422 (0x23<<2) |
53 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5426 (0x24<<2) |
54 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5424 (0x25<<2) |
55 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5428 (0x26<<2) |
56 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5430 (0x28<<2) |
57 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5434 (0x2A<<2) |
58 | a21ae81d | bellard | #define CIRRUS_ID_CLGD5436 (0x2B<<2) |
59 | e6e5ad80 | bellard | #define CIRRUS_ID_CLGD5446 (0x2E<<2) |
60 | e6e5ad80 | bellard | |
61 | e6e5ad80 | bellard | // sequencer 0x07
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62 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_VGA 0x00 |
63 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_SVGA 0x01 |
64 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_MASK 0x0e |
65 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_8 0x00 |
66 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02 |
67 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_24 0x04 |
68 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_16 0x06 |
69 | e6e5ad80 | bellard | #define CIRRUS_SR7_BPP_32 0x08 |
70 | e6e5ad80 | bellard | #define CIRRUS_SR7_ISAADDR_MASK 0xe0 |
71 | e6e5ad80 | bellard | |
72 | e6e5ad80 | bellard | // sequencer 0x0f
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73 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_512k 0x08 |
74 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_1M 0x10 |
75 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZE_2M 0x18 |
76 | e6e5ad80 | bellard | #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled. |
77 | e6e5ad80 | bellard | |
78 | e6e5ad80 | bellard | // sequencer 0x12
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79 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_SHOW 0x01 |
80 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_HIDDENPEL 0x02 |
81 | e6e5ad80 | bellard | #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear |
82 | e6e5ad80 | bellard | |
83 | e6e5ad80 | bellard | // sequencer 0x17
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84 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBFAST 0x10 |
85 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_PCI 0x20 |
86 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_VLBSLOW 0x30 |
87 | e6e5ad80 | bellard | #define CIRRUS_BUSTYPE_ISA 0x38 |
88 | e6e5ad80 | bellard | #define CIRRUS_MMIO_ENABLE 0x04 |
89 | e6e5ad80 | bellard | #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared. |
90 | e6e5ad80 | bellard | #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80 |
91 | e6e5ad80 | bellard | |
92 | e6e5ad80 | bellard | // control 0x0b
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93 | e6e5ad80 | bellard | #define CIRRUS_BANKING_DUAL 0x01 |
94 | e6e5ad80 | bellard | #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k |
95 | e6e5ad80 | bellard | |
96 | e6e5ad80 | bellard | // control 0x30
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97 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_BACKWARDS 0x01 |
98 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSDEST 0x02 |
99 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_MEMSYSSRC 0x04 |
100 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08 |
101 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PATTERNCOPY 0x40 |
102 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_COLOREXPAND 0x80 |
103 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30 |
104 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00 |
105 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10 |
106 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20 |
107 | e6e5ad80 | bellard | #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30 |
108 | e6e5ad80 | bellard | |
109 | e6e5ad80 | bellard | // control 0x31
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110 | e6e5ad80 | bellard | #define CIRRUS_BLT_BUSY 0x01 |
111 | e6e5ad80 | bellard | #define CIRRUS_BLT_START 0x02 |
112 | e6e5ad80 | bellard | #define CIRRUS_BLT_RESET 0x04 |
113 | e6e5ad80 | bellard | #define CIRRUS_BLT_FIFOUSED 0x10 |
114 | a5082316 | bellard | #define CIRRUS_BLT_AUTOSTART 0x80 |
115 | e6e5ad80 | bellard | |
116 | e6e5ad80 | bellard | // control 0x32
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117 | e6e5ad80 | bellard | #define CIRRUS_ROP_0 0x00 |
118 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_DST 0x05 |
119 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOP 0x06 |
120 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_AND_NOTDST 0x09 |
121 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTDST 0x0b |
122 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC 0x0d |
123 | e6e5ad80 | bellard | #define CIRRUS_ROP_1 0x0e |
124 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_DST 0x50 |
125 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_XOR_DST 0x59 |
126 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_DST 0x6d |
127 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90 |
128 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95 |
129 | e6e5ad80 | bellard | #define CIRRUS_ROP_SRC_OR_NOTDST 0xad |
130 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC 0xd0 |
131 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6 |
132 | e6e5ad80 | bellard | #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda |
133 | e6e5ad80 | bellard | |
134 | a5082316 | bellard | #define CIRRUS_ROP_NOP_INDEX 2 |
135 | a5082316 | bellard | #define CIRRUS_ROP_SRC_INDEX 5 |
136 | a5082316 | bellard | |
137 | a21ae81d | bellard | // control 0x33
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138 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04 |
139 | 4c8732d7 | bellard | #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02 |
140 | a5082316 | bellard | #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01 |
141 | a21ae81d | bellard | |
142 | e6e5ad80 | bellard | // memory-mapped IO
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143 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword |
144 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword |
145 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWIDTH 0x08 // word |
146 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word |
147 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word |
148 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word |
149 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword |
150 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword |
151 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte |
152 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODE 0x18 // byte |
153 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTROP 0x1a // byte |
154 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte |
155 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word? |
156 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word? |
157 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word |
158 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word |
159 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word |
160 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word |
161 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte |
162 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte |
163 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte |
164 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte |
165 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word |
166 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word |
167 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word |
168 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word |
169 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte |
170 | e6e5ad80 | bellard | #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
171 | e6e5ad80 | bellard | #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
172 | e6e5ad80 | bellard | |
173 | a21ae81d | bellard | #define CIRRUS_PNPMMIO_SIZE 0x1000 |
174 | e6e5ad80 | bellard | |
175 | b2eb849d | aurel32 | #define BLTUNSAFE(s) \
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176 | b2eb849d | aurel32 | ( \ |
177 | b2eb849d | aurel32 | ( /* check dst is within bounds */ \
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178 | b2b183c2 | aliguori | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \ |
179 | b2eb849d | aurel32 | + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \ |
180 | 4e12cd94 | Avi Kivity | (s)->vga.vram_size \ |
181 | b2eb849d | aurel32 | ) || \ |
182 | b2eb849d | aurel32 | ( /* check src is within bounds */ \
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183 | b2b183c2 | aliguori | (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \ |
184 | b2eb849d | aurel32 | + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \ |
185 | 4e12cd94 | Avi Kivity | (s)->vga.vram_size \ |
186 | b2eb849d | aurel32 | ) \ |
187 | b2eb849d | aurel32 | ) |
188 | b2eb849d | aurel32 | |
189 | a5082316 | bellard | struct CirrusVGAState;
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190 | a5082316 | bellard | typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s, |
191 | a5082316 | bellard | uint8_t * dst, const uint8_t * src,
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192 | e6e5ad80 | bellard | int dstpitch, int srcpitch, |
193 | e6e5ad80 | bellard | int bltwidth, int bltheight); |
194 | a5082316 | bellard | typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, |
195 | a5082316 | bellard | uint8_t *dst, int dst_pitch, int width, int height); |
196 | e6e5ad80 | bellard | |
197 | e6e5ad80 | bellard | typedef struct CirrusVGAState { |
198 | 4e12cd94 | Avi Kivity | VGACommonState vga; |
199 | e6e5ad80 | bellard | |
200 | c75e6d8e | Julien Grall | MemoryRegion cirrus_vga_io; |
201 | b1950430 | Avi Kivity | MemoryRegion cirrus_linear_io; |
202 | b1950430 | Avi Kivity | MemoryRegion cirrus_linear_bitblt_io; |
203 | b1950430 | Avi Kivity | MemoryRegion cirrus_mmio_io; |
204 | b1950430 | Avi Kivity | MemoryRegion pci_bar; |
205 | b1950430 | Avi Kivity | bool linear_vram; /* vga.vram mapped over cirrus_linear_io */ |
206 | b1950430 | Avi Kivity | MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
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207 | b1950430 | Avi Kivity | MemoryRegion low_mem; /* always mapped, overridden by: */
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208 | 7969d9ed | Avi Kivity | MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */ |
209 | e6e5ad80 | bellard | uint32_t cirrus_addr_mask; |
210 | 78e127ef | bellard | uint32_t linear_mmio_mask; |
211 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr0; |
212 | e6e5ad80 | bellard | uint8_t cirrus_shadow_gr1; |
213 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_lockindex; |
214 | e6e5ad80 | bellard | uint8_t cirrus_hidden_dac_data; |
215 | e6e5ad80 | bellard | uint32_t cirrus_bank_base[2];
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216 | e6e5ad80 | bellard | uint32_t cirrus_bank_limit[2];
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217 | e6e5ad80 | bellard | uint8_t cirrus_hidden_palette[48];
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218 | a5082316 | bellard | uint32_t hw_cursor_x; |
219 | a5082316 | bellard | uint32_t hw_cursor_y; |
220 | e6e5ad80 | bellard | int cirrus_blt_pixelwidth;
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221 | e6e5ad80 | bellard | int cirrus_blt_width;
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222 | e6e5ad80 | bellard | int cirrus_blt_height;
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223 | e6e5ad80 | bellard | int cirrus_blt_dstpitch;
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224 | e6e5ad80 | bellard | int cirrus_blt_srcpitch;
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225 | a5082316 | bellard | uint32_t cirrus_blt_fgcol; |
226 | a5082316 | bellard | uint32_t cirrus_blt_bgcol; |
227 | e6e5ad80 | bellard | uint32_t cirrus_blt_dstaddr; |
228 | e6e5ad80 | bellard | uint32_t cirrus_blt_srcaddr; |
229 | e6e5ad80 | bellard | uint8_t cirrus_blt_mode; |
230 | a5082316 | bellard | uint8_t cirrus_blt_modeext; |
231 | e6e5ad80 | bellard | cirrus_bitblt_rop_t cirrus_rop; |
232 | a5082316 | bellard | #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */ |
233 | e6e5ad80 | bellard | uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE]; |
234 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr; |
235 | e6e5ad80 | bellard | uint8_t *cirrus_srcptr_end; |
236 | e6e5ad80 | bellard | uint32_t cirrus_srccounter; |
237 | a5082316 | bellard | /* hwcursor display state */
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238 | a5082316 | bellard | int last_hw_cursor_size;
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239 | a5082316 | bellard | int last_hw_cursor_x;
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240 | a5082316 | bellard | int last_hw_cursor_y;
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241 | a5082316 | bellard | int last_hw_cursor_y_start;
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242 | a5082316 | bellard | int last_hw_cursor_y_end;
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243 | 78e127ef | bellard | int real_vram_size; /* XXX: suppress that */ |
244 | 4abc796d | blueswir1 | int device_id;
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245 | 4abc796d | blueswir1 | int bustype;
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246 | e6e5ad80 | bellard | } CirrusVGAState; |
247 | e6e5ad80 | bellard | |
248 | e6e5ad80 | bellard | typedef struct PCICirrusVGAState { |
249 | e6e5ad80 | bellard | PCIDevice dev; |
250 | e6e5ad80 | bellard | CirrusVGAState cirrus_vga; |
251 | e6e5ad80 | bellard | } PCICirrusVGAState; |
252 | e6e5ad80 | bellard | |
253 | 6d4c2f17 | Andreas Färber | #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga" |
254 | 6d4c2f17 | Andreas Färber | #define ISA_CIRRUS_VGA(obj) \
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255 | 6d4c2f17 | Andreas Färber | OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA) |
256 | 6d4c2f17 | Andreas Färber | |
257 | 3d402831 | Blue Swirl | typedef struct ISACirrusVGAState { |
258 | 6d4c2f17 | Andreas Färber | ISADevice parent_obj; |
259 | 6d4c2f17 | Andreas Färber | |
260 | 3d402831 | Blue Swirl | CirrusVGAState cirrus_vga; |
261 | 3d402831 | Blue Swirl | } ISACirrusVGAState; |
262 | 3d402831 | Blue Swirl | |
263 | a5082316 | bellard | static uint8_t rop_to_index[256]; |
264 | 3b46e624 | ths | |
265 | e6e5ad80 | bellard | /***************************************
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266 | e6e5ad80 | bellard | *
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267 | e6e5ad80 | bellard | * prototypes.
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268 | e6e5ad80 | bellard | *
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269 | e6e5ad80 | bellard | ***************************************/
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270 | e6e5ad80 | bellard | |
271 | e6e5ad80 | bellard | |
272 | 8926b517 | bellard | static void cirrus_bitblt_reset(CirrusVGAState *s); |
273 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s); |
274 | e6e5ad80 | bellard | |
275 | e6e5ad80 | bellard | /***************************************
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276 | e6e5ad80 | bellard | *
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277 | e6e5ad80 | bellard | * raster operations
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278 | e6e5ad80 | bellard | *
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279 | e6e5ad80 | bellard | ***************************************/
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280 | e6e5ad80 | bellard | |
281 | a5082316 | bellard | static void cirrus_bitblt_rop_nop(CirrusVGAState *s, |
282 | a5082316 | bellard | uint8_t *dst,const uint8_t *src,
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283 | a5082316 | bellard | int dstpitch,int srcpitch, |
284 | a5082316 | bellard | int bltwidth,int bltheight) |
285 | a5082316 | bellard | { |
286 | e6e5ad80 | bellard | } |
287 | e6e5ad80 | bellard | |
288 | a5082316 | bellard | static void cirrus_bitblt_fill_nop(CirrusVGAState *s, |
289 | a5082316 | bellard | uint8_t *dst, |
290 | a5082316 | bellard | int dstpitch, int bltwidth,int bltheight) |
291 | e6e5ad80 | bellard | { |
292 | a5082316 | bellard | } |
293 | e6e5ad80 | bellard | |
294 | a5082316 | bellard | #define ROP_NAME 0 |
295 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) 0 |
296 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
297 | e6e5ad80 | bellard | |
298 | a5082316 | bellard | #define ROP_NAME src_and_dst
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299 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) & (d)
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300 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
301 | e6e5ad80 | bellard | |
302 | a5082316 | bellard | #define ROP_NAME src_and_notdst
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303 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) & (~(d))
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304 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
305 | e6e5ad80 | bellard | |
306 | a5082316 | bellard | #define ROP_NAME notdst
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307 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) ~(d)
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308 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
309 | e6e5ad80 | bellard | |
310 | a5082316 | bellard | #define ROP_NAME src
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311 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) s
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312 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
313 | e6e5ad80 | bellard | |
314 | a5082316 | bellard | #define ROP_NAME 1 |
315 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) ~0 |
316 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
317 | a5082316 | bellard | |
318 | a5082316 | bellard | #define ROP_NAME notsrc_and_dst
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319 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) & (d)
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320 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
321 | a5082316 | bellard | |
322 | a5082316 | bellard | #define ROP_NAME src_xor_dst
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323 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) ^ (d)
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324 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
325 | a5082316 | bellard | |
326 | a5082316 | bellard | #define ROP_NAME src_or_dst
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327 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) | (d)
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328 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
329 | a5082316 | bellard | |
330 | a5082316 | bellard | #define ROP_NAME notsrc_or_notdst
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331 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) | (~(d))
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332 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
333 | a5082316 | bellard | |
334 | a5082316 | bellard | #define ROP_NAME src_notxor_dst
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335 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) ~((s) ^ (d))
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336 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
337 | e6e5ad80 | bellard | |
338 | a5082316 | bellard | #define ROP_NAME src_or_notdst
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339 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (s) | (~(d))
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340 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
341 | a5082316 | bellard | |
342 | a5082316 | bellard | #define ROP_NAME notsrc
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343 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s))
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344 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
345 | a5082316 | bellard | |
346 | a5082316 | bellard | #define ROP_NAME notsrc_or_dst
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347 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) | (d)
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348 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
349 | a5082316 | bellard | |
350 | a5082316 | bellard | #define ROP_NAME notsrc_and_notdst
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351 | 8c78881f | Blue Swirl | #define ROP_FN(d, s) (~(s)) & (~(d))
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352 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_rop.h" |
353 | a5082316 | bellard | |
354 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = { |
355 | a5082316 | bellard | cirrus_bitblt_rop_fwd_0, |
356 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_dst, |
357 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
358 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_and_notdst, |
359 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notdst, |
360 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src, |
361 | a5082316 | bellard | cirrus_bitblt_rop_fwd_1, |
362 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_dst, |
363 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_xor_dst, |
364 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_dst, |
365 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_notdst, |
366 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_notxor_dst, |
367 | a5082316 | bellard | cirrus_bitblt_rop_fwd_src_or_notdst, |
368 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc, |
369 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_or_dst, |
370 | a5082316 | bellard | cirrus_bitblt_rop_fwd_notsrc_and_notdst, |
371 | a5082316 | bellard | }; |
372 | a5082316 | bellard | |
373 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = { |
374 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_0, |
375 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_dst, |
376 | a5082316 | bellard | cirrus_bitblt_rop_nop, |
377 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_and_notdst, |
378 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notdst, |
379 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src, |
380 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_1, |
381 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_dst, |
382 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_xor_dst, |
383 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_dst, |
384 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_notdst, |
385 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_notxor_dst, |
386 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_src_or_notdst, |
387 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc, |
388 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_or_dst, |
389 | a5082316 | bellard | cirrus_bitblt_rop_bkwd_notsrc_and_notdst, |
390 | a5082316 | bellard | }; |
391 | 96cf2df8 | ths | |
392 | 96cf2df8 | ths | #define TRANSP_ROP(name) {\
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393 | 96cf2df8 | ths | name ## _8,\ |
394 | 96cf2df8 | ths | name ## _16,\ |
395 | 96cf2df8 | ths | } |
396 | 96cf2df8 | ths | #define TRANSP_NOP(func) {\
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397 | 96cf2df8 | ths | func,\ |
398 | 96cf2df8 | ths | func,\ |
399 | 96cf2df8 | ths | } |
400 | 96cf2df8 | ths | |
401 | 96cf2df8 | ths | static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = { |
402 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0), |
403 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst), |
404 | 96cf2df8 | ths | TRANSP_NOP(cirrus_bitblt_rop_nop), |
405 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst), |
406 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst), |
407 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src), |
408 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1), |
409 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst), |
410 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst), |
411 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst), |
412 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst), |
413 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst), |
414 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst), |
415 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc), |
416 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst), |
417 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst), |
418 | 96cf2df8 | ths | }; |
419 | 96cf2df8 | ths | |
420 | 96cf2df8 | ths | static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = { |
421 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0), |
422 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst), |
423 | 96cf2df8 | ths | TRANSP_NOP(cirrus_bitblt_rop_nop), |
424 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst), |
425 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst), |
426 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src), |
427 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1), |
428 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst), |
429 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst), |
430 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst), |
431 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst), |
432 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst), |
433 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst), |
434 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc), |
435 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst), |
436 | 96cf2df8 | ths | TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst), |
437 | 96cf2df8 | ths | }; |
438 | 96cf2df8 | ths | |
439 | a5082316 | bellard | #define ROP2(name) {\
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440 | a5082316 | bellard | name ## _8,\ |
441 | a5082316 | bellard | name ## _16,\ |
442 | a5082316 | bellard | name ## _24,\ |
443 | a5082316 | bellard | name ## _32,\ |
444 | a5082316 | bellard | } |
445 | a5082316 | bellard | |
446 | a5082316 | bellard | #define ROP_NOP2(func) {\
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447 | a5082316 | bellard | func,\ |
448 | a5082316 | bellard | func,\ |
449 | a5082316 | bellard | func,\ |
450 | a5082316 | bellard | func,\ |
451 | a5082316 | bellard | } |
452 | a5082316 | bellard | |
453 | e69390ce | bellard | static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = { |
454 | e69390ce | bellard | ROP2(cirrus_patternfill_0), |
455 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_dst), |
456 | e69390ce | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
457 | e69390ce | bellard | ROP2(cirrus_patternfill_src_and_notdst), |
458 | e69390ce | bellard | ROP2(cirrus_patternfill_notdst), |
459 | e69390ce | bellard | ROP2(cirrus_patternfill_src), |
460 | e69390ce | bellard | ROP2(cirrus_patternfill_1), |
461 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_dst), |
462 | e69390ce | bellard | ROP2(cirrus_patternfill_src_xor_dst), |
463 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_dst), |
464 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_notdst), |
465 | e69390ce | bellard | ROP2(cirrus_patternfill_src_notxor_dst), |
466 | e69390ce | bellard | ROP2(cirrus_patternfill_src_or_notdst), |
467 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc), |
468 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_or_dst), |
469 | e69390ce | bellard | ROP2(cirrus_patternfill_notsrc_and_notdst), |
470 | e69390ce | bellard | }; |
471 | e69390ce | bellard | |
472 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = { |
473 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_0), |
474 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_dst), |
475 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
476 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_and_notdst), |
477 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notdst), |
478 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src), |
479 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_1), |
480 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_dst), |
481 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_xor_dst), |
482 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_dst), |
483 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_notdst), |
484 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_notxor_dst), |
485 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_src_or_notdst), |
486 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc), |
487 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_or_dst), |
488 | a5082316 | bellard | ROP2(cirrus_colorexpand_transp_notsrc_and_notdst), |
489 | a5082316 | bellard | }; |
490 | a5082316 | bellard | |
491 | a5082316 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = { |
492 | a5082316 | bellard | ROP2(cirrus_colorexpand_0), |
493 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_dst), |
494 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
495 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_and_notdst), |
496 | a5082316 | bellard | ROP2(cirrus_colorexpand_notdst), |
497 | a5082316 | bellard | ROP2(cirrus_colorexpand_src), |
498 | a5082316 | bellard | ROP2(cirrus_colorexpand_1), |
499 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_dst), |
500 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_xor_dst), |
501 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_dst), |
502 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_notdst), |
503 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_notxor_dst), |
504 | a5082316 | bellard | ROP2(cirrus_colorexpand_src_or_notdst), |
505 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc), |
506 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_or_dst), |
507 | a5082316 | bellard | ROP2(cirrus_colorexpand_notsrc_and_notdst), |
508 | a5082316 | bellard | }; |
509 | a5082316 | bellard | |
510 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = { |
511 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_0), |
512 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_dst), |
513 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
514 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst), |
515 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notdst), |
516 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src), |
517 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_1), |
518 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst), |
519 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst), |
520 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_dst), |
521 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst), |
522 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst), |
523 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst), |
524 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc), |
525 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst), |
526 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst), |
527 | b30d4608 | bellard | }; |
528 | b30d4608 | bellard | |
529 | b30d4608 | bellard | static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = { |
530 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_0), |
531 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_dst), |
532 | b30d4608 | bellard | ROP_NOP2(cirrus_bitblt_rop_nop), |
533 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_and_notdst), |
534 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notdst), |
535 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src), |
536 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_1), |
537 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_dst), |
538 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_xor_dst), |
539 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_dst), |
540 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst), |
541 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_notxor_dst), |
542 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_src_or_notdst), |
543 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc), |
544 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_or_dst), |
545 | b30d4608 | bellard | ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst), |
546 | b30d4608 | bellard | }; |
547 | b30d4608 | bellard | |
548 | a5082316 | bellard | static const cirrus_fill_t cirrus_fill[16][4] = { |
549 | a5082316 | bellard | ROP2(cirrus_fill_0), |
550 | a5082316 | bellard | ROP2(cirrus_fill_src_and_dst), |
551 | a5082316 | bellard | ROP_NOP2(cirrus_bitblt_fill_nop), |
552 | a5082316 | bellard | ROP2(cirrus_fill_src_and_notdst), |
553 | a5082316 | bellard | ROP2(cirrus_fill_notdst), |
554 | a5082316 | bellard | ROP2(cirrus_fill_src), |
555 | a5082316 | bellard | ROP2(cirrus_fill_1), |
556 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_dst), |
557 | a5082316 | bellard | ROP2(cirrus_fill_src_xor_dst), |
558 | a5082316 | bellard | ROP2(cirrus_fill_src_or_dst), |
559 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_notdst), |
560 | a5082316 | bellard | ROP2(cirrus_fill_src_notxor_dst), |
561 | a5082316 | bellard | ROP2(cirrus_fill_src_or_notdst), |
562 | a5082316 | bellard | ROP2(cirrus_fill_notsrc), |
563 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_or_dst), |
564 | a5082316 | bellard | ROP2(cirrus_fill_notsrc_and_notdst), |
565 | a5082316 | bellard | }; |
566 | a5082316 | bellard | |
567 | a5082316 | bellard | static inline void cirrus_bitblt_fgcol(CirrusVGAState *s) |
568 | e6e5ad80 | bellard | { |
569 | a5082316 | bellard | unsigned int color; |
570 | a5082316 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
571 | a5082316 | bellard | case 1: |
572 | a5082316 | bellard | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1; |
573 | a5082316 | bellard | break;
|
574 | a5082316 | bellard | case 2: |
575 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8); |
576 | a5082316 | bellard | s->cirrus_blt_fgcol = le16_to_cpu(color); |
577 | a5082316 | bellard | break;
|
578 | a5082316 | bellard | case 3: |
579 | 5fafdf24 | ths | s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 | |
580 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16); |
581 | a5082316 | bellard | break;
|
582 | a5082316 | bellard | default:
|
583 | a5082316 | bellard | case 4: |
584 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) | |
585 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24); |
586 | a5082316 | bellard | s->cirrus_blt_fgcol = le32_to_cpu(color); |
587 | a5082316 | bellard | break;
|
588 | e6e5ad80 | bellard | } |
589 | e6e5ad80 | bellard | } |
590 | e6e5ad80 | bellard | |
591 | a5082316 | bellard | static inline void cirrus_bitblt_bgcol(CirrusVGAState *s) |
592 | e6e5ad80 | bellard | { |
593 | a5082316 | bellard | unsigned int color; |
594 | e6e5ad80 | bellard | switch (s->cirrus_blt_pixelwidth) {
|
595 | e6e5ad80 | bellard | case 1: |
596 | a5082316 | bellard | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0; |
597 | a5082316 | bellard | break;
|
598 | e6e5ad80 | bellard | case 2: |
599 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8); |
600 | a5082316 | bellard | s->cirrus_blt_bgcol = le16_to_cpu(color); |
601 | a5082316 | bellard | break;
|
602 | e6e5ad80 | bellard | case 3: |
603 | 5fafdf24 | ths | s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 | |
604 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16); |
605 | a5082316 | bellard | break;
|
606 | e6e5ad80 | bellard | default:
|
607 | a5082316 | bellard | case 4: |
608 | 4e12cd94 | Avi Kivity | color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) | |
609 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24); |
610 | a5082316 | bellard | s->cirrus_blt_bgcol = le32_to_cpu(color); |
611 | a5082316 | bellard | break;
|
612 | e6e5ad80 | bellard | } |
613 | e6e5ad80 | bellard | } |
614 | e6e5ad80 | bellard | |
615 | e6e5ad80 | bellard | static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, |
616 | e6e5ad80 | bellard | int off_pitch, int bytesperline, |
617 | e6e5ad80 | bellard | int lines)
|
618 | e6e5ad80 | bellard | { |
619 | e6e5ad80 | bellard | int y;
|
620 | e6e5ad80 | bellard | int off_cur;
|
621 | e6e5ad80 | bellard | int off_cur_end;
|
622 | e6e5ad80 | bellard | |
623 | e6e5ad80 | bellard | for (y = 0; y < lines; y++) { |
624 | e6e5ad80 | bellard | off_cur = off_begin; |
625 | b2eb849d | aurel32 | off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; |
626 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur); |
627 | e6e5ad80 | bellard | off_begin += off_pitch; |
628 | e6e5ad80 | bellard | } |
629 | e6e5ad80 | bellard | } |
630 | e6e5ad80 | bellard | |
631 | e6e5ad80 | bellard | static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s, |
632 | e6e5ad80 | bellard | const uint8_t * src)
|
633 | e6e5ad80 | bellard | { |
634 | e6e5ad80 | bellard | uint8_t *dst; |
635 | e6e5ad80 | bellard | |
636 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask); |
637 | b2eb849d | aurel32 | |
638 | b2eb849d | aurel32 | if (BLTUNSAFE(s))
|
639 | b2eb849d | aurel32 | return 0; |
640 | b2eb849d | aurel32 | |
641 | e69390ce | bellard | (*s->cirrus_rop) (s, dst, src, |
642 | 5fafdf24 | ths | s->cirrus_blt_dstpitch, 0,
|
643 | e69390ce | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
644 | e6e5ad80 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
645 | e69390ce | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
646 | e69390ce | bellard | s->cirrus_blt_height); |
647 | e6e5ad80 | bellard | return 1; |
648 | e6e5ad80 | bellard | } |
649 | e6e5ad80 | bellard | |
650 | a21ae81d | bellard | /* fill */
|
651 | a21ae81d | bellard | |
652 | a5082316 | bellard | static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop) |
653 | a21ae81d | bellard | { |
654 | a5082316 | bellard | cirrus_fill_t rop_func; |
655 | a21ae81d | bellard | |
656 | b2eb849d | aurel32 | if (BLTUNSAFE(s))
|
657 | b2eb849d | aurel32 | return 0; |
658 | a5082316 | bellard | rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
659 | 4e12cd94 | Avi Kivity | rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
660 | a5082316 | bellard | s->cirrus_blt_dstpitch, |
661 | a5082316 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
662 | a21ae81d | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
663 | a21ae81d | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
664 | a21ae81d | bellard | s->cirrus_blt_height); |
665 | a21ae81d | bellard | cirrus_bitblt_reset(s); |
666 | a21ae81d | bellard | return 1; |
667 | a21ae81d | bellard | } |
668 | a21ae81d | bellard | |
669 | e6e5ad80 | bellard | /***************************************
|
670 | e6e5ad80 | bellard | *
|
671 | e6e5ad80 | bellard | * bitblt (video-to-video)
|
672 | e6e5ad80 | bellard | *
|
673 | e6e5ad80 | bellard | ***************************************/
|
674 | e6e5ad80 | bellard | |
675 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s) |
676 | e6e5ad80 | bellard | { |
677 | e6e5ad80 | bellard | return cirrus_bitblt_common_patterncopy(s,
|
678 | 4e12cd94 | Avi Kivity | s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
|
679 | b2eb849d | aurel32 | s->cirrus_addr_mask)); |
680 | e6e5ad80 | bellard | } |
681 | e6e5ad80 | bellard | |
682 | 24236869 | bellard | static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h) |
683 | e6e5ad80 | bellard | { |
684 | 78935c4a | Aurelien Jarno | int sx = 0, sy = 0; |
685 | 78935c4a | Aurelien Jarno | int dx = 0, dy = 0; |
686 | 78935c4a | Aurelien Jarno | int depth = 0; |
687 | 24236869 | bellard | int notify = 0; |
688 | 24236869 | bellard | |
689 | 92d675d1 | Aurelien Jarno | /* make sure to only copy if it's a plain copy ROP */
|
690 | 92d675d1 | Aurelien Jarno | if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
|
691 | 92d675d1 | Aurelien Jarno | *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) { |
692 | 24236869 | bellard | |
693 | 92d675d1 | Aurelien Jarno | int width, height;
|
694 | 92d675d1 | Aurelien Jarno | |
695 | 92d675d1 | Aurelien Jarno | depth = s->vga.get_bpp(&s->vga) / 8;
|
696 | 92d675d1 | Aurelien Jarno | s->vga.get_resolution(&s->vga, &width, &height); |
697 | 92d675d1 | Aurelien Jarno | |
698 | 92d675d1 | Aurelien Jarno | /* extra x, y */
|
699 | 92d675d1 | Aurelien Jarno | sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth; |
700 | 92d675d1 | Aurelien Jarno | sy = (src / ABS(s->cirrus_blt_srcpitch)); |
701 | 92d675d1 | Aurelien Jarno | dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth; |
702 | 92d675d1 | Aurelien Jarno | dy = (dst / ABS(s->cirrus_blt_dstpitch)); |
703 | 24236869 | bellard | |
704 | 92d675d1 | Aurelien Jarno | /* normalize width */
|
705 | 92d675d1 | Aurelien Jarno | w /= depth; |
706 | 24236869 | bellard | |
707 | 92d675d1 | Aurelien Jarno | /* if we're doing a backward copy, we have to adjust
|
708 | 92d675d1 | Aurelien Jarno | our x/y to be the upper left corner (instead of the lower
|
709 | 92d675d1 | Aurelien Jarno | right corner) */
|
710 | 92d675d1 | Aurelien Jarno | if (s->cirrus_blt_dstpitch < 0) { |
711 | 92d675d1 | Aurelien Jarno | sx -= (s->cirrus_blt_width / depth) - 1;
|
712 | 92d675d1 | Aurelien Jarno | dx -= (s->cirrus_blt_width / depth) - 1;
|
713 | 92d675d1 | Aurelien Jarno | sy -= s->cirrus_blt_height - 1;
|
714 | 92d675d1 | Aurelien Jarno | dy -= s->cirrus_blt_height - 1;
|
715 | 92d675d1 | Aurelien Jarno | } |
716 | 92d675d1 | Aurelien Jarno | |
717 | 92d675d1 | Aurelien Jarno | /* are we in the visible portion of memory? */
|
718 | 92d675d1 | Aurelien Jarno | if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 && |
719 | 92d675d1 | Aurelien Jarno | (sx + w) <= width && (sy + h) <= height && |
720 | 92d675d1 | Aurelien Jarno | (dx + w) <= width && (dy + h) <= height) { |
721 | 92d675d1 | Aurelien Jarno | notify = 1;
|
722 | 92d675d1 | Aurelien Jarno | } |
723 | 92d675d1 | Aurelien Jarno | } |
724 | 24236869 | bellard | |
725 | 24236869 | bellard | /* we have to flush all pending changes so that the copy
|
726 | 24236869 | bellard | is generated at the appropriate moment in time */
|
727 | 24236869 | bellard | if (notify)
|
728 | 1dbfa005 | Gerd Hoffmann | graphic_hw_update(s->vga.con); |
729 | 24236869 | bellard | |
730 | 4e12cd94 | Avi Kivity | (*s->cirrus_rop) (s, s->vga.vram_ptr + |
731 | b2eb849d | aurel32 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
732 | 4e12cd94 | Avi Kivity | s->vga.vram_ptr + |
733 | b2eb849d | aurel32 | (s->cirrus_blt_srcaddr & s->cirrus_addr_mask), |
734 | e6e5ad80 | bellard | s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch, |
735 | e6e5ad80 | bellard | s->cirrus_blt_width, s->cirrus_blt_height); |
736 | 24236869 | bellard | |
737 | c78f7137 | Gerd Hoffmann | if (notify) {
|
738 | c78f7137 | Gerd Hoffmann | qemu_console_copy(s->vga.con, |
739 | 38334f76 | balrog | sx, sy, dx, dy, |
740 | 38334f76 | balrog | s->cirrus_blt_width / depth, |
741 | 38334f76 | balrog | s->cirrus_blt_height); |
742 | c78f7137 | Gerd Hoffmann | } |
743 | 24236869 | bellard | |
744 | 24236869 | bellard | /* we don't have to notify the display that this portion has
|
745 | 38334f76 | balrog | changed since qemu_console_copy implies this */
|
746 | 24236869 | bellard | |
747 | 31c05501 | aliguori | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, |
748 | 31c05501 | aliguori | s->cirrus_blt_dstpitch, s->cirrus_blt_width, |
749 | 31c05501 | aliguori | s->cirrus_blt_height); |
750 | 24236869 | bellard | } |
751 | 24236869 | bellard | |
752 | 24236869 | bellard | static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s) |
753 | 24236869 | bellard | { |
754 | 65d35a09 | aurel32 | if (BLTUNSAFE(s))
|
755 | 65d35a09 | aurel32 | return 0; |
756 | 65d35a09 | aurel32 | |
757 | 4e12cd94 | Avi Kivity | cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr, |
758 | 4e12cd94 | Avi Kivity | s->cirrus_blt_srcaddr - s->vga.start_addr, |
759 | 7d957bd8 | aliguori | s->cirrus_blt_width, s->cirrus_blt_height); |
760 | 24236869 | bellard | |
761 | e6e5ad80 | bellard | return 1; |
762 | e6e5ad80 | bellard | } |
763 | e6e5ad80 | bellard | |
764 | e6e5ad80 | bellard | /***************************************
|
765 | e6e5ad80 | bellard | *
|
766 | e6e5ad80 | bellard | * bitblt (cpu-to-video)
|
767 | e6e5ad80 | bellard | *
|
768 | e6e5ad80 | bellard | ***************************************/
|
769 | e6e5ad80 | bellard | |
770 | e6e5ad80 | bellard | static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s) |
771 | e6e5ad80 | bellard | { |
772 | e6e5ad80 | bellard | int copy_count;
|
773 | a5082316 | bellard | uint8_t *end_ptr; |
774 | 3b46e624 | ths | |
775 | e6e5ad80 | bellard | if (s->cirrus_srccounter > 0) { |
776 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
777 | a5082316 | bellard | cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf); |
778 | a5082316 | bellard | the_end:
|
779 | a5082316 | bellard | s->cirrus_srccounter = 0;
|
780 | a5082316 | bellard | cirrus_bitblt_reset(s); |
781 | a5082316 | bellard | } else {
|
782 | a5082316 | bellard | /* at least one scan line */
|
783 | a5082316 | bellard | do {
|
784 | 4e12cd94 | Avi Kivity | (*s->cirrus_rop)(s, s->vga.vram_ptr + |
785 | b2eb849d | aurel32 | (s->cirrus_blt_dstaddr & s->cirrus_addr_mask), |
786 | b2eb849d | aurel32 | s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1); |
787 | a5082316 | bellard | cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
|
788 | a5082316 | bellard | s->cirrus_blt_width, 1);
|
789 | a5082316 | bellard | s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch; |
790 | a5082316 | bellard | s->cirrus_srccounter -= s->cirrus_blt_srcpitch; |
791 | a5082316 | bellard | if (s->cirrus_srccounter <= 0) |
792 | a5082316 | bellard | goto the_end;
|
793 | 66a0a2cb | Dong Xu Wang | /* more bytes than needed can be transferred because of
|
794 | a5082316 | bellard | word alignment, so we keep them for the next line */
|
795 | a5082316 | bellard | /* XXX: keep alignment to speed up transfer */
|
796 | a5082316 | bellard | end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
797 | a5082316 | bellard | copy_count = s->cirrus_srcptr_end - end_ptr; |
798 | a5082316 | bellard | memmove(s->cirrus_bltbuf, end_ptr, copy_count); |
799 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf + copy_count; |
800 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
801 | a5082316 | bellard | } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
|
802 | a5082316 | bellard | } |
803 | e6e5ad80 | bellard | } |
804 | e6e5ad80 | bellard | } |
805 | e6e5ad80 | bellard | |
806 | e6e5ad80 | bellard | /***************************************
|
807 | e6e5ad80 | bellard | *
|
808 | e6e5ad80 | bellard | * bitblt wrapper
|
809 | e6e5ad80 | bellard | *
|
810 | e6e5ad80 | bellard | ***************************************/
|
811 | e6e5ad80 | bellard | |
812 | e6e5ad80 | bellard | static void cirrus_bitblt_reset(CirrusVGAState * s) |
813 | e6e5ad80 | bellard | { |
814 | f8b237af | aliguori | int need_update;
|
815 | f8b237af | aliguori | |
816 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] &=
|
817 | e6e5ad80 | bellard | ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED); |
818 | f8b237af | aliguori | need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
|
819 | f8b237af | aliguori | || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
|
820 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
821 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
822 | e6e5ad80 | bellard | s->cirrus_srccounter = 0;
|
823 | f8b237af | aliguori | if (!need_update)
|
824 | f8b237af | aliguori | return;
|
825 | 8926b517 | bellard | cirrus_update_memory_access(s); |
826 | e6e5ad80 | bellard | } |
827 | e6e5ad80 | bellard | |
828 | e6e5ad80 | bellard | static int cirrus_bitblt_cputovideo(CirrusVGAState * s) |
829 | e6e5ad80 | bellard | { |
830 | a5082316 | bellard | int w;
|
831 | a5082316 | bellard | |
832 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC; |
833 | e6e5ad80 | bellard | s->cirrus_srcptr = &s->cirrus_bltbuf[0];
|
834 | e6e5ad80 | bellard | s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
|
835 | e6e5ad80 | bellard | |
836 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
837 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
838 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8;
|
839 | e6e5ad80 | bellard | } else {
|
840 | b30d4608 | bellard | /* XXX: check for 24 bpp */
|
841 | a5082316 | bellard | s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth; |
842 | e6e5ad80 | bellard | } |
843 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch; |
844 | e6e5ad80 | bellard | } else {
|
845 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
846 | a5082316 | bellard | w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth; |
847 | 5fafdf24 | ths | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
|
848 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 31) >> 5); |
849 | a5082316 | bellard | else
|
850 | a5082316 | bellard | s->cirrus_blt_srcpitch = ((w + 7) >> 3); |
851 | e6e5ad80 | bellard | } else {
|
852 | c9c0eae8 | bellard | /* always align input size to 32 bits */
|
853 | c9c0eae8 | bellard | s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3; |
854 | e6e5ad80 | bellard | } |
855 | a5082316 | bellard | s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height; |
856 | e6e5ad80 | bellard | } |
857 | a5082316 | bellard | s->cirrus_srcptr = s->cirrus_bltbuf; |
858 | a5082316 | bellard | s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch; |
859 | 8926b517 | bellard | cirrus_update_memory_access(s); |
860 | e6e5ad80 | bellard | return 1; |
861 | e6e5ad80 | bellard | } |
862 | e6e5ad80 | bellard | |
863 | e6e5ad80 | bellard | static int cirrus_bitblt_videotocpu(CirrusVGAState * s) |
864 | e6e5ad80 | bellard | { |
865 | e6e5ad80 | bellard | /* XXX */
|
866 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
867 | e6e5ad80 | bellard | printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
|
868 | e6e5ad80 | bellard | #endif
|
869 | e6e5ad80 | bellard | return 0; |
870 | e6e5ad80 | bellard | } |
871 | e6e5ad80 | bellard | |
872 | e6e5ad80 | bellard | static int cirrus_bitblt_videotovideo(CirrusVGAState * s) |
873 | e6e5ad80 | bellard | { |
874 | e6e5ad80 | bellard | int ret;
|
875 | e6e5ad80 | bellard | |
876 | e6e5ad80 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
|
877 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_patterncopy(s); |
878 | e6e5ad80 | bellard | } else {
|
879 | e6e5ad80 | bellard | ret = cirrus_bitblt_videotovideo_copy(s); |
880 | e6e5ad80 | bellard | } |
881 | e6e5ad80 | bellard | if (ret)
|
882 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
883 | e6e5ad80 | bellard | return ret;
|
884 | e6e5ad80 | bellard | } |
885 | e6e5ad80 | bellard | |
886 | e6e5ad80 | bellard | static void cirrus_bitblt_start(CirrusVGAState * s) |
887 | e6e5ad80 | bellard | { |
888 | e6e5ad80 | bellard | uint8_t blt_rop; |
889 | e6e5ad80 | bellard | |
890 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
|
891 | a5082316 | bellard | |
892 | 4e12cd94 | Avi Kivity | s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1; |
893 | 4e12cd94 | Avi Kivity | s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1; |
894 | 4e12cd94 | Avi Kivity | s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8)); |
895 | 4e12cd94 | Avi Kivity | s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8)); |
896 | e6e5ad80 | bellard | s->cirrus_blt_dstaddr = |
897 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16)); |
898 | e6e5ad80 | bellard | s->cirrus_blt_srcaddr = |
899 | 4e12cd94 | Avi Kivity | (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16)); |
900 | 4e12cd94 | Avi Kivity | s->cirrus_blt_mode = s->vga.gr[0x30];
|
901 | 4e12cd94 | Avi Kivity | s->cirrus_blt_modeext = s->vga.gr[0x33];
|
902 | 4e12cd94 | Avi Kivity | blt_rop = s->vga.gr[0x32];
|
903 | e6e5ad80 | bellard | |
904 | a21ae81d | bellard | #ifdef DEBUG_BITBLT
|
905 | 0b74ed78 | bellard | printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
|
906 | 5fafdf24 | ths | blt_rop, |
907 | a21ae81d | bellard | s->cirrus_blt_mode, |
908 | a5082316 | bellard | s->cirrus_blt_modeext, |
909 | a21ae81d | bellard | s->cirrus_blt_width, |
910 | a21ae81d | bellard | s->cirrus_blt_height, |
911 | a21ae81d | bellard | s->cirrus_blt_dstpitch, |
912 | a21ae81d | bellard | s->cirrus_blt_srcpitch, |
913 | a21ae81d | bellard | s->cirrus_blt_dstaddr, |
914 | a5082316 | bellard | s->cirrus_blt_srcaddr, |
915 | 4e12cd94 | Avi Kivity | s->vga.gr[0x2f]);
|
916 | a21ae81d | bellard | #endif
|
917 | a21ae81d | bellard | |
918 | e6e5ad80 | bellard | switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
|
919 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH8:
|
920 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 1;
|
921 | e6e5ad80 | bellard | break;
|
922 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH16:
|
923 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 2;
|
924 | e6e5ad80 | bellard | break;
|
925 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH24:
|
926 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 3;
|
927 | e6e5ad80 | bellard | break;
|
928 | e6e5ad80 | bellard | case CIRRUS_BLTMODE_PIXELWIDTH32:
|
929 | e6e5ad80 | bellard | s->cirrus_blt_pixelwidth = 4;
|
930 | e6e5ad80 | bellard | break;
|
931 | e6e5ad80 | bellard | default:
|
932 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
933 | e6e5ad80 | bellard | printf("cirrus: bitblt - pixel width is unknown\n");
|
934 | e6e5ad80 | bellard | #endif
|
935 | e6e5ad80 | bellard | goto bitblt_ignore;
|
936 | e6e5ad80 | bellard | } |
937 | e6e5ad80 | bellard | s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK; |
938 | e6e5ad80 | bellard | |
939 | e6e5ad80 | bellard | if ((s->
|
940 | e6e5ad80 | bellard | cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC | |
941 | e6e5ad80 | bellard | CIRRUS_BLTMODE_MEMSYSDEST)) |
942 | e6e5ad80 | bellard | == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) { |
943 | a5082316 | bellard | #ifdef DEBUG_BITBLT
|
944 | e6e5ad80 | bellard | printf("cirrus: bitblt - memory-to-memory copy is requested\n");
|
945 | e6e5ad80 | bellard | #endif
|
946 | e6e5ad80 | bellard | goto bitblt_ignore;
|
947 | e6e5ad80 | bellard | } |
948 | e6e5ad80 | bellard | |
949 | a5082316 | bellard | if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
|
950 | 5fafdf24 | ths | (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST | |
951 | a21ae81d | bellard | CIRRUS_BLTMODE_TRANSPARENTCOMP | |
952 | 5fafdf24 | ths | CIRRUS_BLTMODE_PATTERNCOPY | |
953 | 5fafdf24 | ths | CIRRUS_BLTMODE_COLOREXPAND)) == |
954 | a21ae81d | bellard | (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) { |
955 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
956 | a5082316 | bellard | cirrus_bitblt_solidfill(s, blt_rop); |
957 | e6e5ad80 | bellard | } else {
|
958 | 5fafdf24 | ths | if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
|
959 | 5fafdf24 | ths | CIRRUS_BLTMODE_PATTERNCOPY)) == |
960 | a5082316 | bellard | CIRRUS_BLTMODE_COLOREXPAND) { |
961 | a5082316 | bellard | |
962 | a5082316 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
963 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
964 | 4c8732d7 | bellard | cirrus_bitblt_bgcol(s); |
965 | b30d4608 | bellard | else
|
966 | 4c8732d7 | bellard | cirrus_bitblt_fgcol(s); |
967 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
968 | a5082316 | bellard | } else {
|
969 | a5082316 | bellard | cirrus_bitblt_fgcol(s); |
970 | a5082316 | bellard | cirrus_bitblt_bgcol(s); |
971 | a5082316 | bellard | s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
972 | a5082316 | bellard | } |
973 | e69390ce | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) { |
974 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
|
975 | b30d4608 | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
976 | b30d4608 | bellard | if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
|
977 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
978 | b30d4608 | bellard | else
|
979 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
980 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
981 | b30d4608 | bellard | } else {
|
982 | b30d4608 | bellard | cirrus_bitblt_fgcol(s); |
983 | b30d4608 | bellard | cirrus_bitblt_bgcol(s); |
984 | b30d4608 | bellard | s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
985 | b30d4608 | bellard | } |
986 | b30d4608 | bellard | } else {
|
987 | b30d4608 | bellard | s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
988 | b30d4608 | bellard | } |
989 | a21ae81d | bellard | } else {
|
990 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
|
991 | 96cf2df8 | ths | if (s->cirrus_blt_pixelwidth > 2) { |
992 | 96cf2df8 | ths | printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
|
993 | 96cf2df8 | ths | goto bitblt_ignore;
|
994 | 96cf2df8 | ths | } |
995 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
996 | 96cf2df8 | ths | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
997 | 96cf2df8 | ths | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
998 | 96cf2df8 | ths | s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
999 | 96cf2df8 | ths | } else {
|
1000 | 96cf2df8 | ths | s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
|
1001 | 96cf2df8 | ths | } |
1002 | 96cf2df8 | ths | } else {
|
1003 | 96cf2df8 | ths | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
|
1004 | 96cf2df8 | ths | s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch; |
1005 | 96cf2df8 | ths | s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch; |
1006 | 96cf2df8 | ths | s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]]; |
1007 | 96cf2df8 | ths | } else {
|
1008 | 96cf2df8 | ths | s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]]; |
1009 | 96cf2df8 | ths | } |
1010 | 96cf2df8 | ths | } |
1011 | 96cf2df8 | ths | } |
1012 | a21ae81d | bellard | // setup bitblt engine.
|
1013 | a21ae81d | bellard | if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
|
1014 | a21ae81d | bellard | if (!cirrus_bitblt_cputovideo(s))
|
1015 | a21ae81d | bellard | goto bitblt_ignore;
|
1016 | a21ae81d | bellard | } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) { |
1017 | a21ae81d | bellard | if (!cirrus_bitblt_videotocpu(s))
|
1018 | a21ae81d | bellard | goto bitblt_ignore;
|
1019 | a21ae81d | bellard | } else {
|
1020 | a21ae81d | bellard | if (!cirrus_bitblt_videotovideo(s))
|
1021 | a21ae81d | bellard | goto bitblt_ignore;
|
1022 | a21ae81d | bellard | } |
1023 | e6e5ad80 | bellard | } |
1024 | e6e5ad80 | bellard | return;
|
1025 | e6e5ad80 | bellard | bitblt_ignore:;
|
1026 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1027 | e6e5ad80 | bellard | } |
1028 | e6e5ad80 | bellard | |
1029 | e6e5ad80 | bellard | static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value) |
1030 | e6e5ad80 | bellard | { |
1031 | e6e5ad80 | bellard | unsigned old_value;
|
1032 | e6e5ad80 | bellard | |
1033 | 4e12cd94 | Avi Kivity | old_value = s->vga.gr[0x31];
|
1034 | 4e12cd94 | Avi Kivity | s->vga.gr[0x31] = reg_value;
|
1035 | e6e5ad80 | bellard | |
1036 | e6e5ad80 | bellard | if (((old_value & CIRRUS_BLT_RESET) != 0) && |
1037 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_RESET) == 0)) {
|
1038 | e6e5ad80 | bellard | cirrus_bitblt_reset(s); |
1039 | e6e5ad80 | bellard | } else if (((old_value & CIRRUS_BLT_START) == 0) && |
1040 | e6e5ad80 | bellard | ((reg_value & CIRRUS_BLT_START) != 0)) {
|
1041 | e6e5ad80 | bellard | cirrus_bitblt_start(s); |
1042 | e6e5ad80 | bellard | } |
1043 | e6e5ad80 | bellard | } |
1044 | e6e5ad80 | bellard | |
1045 | e6e5ad80 | bellard | |
1046 | e6e5ad80 | bellard | /***************************************
|
1047 | e6e5ad80 | bellard | *
|
1048 | e6e5ad80 | bellard | * basic parameters
|
1049 | e6e5ad80 | bellard | *
|
1050 | e6e5ad80 | bellard | ***************************************/
|
1051 | e6e5ad80 | bellard | |
1052 | a4a2f59c | Juan Quintela | static void cirrus_get_offsets(VGACommonState *s1, |
1053 | 83acc96b | bellard | uint32_t *pline_offset, |
1054 | 83acc96b | bellard | uint32_t *pstart_addr, |
1055 | 83acc96b | bellard | uint32_t *pline_compare) |
1056 | e6e5ad80 | bellard | { |
1057 | 4e12cd94 | Avi Kivity | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
1058 | 83acc96b | bellard | uint32_t start_addr, line_offset, line_compare; |
1059 | e6e5ad80 | bellard | |
1060 | 4e12cd94 | Avi Kivity | line_offset = s->vga.cr[0x13]
|
1061 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x10) << 4); |
1062 | e6e5ad80 | bellard | line_offset <<= 3;
|
1063 | e6e5ad80 | bellard | *pline_offset = line_offset; |
1064 | e6e5ad80 | bellard | |
1065 | 4e12cd94 | Avi Kivity | start_addr = (s->vga.cr[0x0c] << 8) |
1066 | 4e12cd94 | Avi Kivity | | s->vga.cr[0x0d]
|
1067 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x01) << 16) |
1068 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1b] & 0x0c) << 15) |
1069 | 4e12cd94 | Avi Kivity | | ((s->vga.cr[0x1d] & 0x80) << 12); |
1070 | e6e5ad80 | bellard | *pstart_addr = start_addr; |
1071 | 83acc96b | bellard | |
1072 | 4e12cd94 | Avi Kivity | line_compare = s->vga.cr[0x18] |
|
1073 | 4e12cd94 | Avi Kivity | ((s->vga.cr[0x07] & 0x10) << 4) | |
1074 | 4e12cd94 | Avi Kivity | ((s->vga.cr[0x09] & 0x40) << 3); |
1075 | 83acc96b | bellard | *pline_compare = line_compare; |
1076 | e6e5ad80 | bellard | } |
1077 | e6e5ad80 | bellard | |
1078 | e6e5ad80 | bellard | static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
|
1079 | e6e5ad80 | bellard | { |
1080 | e6e5ad80 | bellard | uint32_t ret = 16;
|
1081 | e6e5ad80 | bellard | |
1082 | e6e5ad80 | bellard | switch (s->cirrus_hidden_dac_data & 0xf) { |
1083 | e6e5ad80 | bellard | case 0: |
1084 | e6e5ad80 | bellard | ret = 15;
|
1085 | e6e5ad80 | bellard | break; /* Sierra HiColor */ |
1086 | e6e5ad80 | bellard | case 1: |
1087 | e6e5ad80 | bellard | ret = 16;
|
1088 | e6e5ad80 | bellard | break; /* XGA HiColor */ |
1089 | e6e5ad80 | bellard | default:
|
1090 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1091 | e6e5ad80 | bellard | printf("cirrus: invalid DAC value %x in 16bpp\n",
|
1092 | e6e5ad80 | bellard | (s->cirrus_hidden_dac_data & 0xf));
|
1093 | e6e5ad80 | bellard | #endif
|
1094 | e6e5ad80 | bellard | ret = 15; /* XXX */ |
1095 | e6e5ad80 | bellard | break;
|
1096 | e6e5ad80 | bellard | } |
1097 | e6e5ad80 | bellard | return ret;
|
1098 | e6e5ad80 | bellard | } |
1099 | e6e5ad80 | bellard | |
1100 | a4a2f59c | Juan Quintela | static int cirrus_get_bpp(VGACommonState *s1) |
1101 | e6e5ad80 | bellard | { |
1102 | 4e12cd94 | Avi Kivity | CirrusVGAState * s = container_of(s1, CirrusVGAState, vga); |
1103 | e6e5ad80 | bellard | uint32_t ret = 8;
|
1104 | e6e5ad80 | bellard | |
1105 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) != 0) { |
1106 | e6e5ad80 | bellard | /* Cirrus SVGA */
|
1107 | 4e12cd94 | Avi Kivity | switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) { |
1108 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_8:
|
1109 | e6e5ad80 | bellard | ret = 8;
|
1110 | e6e5ad80 | bellard | break;
|
1111 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
|
1112 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1113 | e6e5ad80 | bellard | break;
|
1114 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_24:
|
1115 | e6e5ad80 | bellard | ret = 24;
|
1116 | e6e5ad80 | bellard | break;
|
1117 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_16:
|
1118 | e6e5ad80 | bellard | ret = cirrus_get_bpp16_depth(s); |
1119 | e6e5ad80 | bellard | break;
|
1120 | e6e5ad80 | bellard | case CIRRUS_SR7_BPP_32:
|
1121 | e6e5ad80 | bellard | ret = 32;
|
1122 | e6e5ad80 | bellard | break;
|
1123 | e6e5ad80 | bellard | default:
|
1124 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1125 | 4e12cd94 | Avi Kivity | printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]); |
1126 | e6e5ad80 | bellard | #endif
|
1127 | e6e5ad80 | bellard | ret = 8;
|
1128 | e6e5ad80 | bellard | break;
|
1129 | e6e5ad80 | bellard | } |
1130 | e6e5ad80 | bellard | } else {
|
1131 | e6e5ad80 | bellard | /* VGA */
|
1132 | aeb3c85f | bellard | ret = 0;
|
1133 | e6e5ad80 | bellard | } |
1134 | e6e5ad80 | bellard | |
1135 | e6e5ad80 | bellard | return ret;
|
1136 | e6e5ad80 | bellard | } |
1137 | e6e5ad80 | bellard | |
1138 | a4a2f59c | Juan Quintela | static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight) |
1139 | 78e127ef | bellard | { |
1140 | 78e127ef | bellard | int width, height;
|
1141 | 3b46e624 | ths | |
1142 | 78e127ef | bellard | width = (s->cr[0x01] + 1) * 8; |
1143 | 5fafdf24 | ths | height = s->cr[0x12] |
|
1144 | 5fafdf24 | ths | ((s->cr[0x07] & 0x02) << 7) | |
1145 | 78e127ef | bellard | ((s->cr[0x07] & 0x40) << 3); |
1146 | 78e127ef | bellard | height = (height + 1);
|
1147 | 78e127ef | bellard | /* interlace support */
|
1148 | 78e127ef | bellard | if (s->cr[0x1a] & 0x01) |
1149 | 78e127ef | bellard | height = height * 2;
|
1150 | 78e127ef | bellard | *pwidth = width; |
1151 | 78e127ef | bellard | *pheight = height; |
1152 | 78e127ef | bellard | } |
1153 | 78e127ef | bellard | |
1154 | e6e5ad80 | bellard | /***************************************
|
1155 | e6e5ad80 | bellard | *
|
1156 | e6e5ad80 | bellard | * bank memory
|
1157 | e6e5ad80 | bellard | *
|
1158 | e6e5ad80 | bellard | ***************************************/
|
1159 | e6e5ad80 | bellard | |
1160 | e6e5ad80 | bellard | static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) |
1161 | e6e5ad80 | bellard | { |
1162 | e6e5ad80 | bellard | unsigned offset;
|
1163 | e6e5ad80 | bellard | unsigned limit;
|
1164 | e6e5ad80 | bellard | |
1165 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */ |
1166 | 4e12cd94 | Avi Kivity | offset = s->vga.gr[0x09 + bank_index];
|
1167 | e6e5ad80 | bellard | else /* single bank */ |
1168 | 4e12cd94 | Avi Kivity | offset = s->vga.gr[0x09];
|
1169 | e6e5ad80 | bellard | |
1170 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0b] & 0x20) != 0) |
1171 | e6e5ad80 | bellard | offset <<= 14;
|
1172 | e6e5ad80 | bellard | else
|
1173 | e6e5ad80 | bellard | offset <<= 12;
|
1174 | e6e5ad80 | bellard | |
1175 | e3a4e4b6 | bellard | if (s->real_vram_size <= offset)
|
1176 | e6e5ad80 | bellard | limit = 0;
|
1177 | e6e5ad80 | bellard | else
|
1178 | e3a4e4b6 | bellard | limit = s->real_vram_size - offset; |
1179 | e6e5ad80 | bellard | |
1180 | 4e12cd94 | Avi Kivity | if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { |
1181 | e6e5ad80 | bellard | if (limit > 0x8000) { |
1182 | e6e5ad80 | bellard | offset += 0x8000;
|
1183 | e6e5ad80 | bellard | limit -= 0x8000;
|
1184 | e6e5ad80 | bellard | } else {
|
1185 | e6e5ad80 | bellard | limit = 0;
|
1186 | e6e5ad80 | bellard | } |
1187 | e6e5ad80 | bellard | } |
1188 | e6e5ad80 | bellard | |
1189 | e6e5ad80 | bellard | if (limit > 0) { |
1190 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = offset; |
1191 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = limit; |
1192 | e6e5ad80 | bellard | } else {
|
1193 | e6e5ad80 | bellard | s->cirrus_bank_base[bank_index] = 0;
|
1194 | e6e5ad80 | bellard | s->cirrus_bank_limit[bank_index] = 0;
|
1195 | e6e5ad80 | bellard | } |
1196 | e6e5ad80 | bellard | } |
1197 | e6e5ad80 | bellard | |
1198 | e6e5ad80 | bellard | /***************************************
|
1199 | e6e5ad80 | bellard | *
|
1200 | e6e5ad80 | bellard | * I/O access between 0x3c4-0x3c5
|
1201 | e6e5ad80 | bellard | *
|
1202 | e6e5ad80 | bellard | ***************************************/
|
1203 | e6e5ad80 | bellard | |
1204 | 8a82c322 | Juan Quintela | static int cirrus_vga_read_sr(CirrusVGAState * s) |
1205 | e6e5ad80 | bellard | { |
1206 | 8a82c322 | Juan Quintela | switch (s->vga.sr_index) {
|
1207 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1208 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1209 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1210 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1211 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1212 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1213 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1214 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1215 | e6e5ad80 | bellard | case 0x10: |
1216 | e6e5ad80 | bellard | case 0x30: |
1217 | e6e5ad80 | bellard | case 0x50: |
1218 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1219 | e6e5ad80 | bellard | case 0x90: |
1220 | e6e5ad80 | bellard | case 0xb0: |
1221 | e6e5ad80 | bellard | case 0xd0: |
1222 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1223 | 8a82c322 | Juan Quintela | return s->vga.sr[0x10]; |
1224 | e6e5ad80 | bellard | case 0x11: |
1225 | e6e5ad80 | bellard | case 0x31: |
1226 | e6e5ad80 | bellard | case 0x51: |
1227 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1228 | e6e5ad80 | bellard | case 0x91: |
1229 | e6e5ad80 | bellard | case 0xb1: |
1230 | e6e5ad80 | bellard | case 0xd1: |
1231 | a5082316 | bellard | case 0xf1: // Graphics Cursor Y |
1232 | 8a82c322 | Juan Quintela | return s->vga.sr[0x11]; |
1233 | aeb3c85f | bellard | case 0x05: // ??? |
1234 | aeb3c85f | bellard | case 0x07: // Extended Sequencer Mode |
1235 | aeb3c85f | bellard | case 0x08: // EEPROM Control |
1236 | aeb3c85f | bellard | case 0x09: // Scratch Register 0 |
1237 | aeb3c85f | bellard | case 0x0a: // Scratch Register 1 |
1238 | aeb3c85f | bellard | case 0x0b: // VCLK 0 |
1239 | aeb3c85f | bellard | case 0x0c: // VCLK 1 |
1240 | aeb3c85f | bellard | case 0x0d: // VCLK 2 |
1241 | aeb3c85f | bellard | case 0x0e: // VCLK 3 |
1242 | aeb3c85f | bellard | case 0x0f: // DRAM Control |
1243 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1244 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1245 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1246 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1247 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1248 | e6e5ad80 | bellard | case 0x17: // Configuration Readback and Extended Control |
1249 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1250 | e6e5ad80 | bellard | case 0x19: // Signal Generator Result |
1251 | e6e5ad80 | bellard | case 0x1a: // Signal Generator Result |
1252 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1253 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1254 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1255 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1256 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1257 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1258 | 8a82c322 | Juan Quintela | printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
|
1259 | e6e5ad80 | bellard | #endif
|
1260 | 8a82c322 | Juan Quintela | return s->vga.sr[s->vga.sr_index];
|
1261 | e6e5ad80 | bellard | default:
|
1262 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1263 | 8a82c322 | Juan Quintela | printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
|
1264 | e6e5ad80 | bellard | #endif
|
1265 | 8a82c322 | Juan Quintela | return 0xff; |
1266 | e6e5ad80 | bellard | break;
|
1267 | e6e5ad80 | bellard | } |
1268 | e6e5ad80 | bellard | } |
1269 | e6e5ad80 | bellard | |
1270 | 31c63201 | Juan Quintela | static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val) |
1271 | e6e5ad80 | bellard | { |
1272 | 31c63201 | Juan Quintela | switch (s->vga.sr_index) {
|
1273 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1274 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1275 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1276 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1277 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1278 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index]; |
1279 | 31c63201 | Juan Quintela | if (s->vga.sr_index == 1) |
1280 | 31c63201 | Juan Quintela | s->vga.update_retrace_info(&s->vga); |
1281 | 31c63201 | Juan Quintela | break;
|
1282 | e6e5ad80 | bellard | case 0x06: // Unlock Cirrus extensions |
1283 | 31c63201 | Juan Quintela | val &= 0x17;
|
1284 | 31c63201 | Juan Quintela | if (val == 0x12) { |
1285 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = 0x12;
|
1286 | e6e5ad80 | bellard | } else {
|
1287 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = 0x0f;
|
1288 | e6e5ad80 | bellard | } |
1289 | e6e5ad80 | bellard | break;
|
1290 | e6e5ad80 | bellard | case 0x10: |
1291 | e6e5ad80 | bellard | case 0x30: |
1292 | e6e5ad80 | bellard | case 0x50: |
1293 | e6e5ad80 | bellard | case 0x70: // Graphics Cursor X |
1294 | e6e5ad80 | bellard | case 0x90: |
1295 | e6e5ad80 | bellard | case 0xb0: |
1296 | e6e5ad80 | bellard | case 0xd0: |
1297 | e6e5ad80 | bellard | case 0xf0: // Graphics Cursor X |
1298 | 31c63201 | Juan Quintela | s->vga.sr[0x10] = val;
|
1299 | 31c63201 | Juan Quintela | s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5); |
1300 | e6e5ad80 | bellard | break;
|
1301 | e6e5ad80 | bellard | case 0x11: |
1302 | e6e5ad80 | bellard | case 0x31: |
1303 | e6e5ad80 | bellard | case 0x51: |
1304 | e6e5ad80 | bellard | case 0x71: // Graphics Cursor Y |
1305 | e6e5ad80 | bellard | case 0x91: |
1306 | e6e5ad80 | bellard | case 0xb1: |
1307 | e6e5ad80 | bellard | case 0xd1: |
1308 | e6e5ad80 | bellard | case 0xf1: // Graphics Cursor Y |
1309 | 31c63201 | Juan Quintela | s->vga.sr[0x11] = val;
|
1310 | 31c63201 | Juan Quintela | s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5); |
1311 | e6e5ad80 | bellard | break;
|
1312 | e6e5ad80 | bellard | case 0x07: // Extended Sequencer Mode |
1313 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
1314 | e6e5ad80 | bellard | case 0x08: // EEPROM Control |
1315 | e6e5ad80 | bellard | case 0x09: // Scratch Register 0 |
1316 | e6e5ad80 | bellard | case 0x0a: // Scratch Register 1 |
1317 | e6e5ad80 | bellard | case 0x0b: // VCLK 0 |
1318 | e6e5ad80 | bellard | case 0x0c: // VCLK 1 |
1319 | e6e5ad80 | bellard | case 0x0d: // VCLK 2 |
1320 | e6e5ad80 | bellard | case 0x0e: // VCLK 3 |
1321 | e6e5ad80 | bellard | case 0x0f: // DRAM Control |
1322 | e6e5ad80 | bellard | case 0x12: // Graphics Cursor Attribute |
1323 | e6e5ad80 | bellard | case 0x13: // Graphics Cursor Pattern Address |
1324 | e6e5ad80 | bellard | case 0x14: // Scratch Register 2 |
1325 | e6e5ad80 | bellard | case 0x15: // Scratch Register 3 |
1326 | e6e5ad80 | bellard | case 0x16: // Performance Tuning Register |
1327 | e6e5ad80 | bellard | case 0x18: // Signature Generator Control |
1328 | e6e5ad80 | bellard | case 0x19: // Signature Generator Result |
1329 | e6e5ad80 | bellard | case 0x1a: // Signature Generator Result |
1330 | e6e5ad80 | bellard | case 0x1b: // VCLK 0 Denominator & Post |
1331 | e6e5ad80 | bellard | case 0x1c: // VCLK 1 Denominator & Post |
1332 | e6e5ad80 | bellard | case 0x1d: // VCLK 2 Denominator & Post |
1333 | e6e5ad80 | bellard | case 0x1e: // VCLK 3 Denominator & Post |
1334 | e6e5ad80 | bellard | case 0x1f: // BIOS Write Enable and MCLK select |
1335 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = val; |
1336 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1337 | e6e5ad80 | bellard | printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
|
1338 | 31c63201 | Juan Quintela | s->vga.sr_index, val); |
1339 | e6e5ad80 | bellard | #endif
|
1340 | e6e5ad80 | bellard | break;
|
1341 | 8926b517 | bellard | case 0x17: // Configuration Readback and Extended Control |
1342 | 31c63201 | Juan Quintela | s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
|
1343 | 31c63201 | Juan Quintela | | (val & 0xc7);
|
1344 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1345 | 8926b517 | bellard | break;
|
1346 | e6e5ad80 | bellard | default:
|
1347 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1348 | 31c63201 | Juan Quintela | printf("cirrus: outport sr_index %02x, sr_value %02x\n",
|
1349 | 31c63201 | Juan Quintela | s->vga.sr_index, val); |
1350 | e6e5ad80 | bellard | #endif
|
1351 | e6e5ad80 | bellard | break;
|
1352 | e6e5ad80 | bellard | } |
1353 | e6e5ad80 | bellard | } |
1354 | e6e5ad80 | bellard | |
1355 | e6e5ad80 | bellard | /***************************************
|
1356 | e6e5ad80 | bellard | *
|
1357 | e6e5ad80 | bellard | * I/O access at 0x3c6
|
1358 | e6e5ad80 | bellard | *
|
1359 | e6e5ad80 | bellard | ***************************************/
|
1360 | e6e5ad80 | bellard | |
1361 | 957c9db5 | Juan Quintela | static int cirrus_read_hidden_dac(CirrusVGAState * s) |
1362 | e6e5ad80 | bellard | { |
1363 | a21ae81d | bellard | if (++s->cirrus_hidden_dac_lockindex == 5) { |
1364 | 957c9db5 | Juan Quintela | s->cirrus_hidden_dac_lockindex = 0;
|
1365 | 957c9db5 | Juan Quintela | return s->cirrus_hidden_dac_data;
|
1366 | e6e5ad80 | bellard | } |
1367 | 957c9db5 | Juan Quintela | return 0xff; |
1368 | e6e5ad80 | bellard | } |
1369 | e6e5ad80 | bellard | |
1370 | e6e5ad80 | bellard | static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value) |
1371 | e6e5ad80 | bellard | { |
1372 | e6e5ad80 | bellard | if (s->cirrus_hidden_dac_lockindex == 4) { |
1373 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = reg_value; |
1374 | a21ae81d | bellard | #if defined(DEBUG_CIRRUS)
|
1375 | e6e5ad80 | bellard | printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
|
1376 | e6e5ad80 | bellard | #endif
|
1377 | e6e5ad80 | bellard | } |
1378 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 0;
|
1379 | e6e5ad80 | bellard | } |
1380 | e6e5ad80 | bellard | |
1381 | e6e5ad80 | bellard | /***************************************
|
1382 | e6e5ad80 | bellard | *
|
1383 | e6e5ad80 | bellard | * I/O access at 0x3c9
|
1384 | e6e5ad80 | bellard | *
|
1385 | e6e5ad80 | bellard | ***************************************/
|
1386 | e6e5ad80 | bellard | |
1387 | 5deaeee3 | Juan Quintela | static int cirrus_vga_read_palette(CirrusVGAState * s) |
1388 | e6e5ad80 | bellard | { |
1389 | 5deaeee3 | Juan Quintela | int val;
|
1390 | 5deaeee3 | Juan Quintela | |
1391 | 5deaeee3 | Juan Quintela | if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
1392 | 5deaeee3 | Juan Quintela | val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 + |
1393 | 5deaeee3 | Juan Quintela | s->vga.dac_sub_index]; |
1394 | 5deaeee3 | Juan Quintela | } else {
|
1395 | 5deaeee3 | Juan Quintela | val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
|
1396 | 5deaeee3 | Juan Quintela | } |
1397 | 4e12cd94 | Avi Kivity | if (++s->vga.dac_sub_index == 3) { |
1398 | 4e12cd94 | Avi Kivity | s->vga.dac_sub_index = 0;
|
1399 | 4e12cd94 | Avi Kivity | s->vga.dac_read_index++; |
1400 | e6e5ad80 | bellard | } |
1401 | 5deaeee3 | Juan Quintela | return val;
|
1402 | e6e5ad80 | bellard | } |
1403 | e6e5ad80 | bellard | |
1404 | 86948bb1 | Juan Quintela | static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value) |
1405 | e6e5ad80 | bellard | { |
1406 | 4e12cd94 | Avi Kivity | s->vga.dac_cache[s->vga.dac_sub_index] = reg_value; |
1407 | 4e12cd94 | Avi Kivity | if (++s->vga.dac_sub_index == 3) { |
1408 | 86948bb1 | Juan Quintela | if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) { |
1409 | 86948bb1 | Juan Quintela | memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3], |
1410 | 86948bb1 | Juan Quintela | s->vga.dac_cache, 3);
|
1411 | 86948bb1 | Juan Quintela | } else {
|
1412 | 86948bb1 | Juan Quintela | memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3); |
1413 | 86948bb1 | Juan Quintela | } |
1414 | a5082316 | bellard | /* XXX update cursor */
|
1415 | 4e12cd94 | Avi Kivity | s->vga.dac_sub_index = 0;
|
1416 | 4e12cd94 | Avi Kivity | s->vga.dac_write_index++; |
1417 | e6e5ad80 | bellard | } |
1418 | e6e5ad80 | bellard | } |
1419 | e6e5ad80 | bellard | |
1420 | e6e5ad80 | bellard | /***************************************
|
1421 | e6e5ad80 | bellard | *
|
1422 | e6e5ad80 | bellard | * I/O access between 0x3ce-0x3cf
|
1423 | e6e5ad80 | bellard | *
|
1424 | e6e5ad80 | bellard | ***************************************/
|
1425 | e6e5ad80 | bellard | |
1426 | f705db9d | Juan Quintela | static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index) |
1427 | e6e5ad80 | bellard | { |
1428 | e6e5ad80 | bellard | switch (reg_index) {
|
1429 | aeb3c85f | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1430 | f705db9d | Juan Quintela | return s->cirrus_shadow_gr0;
|
1431 | aeb3c85f | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1432 | f705db9d | Juan Quintela | return s->cirrus_shadow_gr1;
|
1433 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1434 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1435 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1436 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1437 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1438 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1439 | f705db9d | Juan Quintela | return s->vga.gr[s->vga.gr_index];
|
1440 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1441 | e6e5ad80 | bellard | default:
|
1442 | e6e5ad80 | bellard | break;
|
1443 | e6e5ad80 | bellard | } |
1444 | e6e5ad80 | bellard | |
1445 | e6e5ad80 | bellard | if (reg_index < 0x3a) { |
1446 | f705db9d | Juan Quintela | return s->vga.gr[reg_index];
|
1447 | e6e5ad80 | bellard | } else {
|
1448 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1449 | e6e5ad80 | bellard | printf("cirrus: inport gr_index %02x\n", reg_index);
|
1450 | e6e5ad80 | bellard | #endif
|
1451 | f705db9d | Juan Quintela | return 0xff; |
1452 | e6e5ad80 | bellard | } |
1453 | e6e5ad80 | bellard | } |
1454 | e6e5ad80 | bellard | |
1455 | 22286bc6 | Juan Quintela | static void |
1456 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value) |
1457 | e6e5ad80 | bellard | { |
1458 | a5082316 | bellard | #if defined(DEBUG_BITBLT) && 0 |
1459 | a5082316 | bellard | printf("gr%02x: %02x\n", reg_index, reg_value);
|
1460 | a5082316 | bellard | #endif
|
1461 | e6e5ad80 | bellard | switch (reg_index) {
|
1462 | e6e5ad80 | bellard | case 0x00: // Standard VGA, BGCOLOR 0x000000ff |
1463 | f22f5b07 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1464 | aeb3c85f | bellard | s->cirrus_shadow_gr0 = reg_value; |
1465 | 22286bc6 | Juan Quintela | break;
|
1466 | e6e5ad80 | bellard | case 0x01: // Standard VGA, FGCOLOR 0x000000ff |
1467 | f22f5b07 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1468 | aeb3c85f | bellard | s->cirrus_shadow_gr1 = reg_value; |
1469 | 22286bc6 | Juan Quintela | break;
|
1470 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1471 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1472 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1473 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1474 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1475 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1476 | 22286bc6 | Juan Quintela | s->vga.gr[reg_index] = reg_value & gr_mask[reg_index]; |
1477 | 22286bc6 | Juan Quintela | break;
|
1478 | e6e5ad80 | bellard | case 0x05: // Standard VGA, Cirrus extended mode |
1479 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x7f;
|
1480 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1481 | e6e5ad80 | bellard | break;
|
1482 | e6e5ad80 | bellard | case 0x09: // bank offset #0 |
1483 | e6e5ad80 | bellard | case 0x0A: // bank offset #1 |
1484 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1485 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 0);
|
1486 | 8926b517 | bellard | cirrus_update_bank_ptr(s, 1);
|
1487 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
1488 | 8926b517 | bellard | break;
|
1489 | e6e5ad80 | bellard | case 0x0B: |
1490 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1491 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 0);
|
1492 | e6e5ad80 | bellard | cirrus_update_bank_ptr(s, 1);
|
1493 | 8926b517 | bellard | cirrus_update_memory_access(s); |
1494 | e6e5ad80 | bellard | break;
|
1495 | e6e5ad80 | bellard | case 0x10: // BGCOLOR 0x0000ff00 |
1496 | e6e5ad80 | bellard | case 0x11: // FGCOLOR 0x0000ff00 |
1497 | e6e5ad80 | bellard | case 0x12: // BGCOLOR 0x00ff0000 |
1498 | e6e5ad80 | bellard | case 0x13: // FGCOLOR 0x00ff0000 |
1499 | e6e5ad80 | bellard | case 0x14: // BGCOLOR 0xff000000 |
1500 | e6e5ad80 | bellard | case 0x15: // FGCOLOR 0xff000000 |
1501 | e6e5ad80 | bellard | case 0x20: // BLT WIDTH 0x0000ff |
1502 | e6e5ad80 | bellard | case 0x22: // BLT HEIGHT 0x0000ff |
1503 | e6e5ad80 | bellard | case 0x24: // BLT DEST PITCH 0x0000ff |
1504 | e6e5ad80 | bellard | case 0x26: // BLT SRC PITCH 0x0000ff |
1505 | e6e5ad80 | bellard | case 0x28: // BLT DEST ADDR 0x0000ff |
1506 | e6e5ad80 | bellard | case 0x29: // BLT DEST ADDR 0x00ff00 |
1507 | e6e5ad80 | bellard | case 0x2c: // BLT SRC ADDR 0x0000ff |
1508 | e6e5ad80 | bellard | case 0x2d: // BLT SRC ADDR 0x00ff00 |
1509 | a5082316 | bellard | case 0x2f: // BLT WRITEMASK |
1510 | e6e5ad80 | bellard | case 0x30: // BLT MODE |
1511 | e6e5ad80 | bellard | case 0x32: // RASTER OP |
1512 | a21ae81d | bellard | case 0x33: // BLT MODEEXT |
1513 | e6e5ad80 | bellard | case 0x34: // BLT TRANSPARENT COLOR 0x00ff |
1514 | e6e5ad80 | bellard | case 0x35: // BLT TRANSPARENT COLOR 0xff00 |
1515 | e6e5ad80 | bellard | case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff |
1516 | e6e5ad80 | bellard | case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00 |
1517 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value; |
1518 | e6e5ad80 | bellard | break;
|
1519 | e6e5ad80 | bellard | case 0x21: // BLT WIDTH 0x001f00 |
1520 | e6e5ad80 | bellard | case 0x23: // BLT HEIGHT 0x001f00 |
1521 | e6e5ad80 | bellard | case 0x25: // BLT DEST PITCH 0x001f00 |
1522 | e6e5ad80 | bellard | case 0x27: // BLT SRC PITCH 0x001f00 |
1523 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x1f;
|
1524 | e6e5ad80 | bellard | break;
|
1525 | e6e5ad80 | bellard | case 0x2a: // BLT DEST ADDR 0x3f0000 |
1526 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x3f;
|
1527 | a5082316 | bellard | /* if auto start mode, starts bit blt now */
|
1528 | 4e12cd94 | Avi Kivity | if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) { |
1529 | a5082316 | bellard | cirrus_bitblt_start(s); |
1530 | a5082316 | bellard | } |
1531 | a5082316 | bellard | break;
|
1532 | e6e5ad80 | bellard | case 0x2e: // BLT SRC ADDR 0x3f0000 |
1533 | 4e12cd94 | Avi Kivity | s->vga.gr[reg_index] = reg_value & 0x3f;
|
1534 | e6e5ad80 | bellard | break;
|
1535 | e6e5ad80 | bellard | case 0x31: // BLT STATUS/START |
1536 | e6e5ad80 | bellard | cirrus_write_bitblt(s, reg_value); |
1537 | e6e5ad80 | bellard | break;
|
1538 | e6e5ad80 | bellard | default:
|
1539 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1540 | e6e5ad80 | bellard | printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
|
1541 | e6e5ad80 | bellard | reg_value); |
1542 | e6e5ad80 | bellard | #endif
|
1543 | e6e5ad80 | bellard | break;
|
1544 | e6e5ad80 | bellard | } |
1545 | e6e5ad80 | bellard | } |
1546 | e6e5ad80 | bellard | |
1547 | e6e5ad80 | bellard | /***************************************
|
1548 | e6e5ad80 | bellard | *
|
1549 | e6e5ad80 | bellard | * I/O access between 0x3d4-0x3d5
|
1550 | e6e5ad80 | bellard | *
|
1551 | e6e5ad80 | bellard | ***************************************/
|
1552 | e6e5ad80 | bellard | |
1553 | b863d514 | Juan Quintela | static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index) |
1554 | e6e5ad80 | bellard | { |
1555 | e6e5ad80 | bellard | switch (reg_index) {
|
1556 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1557 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1558 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1559 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1560 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1561 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1562 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1563 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1564 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1565 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1566 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1567 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1568 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1569 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1570 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1571 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1572 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1573 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1574 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1575 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1576 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1577 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1578 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1579 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1580 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1581 | b863d514 | Juan Quintela | return s->vga.cr[s->vga.cr_index];
|
1582 | ca896ef3 | aurel32 | case 0x24: // Attribute Controller Toggle Readback (R) |
1583 | b863d514 | Juan Quintela | return (s->vga.ar_flip_flop << 7); |
1584 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1585 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1586 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1587 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1588 | e6e5ad80 | bellard | case 0x1d: // Overlay Extended Control |
1589 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1590 | e6e5ad80 | bellard | case 0x25: // Part Status |
1591 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1592 | b863d514 | Juan Quintela | return s->vga.cr[s->vga.cr_index];
|
1593 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1594 | b863d514 | Juan Quintela | return s->vga.ar_index & 0x3f; |
1595 | e6e5ad80 | bellard | break;
|
1596 | e6e5ad80 | bellard | default:
|
1597 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1598 | e6e5ad80 | bellard | printf("cirrus: inport cr_index %02x\n", reg_index);
|
1599 | e6e5ad80 | bellard | #endif
|
1600 | b863d514 | Juan Quintela | return 0xff; |
1601 | e6e5ad80 | bellard | } |
1602 | e6e5ad80 | bellard | } |
1603 | e6e5ad80 | bellard | |
1604 | 4ec1ce04 | Juan Quintela | static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value) |
1605 | e6e5ad80 | bellard | { |
1606 | 4ec1ce04 | Juan Quintela | switch (s->vga.cr_index) {
|
1607 | e6e5ad80 | bellard | case 0x00: // Standard VGA |
1608 | e6e5ad80 | bellard | case 0x01: // Standard VGA |
1609 | e6e5ad80 | bellard | case 0x02: // Standard VGA |
1610 | e6e5ad80 | bellard | case 0x03: // Standard VGA |
1611 | e6e5ad80 | bellard | case 0x04: // Standard VGA |
1612 | e6e5ad80 | bellard | case 0x05: // Standard VGA |
1613 | e6e5ad80 | bellard | case 0x06: // Standard VGA |
1614 | e6e5ad80 | bellard | case 0x07: // Standard VGA |
1615 | e6e5ad80 | bellard | case 0x08: // Standard VGA |
1616 | e6e5ad80 | bellard | case 0x09: // Standard VGA |
1617 | e6e5ad80 | bellard | case 0x0a: // Standard VGA |
1618 | e6e5ad80 | bellard | case 0x0b: // Standard VGA |
1619 | e6e5ad80 | bellard | case 0x0c: // Standard VGA |
1620 | e6e5ad80 | bellard | case 0x0d: // Standard VGA |
1621 | e6e5ad80 | bellard | case 0x0e: // Standard VGA |
1622 | e6e5ad80 | bellard | case 0x0f: // Standard VGA |
1623 | e6e5ad80 | bellard | case 0x10: // Standard VGA |
1624 | e6e5ad80 | bellard | case 0x11: // Standard VGA |
1625 | e6e5ad80 | bellard | case 0x12: // Standard VGA |
1626 | e6e5ad80 | bellard | case 0x13: // Standard VGA |
1627 | e6e5ad80 | bellard | case 0x14: // Standard VGA |
1628 | e6e5ad80 | bellard | case 0x15: // Standard VGA |
1629 | e6e5ad80 | bellard | case 0x16: // Standard VGA |
1630 | e6e5ad80 | bellard | case 0x17: // Standard VGA |
1631 | e6e5ad80 | bellard | case 0x18: // Standard VGA |
1632 | 4ec1ce04 | Juan Quintela | /* handle CR0-7 protection */
|
1633 | 4ec1ce04 | Juan Quintela | if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) { |
1634 | 4ec1ce04 | Juan Quintela | /* can always write bit 4 of CR7 */
|
1635 | 4ec1ce04 | Juan Quintela | if (s->vga.cr_index == 7) |
1636 | 4ec1ce04 | Juan Quintela | s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10); |
1637 | 4ec1ce04 | Juan Quintela | return;
|
1638 | 4ec1ce04 | Juan Quintela | } |
1639 | 4ec1ce04 | Juan Quintela | s->vga.cr[s->vga.cr_index] = reg_value; |
1640 | 4ec1ce04 | Juan Quintela | switch(s->vga.cr_index) {
|
1641 | 4ec1ce04 | Juan Quintela | case 0x00: |
1642 | 4ec1ce04 | Juan Quintela | case 0x04: |
1643 | 4ec1ce04 | Juan Quintela | case 0x05: |
1644 | 4ec1ce04 | Juan Quintela | case 0x06: |
1645 | 4ec1ce04 | Juan Quintela | case 0x07: |
1646 | 4ec1ce04 | Juan Quintela | case 0x11: |
1647 | 4ec1ce04 | Juan Quintela | case 0x17: |
1648 | 4ec1ce04 | Juan Quintela | s->vga.update_retrace_info(&s->vga); |
1649 | 4ec1ce04 | Juan Quintela | break;
|
1650 | 4ec1ce04 | Juan Quintela | } |
1651 | 4ec1ce04 | Juan Quintela | break;
|
1652 | e6e5ad80 | bellard | case 0x19: // Interlace End |
1653 | e6e5ad80 | bellard | case 0x1a: // Miscellaneous Control |
1654 | e6e5ad80 | bellard | case 0x1b: // Extended Display Control |
1655 | e6e5ad80 | bellard | case 0x1c: // Sync Adjust and Genlock |
1656 | ae184e4a | bellard | case 0x1d: // Overlay Extended Control |
1657 | 4ec1ce04 | Juan Quintela | s->vga.cr[s->vga.cr_index] = reg_value; |
1658 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1659 | e6e5ad80 | bellard | printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
|
1660 | 4ec1ce04 | Juan Quintela | s->vga.cr_index, reg_value); |
1661 | e6e5ad80 | bellard | #endif
|
1662 | e6e5ad80 | bellard | break;
|
1663 | e6e5ad80 | bellard | case 0x22: // Graphics Data Latches Readback (R) |
1664 | e6e5ad80 | bellard | case 0x24: // Attribute Controller Toggle Readback (R) |
1665 | e6e5ad80 | bellard | case 0x26: // Attribute Controller Index Readback (R) |
1666 | e6e5ad80 | bellard | case 0x27: // Part ID (R) |
1667 | e6e5ad80 | bellard | break;
|
1668 | e6e5ad80 | bellard | case 0x25: // Part Status |
1669 | e6e5ad80 | bellard | default:
|
1670 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1671 | 4ec1ce04 | Juan Quintela | printf("cirrus: outport cr_index %02x, cr_value %02x\n",
|
1672 | 4ec1ce04 | Juan Quintela | s->vga.cr_index, reg_value); |
1673 | e6e5ad80 | bellard | #endif
|
1674 | e6e5ad80 | bellard | break;
|
1675 | e6e5ad80 | bellard | } |
1676 | e6e5ad80 | bellard | } |
1677 | e6e5ad80 | bellard | |
1678 | e6e5ad80 | bellard | /***************************************
|
1679 | e6e5ad80 | bellard | *
|
1680 | e6e5ad80 | bellard | * memory-mapped I/O (bitblt)
|
1681 | e6e5ad80 | bellard | *
|
1682 | e6e5ad80 | bellard | ***************************************/
|
1683 | e6e5ad80 | bellard | |
1684 | e6e5ad80 | bellard | static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address) |
1685 | e6e5ad80 | bellard | { |
1686 | e6e5ad80 | bellard | int value = 0xff; |
1687 | e6e5ad80 | bellard | |
1688 | e6e5ad80 | bellard | switch (address) {
|
1689 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1690 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x00);
|
1691 | e6e5ad80 | bellard | break;
|
1692 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1693 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x10);
|
1694 | e6e5ad80 | bellard | break;
|
1695 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1696 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x12);
|
1697 | e6e5ad80 | bellard | break;
|
1698 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1699 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x14);
|
1700 | e6e5ad80 | bellard | break;
|
1701 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1702 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x01);
|
1703 | e6e5ad80 | bellard | break;
|
1704 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1705 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x11);
|
1706 | e6e5ad80 | bellard | break;
|
1707 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1708 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x13);
|
1709 | e6e5ad80 | bellard | break;
|
1710 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1711 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x15);
|
1712 | e6e5ad80 | bellard | break;
|
1713 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1714 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x20);
|
1715 | e6e5ad80 | bellard | break;
|
1716 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1717 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x21);
|
1718 | e6e5ad80 | bellard | break;
|
1719 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1720 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x22);
|
1721 | e6e5ad80 | bellard | break;
|
1722 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1723 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x23);
|
1724 | e6e5ad80 | bellard | break;
|
1725 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1726 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x24);
|
1727 | e6e5ad80 | bellard | break;
|
1728 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1729 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x25);
|
1730 | e6e5ad80 | bellard | break;
|
1731 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1732 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x26);
|
1733 | e6e5ad80 | bellard | break;
|
1734 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1735 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x27);
|
1736 | e6e5ad80 | bellard | break;
|
1737 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1738 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x28);
|
1739 | e6e5ad80 | bellard | break;
|
1740 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1741 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x29);
|
1742 | e6e5ad80 | bellard | break;
|
1743 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1744 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2a);
|
1745 | e6e5ad80 | bellard | break;
|
1746 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1747 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2c);
|
1748 | e6e5ad80 | bellard | break;
|
1749 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1750 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2d);
|
1751 | e6e5ad80 | bellard | break;
|
1752 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1753 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2e);
|
1754 | e6e5ad80 | bellard | break;
|
1755 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1756 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x2f);
|
1757 | e6e5ad80 | bellard | break;
|
1758 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1759 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x30);
|
1760 | e6e5ad80 | bellard | break;
|
1761 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1762 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x32);
|
1763 | e6e5ad80 | bellard | break;
|
1764 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1765 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x33);
|
1766 | a21ae81d | bellard | break;
|
1767 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1768 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x34);
|
1769 | e6e5ad80 | bellard | break;
|
1770 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1771 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x35);
|
1772 | e6e5ad80 | bellard | break;
|
1773 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1774 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x38);
|
1775 | e6e5ad80 | bellard | break;
|
1776 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1777 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x39);
|
1778 | e6e5ad80 | bellard | break;
|
1779 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1780 | f705db9d | Juan Quintela | value = cirrus_vga_read_gr(s, 0x31);
|
1781 | e6e5ad80 | bellard | break;
|
1782 | e6e5ad80 | bellard | default:
|
1783 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1784 | e6e5ad80 | bellard | printf("cirrus: mmio read - address 0x%04x\n", address);
|
1785 | e6e5ad80 | bellard | #endif
|
1786 | e6e5ad80 | bellard | break;
|
1787 | e6e5ad80 | bellard | } |
1788 | e6e5ad80 | bellard | |
1789 | e6e5ad80 | bellard | return (uint8_t) value;
|
1790 | e6e5ad80 | bellard | } |
1791 | e6e5ad80 | bellard | |
1792 | e6e5ad80 | bellard | static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address, |
1793 | e6e5ad80 | bellard | uint8_t value) |
1794 | e6e5ad80 | bellard | { |
1795 | e6e5ad80 | bellard | switch (address) {
|
1796 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 0): |
1797 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x00, value);
|
1798 | e6e5ad80 | bellard | break;
|
1799 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 1): |
1800 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x10, value);
|
1801 | e6e5ad80 | bellard | break;
|
1802 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 2): |
1803 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x12, value);
|
1804 | e6e5ad80 | bellard | break;
|
1805 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTBGCOLOR + 3): |
1806 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x14, value);
|
1807 | e6e5ad80 | bellard | break;
|
1808 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 0): |
1809 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x01, value);
|
1810 | e6e5ad80 | bellard | break;
|
1811 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 1): |
1812 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x11, value);
|
1813 | e6e5ad80 | bellard | break;
|
1814 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 2): |
1815 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x13, value);
|
1816 | e6e5ad80 | bellard | break;
|
1817 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTFGCOLOR + 3): |
1818 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x15, value);
|
1819 | e6e5ad80 | bellard | break;
|
1820 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 0): |
1821 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x20, value);
|
1822 | e6e5ad80 | bellard | break;
|
1823 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTWIDTH + 1): |
1824 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x21, value);
|
1825 | e6e5ad80 | bellard | break;
|
1826 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 0): |
1827 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x22, value);
|
1828 | e6e5ad80 | bellard | break;
|
1829 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTHEIGHT + 1): |
1830 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x23, value);
|
1831 | e6e5ad80 | bellard | break;
|
1832 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 0): |
1833 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x24, value);
|
1834 | e6e5ad80 | bellard | break;
|
1835 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTPITCH + 1): |
1836 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x25, value);
|
1837 | e6e5ad80 | bellard | break;
|
1838 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 0): |
1839 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x26, value);
|
1840 | e6e5ad80 | bellard | break;
|
1841 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCPITCH + 1): |
1842 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x27, value);
|
1843 | e6e5ad80 | bellard | break;
|
1844 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 0): |
1845 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x28, value);
|
1846 | e6e5ad80 | bellard | break;
|
1847 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 1): |
1848 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x29, value);
|
1849 | e6e5ad80 | bellard | break;
|
1850 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 2): |
1851 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2a, value);
|
1852 | e6e5ad80 | bellard | break;
|
1853 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTDESTADDR + 3): |
1854 | e6e5ad80 | bellard | /* ignored */
|
1855 | e6e5ad80 | bellard | break;
|
1856 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 0): |
1857 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2c, value);
|
1858 | e6e5ad80 | bellard | break;
|
1859 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 1): |
1860 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2d, value);
|
1861 | e6e5ad80 | bellard | break;
|
1862 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTSRCADDR + 2): |
1863 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2e, value);
|
1864 | e6e5ad80 | bellard | break;
|
1865 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTWRITEMASK:
|
1866 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x2f, value);
|
1867 | e6e5ad80 | bellard | break;
|
1868 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTMODE:
|
1869 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x30, value);
|
1870 | e6e5ad80 | bellard | break;
|
1871 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTROP:
|
1872 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x32, value);
|
1873 | e6e5ad80 | bellard | break;
|
1874 | a21ae81d | bellard | case CIRRUS_MMIO_BLTMODEEXT:
|
1875 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x33, value);
|
1876 | a21ae81d | bellard | break;
|
1877 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0): |
1878 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x34, value);
|
1879 | e6e5ad80 | bellard | break;
|
1880 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1): |
1881 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x35, value);
|
1882 | e6e5ad80 | bellard | break;
|
1883 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0): |
1884 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x38, value);
|
1885 | e6e5ad80 | bellard | break;
|
1886 | e6e5ad80 | bellard | case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1): |
1887 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x39, value);
|
1888 | e6e5ad80 | bellard | break;
|
1889 | e6e5ad80 | bellard | case CIRRUS_MMIO_BLTSTATUS:
|
1890 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(s, 0x31, value);
|
1891 | e6e5ad80 | bellard | break;
|
1892 | e6e5ad80 | bellard | default:
|
1893 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1894 | e6e5ad80 | bellard | printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
|
1895 | e6e5ad80 | bellard | address, value); |
1896 | e6e5ad80 | bellard | #endif
|
1897 | e6e5ad80 | bellard | break;
|
1898 | e6e5ad80 | bellard | } |
1899 | e6e5ad80 | bellard | } |
1900 | e6e5ad80 | bellard | |
1901 | e6e5ad80 | bellard | /***************************************
|
1902 | e6e5ad80 | bellard | *
|
1903 | e6e5ad80 | bellard | * write mode 4/5
|
1904 | e6e5ad80 | bellard | *
|
1905 | e6e5ad80 | bellard | ***************************************/
|
1906 | e6e5ad80 | bellard | |
1907 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, |
1908 | e6e5ad80 | bellard | unsigned mode,
|
1909 | e6e5ad80 | bellard | unsigned offset,
|
1910 | e6e5ad80 | bellard | uint32_t mem_value) |
1911 | e6e5ad80 | bellard | { |
1912 | e6e5ad80 | bellard | int x;
|
1913 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1914 | e6e5ad80 | bellard | uint8_t *dst; |
1915 | e6e5ad80 | bellard | |
1916 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
1917 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1918 | e6e5ad80 | bellard | if (val & 0x80) { |
1919 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1920 | e6e5ad80 | bellard | } else if (mode == 5) { |
1921 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1922 | e6e5ad80 | bellard | } |
1923 | e6e5ad80 | bellard | val <<= 1;
|
1924 | 0b74ed78 | bellard | dst++; |
1925 | e6e5ad80 | bellard | } |
1926 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, offset, 8);
|
1927 | e6e5ad80 | bellard | } |
1928 | e6e5ad80 | bellard | |
1929 | e6e5ad80 | bellard | static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, |
1930 | e6e5ad80 | bellard | unsigned mode,
|
1931 | e6e5ad80 | bellard | unsigned offset,
|
1932 | e6e5ad80 | bellard | uint32_t mem_value) |
1933 | e6e5ad80 | bellard | { |
1934 | e6e5ad80 | bellard | int x;
|
1935 | e6e5ad80 | bellard | unsigned val = mem_value;
|
1936 | e6e5ad80 | bellard | uint8_t *dst; |
1937 | e6e5ad80 | bellard | |
1938 | 4e12cd94 | Avi Kivity | dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask); |
1939 | e6e5ad80 | bellard | for (x = 0; x < 8; x++) { |
1940 | e6e5ad80 | bellard | if (val & 0x80) { |
1941 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr1; |
1942 | 4e12cd94 | Avi Kivity | *(dst + 1) = s->vga.gr[0x11]; |
1943 | e6e5ad80 | bellard | } else if (mode == 5) { |
1944 | 0b74ed78 | bellard | *dst = s->cirrus_shadow_gr0; |
1945 | 4e12cd94 | Avi Kivity | *(dst + 1) = s->vga.gr[0x10]; |
1946 | e6e5ad80 | bellard | } |
1947 | e6e5ad80 | bellard | val <<= 1;
|
1948 | 0b74ed78 | bellard | dst += 2;
|
1949 | e6e5ad80 | bellard | } |
1950 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, offset, 16);
|
1951 | e6e5ad80 | bellard | } |
1952 | e6e5ad80 | bellard | |
1953 | e6e5ad80 | bellard | /***************************************
|
1954 | e6e5ad80 | bellard | *
|
1955 | e6e5ad80 | bellard | * memory access between 0xa0000-0xbffff
|
1956 | e6e5ad80 | bellard | *
|
1957 | e6e5ad80 | bellard | ***************************************/
|
1958 | e6e5ad80 | bellard | |
1959 | a815b166 | Avi Kivity | static uint64_t cirrus_vga_mem_read(void *opaque, |
1960 | a8170e5e | Avi Kivity | hwaddr addr, |
1961 | a815b166 | Avi Kivity | uint32_t size) |
1962 | e6e5ad80 | bellard | { |
1963 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
1964 | e6e5ad80 | bellard | unsigned bank_index;
|
1965 | e6e5ad80 | bellard | unsigned bank_offset;
|
1966 | e6e5ad80 | bellard | uint32_t val; |
1967 | e6e5ad80 | bellard | |
1968 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) == 0) { |
1969 | b2a5e761 | Avi Kivity | return vga_mem_readb(&s->vga, addr);
|
1970 | e6e5ad80 | bellard | } |
1971 | e6e5ad80 | bellard | |
1972 | e6e5ad80 | bellard | if (addr < 0x10000) { |
1973 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
1974 | e6e5ad80 | bellard | /* video memory */
|
1975 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
1976 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
1977 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
1978 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
1979 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
1980 | e6e5ad80 | bellard | bank_offset <<= 4;
|
1981 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
1982 | e6e5ad80 | bellard | bank_offset <<= 3;
|
1983 | e6e5ad80 | bellard | } |
1984 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
1985 | 4e12cd94 | Avi Kivity | val = *(s->vga.vram_ptr + bank_offset); |
1986 | e6e5ad80 | bellard | } else
|
1987 | e6e5ad80 | bellard | val = 0xff;
|
1988 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
1989 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
1990 | e6e5ad80 | bellard | val = 0xff;
|
1991 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
1992 | e6e5ad80 | bellard | val = cirrus_mmio_blt_read(s, addr & 0xff);
|
1993 | e6e5ad80 | bellard | } |
1994 | e6e5ad80 | bellard | } else {
|
1995 | e6e5ad80 | bellard | val = 0xff;
|
1996 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
1997 | 0bf9e31a | Blue Swirl | printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr); |
1998 | e6e5ad80 | bellard | #endif
|
1999 | e6e5ad80 | bellard | } |
2000 | e6e5ad80 | bellard | return val;
|
2001 | e6e5ad80 | bellard | } |
2002 | e6e5ad80 | bellard | |
2003 | a815b166 | Avi Kivity | static void cirrus_vga_mem_write(void *opaque, |
2004 | a8170e5e | Avi Kivity | hwaddr addr, |
2005 | a815b166 | Avi Kivity | uint64_t mem_value, |
2006 | a815b166 | Avi Kivity | uint32_t size) |
2007 | e6e5ad80 | bellard | { |
2008 | e6e5ad80 | bellard | CirrusVGAState *s = opaque; |
2009 | e6e5ad80 | bellard | unsigned bank_index;
|
2010 | e6e5ad80 | bellard | unsigned bank_offset;
|
2011 | e6e5ad80 | bellard | unsigned mode;
|
2012 | e6e5ad80 | bellard | |
2013 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x07] & 0x01) == 0) { |
2014 | b2a5e761 | Avi Kivity | vga_mem_writeb(&s->vga, addr, mem_value); |
2015 | e6e5ad80 | bellard | return;
|
2016 | e6e5ad80 | bellard | } |
2017 | e6e5ad80 | bellard | |
2018 | e6e5ad80 | bellard | if (addr < 0x10000) { |
2019 | e6e5ad80 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
2020 | e6e5ad80 | bellard | /* bitblt */
|
2021 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) mem_value; |
2022 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2023 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2024 | e6e5ad80 | bellard | } |
2025 | e6e5ad80 | bellard | } else {
|
2026 | e6e5ad80 | bellard | /* video memory */
|
2027 | e6e5ad80 | bellard | bank_index = addr >> 15;
|
2028 | e6e5ad80 | bellard | bank_offset = addr & 0x7fff;
|
2029 | e6e5ad80 | bellard | if (bank_offset < s->cirrus_bank_limit[bank_index]) {
|
2030 | e6e5ad80 | bellard | bank_offset += s->cirrus_bank_base[bank_index]; |
2031 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2032 | e6e5ad80 | bellard | bank_offset <<= 4;
|
2033 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2034 | e6e5ad80 | bellard | bank_offset <<= 3;
|
2035 | e6e5ad80 | bellard | } |
2036 | e6e5ad80 | bellard | bank_offset &= s->cirrus_addr_mask; |
2037 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2038 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2039 | 4e12cd94 | Avi Kivity | *(s->vga.vram_ptr + bank_offset) = mem_value; |
2040 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, bank_offset, |
2041 | fd4aa979 | Blue Swirl | sizeof(mem_value));
|
2042 | e6e5ad80 | bellard | } else {
|
2043 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
2044 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, |
2045 | e6e5ad80 | bellard | bank_offset, |
2046 | e6e5ad80 | bellard | mem_value); |
2047 | e6e5ad80 | bellard | } else {
|
2048 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, |
2049 | e6e5ad80 | bellard | bank_offset, |
2050 | e6e5ad80 | bellard | mem_value); |
2051 | e6e5ad80 | bellard | } |
2052 | e6e5ad80 | bellard | } |
2053 | e6e5ad80 | bellard | } |
2054 | e6e5ad80 | bellard | } |
2055 | e6e5ad80 | bellard | } else if (addr >= 0x18000 && addr < 0x18100) { |
2056 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2057 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x04) { |
2058 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
|
2059 | e6e5ad80 | bellard | } |
2060 | e6e5ad80 | bellard | } else {
|
2061 | e6e5ad80 | bellard | #ifdef DEBUG_CIRRUS
|
2062 | 08406b03 | malc | printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr, |
2063 | 08406b03 | malc | mem_value); |
2064 | e6e5ad80 | bellard | #endif
|
2065 | e6e5ad80 | bellard | } |
2066 | e6e5ad80 | bellard | } |
2067 | e6e5ad80 | bellard | |
2068 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_vga_mem_ops = { |
2069 | b1950430 | Avi Kivity | .read = cirrus_vga_mem_read, |
2070 | b1950430 | Avi Kivity | .write = cirrus_vga_mem_write, |
2071 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2072 | a815b166 | Avi Kivity | .impl = { |
2073 | a815b166 | Avi Kivity | .min_access_size = 1,
|
2074 | a815b166 | Avi Kivity | .max_access_size = 1,
|
2075 | a815b166 | Avi Kivity | }, |
2076 | e6e5ad80 | bellard | }; |
2077 | e6e5ad80 | bellard | |
2078 | e6e5ad80 | bellard | /***************************************
|
2079 | e6e5ad80 | bellard | *
|
2080 | a5082316 | bellard | * hardware cursor
|
2081 | a5082316 | bellard | *
|
2082 | a5082316 | bellard | ***************************************/
|
2083 | a5082316 | bellard | |
2084 | a5082316 | bellard | static inline void invalidate_cursor1(CirrusVGAState *s) |
2085 | a5082316 | bellard | { |
2086 | a5082316 | bellard | if (s->last_hw_cursor_size) {
|
2087 | 4e12cd94 | Avi Kivity | vga_invalidate_scanlines(&s->vga, |
2088 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_start, |
2089 | a5082316 | bellard | s->last_hw_cursor_y + s->last_hw_cursor_y_end); |
2090 | a5082316 | bellard | } |
2091 | a5082316 | bellard | } |
2092 | a5082316 | bellard | |
2093 | a5082316 | bellard | static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s) |
2094 | a5082316 | bellard | { |
2095 | a5082316 | bellard | const uint8_t *src;
|
2096 | a5082316 | bellard | uint32_t content; |
2097 | a5082316 | bellard | int y, y_min, y_max;
|
2098 | a5082316 | bellard | |
2099 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2100 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2101 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3c) * 256; |
2102 | a5082316 | bellard | y_min = 64;
|
2103 | a5082316 | bellard | y_max = -1;
|
2104 | a5082316 | bellard | for(y = 0; y < 64; y++) { |
2105 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2106 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2107 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2108 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2109 | a5082316 | bellard | if (content) {
|
2110 | a5082316 | bellard | if (y < y_min)
|
2111 | a5082316 | bellard | y_min = y; |
2112 | a5082316 | bellard | if (y > y_max)
|
2113 | a5082316 | bellard | y_max = y; |
2114 | a5082316 | bellard | } |
2115 | a5082316 | bellard | src += 16;
|
2116 | a5082316 | bellard | } |
2117 | a5082316 | bellard | } else {
|
2118 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3f) * 256; |
2119 | a5082316 | bellard | y_min = 32;
|
2120 | a5082316 | bellard | y_max = -1;
|
2121 | a5082316 | bellard | for(y = 0; y < 32; y++) { |
2122 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2123 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2124 | a5082316 | bellard | if (content) {
|
2125 | a5082316 | bellard | if (y < y_min)
|
2126 | a5082316 | bellard | y_min = y; |
2127 | a5082316 | bellard | if (y > y_max)
|
2128 | a5082316 | bellard | y_max = y; |
2129 | a5082316 | bellard | } |
2130 | a5082316 | bellard | src += 4;
|
2131 | a5082316 | bellard | } |
2132 | a5082316 | bellard | } |
2133 | a5082316 | bellard | if (y_min > y_max) {
|
2134 | a5082316 | bellard | s->last_hw_cursor_y_start = 0;
|
2135 | a5082316 | bellard | s->last_hw_cursor_y_end = 0;
|
2136 | a5082316 | bellard | } else {
|
2137 | a5082316 | bellard | s->last_hw_cursor_y_start = y_min; |
2138 | a5082316 | bellard | s->last_hw_cursor_y_end = y_max + 1;
|
2139 | a5082316 | bellard | } |
2140 | a5082316 | bellard | } |
2141 | a5082316 | bellard | |
2142 | a5082316 | bellard | /* NOTE: we do not currently handle the cursor bitmap change, so we
|
2143 | a5082316 | bellard | update the cursor only if it moves. */
|
2144 | a4a2f59c | Juan Quintela | static void cirrus_cursor_invalidate(VGACommonState *s1) |
2145 | a5082316 | bellard | { |
2146 | 4e12cd94 | Avi Kivity | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
2147 | a5082316 | bellard | int size;
|
2148 | a5082316 | bellard | |
2149 | 4e12cd94 | Avi Kivity | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) { |
2150 | a5082316 | bellard | size = 0;
|
2151 | a5082316 | bellard | } else {
|
2152 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) |
2153 | a5082316 | bellard | size = 64;
|
2154 | a5082316 | bellard | else
|
2155 | a5082316 | bellard | size = 32;
|
2156 | a5082316 | bellard | } |
2157 | a5082316 | bellard | /* invalidate last cursor and new cursor if any change */
|
2158 | a5082316 | bellard | if (s->last_hw_cursor_size != size ||
|
2159 | a5082316 | bellard | s->last_hw_cursor_x != s->hw_cursor_x || |
2160 | a5082316 | bellard | s->last_hw_cursor_y != s->hw_cursor_y) { |
2161 | a5082316 | bellard | |
2162 | a5082316 | bellard | invalidate_cursor1(s); |
2163 | 3b46e624 | ths | |
2164 | a5082316 | bellard | s->last_hw_cursor_size = size; |
2165 | a5082316 | bellard | s->last_hw_cursor_x = s->hw_cursor_x; |
2166 | a5082316 | bellard | s->last_hw_cursor_y = s->hw_cursor_y; |
2167 | a5082316 | bellard | /* compute the real cursor min and max y */
|
2168 | a5082316 | bellard | cirrus_cursor_compute_yrange(s); |
2169 | a5082316 | bellard | invalidate_cursor1(s); |
2170 | a5082316 | bellard | } |
2171 | a5082316 | bellard | } |
2172 | a5082316 | bellard | |
2173 | 94d7b483 | Blue Swirl | #define DEPTH 8 |
2174 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_template.h" |
2175 | 94d7b483 | Blue Swirl | |
2176 | 94d7b483 | Blue Swirl | #define DEPTH 16 |
2177 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_template.h" |
2178 | 94d7b483 | Blue Swirl | |
2179 | 94d7b483 | Blue Swirl | #define DEPTH 32 |
2180 | 47b43a1f | Paolo Bonzini | #include "cirrus_vga_template.h" |
2181 | 94d7b483 | Blue Swirl | |
2182 | a4a2f59c | Juan Quintela | static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y) |
2183 | a5082316 | bellard | { |
2184 | 4e12cd94 | Avi Kivity | CirrusVGAState *s = container_of(s1, CirrusVGAState, vga); |
2185 | c78f7137 | Gerd Hoffmann | DisplaySurface *surface = qemu_console_surface(s->vga.con); |
2186 | a5082316 | bellard | int w, h, bpp, x1, x2, poffset;
|
2187 | a5082316 | bellard | unsigned int color0, color1; |
2188 | a5082316 | bellard | const uint8_t *palette, *src;
|
2189 | a5082316 | bellard | uint32_t content; |
2190 | 3b46e624 | ths | |
2191 | 4e12cd94 | Avi Kivity | if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) |
2192 | a5082316 | bellard | return;
|
2193 | a5082316 | bellard | /* fast test to see if the cursor intersects with the scan line */
|
2194 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2195 | a5082316 | bellard | h = 64;
|
2196 | a5082316 | bellard | } else {
|
2197 | a5082316 | bellard | h = 32;
|
2198 | a5082316 | bellard | } |
2199 | a5082316 | bellard | if (scr_y < s->hw_cursor_y ||
|
2200 | a5082316 | bellard | scr_y >= (s->hw_cursor_y + h)) |
2201 | a5082316 | bellard | return;
|
2202 | 3b46e624 | ths | |
2203 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024; |
2204 | 4e12cd94 | Avi Kivity | if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) { |
2205 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3c) * 256; |
2206 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 16;
|
2207 | a5082316 | bellard | poffset = 8;
|
2208 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2209 | a5082316 | bellard | ((uint32_t *)src)[1] |
|
2210 | a5082316 | bellard | ((uint32_t *)src)[2] |
|
2211 | a5082316 | bellard | ((uint32_t *)src)[3];
|
2212 | a5082316 | bellard | } else {
|
2213 | 4e12cd94 | Avi Kivity | src += (s->vga.sr[0x13] & 0x3f) * 256; |
2214 | a5082316 | bellard | src += (scr_y - s->hw_cursor_y) * 4;
|
2215 | a5082316 | bellard | poffset = 128;
|
2216 | a5082316 | bellard | content = ((uint32_t *)src)[0] |
|
2217 | a5082316 | bellard | ((uint32_t *)(src + 128))[0]; |
2218 | a5082316 | bellard | } |
2219 | a5082316 | bellard | /* if nothing to draw, no need to continue */
|
2220 | a5082316 | bellard | if (!content)
|
2221 | a5082316 | bellard | return;
|
2222 | a5082316 | bellard | w = h; |
2223 | a5082316 | bellard | |
2224 | a5082316 | bellard | x1 = s->hw_cursor_x; |
2225 | 4e12cd94 | Avi Kivity | if (x1 >= s->vga.last_scr_width)
|
2226 | a5082316 | bellard | return;
|
2227 | a5082316 | bellard | x2 = s->hw_cursor_x + w; |
2228 | 4e12cd94 | Avi Kivity | if (x2 > s->vga.last_scr_width)
|
2229 | 4e12cd94 | Avi Kivity | x2 = s->vga.last_scr_width; |
2230 | a5082316 | bellard | w = x2 - x1; |
2231 | a5082316 | bellard | palette = s->cirrus_hidden_palette; |
2232 | 4e12cd94 | Avi Kivity | color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]), |
2233 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0x0 * 3 + 1]), |
2234 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0x0 * 3 + 2])); |
2235 | 4e12cd94 | Avi Kivity | color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]), |
2236 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0xf * 3 + 1]), |
2237 | 4e12cd94 | Avi Kivity | c6_to_8(palette[0xf * 3 + 2])); |
2238 | c78f7137 | Gerd Hoffmann | bpp = surface_bytes_per_pixel(surface); |
2239 | a5082316 | bellard | d1 += x1 * bpp; |
2240 | c78f7137 | Gerd Hoffmann | switch (surface_bits_per_pixel(surface)) {
|
2241 | a5082316 | bellard | default:
|
2242 | a5082316 | bellard | break;
|
2243 | a5082316 | bellard | case 8: |
2244 | a5082316 | bellard | vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
|
2245 | a5082316 | bellard | break;
|
2246 | a5082316 | bellard | case 15: |
2247 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
|
2248 | a5082316 | bellard | break;
|
2249 | a5082316 | bellard | case 16: |
2250 | a5082316 | bellard | vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
|
2251 | a5082316 | bellard | break;
|
2252 | a5082316 | bellard | case 32: |
2253 | a5082316 | bellard | vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
|
2254 | a5082316 | bellard | break;
|
2255 | a5082316 | bellard | } |
2256 | a5082316 | bellard | } |
2257 | a5082316 | bellard | |
2258 | a5082316 | bellard | /***************************************
|
2259 | a5082316 | bellard | *
|
2260 | e6e5ad80 | bellard | * LFB memory access
|
2261 | e6e5ad80 | bellard | *
|
2262 | e6e5ad80 | bellard | ***************************************/
|
2263 | e6e5ad80 | bellard | |
2264 | a8170e5e | Avi Kivity | static uint64_t cirrus_linear_read(void *opaque, hwaddr addr, |
2265 | 899adf81 | Avi Kivity | unsigned size)
|
2266 | e6e5ad80 | bellard | { |
2267 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2268 | e6e5ad80 | bellard | uint32_t ret; |
2269 | e6e5ad80 | bellard | |
2270 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2271 | e6e5ad80 | bellard | |
2272 | 4e12cd94 | Avi Kivity | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
2273 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2274 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2275 | e6e5ad80 | bellard | ret = cirrus_mmio_blt_read(s, addr & 0xff);
|
2276 | e6e5ad80 | bellard | } else if (0) { |
2277 | e6e5ad80 | bellard | /* XXX handle bitblt */
|
2278 | e6e5ad80 | bellard | ret = 0xff;
|
2279 | e6e5ad80 | bellard | } else {
|
2280 | e6e5ad80 | bellard | /* video memory */
|
2281 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2282 | e6e5ad80 | bellard | addr <<= 4;
|
2283 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2284 | e6e5ad80 | bellard | addr <<= 3;
|
2285 | e6e5ad80 | bellard | } |
2286 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2287 | 4e12cd94 | Avi Kivity | ret = *(s->vga.vram_ptr + addr); |
2288 | e6e5ad80 | bellard | } |
2289 | e6e5ad80 | bellard | |
2290 | e6e5ad80 | bellard | return ret;
|
2291 | e6e5ad80 | bellard | } |
2292 | e6e5ad80 | bellard | |
2293 | a8170e5e | Avi Kivity | static void cirrus_linear_write(void *opaque, hwaddr addr, |
2294 | 899adf81 | Avi Kivity | uint64_t val, unsigned size)
|
2295 | e6e5ad80 | bellard | { |
2296 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2297 | e6e5ad80 | bellard | unsigned mode;
|
2298 | e6e5ad80 | bellard | |
2299 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2300 | 3b46e624 | ths | |
2301 | 4e12cd94 | Avi Kivity | if (((s->vga.sr[0x17] & 0x44) == 0x44) && |
2302 | 78e127ef | bellard | ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) { |
2303 | e6e5ad80 | bellard | /* memory-mapped I/O */
|
2304 | e6e5ad80 | bellard | cirrus_mmio_blt_write(s, addr & 0xff, val);
|
2305 | e6e5ad80 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2306 | e6e5ad80 | bellard | /* bitblt */
|
2307 | e6e5ad80 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2308 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2309 | e6e5ad80 | bellard | cirrus_bitblt_cputovideo_next(s); |
2310 | e6e5ad80 | bellard | } |
2311 | e6e5ad80 | bellard | } else {
|
2312 | e6e5ad80 | bellard | /* video memory */
|
2313 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2314 | e6e5ad80 | bellard | addr <<= 4;
|
2315 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2316 | e6e5ad80 | bellard | addr <<= 3;
|
2317 | e6e5ad80 | bellard | } |
2318 | e6e5ad80 | bellard | addr &= s->cirrus_addr_mask; |
2319 | e6e5ad80 | bellard | |
2320 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2321 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2322 | 4e12cd94 | Avi Kivity | *(s->vga.vram_ptr + addr) = (uint8_t) val; |
2323 | fd4aa979 | Blue Swirl | memory_region_set_dirty(&s->vga.vram, addr, 1);
|
2324 | e6e5ad80 | bellard | } else {
|
2325 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) != 0x14) { |
2326 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val); |
2327 | e6e5ad80 | bellard | } else {
|
2328 | e6e5ad80 | bellard | cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val); |
2329 | e6e5ad80 | bellard | } |
2330 | e6e5ad80 | bellard | } |
2331 | e6e5ad80 | bellard | } |
2332 | e6e5ad80 | bellard | } |
2333 | e6e5ad80 | bellard | |
2334 | a5082316 | bellard | /***************************************
|
2335 | a5082316 | bellard | *
|
2336 | a5082316 | bellard | * system to screen memory access
|
2337 | a5082316 | bellard | *
|
2338 | a5082316 | bellard | ***************************************/
|
2339 | a5082316 | bellard | |
2340 | a5082316 | bellard | |
2341 | 4e56f089 | Avi Kivity | static uint64_t cirrus_linear_bitblt_read(void *opaque, |
2342 | a8170e5e | Avi Kivity | hwaddr addr, |
2343 | 4e56f089 | Avi Kivity | unsigned size)
|
2344 | a5082316 | bellard | { |
2345 | 4e56f089 | Avi Kivity | CirrusVGAState *s = opaque; |
2346 | a5082316 | bellard | uint32_t ret; |
2347 | a5082316 | bellard | |
2348 | a5082316 | bellard | /* XXX handle bitblt */
|
2349 | 4e56f089 | Avi Kivity | (void)s;
|
2350 | a5082316 | bellard | ret = 0xff;
|
2351 | a5082316 | bellard | return ret;
|
2352 | a5082316 | bellard | } |
2353 | a5082316 | bellard | |
2354 | 4e56f089 | Avi Kivity | static void cirrus_linear_bitblt_write(void *opaque, |
2355 | a8170e5e | Avi Kivity | hwaddr addr, |
2356 | 4e56f089 | Avi Kivity | uint64_t val, |
2357 | 4e56f089 | Avi Kivity | unsigned size)
|
2358 | a5082316 | bellard | { |
2359 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2360 | a5082316 | bellard | |
2361 | a5082316 | bellard | if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
|
2362 | a5082316 | bellard | /* bitblt */
|
2363 | a5082316 | bellard | *s->cirrus_srcptr++ = (uint8_t) val; |
2364 | a5082316 | bellard | if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
|
2365 | a5082316 | bellard | cirrus_bitblt_cputovideo_next(s); |
2366 | a5082316 | bellard | } |
2367 | a5082316 | bellard | } |
2368 | a5082316 | bellard | } |
2369 | a5082316 | bellard | |
2370 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { |
2371 | b1950430 | Avi Kivity | .read = cirrus_linear_bitblt_read, |
2372 | b1950430 | Avi Kivity | .write = cirrus_linear_bitblt_write, |
2373 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2374 | 4e56f089 | Avi Kivity | .impl = { |
2375 | 4e56f089 | Avi Kivity | .min_access_size = 1,
|
2376 | 4e56f089 | Avi Kivity | .max_access_size = 1,
|
2377 | 4e56f089 | Avi Kivity | }, |
2378 | a5082316 | bellard | }; |
2379 | a5082316 | bellard | |
2380 | b1950430 | Avi Kivity | static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank) |
2381 | b1950430 | Avi Kivity | { |
2382 | 7969d9ed | Avi Kivity | MemoryRegion *mr = &s->cirrus_bank[bank]; |
2383 | 7969d9ed | Avi Kivity | bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
|
2384 | 4e12cd94 | Avi Kivity | && !((s->vga.sr[0x07] & 0x01) == 0) |
2385 | 4e12cd94 | Avi Kivity | && !((s->vga.gr[0x0B] & 0x14) == 0x14) |
2386 | 7969d9ed | Avi Kivity | && !(s->vga.gr[0x0B] & 0x02); |
2387 | 7969d9ed | Avi Kivity | |
2388 | 7969d9ed | Avi Kivity | memory_region_set_enabled(mr, enabled); |
2389 | 7969d9ed | Avi Kivity | memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]); |
2390 | b1950430 | Avi Kivity | } |
2391 | 2bec46dc | aliguori | |
2392 | b1950430 | Avi Kivity | static void map_linear_vram(CirrusVGAState *s) |
2393 | b1950430 | Avi Kivity | { |
2394 | 4c08fd1e | Jan Kiszka | if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
|
2395 | b1950430 | Avi Kivity | s->linear_vram = true;
|
2396 | b1950430 | Avi Kivity | memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1); |
2397 | b1950430 | Avi Kivity | } |
2398 | b1950430 | Avi Kivity | map_linear_vram_bank(s, 0);
|
2399 | b1950430 | Avi Kivity | map_linear_vram_bank(s, 1);
|
2400 | 2bec46dc | aliguori | } |
2401 | 2bec46dc | aliguori | |
2402 | 2bec46dc | aliguori | static void unmap_linear_vram(CirrusVGAState *s) |
2403 | 2bec46dc | aliguori | { |
2404 | 4c08fd1e | Jan Kiszka | if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
|
2405 | b1950430 | Avi Kivity | s->linear_vram = false;
|
2406 | b1950430 | Avi Kivity | memory_region_del_subregion(&s->pci_bar, &s->vga.vram); |
2407 | 4516e45f | Jan Kiszka | } |
2408 | 7969d9ed | Avi Kivity | memory_region_set_enabled(&s->cirrus_bank[0], false); |
2409 | 7969d9ed | Avi Kivity | memory_region_set_enabled(&s->cirrus_bank[1], false); |
2410 | 2bec46dc | aliguori | } |
2411 | 2bec46dc | aliguori | |
2412 | 8926b517 | bellard | /* Compute the memory access functions */
|
2413 | 8926b517 | bellard | static void cirrus_update_memory_access(CirrusVGAState *s) |
2414 | 8926b517 | bellard | { |
2415 | 8926b517 | bellard | unsigned mode;
|
2416 | 8926b517 | bellard | |
2417 | 64c048f4 | Avi Kivity | memory_region_transaction_begin(); |
2418 | 4e12cd94 | Avi Kivity | if ((s->vga.sr[0x17] & 0x44) == 0x44) { |
2419 | 8926b517 | bellard | goto generic_io;
|
2420 | 8926b517 | bellard | } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) { |
2421 | 8926b517 | bellard | goto generic_io;
|
2422 | 8926b517 | bellard | } else {
|
2423 | 4e12cd94 | Avi Kivity | if ((s->vga.gr[0x0B] & 0x14) == 0x14) { |
2424 | 8926b517 | bellard | goto generic_io;
|
2425 | 4e12cd94 | Avi Kivity | } else if (s->vga.gr[0x0B] & 0x02) { |
2426 | 8926b517 | bellard | goto generic_io;
|
2427 | 8926b517 | bellard | } |
2428 | 3b46e624 | ths | |
2429 | 4e12cd94 | Avi Kivity | mode = s->vga.gr[0x05] & 0x7; |
2430 | 4e12cd94 | Avi Kivity | if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) { |
2431 | 2bec46dc | aliguori | map_linear_vram(s); |
2432 | 8926b517 | bellard | } else {
|
2433 | 8926b517 | bellard | generic_io:
|
2434 | 2bec46dc | aliguori | unmap_linear_vram(s); |
2435 | 8926b517 | bellard | } |
2436 | 8926b517 | bellard | } |
2437 | 64c048f4 | Avi Kivity | memory_region_transaction_commit(); |
2438 | 8926b517 | bellard | } |
2439 | 8926b517 | bellard | |
2440 | 8926b517 | bellard | |
2441 | e6e5ad80 | bellard | /* I/O ports */
|
2442 | e6e5ad80 | bellard | |
2443 | c75e6d8e | Julien Grall | static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr, |
2444 | c75e6d8e | Julien Grall | unsigned size)
|
2445 | e6e5ad80 | bellard | { |
2446 | b6343073 | Juan Quintela | CirrusVGAState *c = opaque; |
2447 | b6343073 | Juan Quintela | VGACommonState *s = &c->vga; |
2448 | e6e5ad80 | bellard | int val, index;
|
2449 | e6e5ad80 | bellard | |
2450 | bd8f2f5d | Jan Kiszka | qemu_flush_coalesced_mmio_buffer(); |
2451 | c75e6d8e | Julien Grall | addr += 0x3b0;
|
2452 | bd8f2f5d | Jan Kiszka | |
2453 | b6343073 | Juan Quintela | if (vga_ioport_invalid(s, addr)) {
|
2454 | e6e5ad80 | bellard | val = 0xff;
|
2455 | e6e5ad80 | bellard | } else {
|
2456 | e6e5ad80 | bellard | switch (addr) {
|
2457 | e6e5ad80 | bellard | case 0x3c0: |
2458 | b6343073 | Juan Quintela | if (s->ar_flip_flop == 0) { |
2459 | b6343073 | Juan Quintela | val = s->ar_index; |
2460 | e6e5ad80 | bellard | } else {
|
2461 | e6e5ad80 | bellard | val = 0;
|
2462 | e6e5ad80 | bellard | } |
2463 | e6e5ad80 | bellard | break;
|
2464 | e6e5ad80 | bellard | case 0x3c1: |
2465 | b6343073 | Juan Quintela | index = s->ar_index & 0x1f;
|
2466 | e6e5ad80 | bellard | if (index < 21) |
2467 | b6343073 | Juan Quintela | val = s->ar[index]; |
2468 | e6e5ad80 | bellard | else
|
2469 | e6e5ad80 | bellard | val = 0;
|
2470 | e6e5ad80 | bellard | break;
|
2471 | e6e5ad80 | bellard | case 0x3c2: |
2472 | b6343073 | Juan Quintela | val = s->st00; |
2473 | e6e5ad80 | bellard | break;
|
2474 | e6e5ad80 | bellard | case 0x3c4: |
2475 | b6343073 | Juan Quintela | val = s->sr_index; |
2476 | e6e5ad80 | bellard | break;
|
2477 | e6e5ad80 | bellard | case 0x3c5: |
2478 | 8a82c322 | Juan Quintela | val = cirrus_vga_read_sr(c); |
2479 | 8a82c322 | Juan Quintela | break;
|
2480 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2481 | b6343073 | Juan Quintela | printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
|
2482 | e6e5ad80 | bellard | #endif
|
2483 | e6e5ad80 | bellard | break;
|
2484 | e6e5ad80 | bellard | case 0x3c6: |
2485 | 957c9db5 | Juan Quintela | val = cirrus_read_hidden_dac(c); |
2486 | e6e5ad80 | bellard | break;
|
2487 | e6e5ad80 | bellard | case 0x3c7: |
2488 | b6343073 | Juan Quintela | val = s->dac_state; |
2489 | e6e5ad80 | bellard | break;
|
2490 | ae184e4a | bellard | case 0x3c8: |
2491 | b6343073 | Juan Quintela | val = s->dac_write_index; |
2492 | b6343073 | Juan Quintela | c->cirrus_hidden_dac_lockindex = 0;
|
2493 | ae184e4a | bellard | break;
|
2494 | ae184e4a | bellard | case 0x3c9: |
2495 | 5deaeee3 | Juan Quintela | val = cirrus_vga_read_palette(c); |
2496 | 5deaeee3 | Juan Quintela | break;
|
2497 | e6e5ad80 | bellard | case 0x3ca: |
2498 | b6343073 | Juan Quintela | val = s->fcr; |
2499 | e6e5ad80 | bellard | break;
|
2500 | e6e5ad80 | bellard | case 0x3cc: |
2501 | b6343073 | Juan Quintela | val = s->msr; |
2502 | e6e5ad80 | bellard | break;
|
2503 | e6e5ad80 | bellard | case 0x3ce: |
2504 | b6343073 | Juan Quintela | val = s->gr_index; |
2505 | e6e5ad80 | bellard | break;
|
2506 | e6e5ad80 | bellard | case 0x3cf: |
2507 | f705db9d | Juan Quintela | val = cirrus_vga_read_gr(c, s->gr_index); |
2508 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2509 | b6343073 | Juan Quintela | printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
|
2510 | e6e5ad80 | bellard | #endif
|
2511 | e6e5ad80 | bellard | break;
|
2512 | e6e5ad80 | bellard | case 0x3b4: |
2513 | e6e5ad80 | bellard | case 0x3d4: |
2514 | b6343073 | Juan Quintela | val = s->cr_index; |
2515 | e6e5ad80 | bellard | break;
|
2516 | e6e5ad80 | bellard | case 0x3b5: |
2517 | e6e5ad80 | bellard | case 0x3d5: |
2518 | b863d514 | Juan Quintela | val = cirrus_vga_read_cr(c, s->cr_index); |
2519 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2520 | b6343073 | Juan Quintela | printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
|
2521 | e6e5ad80 | bellard | #endif
|
2522 | e6e5ad80 | bellard | break;
|
2523 | e6e5ad80 | bellard | case 0x3ba: |
2524 | e6e5ad80 | bellard | case 0x3da: |
2525 | e6e5ad80 | bellard | /* just toggle to fool polling */
|
2526 | b6343073 | Juan Quintela | val = s->st01 = s->retrace(s); |
2527 | b6343073 | Juan Quintela | s->ar_flip_flop = 0;
|
2528 | e6e5ad80 | bellard | break;
|
2529 | e6e5ad80 | bellard | default:
|
2530 | e6e5ad80 | bellard | val = 0x00;
|
2531 | e6e5ad80 | bellard | break;
|
2532 | e6e5ad80 | bellard | } |
2533 | e6e5ad80 | bellard | } |
2534 | e6e5ad80 | bellard | #if defined(DEBUG_VGA)
|
2535 | e6e5ad80 | bellard | printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
|
2536 | e6e5ad80 | bellard | #endif
|
2537 | e6e5ad80 | bellard | return val;
|
2538 | e6e5ad80 | bellard | } |
2539 | e6e5ad80 | bellard | |
2540 | c75e6d8e | Julien Grall | static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val, |
2541 | c75e6d8e | Julien Grall | unsigned size)
|
2542 | e6e5ad80 | bellard | { |
2543 | b6343073 | Juan Quintela | CirrusVGAState *c = opaque; |
2544 | b6343073 | Juan Quintela | VGACommonState *s = &c->vga; |
2545 | e6e5ad80 | bellard | int index;
|
2546 | e6e5ad80 | bellard | |
2547 | bd8f2f5d | Jan Kiszka | qemu_flush_coalesced_mmio_buffer(); |
2548 | c75e6d8e | Julien Grall | addr += 0x3b0;
|
2549 | bd8f2f5d | Jan Kiszka | |
2550 | e6e5ad80 | bellard | /* check port range access depending on color/monochrome mode */
|
2551 | b6343073 | Juan Quintela | if (vga_ioport_invalid(s, addr)) {
|
2552 | e6e5ad80 | bellard | return;
|
2553 | 25a18cbd | Juan Quintela | } |
2554 | e6e5ad80 | bellard | #ifdef DEBUG_VGA
|
2555 | e6e5ad80 | bellard | printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
|
2556 | e6e5ad80 | bellard | #endif
|
2557 | e6e5ad80 | bellard | |
2558 | e6e5ad80 | bellard | switch (addr) {
|
2559 | e6e5ad80 | bellard | case 0x3c0: |
2560 | b6343073 | Juan Quintela | if (s->ar_flip_flop == 0) { |
2561 | e6e5ad80 | bellard | val &= 0x3f;
|
2562 | b6343073 | Juan Quintela | s->ar_index = val; |
2563 | e6e5ad80 | bellard | } else {
|
2564 | b6343073 | Juan Quintela | index = s->ar_index & 0x1f;
|
2565 | e6e5ad80 | bellard | switch (index) {
|
2566 | e6e5ad80 | bellard | case 0x00 ... 0x0f: |
2567 | b6343073 | Juan Quintela | s->ar[index] = val & 0x3f;
|
2568 | e6e5ad80 | bellard | break;
|
2569 | e6e5ad80 | bellard | case 0x10: |
2570 | b6343073 | Juan Quintela | s->ar[index] = val & ~0x10;
|
2571 | e6e5ad80 | bellard | break;
|
2572 | e6e5ad80 | bellard | case 0x11: |
2573 | b6343073 | Juan Quintela | s->ar[index] = val; |
2574 | e6e5ad80 | bellard | break;
|
2575 | e6e5ad80 | bellard | case 0x12: |
2576 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xc0;
|
2577 | e6e5ad80 | bellard | break;
|
2578 | e6e5ad80 | bellard | case 0x13: |
2579 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xf0;
|
2580 | e6e5ad80 | bellard | break;
|
2581 | e6e5ad80 | bellard | case 0x14: |
2582 | b6343073 | Juan Quintela | s->ar[index] = val & ~0xf0;
|
2583 | e6e5ad80 | bellard | break;
|
2584 | e6e5ad80 | bellard | default:
|
2585 | e6e5ad80 | bellard | break;
|
2586 | e6e5ad80 | bellard | } |
2587 | e6e5ad80 | bellard | } |
2588 | b6343073 | Juan Quintela | s->ar_flip_flop ^= 1;
|
2589 | e6e5ad80 | bellard | break;
|
2590 | e6e5ad80 | bellard | case 0x3c2: |
2591 | b6343073 | Juan Quintela | s->msr = val & ~0x10;
|
2592 | b6343073 | Juan Quintela | s->update_retrace_info(s); |
2593 | e6e5ad80 | bellard | break;
|
2594 | e6e5ad80 | bellard | case 0x3c4: |
2595 | b6343073 | Juan Quintela | s->sr_index = val; |
2596 | e6e5ad80 | bellard | break;
|
2597 | e6e5ad80 | bellard | case 0x3c5: |
2598 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2599 | b6343073 | Juan Quintela | printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
|
2600 | e6e5ad80 | bellard | #endif
|
2601 | 31c63201 | Juan Quintela | cirrus_vga_write_sr(c, val); |
2602 | 31c63201 | Juan Quintela | break;
|
2603 | e6e5ad80 | bellard | case 0x3c6: |
2604 | b6343073 | Juan Quintela | cirrus_write_hidden_dac(c, val); |
2605 | e6e5ad80 | bellard | break;
|
2606 | e6e5ad80 | bellard | case 0x3c7: |
2607 | b6343073 | Juan Quintela | s->dac_read_index = val; |
2608 | b6343073 | Juan Quintela | s->dac_sub_index = 0;
|
2609 | b6343073 | Juan Quintela | s->dac_state = 3;
|
2610 | e6e5ad80 | bellard | break;
|
2611 | e6e5ad80 | bellard | case 0x3c8: |
2612 | b6343073 | Juan Quintela | s->dac_write_index = val; |
2613 | b6343073 | Juan Quintela | s->dac_sub_index = 0;
|
2614 | b6343073 | Juan Quintela | s->dac_state = 0;
|
2615 | e6e5ad80 | bellard | break;
|
2616 | e6e5ad80 | bellard | case 0x3c9: |
2617 | 86948bb1 | Juan Quintela | cirrus_vga_write_palette(c, val); |
2618 | 86948bb1 | Juan Quintela | break;
|
2619 | e6e5ad80 | bellard | case 0x3ce: |
2620 | b6343073 | Juan Quintela | s->gr_index = val; |
2621 | e6e5ad80 | bellard | break;
|
2622 | e6e5ad80 | bellard | case 0x3cf: |
2623 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2624 | b6343073 | Juan Quintela | printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
|
2625 | e6e5ad80 | bellard | #endif
|
2626 | 22286bc6 | Juan Quintela | cirrus_vga_write_gr(c, s->gr_index, val); |
2627 | e6e5ad80 | bellard | break;
|
2628 | e6e5ad80 | bellard | case 0x3b4: |
2629 | e6e5ad80 | bellard | case 0x3d4: |
2630 | b6343073 | Juan Quintela | s->cr_index = val; |
2631 | e6e5ad80 | bellard | break;
|
2632 | e6e5ad80 | bellard | case 0x3b5: |
2633 | e6e5ad80 | bellard | case 0x3d5: |
2634 | e6e5ad80 | bellard | #ifdef DEBUG_VGA_REG
|
2635 | b6343073 | Juan Quintela | printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
|
2636 | e6e5ad80 | bellard | #endif
|
2637 | 4ec1ce04 | Juan Quintela | cirrus_vga_write_cr(c, val); |
2638 | e6e5ad80 | bellard | break;
|
2639 | e6e5ad80 | bellard | case 0x3ba: |
2640 | e6e5ad80 | bellard | case 0x3da: |
2641 | b6343073 | Juan Quintela | s->fcr = val & 0x10;
|
2642 | e6e5ad80 | bellard | break;
|
2643 | e6e5ad80 | bellard | } |
2644 | e6e5ad80 | bellard | } |
2645 | e6e5ad80 | bellard | |
2646 | e6e5ad80 | bellard | /***************************************
|
2647 | e6e5ad80 | bellard | *
|
2648 | e36f36e1 | bellard | * memory-mapped I/O access
|
2649 | e36f36e1 | bellard | *
|
2650 | e36f36e1 | bellard | ***************************************/
|
2651 | e36f36e1 | bellard | |
2652 | a8170e5e | Avi Kivity | static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr, |
2653 | 1e04d4d6 | Avi Kivity | unsigned size)
|
2654 | e36f36e1 | bellard | { |
2655 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2656 | e36f36e1 | bellard | |
2657 | e36f36e1 | bellard | if (addr >= 0x100) { |
2658 | e36f36e1 | bellard | return cirrus_mmio_blt_read(s, addr - 0x100); |
2659 | e36f36e1 | bellard | } else {
|
2660 | c75e6d8e | Julien Grall | return cirrus_vga_ioport_read(s, addr + 0x10, size); |
2661 | e36f36e1 | bellard | } |
2662 | e36f36e1 | bellard | } |
2663 | e36f36e1 | bellard | |
2664 | a8170e5e | Avi Kivity | static void cirrus_mmio_write(void *opaque, hwaddr addr, |
2665 | 1e04d4d6 | Avi Kivity | uint64_t val, unsigned size)
|
2666 | e36f36e1 | bellard | { |
2667 | e05587e8 | Juan Quintela | CirrusVGAState *s = opaque; |
2668 | e36f36e1 | bellard | |
2669 | e36f36e1 | bellard | if (addr >= 0x100) { |
2670 | e36f36e1 | bellard | cirrus_mmio_blt_write(s, addr - 0x100, val);
|
2671 | e36f36e1 | bellard | } else {
|
2672 | c75e6d8e | Julien Grall | cirrus_vga_ioport_write(s, addr + 0x10, val, size);
|
2673 | e36f36e1 | bellard | } |
2674 | e36f36e1 | bellard | } |
2675 | e36f36e1 | bellard | |
2676 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_mmio_io_ops = { |
2677 | b1950430 | Avi Kivity | .read = cirrus_mmio_read, |
2678 | b1950430 | Avi Kivity | .write = cirrus_mmio_write, |
2679 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2680 | 1e04d4d6 | Avi Kivity | .impl = { |
2681 | 1e04d4d6 | Avi Kivity | .min_access_size = 1,
|
2682 | 1e04d4d6 | Avi Kivity | .max_access_size = 1,
|
2683 | 1e04d4d6 | Avi Kivity | }, |
2684 | e36f36e1 | bellard | }; |
2685 | e36f36e1 | bellard | |
2686 | 2c6ab832 | bellard | /* load/save state */
|
2687 | 2c6ab832 | bellard | |
2688 | e59fb374 | Juan Quintela | static int cirrus_post_load(void *opaque, int version_id) |
2689 | 2c6ab832 | bellard | { |
2690 | 2c6ab832 | bellard | CirrusVGAState *s = opaque; |
2691 | 2c6ab832 | bellard | |
2692 | 4e12cd94 | Avi Kivity | s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f; |
2693 | 4e12cd94 | Avi Kivity | s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f; |
2694 | 2c6ab832 | bellard | |
2695 | 2bec46dc | aliguori | cirrus_update_memory_access(s); |
2696 | 2c6ab832 | bellard | /* force refresh */
|
2697 | 4e12cd94 | Avi Kivity | s->vga.graphic_mode = -1;
|
2698 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 0);
|
2699 | 2c6ab832 | bellard | cirrus_update_bank_ptr(s, 1);
|
2700 | 2c6ab832 | bellard | return 0; |
2701 | 2c6ab832 | bellard | } |
2702 | 2c6ab832 | bellard | |
2703 | 7e72abc3 | Juan Quintela | static const VMStateDescription vmstate_cirrus_vga = { |
2704 | 7e72abc3 | Juan Quintela | .name = "cirrus_vga",
|
2705 | 7e72abc3 | Juan Quintela | .version_id = 2,
|
2706 | 7e72abc3 | Juan Quintela | .minimum_version_id = 1,
|
2707 | 7e72abc3 | Juan Quintela | .minimum_version_id_old = 1,
|
2708 | 7e72abc3 | Juan Quintela | .post_load = cirrus_post_load, |
2709 | 7e72abc3 | Juan Quintela | .fields = (VMStateField []) { |
2710 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(vga.latch, CirrusVGAState), |
2711 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.sr_index, CirrusVGAState), |
2712 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.sr, CirrusVGAState), |
2713 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.gr_index, CirrusVGAState), |
2714 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState), |
2715 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState), |
2716 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
|
2717 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.ar_index, CirrusVGAState), |
2718 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.ar, CirrusVGAState), |
2719 | 7e72abc3 | Juan Quintela | VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState), |
2720 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.cr_index, CirrusVGAState), |
2721 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.cr, CirrusVGAState), |
2722 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.msr, CirrusVGAState), |
2723 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.fcr, CirrusVGAState), |
2724 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.st00, CirrusVGAState), |
2725 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.st01, CirrusVGAState), |
2726 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_state, CirrusVGAState), |
2727 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState), |
2728 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState), |
2729 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState), |
2730 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState), |
2731 | 7e72abc3 | Juan Quintela | VMSTATE_BUFFER(vga.palette, CirrusVGAState), |
2732 | 7e72abc3 | Juan Quintela | VMSTATE_INT32(vga.bank_offset, CirrusVGAState), |
2733 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState), |
2734 | 7e72abc3 | Juan Quintela | VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState), |
2735 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(hw_cursor_x, CirrusVGAState), |
2736 | 7e72abc3 | Juan Quintela | VMSTATE_UINT32(hw_cursor_y, CirrusVGAState), |
2737 | 7e72abc3 | Juan Quintela | /* XXX: we do not save the bitblt state - we assume we do not save
|
2738 | 7e72abc3 | Juan Quintela | the state when the blitter is active */
|
2739 | 7e72abc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
2740 | 4f335feb | Juan Quintela | } |
2741 | 7e72abc3 | Juan Quintela | }; |
2742 | 4f335feb | Juan Quintela | |
2743 | 7e72abc3 | Juan Quintela | static const VMStateDescription vmstate_pci_cirrus_vga = { |
2744 | 7e72abc3 | Juan Quintela | .name = "cirrus_vga",
|
2745 | 7e72abc3 | Juan Quintela | .version_id = 2,
|
2746 | 7e72abc3 | Juan Quintela | .minimum_version_id = 2,
|
2747 | 7e72abc3 | Juan Quintela | .minimum_version_id_old = 2,
|
2748 | 7e72abc3 | Juan Quintela | .fields = (VMStateField []) { |
2749 | 7e72abc3 | Juan Quintela | VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState), |
2750 | 7e72abc3 | Juan Quintela | VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
|
2751 | 7e72abc3 | Juan Quintela | vmstate_cirrus_vga, CirrusVGAState), |
2752 | 7e72abc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
2753 | 7e72abc3 | Juan Quintela | } |
2754 | 7e72abc3 | Juan Quintela | }; |
2755 | 4f335feb | Juan Quintela | |
2756 | e36f36e1 | bellard | /***************************************
|
2757 | e36f36e1 | bellard | *
|
2758 | e6e5ad80 | bellard | * initialize
|
2759 | e6e5ad80 | bellard | *
|
2760 | e6e5ad80 | bellard | ***************************************/
|
2761 | e6e5ad80 | bellard | |
2762 | 4abc796d | blueswir1 | static void cirrus_reset(void *opaque) |
2763 | e6e5ad80 | bellard | { |
2764 | 4abc796d | blueswir1 | CirrusVGAState *s = opaque; |
2765 | e6e5ad80 | bellard | |
2766 | 03a3e7ba | Juan Quintela | vga_common_reset(&s->vga); |
2767 | ee50c6bc | aliguori | unmap_linear_vram(s); |
2768 | 4e12cd94 | Avi Kivity | s->vga.sr[0x06] = 0x0f; |
2769 | 4abc796d | blueswir1 | if (s->device_id == CIRRUS_ID_CLGD5446) {
|
2770 | 78e127ef | bellard | /* 4MB 64 bit memory config, always PCI */
|
2771 | 4e12cd94 | Avi Kivity | s->vga.sr[0x1F] = 0x2d; // MemClock |
2772 | 4e12cd94 | Avi Kivity | s->vga.gr[0x18] = 0x0f; // fastest memory configuration |
2773 | 4e12cd94 | Avi Kivity | s->vga.sr[0x0f] = 0x98; |
2774 | 4e12cd94 | Avi Kivity | s->vga.sr[0x17] = 0x20; |
2775 | 4e12cd94 | Avi Kivity | s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */ |
2776 | 78e127ef | bellard | } else {
|
2777 | 4e12cd94 | Avi Kivity | s->vga.sr[0x1F] = 0x22; // MemClock |
2778 | 4e12cd94 | Avi Kivity | s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
2779 | 4e12cd94 | Avi Kivity | s->vga.sr[0x17] = s->bustype;
|
2780 | 4e12cd94 | Avi Kivity | s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */ |
2781 | 78e127ef | bellard | } |
2782 | 4e12cd94 | Avi Kivity | s->vga.cr[0x27] = s->device_id;
|
2783 | e6e5ad80 | bellard | |
2784 | e6e5ad80 | bellard | s->cirrus_hidden_dac_lockindex = 5;
|
2785 | e6e5ad80 | bellard | s->cirrus_hidden_dac_data = 0;
|
2786 | 4abc796d | blueswir1 | } |
2787 | 4abc796d | blueswir1 | |
2788 | b1950430 | Avi Kivity | static const MemoryRegionOps cirrus_linear_io_ops = { |
2789 | b1950430 | Avi Kivity | .read = cirrus_linear_read, |
2790 | b1950430 | Avi Kivity | .write = cirrus_linear_write, |
2791 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
2792 | 899adf81 | Avi Kivity | .impl = { |
2793 | 899adf81 | Avi Kivity | .min_access_size = 1,
|
2794 | 899adf81 | Avi Kivity | .max_access_size = 1,
|
2795 | 899adf81 | Avi Kivity | }, |
2796 | b1950430 | Avi Kivity | }; |
2797 | b1950430 | Avi Kivity | |
2798 | c75e6d8e | Julien Grall | static const MemoryRegionOps cirrus_vga_io_ops = { |
2799 | c75e6d8e | Julien Grall | .read = cirrus_vga_ioport_read, |
2800 | c75e6d8e | Julien Grall | .write = cirrus_vga_ioport_write, |
2801 | c75e6d8e | Julien Grall | .endianness = DEVICE_LITTLE_ENDIAN, |
2802 | c75e6d8e | Julien Grall | .impl = { |
2803 | c75e6d8e | Julien Grall | .min_access_size = 1,
|
2804 | c75e6d8e | Julien Grall | .max_access_size = 1,
|
2805 | c75e6d8e | Julien Grall | }, |
2806 | c75e6d8e | Julien Grall | }; |
2807 | c75e6d8e | Julien Grall | |
2808 | be20f9e9 | Avi Kivity | static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci, |
2809 | c75e6d8e | Julien Grall | MemoryRegion *system_memory, |
2810 | c75e6d8e | Julien Grall | MemoryRegion *system_io) |
2811 | 4abc796d | blueswir1 | { |
2812 | 4abc796d | blueswir1 | int i;
|
2813 | 4abc796d | blueswir1 | static int inited; |
2814 | 4abc796d | blueswir1 | |
2815 | 4abc796d | blueswir1 | if (!inited) {
|
2816 | 4abc796d | blueswir1 | inited = 1;
|
2817 | 4abc796d | blueswir1 | for(i = 0;i < 256; i++) |
2818 | 4abc796d | blueswir1 | rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
|
2819 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_0] = 0;
|
2820 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
|
2821 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOP] = 2;
|
2822 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
|
2823 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTDST] = 4;
|
2824 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC] = 5;
|
2825 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_1] = 6;
|
2826 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
|
2827 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
|
2828 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
|
2829 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
|
2830 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
|
2831 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
|
2832 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
|
2833 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
|
2834 | 4abc796d | blueswir1 | rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
|
2835 | 4abc796d | blueswir1 | s->device_id = device_id; |
2836 | 4abc796d | blueswir1 | if (is_pci)
|
2837 | 4abc796d | blueswir1 | s->bustype = CIRRUS_BUSTYPE_PCI; |
2838 | 4abc796d | blueswir1 | else
|
2839 | 4abc796d | blueswir1 | s->bustype = CIRRUS_BUSTYPE_ISA; |
2840 | 4abc796d | blueswir1 | } |
2841 | 4abc796d | blueswir1 | |
2842 | c75e6d8e | Julien Grall | /* Register ioport 0x3b0 - 0x3df */
|
2843 | c75e6d8e | Julien Grall | memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s, |
2844 | c75e6d8e | Julien Grall | "cirrus-io", 0x30); |
2845 | c75e6d8e | Julien Grall | memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
|
2846 | 4abc796d | blueswir1 | |
2847 | b1950430 | Avi Kivity | memory_region_init(&s->low_mem_container, |
2848 | b1950430 | Avi Kivity | "cirrus-lowmem-container",
|
2849 | b1950430 | Avi Kivity | 0x20000);
|
2850 | b1950430 | Avi Kivity | |
2851 | b1950430 | Avi Kivity | memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s, |
2852 | b1950430 | Avi Kivity | "cirrus-low-memory", 0x20000); |
2853 | b1950430 | Avi Kivity | memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
|
2854 | 7969d9ed | Avi Kivity | for (i = 0; i < 2; ++i) { |
2855 | 7969d9ed | Avi Kivity | static const char *names[] = { "vga.bank0", "vga.bank1" }; |
2856 | 7969d9ed | Avi Kivity | MemoryRegion *bank = &s->cirrus_bank[i]; |
2857 | 7969d9ed | Avi Kivity | memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000); |
2858 | 7969d9ed | Avi Kivity | memory_region_set_enabled(bank, false);
|
2859 | 7969d9ed | Avi Kivity | memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
|
2860 | 7969d9ed | Avi Kivity | bank, 1);
|
2861 | 7969d9ed | Avi Kivity | } |
2862 | be20f9e9 | Avi Kivity | memory_region_add_subregion_overlap(system_memory, |
2863 | b1950430 | Avi Kivity | isa_mem_base + 0x000a0000,
|
2864 | b1950430 | Avi Kivity | &s->low_mem_container, |
2865 | b1950430 | Avi Kivity | 1);
|
2866 | b1950430 | Avi Kivity | memory_region_set_coalescing(&s->low_mem); |
2867 | 2c6ab832 | bellard | |
2868 | fefe54e3 | aliguori | /* I/O handler for LFB */
|
2869 | b1950430 | Avi Kivity | memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s, |
2870 | 19403a68 | Marcelo Tosatti | "cirrus-linear-io", s->vga.vram_size_mb
|
2871 | 19403a68 | Marcelo Tosatti | * 1024 * 1024); |
2872 | bd8f2f5d | Jan Kiszka | memory_region_set_flush_coalesced(&s->cirrus_linear_io); |
2873 | fefe54e3 | aliguori | |
2874 | fefe54e3 | aliguori | /* I/O handler for LFB */
|
2875 | b1950430 | Avi Kivity | memory_region_init_io(&s->cirrus_linear_bitblt_io, |
2876 | b1950430 | Avi Kivity | &cirrus_linear_bitblt_io_ops, |
2877 | b1950430 | Avi Kivity | s, |
2878 | b1950430 | Avi Kivity | "cirrus-bitblt-mmio",
|
2879 | b1950430 | Avi Kivity | 0x400000);
|
2880 | bd8f2f5d | Jan Kiszka | memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io); |
2881 | fefe54e3 | aliguori | |
2882 | fefe54e3 | aliguori | /* I/O handler for memory-mapped I/O */
|
2883 | b1950430 | Avi Kivity | memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s, |
2884 | b1950430 | Avi Kivity | "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
|
2885 | bd8f2f5d | Jan Kiszka | memory_region_set_flush_coalesced(&s->cirrus_mmio_io); |
2886 | fefe54e3 | aliguori | |
2887 | fefe54e3 | aliguori | s->real_vram_size = |
2888 | fefe54e3 | aliguori | (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024; |
2889 | fefe54e3 | aliguori | |
2890 | 4e12cd94 | Avi Kivity | /* XXX: s->vga.vram_size must be a power of two */
|
2891 | fefe54e3 | aliguori | s->cirrus_addr_mask = s->real_vram_size - 1;
|
2892 | fefe54e3 | aliguori | s->linear_mmio_mask = s->real_vram_size - 256;
|
2893 | fefe54e3 | aliguori | |
2894 | 4e12cd94 | Avi Kivity | s->vga.get_bpp = cirrus_get_bpp; |
2895 | 4e12cd94 | Avi Kivity | s->vga.get_offsets = cirrus_get_offsets; |
2896 | 4e12cd94 | Avi Kivity | s->vga.get_resolution = cirrus_get_resolution; |
2897 | 4e12cd94 | Avi Kivity | s->vga.cursor_invalidate = cirrus_cursor_invalidate; |
2898 | 4e12cd94 | Avi Kivity | s->vga.cursor_draw_line = cirrus_cursor_draw_line; |
2899 | fefe54e3 | aliguori | |
2900 | a08d4367 | Jan Kiszka | qemu_register_reset(cirrus_reset, s); |
2901 | e6e5ad80 | bellard | } |
2902 | e6e5ad80 | bellard | |
2903 | e6e5ad80 | bellard | /***************************************
|
2904 | e6e5ad80 | bellard | *
|
2905 | e6e5ad80 | bellard | * ISA bus support
|
2906 | e6e5ad80 | bellard | *
|
2907 | e6e5ad80 | bellard | ***************************************/
|
2908 | e6e5ad80 | bellard | |
2909 | db895a1e | Andreas Färber | static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp) |
2910 | e6e5ad80 | bellard | { |
2911 | db895a1e | Andreas Färber | ISADevice *isadev = ISA_DEVICE(dev); |
2912 | 6d4c2f17 | Andreas Färber | ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev); |
2913 | 3d402831 | Blue Swirl | VGACommonState *s = &d->cirrus_vga.vga; |
2914 | 3d402831 | Blue Swirl | |
2915 | 4a1e244e | Gerd Hoffmann | vga_common_init(s); |
2916 | 3d402831 | Blue Swirl | cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
|
2917 | db895a1e | Andreas Färber | isa_address_space(isadev), |
2918 | db895a1e | Andreas Färber | isa_address_space_io(isadev)); |
2919 | db895a1e | Andreas Färber | s->con = graphic_console_init(dev, s->hw_ops, s); |
2920 | 5245d57a | Gerd Hoffmann | rom_add_vga(VGABIOS_CIRRUS_FILENAME); |
2921 | e6e5ad80 | bellard | /* XXX ISA-LFB support */
|
2922 | ad6d45fa | Anthony Liguori | /* FIXME not qdev yet */
|
2923 | 3d402831 | Blue Swirl | } |
2924 | 3d402831 | Blue Swirl | |
2925 | 6d4c2f17 | Andreas Färber | static Property isa_cirrus_vga_properties[] = {
|
2926 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState, |
2927 | 19403a68 | Marcelo Tosatti | cirrus_vga.vga.vram_size_mb, 8),
|
2928 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_END_OF_LIST(), |
2929 | 19403a68 | Marcelo Tosatti | }; |
2930 | 19403a68 | Marcelo Tosatti | |
2931 | 8f04ee08 | Anthony Liguori | static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) |
2932 | 8f04ee08 | Anthony Liguori | { |
2933 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
2934 | 8f04ee08 | Anthony Liguori | |
2935 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_cirrus_vga; |
2936 | db895a1e | Andreas Färber | dc->realize = isa_cirrus_vga_realizefn; |
2937 | 6d4c2f17 | Andreas Färber | dc->props = isa_cirrus_vga_properties; |
2938 | 8f04ee08 | Anthony Liguori | } |
2939 | 8f04ee08 | Anthony Liguori | |
2940 | 8c43a6f0 | Andreas Färber | static const TypeInfo isa_cirrus_vga_info = { |
2941 | 6d4c2f17 | Andreas Färber | .name = TYPE_ISA_CIRRUS_VGA, |
2942 | 39bffca2 | Anthony Liguori | .parent = TYPE_ISA_DEVICE, |
2943 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(ISACirrusVGAState),
|
2944 | 8f04ee08 | Anthony Liguori | .class_init = isa_cirrus_vga_class_init, |
2945 | 3d402831 | Blue Swirl | }; |
2946 | 3d402831 | Blue Swirl | |
2947 | e6e5ad80 | bellard | /***************************************
|
2948 | e6e5ad80 | bellard | *
|
2949 | e6e5ad80 | bellard | * PCI bus support
|
2950 | e6e5ad80 | bellard | *
|
2951 | e6e5ad80 | bellard | ***************************************/
|
2952 | e6e5ad80 | bellard | |
2953 | 81a322d4 | Gerd Hoffmann | static int pci_cirrus_vga_initfn(PCIDevice *dev) |
2954 | a414c306 | Gerd Hoffmann | { |
2955 | a414c306 | Gerd Hoffmann | PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev); |
2956 | a414c306 | Gerd Hoffmann | CirrusVGAState *s = &d->cirrus_vga; |
2957 | 40021f08 | Anthony Liguori | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
2958 | 40021f08 | Anthony Liguori | int16_t device_id = pc->device_id; |
2959 | a414c306 | Gerd Hoffmann | |
2960 | a414c306 | Gerd Hoffmann | /* setup VGA */
|
2961 | 4a1e244e | Gerd Hoffmann | vga_common_init(&s->vga); |
2962 | c75e6d8e | Julien Grall | cirrus_init_common(s, device_id, 1, pci_address_space(dev),
|
2963 | c75e6d8e | Julien Grall | pci_address_space_io(dev)); |
2964 | aa2beaa1 | Gerd Hoffmann | s->vga.con = graphic_console_init(DEVICE(dev), s->vga.hw_ops, &s->vga); |
2965 | a414c306 | Gerd Hoffmann | |
2966 | a414c306 | Gerd Hoffmann | /* setup PCI */
|
2967 | a414c306 | Gerd Hoffmann | |
2968 | b1950430 | Avi Kivity | memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000); |
2969 | b1950430 | Avi Kivity | |
2970 | b1950430 | Avi Kivity | /* XXX: add byte swapping apertures */
|
2971 | b1950430 | Avi Kivity | memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
|
2972 | b1950430 | Avi Kivity | memory_region_add_subregion(&s->pci_bar, 0x1000000,
|
2973 | b1950430 | Avi Kivity | &s->cirrus_linear_bitblt_io); |
2974 | b1950430 | Avi Kivity | |
2975 | a414c306 | Gerd Hoffmann | /* setup memory space */
|
2976 | a414c306 | Gerd Hoffmann | /* memory #0 LFB */
|
2977 | a414c306 | Gerd Hoffmann | /* memory #1 memory-mapped I/O */
|
2978 | a414c306 | Gerd Hoffmann | /* XXX: s->vga.vram_size must be a power of two */
|
2979 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
|
2980 | a414c306 | Gerd Hoffmann | if (device_id == CIRRUS_ID_CLGD5446) {
|
2981 | e824b2cc | Avi Kivity | pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io); |
2982 | a414c306 | Gerd Hoffmann | } |
2983 | 81a322d4 | Gerd Hoffmann | return 0; |
2984 | a414c306 | Gerd Hoffmann | } |
2985 | a414c306 | Gerd Hoffmann | |
2986 | 19403a68 | Marcelo Tosatti | static Property pci_vga_cirrus_properties[] = {
|
2987 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState, |
2988 | 19403a68 | Marcelo Tosatti | cirrus_vga.vga.vram_size_mb, 8),
|
2989 | 19403a68 | Marcelo Tosatti | DEFINE_PROP_END_OF_LIST(), |
2990 | 19403a68 | Marcelo Tosatti | }; |
2991 | 19403a68 | Marcelo Tosatti | |
2992 | 40021f08 | Anthony Liguori | static void cirrus_vga_class_init(ObjectClass *klass, void *data) |
2993 | 40021f08 | Anthony Liguori | { |
2994 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
2995 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2996 | 40021f08 | Anthony Liguori | |
2997 | 40021f08 | Anthony Liguori | k->no_hotplug = 1;
|
2998 | 40021f08 | Anthony Liguori | k->init = pci_cirrus_vga_initfn; |
2999 | 40021f08 | Anthony Liguori | k->romfile = VGABIOS_CIRRUS_FILENAME; |
3000 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_CIRRUS; |
3001 | 40021f08 | Anthony Liguori | k->device_id = CIRRUS_ID_CLGD5446; |
3002 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_DISPLAY_VGA; |
3003 | 39bffca2 | Anthony Liguori | dc->desc = "Cirrus CLGD 54xx VGA";
|
3004 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_pci_cirrus_vga; |
3005 | 19403a68 | Marcelo Tosatti | dc->props = pci_vga_cirrus_properties; |
3006 | 40021f08 | Anthony Liguori | } |
3007 | 40021f08 | Anthony Liguori | |
3008 | 8c43a6f0 | Andreas Färber | static const TypeInfo cirrus_vga_info = { |
3009 | 39bffca2 | Anthony Liguori | .name = "cirrus-vga",
|
3010 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
3011 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCICirrusVGAState),
|
3012 | 39bffca2 | Anthony Liguori | .class_init = cirrus_vga_class_init, |
3013 | a414c306 | Gerd Hoffmann | }; |
3014 | e6e5ad80 | bellard | |
3015 | 83f7d43a | Andreas Färber | static void cirrus_vga_register_types(void) |
3016 | a414c306 | Gerd Hoffmann | { |
3017 | 83f7d43a | Andreas Färber | type_register_static(&isa_cirrus_vga_info); |
3018 | 39bffca2 | Anthony Liguori | type_register_static(&cirrus_vga_info); |
3019 | e6e5ad80 | bellard | } |
3020 | 83f7d43a | Andreas Färber | |
3021 | 83f7d43a | Andreas Färber | type_init(cirrus_vga_register_types) |