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1 | 3ef693a0 | bellard | /*
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2 | 3ef693a0 | bellard | * i386 virtual CPU header
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3 | 3ef693a0 | bellard | *
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4 | 3ef693a0 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 3ef693a0 | bellard | *
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6 | 3ef693a0 | bellard | * This library is free software; you can redistribute it and/or
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7 | 3ef693a0 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 3ef693a0 | bellard | * License as published by the Free Software Foundation; either
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9 | 3ef693a0 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 3ef693a0 | bellard | *
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11 | 3ef693a0 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 3ef693a0 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 3ef693a0 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 3ef693a0 | bellard | * Lesser General Public License for more details.
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15 | 3ef693a0 | bellard | *
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16 | 3ef693a0 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 3ef693a0 | bellard | * License along with this library; if not, write to the Free Software
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18 | 3ef693a0 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 0ecfa993 | bellard | */
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20 | 367e86e8 | bellard | #ifndef CPU_I386_H
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21 | 367e86e8 | bellard | #define CPU_I386_H
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22 | 367e86e8 | bellard | |
23 | 33417e70 | bellard | #include "cpu-defs.h" |
24 | 0ecfa993 | bellard | |
25 | 367e86e8 | bellard | #define R_EAX 0 |
26 | 367e86e8 | bellard | #define R_ECX 1 |
27 | 367e86e8 | bellard | #define R_EDX 2 |
28 | 367e86e8 | bellard | #define R_EBX 3 |
29 | 367e86e8 | bellard | #define R_ESP 4 |
30 | 367e86e8 | bellard | #define R_EBP 5 |
31 | 367e86e8 | bellard | #define R_ESI 6 |
32 | 367e86e8 | bellard | #define R_EDI 7 |
33 | 367e86e8 | bellard | |
34 | 367e86e8 | bellard | #define R_AL 0 |
35 | 367e86e8 | bellard | #define R_CL 1 |
36 | 367e86e8 | bellard | #define R_DL 2 |
37 | 367e86e8 | bellard | #define R_BL 3 |
38 | 367e86e8 | bellard | #define R_AH 4 |
39 | 367e86e8 | bellard | #define R_CH 5 |
40 | 367e86e8 | bellard | #define R_DH 6 |
41 | 367e86e8 | bellard | #define R_BH 7 |
42 | 367e86e8 | bellard | |
43 | 367e86e8 | bellard | #define R_ES 0 |
44 | 367e86e8 | bellard | #define R_CS 1 |
45 | 367e86e8 | bellard | #define R_SS 2 |
46 | 367e86e8 | bellard | #define R_DS 3 |
47 | 367e86e8 | bellard | #define R_FS 4 |
48 | 367e86e8 | bellard | #define R_GS 5 |
49 | 367e86e8 | bellard | |
50 | aad13cd1 | bellard | /* segment descriptor fields */
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51 | aad13cd1 | bellard | #define DESC_G_MASK (1 << 23) |
52 | 66e85a21 | bellard | #define DESC_B_SHIFT 22 |
53 | 66e85a21 | bellard | #define DESC_B_MASK (1 << DESC_B_SHIFT) |
54 | aad13cd1 | bellard | #define DESC_AVL_MASK (1 << 20) |
55 | aad13cd1 | bellard | #define DESC_P_MASK (1 << 15) |
56 | aad13cd1 | bellard | #define DESC_DPL_SHIFT 13 |
57 | aad13cd1 | bellard | #define DESC_S_MASK (1 << 12) |
58 | aad13cd1 | bellard | #define DESC_TYPE_SHIFT 8 |
59 | aad13cd1 | bellard | #define DESC_A_MASK (1 << 8) |
60 | aad13cd1 | bellard | |
61 | aad13cd1 | bellard | #define DESC_CS_MASK (1 << 11) |
62 | aad13cd1 | bellard | #define DESC_C_MASK (1 << 10) |
63 | aad13cd1 | bellard | #define DESC_R_MASK (1 << 9) |
64 | aad13cd1 | bellard | |
65 | aad13cd1 | bellard | #define DESC_E_MASK (1 << 10) |
66 | aad13cd1 | bellard | #define DESC_W_MASK (1 << 9) |
67 | aad13cd1 | bellard | |
68 | fc2b4c48 | bellard | /* eflags masks */
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69 | 367e86e8 | bellard | #define CC_C 0x0001 |
70 | 367e86e8 | bellard | #define CC_P 0x0004 |
71 | 367e86e8 | bellard | #define CC_A 0x0010 |
72 | 367e86e8 | bellard | #define CC_Z 0x0040 |
73 | 367e86e8 | bellard | #define CC_S 0x0080 |
74 | 367e86e8 | bellard | #define CC_O 0x0800 |
75 | 367e86e8 | bellard | |
76 | 3f337316 | bellard | #define TF_SHIFT 8 |
77 | 3f337316 | bellard | #define IOPL_SHIFT 12 |
78 | 3f337316 | bellard | #define VM_SHIFT 17 |
79 | 3f337316 | bellard | |
80 | fc2b4c48 | bellard | #define TF_MASK 0x00000100 |
81 | fc2b4c48 | bellard | #define IF_MASK 0x00000200 |
82 | fc2b4c48 | bellard | #define DF_MASK 0x00000400 |
83 | fc2b4c48 | bellard | #define IOPL_MASK 0x00003000 |
84 | fc2b4c48 | bellard | #define NT_MASK 0x00004000 |
85 | fc2b4c48 | bellard | #define RF_MASK 0x00010000 |
86 | fc2b4c48 | bellard | #define VM_MASK 0x00020000 |
87 | fc2b4c48 | bellard | #define AC_MASK 0x00040000 |
88 | fc2b4c48 | bellard | #define VIF_MASK 0x00080000 |
89 | fc2b4c48 | bellard | #define VIP_MASK 0x00100000 |
90 | fc2b4c48 | bellard | #define ID_MASK 0x00200000 |
91 | 367e86e8 | bellard | |
92 | 3f337316 | bellard | /* hidden flags - used internally by qemu to represent additionnal cpu
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93 | 3f337316 | bellard | states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
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94 | 3f337316 | bellard | using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
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95 | 3f337316 | bellard | with eflags. */
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96 | 3f337316 | bellard | /* current cpl */
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97 | 3f337316 | bellard | #define HF_CPL_SHIFT 0 |
98 | 3f337316 | bellard | /* true if soft mmu is being used */
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99 | 3f337316 | bellard | #define HF_SOFTMMU_SHIFT 2 |
100 | 3f337316 | bellard | /* true if hardware interrupts must be disabled for next instruction */
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101 | 3f337316 | bellard | #define HF_INHIBIT_IRQ_SHIFT 3 |
102 | 3f337316 | bellard | /* 16 or 32 segments */
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103 | 3f337316 | bellard | #define HF_CS32_SHIFT 4 |
104 | 3f337316 | bellard | #define HF_SS32_SHIFT 5 |
105 | 3f337316 | bellard | /* zero base for DS, ES and SS */
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106 | 3f337316 | bellard | #define HF_ADDSEG_SHIFT 6 |
107 | 3f337316 | bellard | |
108 | 3f337316 | bellard | #define HF_CPL_MASK (3 << HF_CPL_SHIFT) |
109 | 3f337316 | bellard | #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) |
110 | 3f337316 | bellard | #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT) |
111 | 3f337316 | bellard | #define HF_CS32_MASK (1 << HF_CS32_SHIFT) |
112 | 2e255c6b | bellard | #define HF_SS32_MASK (1 << HF_SS32_SHIFT) |
113 | 3f337316 | bellard | #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) |
114 | 3f337316 | bellard | |
115 | 13b55754 | bellard | #define CR0_PE_MASK (1 << 0) |
116 | 13b55754 | bellard | #define CR0_TS_MASK (1 << 3) |
117 | 13b55754 | bellard | #define CR0_WP_MASK (1 << 16) |
118 | 13b55754 | bellard | #define CR0_AM_MASK (1 << 18) |
119 | 13b55754 | bellard | #define CR0_PG_MASK (1 << 31) |
120 | 13b55754 | bellard | |
121 | 13b55754 | bellard | #define CR4_VME_MASK (1 << 0) |
122 | 13b55754 | bellard | #define CR4_PVI_MASK (1 << 1) |
123 | 13b55754 | bellard | #define CR4_TSD_MASK (1 << 2) |
124 | 13b55754 | bellard | #define CR4_DE_MASK (1 << 3) |
125 | 66e85a21 | bellard | #define CR4_PSE_MASK (1 << 4) |
126 | 66e85a21 | bellard | |
127 | 66e85a21 | bellard | #define PG_PRESENT_BIT 0 |
128 | 66e85a21 | bellard | #define PG_RW_BIT 1 |
129 | 66e85a21 | bellard | #define PG_USER_BIT 2 |
130 | 66e85a21 | bellard | #define PG_PWT_BIT 3 |
131 | 66e85a21 | bellard | #define PG_PCD_BIT 4 |
132 | 66e85a21 | bellard | #define PG_ACCESSED_BIT 5 |
133 | 66e85a21 | bellard | #define PG_DIRTY_BIT 6 |
134 | 66e85a21 | bellard | #define PG_PSE_BIT 7 |
135 | 66e85a21 | bellard | #define PG_GLOBAL_BIT 8 |
136 | 66e85a21 | bellard | |
137 | 66e85a21 | bellard | #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) |
138 | 66e85a21 | bellard | #define PG_RW_MASK (1 << PG_RW_BIT) |
139 | 66e85a21 | bellard | #define PG_USER_MASK (1 << PG_USER_BIT) |
140 | 66e85a21 | bellard | #define PG_PWT_MASK (1 << PG_PWT_BIT) |
141 | 66e85a21 | bellard | #define PG_PCD_MASK (1 << PG_PCD_BIT) |
142 | 66e85a21 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
143 | 66e85a21 | bellard | #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) |
144 | 66e85a21 | bellard | #define PG_PSE_MASK (1 << PG_PSE_BIT) |
145 | 66e85a21 | bellard | #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) |
146 | 66e85a21 | bellard | |
147 | 66e85a21 | bellard | #define PG_ERROR_W_BIT 1 |
148 | 66e85a21 | bellard | |
149 | 66e85a21 | bellard | #define PG_ERROR_P_MASK 0x01 |
150 | 66e85a21 | bellard | #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) |
151 | 66e85a21 | bellard | #define PG_ERROR_U_MASK 0x04 |
152 | 66e85a21 | bellard | #define PG_ERROR_RSVD_MASK 0x08 |
153 | 13b55754 | bellard | |
154 | 3c1cf9fa | bellard | #define MSR_IA32_APICBASE 0x1b |
155 | 3c1cf9fa | bellard | #define MSR_IA32_APICBASE_BSP (1<<8) |
156 | 3c1cf9fa | bellard | #define MSR_IA32_APICBASE_ENABLE (1<<11) |
157 | 3c1cf9fa | bellard | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) |
158 | 3c1cf9fa | bellard | |
159 | 3c1cf9fa | bellard | #define MSR_IA32_SYSENTER_CS 0x174 |
160 | 3c1cf9fa | bellard | #define MSR_IA32_SYSENTER_ESP 0x175 |
161 | 3c1cf9fa | bellard | #define MSR_IA32_SYSENTER_EIP 0x176 |
162 | 3c1cf9fa | bellard | |
163 | bc8a22cc | bellard | #define EXCP00_DIVZ 0 |
164 | bc8a22cc | bellard | #define EXCP01_SSTP 1 |
165 | bc8a22cc | bellard | #define EXCP02_NMI 2 |
166 | bc8a22cc | bellard | #define EXCP03_INT3 3 |
167 | bc8a22cc | bellard | #define EXCP04_INTO 4 |
168 | bc8a22cc | bellard | #define EXCP05_BOUND 5 |
169 | bc8a22cc | bellard | #define EXCP06_ILLOP 6 |
170 | bc8a22cc | bellard | #define EXCP07_PREX 7 |
171 | bc8a22cc | bellard | #define EXCP08_DBLE 8 |
172 | bc8a22cc | bellard | #define EXCP09_XERR 9 |
173 | bc8a22cc | bellard | #define EXCP0A_TSS 10 |
174 | bc8a22cc | bellard | #define EXCP0B_NOSEG 11 |
175 | bc8a22cc | bellard | #define EXCP0C_STACK 12 |
176 | bc8a22cc | bellard | #define EXCP0D_GPF 13 |
177 | bc8a22cc | bellard | #define EXCP0E_PAGE 14 |
178 | bc8a22cc | bellard | #define EXCP10_COPR 16 |
179 | bc8a22cc | bellard | #define EXCP11_ALGN 17 |
180 | bc8a22cc | bellard | #define EXCP12_MCHK 18 |
181 | 0ecfa993 | bellard | |
182 | 367e86e8 | bellard | enum {
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183 | 367e86e8 | bellard | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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184 | 367e86e8 | bellard | CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
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185 | 367e86e8 | bellard | CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
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186 | 367e86e8 | bellard | |
187 | 367e86e8 | bellard | CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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188 | 367e86e8 | bellard | CC_OP_ADDW, |
189 | 367e86e8 | bellard | CC_OP_ADDL, |
190 | 367e86e8 | bellard | |
191 | 4b74fe1f | bellard | CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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192 | 4b74fe1f | bellard | CC_OP_ADCW, |
193 | 4b74fe1f | bellard | CC_OP_ADCL, |
194 | 4b74fe1f | bellard | |
195 | 367e86e8 | bellard | CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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196 | 367e86e8 | bellard | CC_OP_SUBW, |
197 | 367e86e8 | bellard | CC_OP_SUBL, |
198 | 367e86e8 | bellard | |
199 | 4b74fe1f | bellard | CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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200 | 4b74fe1f | bellard | CC_OP_SBBW, |
201 | 4b74fe1f | bellard | CC_OP_SBBL, |
202 | 4b74fe1f | bellard | |
203 | 367e86e8 | bellard | CC_OP_LOGICB, /* modify all flags, CC_DST = res */
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204 | 367e86e8 | bellard | CC_OP_LOGICW, |
205 | 367e86e8 | bellard | CC_OP_LOGICL, |
206 | 367e86e8 | bellard | |
207 | 4b74fe1f | bellard | CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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208 | 367e86e8 | bellard | CC_OP_INCW, |
209 | 367e86e8 | bellard | CC_OP_INCL, |
210 | 367e86e8 | bellard | |
211 | 4b74fe1f | bellard | CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
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212 | 367e86e8 | bellard | CC_OP_DECW, |
213 | 367e86e8 | bellard | CC_OP_DECL, |
214 | 367e86e8 | bellard | |
215 | 367e86e8 | bellard | CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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216 | 367e86e8 | bellard | CC_OP_SHLW, |
217 | 367e86e8 | bellard | CC_OP_SHLL, |
218 | 367e86e8 | bellard | |
219 | 4b74fe1f | bellard | CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
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220 | 4b74fe1f | bellard | CC_OP_SARW, |
221 | 4b74fe1f | bellard | CC_OP_SARL, |
222 | 4b74fe1f | bellard | |
223 | 367e86e8 | bellard | CC_OP_NB, |
224 | 367e86e8 | bellard | }; |
225 | 367e86e8 | bellard | |
226 | 927f621e | bellard | #ifdef __i386__
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227 | 27362c82 | bellard | #define USE_X86LDOUBLE
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228 | 927f621e | bellard | #endif
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229 | 927f621e | bellard | |
230 | 927f621e | bellard | #ifdef USE_X86LDOUBLE
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231 | 927f621e | bellard | typedef long double CPU86_LDouble; |
232 | 927f621e | bellard | #else
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233 | 927f621e | bellard | typedef double CPU86_LDouble; |
234 | 927f621e | bellard | #endif
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235 | 927f621e | bellard | |
236 | 6dbad63e | bellard | typedef struct SegmentCache { |
237 | 13b55754 | bellard | uint32_t selector; |
238 | 6dbad63e | bellard | uint8_t *base; |
239 | 66e85a21 | bellard | uint32_t limit; |
240 | 66e85a21 | bellard | uint32_t flags; |
241 | 6dbad63e | bellard | } SegmentCache; |
242 | 6dbad63e | bellard | |
243 | ba1c6e37 | bellard | typedef struct CPUX86State { |
244 | 367e86e8 | bellard | /* standard registers */
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245 | 367e86e8 | bellard | uint32_t regs[8];
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246 | dab2ed99 | bellard | uint32_t eip; |
247 | fc2b4c48 | bellard | uint32_t eflags; /* eflags register. During CPU emulation, CC
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248 | fc2b4c48 | bellard | flags and DF are set to zero because they are
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249 | d34720fd | bellard | stored elsewhere */
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250 | 0ecfa993 | bellard | |
251 | 0ecfa993 | bellard | /* emulator internal eflags handling */
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252 | 367e86e8 | bellard | uint32_t cc_src; |
253 | 367e86e8 | bellard | uint32_t cc_dst; |
254 | 367e86e8 | bellard | uint32_t cc_op; |
255 | 367e86e8 | bellard | int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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256 | 3f337316 | bellard | uint32_t hflags; /* hidden flags, see HF_xxx constants */
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257 | 0ecfa993 | bellard | |
258 | 927f621e | bellard | /* FPU state */
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259 | 927f621e | bellard | unsigned int fpstt; /* top of stack index */ |
260 | 927f621e | bellard | unsigned int fpus; |
261 | 927f621e | bellard | unsigned int fpuc; |
262 | 0ecfa993 | bellard | uint8_t fptags[8]; /* 0 = valid, 1 = empty */ |
263 | 0ecfa993 | bellard | CPU86_LDouble fpregs[8];
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264 | 0ecfa993 | bellard | |
265 | 367e86e8 | bellard | /* emulator internal variables */
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266 | 927f621e | bellard | CPU86_LDouble ft0; |
267 | d014c98c | bellard | union {
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268 | d014c98c | bellard | float f;
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269 | d014c98c | bellard | double d;
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270 | d014c98c | bellard | int i32;
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271 | d014c98c | bellard | int64_t i64; |
272 | d014c98c | bellard | } fp_convert; |
273 | d57c4e01 | bellard | |
274 | 6dbad63e | bellard | /* segments */
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275 | 13b55754 | bellard | SegmentCache segs[6]; /* selector values */ |
276 | 13b55754 | bellard | SegmentCache ldt; |
277 | 13b55754 | bellard | SegmentCache tr; |
278 | 13b55754 | bellard | SegmentCache gdt; /* only base and limit are used */
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279 | 13b55754 | bellard | SegmentCache idt; /* only base and limit are used */
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280 | 33417e70 | bellard | |
281 | 3c1cf9fa | bellard | /* sysenter registers */
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282 | 3c1cf9fa | bellard | uint32_t sysenter_cs; |
283 | 3c1cf9fa | bellard | uint32_t sysenter_esp; |
284 | 3c1cf9fa | bellard | uint32_t sysenter_eip; |
285 | 6dbad63e | bellard | |
286 | 9de5e440 | bellard | /* exception/interrupt handling */
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287 | 0ecfa993 | bellard | jmp_buf jmp_env; |
288 | 0ecfa993 | bellard | int exception_index;
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289 | 9ba5695c | bellard | int error_code;
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290 | 66e85a21 | bellard | int exception_is_int;
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291 | 66e85a21 | bellard | int exception_next_eip;
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292 | ea041c0e | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ |
293 | 13b55754 | bellard | uint32_t cr[5]; /* NOTE: cr1 is unused */ |
294 | 13b55754 | bellard | uint32_t dr[8]; /* debug registers */ |
295 | 68a79315 | bellard | int interrupt_request;
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296 | 66e85a21 | bellard | int user_mode_only; /* user mode only simulation */ |
297 | 4c3a88a2 | bellard | |
298 | 33417e70 | bellard | /* soft mmu support */
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299 | 33417e70 | bellard | /* 0 = kernel, 1 = user */
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300 | 33417e70 | bellard | CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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301 | 33417e70 | bellard | CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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302 | 33417e70 | bellard | |
303 | 33417e70 | bellard | /* ice debug support */
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304 | 4c3a88a2 | bellard | uint32_t breakpoints[MAX_BREAKPOINTS]; |
305 | 4c3a88a2 | bellard | int nb_breakpoints;
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306 | b6d78bfa | bellard | int singlestep_enabled;
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307 | 33417e70 | bellard | |
308 | fc2b4c48 | bellard | /* user data */
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309 | fc2b4c48 | bellard | void *opaque;
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310 | ba1c6e37 | bellard | } CPUX86State; |
311 | 367e86e8 | bellard | |
312 | 927f621e | bellard | #ifndef IN_OP_I386
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313 | 9ba5695c | bellard | void cpu_x86_outb(CPUX86State *env, int addr, int val); |
314 | 9ba5695c | bellard | void cpu_x86_outw(CPUX86State *env, int addr, int val); |
315 | 9ba5695c | bellard | void cpu_x86_outl(CPUX86State *env, int addr, int val); |
316 | 9ba5695c | bellard | int cpu_x86_inb(CPUX86State *env, int addr); |
317 | 9ba5695c | bellard | int cpu_x86_inw(CPUX86State *env, int addr); |
318 | 9ba5695c | bellard | int cpu_x86_inl(CPUX86State *env, int addr); |
319 | 927f621e | bellard | #endif
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320 | 367e86e8 | bellard | |
321 | ba1c6e37 | bellard | CPUX86State *cpu_x86_init(void);
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322 | ba1c6e37 | bellard | int cpu_x86_exec(CPUX86State *s);
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323 | ba1c6e37 | bellard | void cpu_x86_close(CPUX86State *s);
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324 | 66e85a21 | bellard | int cpu_x86_get_pic_interrupt(CPUX86State *s);
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325 | ba1c6e37 | bellard | |
326 | 2e255c6b | bellard | /* this function must always be used to load data in the segment
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327 | 2e255c6b | bellard | cache: it synchronizes the hflags with the segment cache values */
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328 | 2e255c6b | bellard | static inline void cpu_x86_load_seg_cache(CPUX86State *env, |
329 | 2e255c6b | bellard | int seg_reg, unsigned int selector, |
330 | 2e255c6b | bellard | uint8_t *base, unsigned int limit, |
331 | 2e255c6b | bellard | unsigned int flags) |
332 | 2e255c6b | bellard | { |
333 | 2e255c6b | bellard | SegmentCache *sc; |
334 | 2e255c6b | bellard | unsigned int new_hflags; |
335 | 2e255c6b | bellard | |
336 | 2e255c6b | bellard | sc = &env->segs[seg_reg]; |
337 | 2e255c6b | bellard | sc->selector = selector; |
338 | 2e255c6b | bellard | sc->base = base; |
339 | 2e255c6b | bellard | sc->limit = limit; |
340 | 2e255c6b | bellard | sc->flags = flags; |
341 | 2e255c6b | bellard | |
342 | 2e255c6b | bellard | /* update the hidden flags */
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343 | 2e255c6b | bellard | new_hflags = (env->segs[R_CS].flags & DESC_B_MASK) |
344 | 2e255c6b | bellard | >> (DESC_B_SHIFT - HF_CS32_SHIFT); |
345 | 2e255c6b | bellard | new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK) |
346 | 2e255c6b | bellard | >> (DESC_B_SHIFT - HF_SS32_SHIFT); |
347 | 2e255c6b | bellard | if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
348 | 2e255c6b | bellard | /* XXX: try to avoid this test. The problem comes from the
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349 | 2e255c6b | bellard | fact that is real mode or vm86 mode we only modify the
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350 | 2e255c6b | bellard | 'base' and 'selector' fields of the segment cache to go
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351 | 2e255c6b | bellard | faster. A solution may be to force addseg to one in
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352 | 2e255c6b | bellard | translate-i386.c. */
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353 | 2e255c6b | bellard | new_hflags |= HF_ADDSEG_MASK; |
354 | 2e255c6b | bellard | } else {
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355 | 2e255c6b | bellard | new_hflags |= (((unsigned long)env->segs[R_DS].base | |
356 | 2e255c6b | bellard | (unsigned long)env->segs[R_ES].base | |
357 | 2e255c6b | bellard | (unsigned long)env->segs[R_SS].base) != 0) << |
358 | 2e255c6b | bellard | HF_ADDSEG_SHIFT; |
359 | 2e255c6b | bellard | } |
360 | 2e255c6b | bellard | env->hflags = (env->hflags & |
361 | 2e255c6b | bellard | ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags; |
362 | 2e255c6b | bellard | } |
363 | 6dbad63e | bellard | |
364 | b6d78bfa | bellard | /* wrapper, just in case memory mappings must be changed */
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365 | b6d78bfa | bellard | static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl) |
366 | b6d78bfa | bellard | { |
367 | 3f337316 | bellard | #if HF_CPL_MASK == 3 |
368 | 3f337316 | bellard | s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl; |
369 | 3f337316 | bellard | #else
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370 | 3f337316 | bellard | #error HF_CPL_MASK is hardcoded
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371 | 3f337316 | bellard | #endif
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372 | b6d78bfa | bellard | } |
373 | b6d78bfa | bellard | |
374 | 2e255c6b | bellard | /* the following helpers are only usable in user mode simulation as
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375 | 2e255c6b | bellard | they can trigger unexpected exceptions */
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376 | 2e255c6b | bellard | void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); |
377 | d0a1ffc9 | bellard | void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); |
378 | d0a1ffc9 | bellard | void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); |
379 | d0a1ffc9 | bellard | |
380 | d691f669 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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381 | 9de5e440 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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382 | 9de5e440 | bellard | is returned if the signal was handled by the virtual CPU. */
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383 | 9de5e440 | bellard | struct siginfo;
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384 | 9de5e440 | bellard | int cpu_x86_signal_handler(int host_signum, struct siginfo *info, |
385 | 9de5e440 | bellard | void *puc);
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386 | 9de5e440 | bellard | |
387 | 66e85a21 | bellard | /* MMU defines */
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388 | 66e85a21 | bellard | void cpu_x86_init_mmu(CPUX86State *env);
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389 | 66e85a21 | bellard | extern int phys_ram_size; |
390 | 66e85a21 | bellard | extern int phys_ram_fd; |
391 | 66e85a21 | bellard | extern uint8_t *phys_ram_base;
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392 | 66e85a21 | bellard | |
393 | f351077e | bellard | /* used to debug */
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394 | f351077e | bellard | #define X86_DUMP_FPU 0x0001 /* dump FPU state too */ |
395 | f351077e | bellard | #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ |
396 | f351077e | bellard | void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags); |
397 | f351077e | bellard | |
398 | 54936004 | bellard | #define TARGET_PAGE_BITS 12 |
399 | 5a9fdfec | bellard | #include "cpu-all.h" |
400 | 54936004 | bellard | |
401 | 367e86e8 | bellard | #endif /* CPU_I386_H */ |