root / hw / slavio_misc.c @ dbdd2506
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1 | 3475187d | bellard | /*
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2 | 3475187d | bellard | * QEMU Sparc SLAVIO aux io port emulation
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 3475187d | bellard | #include "vl.h" |
25 | 3475187d | bellard | /* debug misc */
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26 | 3475187d | bellard | //#define DEBUG_MISC
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27 | 3475187d | bellard | |
28 | 3475187d | bellard | /*
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29 | 3475187d | bellard | * This is the auxio port, chip control and system control part of
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30 | 3475187d | bellard | * chip STP2001 (Slave I/O), also produced as NCR89C105. See
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31 | 3475187d | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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32 | 3475187d | bellard | *
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33 | 3475187d | bellard | * This also includes the PMC CPU idle controller.
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34 | 3475187d | bellard | */
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35 | 3475187d | bellard | |
36 | 3475187d | bellard | #ifdef DEBUG_MISC
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37 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...) \
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38 | 3475187d | bellard | do { printf("MISC: " fmt , ##args); } while (0) |
39 | 3475187d | bellard | #else
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40 | 3475187d | bellard | #define MISC_DPRINTF(fmt, args...)
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41 | 3475187d | bellard | #endif
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42 | 3475187d | bellard | |
43 | 3475187d | bellard | typedef struct MiscState { |
44 | d537cf6c | pbrook | qemu_irq irq; |
45 | 3475187d | bellard | uint8_t config; |
46 | 3475187d | bellard | uint8_t aux1, aux2; |
47 | 4e3b1ea1 | bellard | uint8_t diag, mctrl, sysctrl; |
48 | 3475187d | bellard | } MiscState; |
49 | 3475187d | bellard | |
50 | 5aca8c3b | blueswir1 | #define MISC_SIZE 1 |
51 | 3475187d | bellard | |
52 | 3475187d | bellard | static void slavio_misc_update_irq(void *opaque) |
53 | 3475187d | bellard | { |
54 | 3475187d | bellard | MiscState *s = opaque; |
55 | 3475187d | bellard | |
56 | 3475187d | bellard | if ((s->aux2 & 0x4) && (s->config & 0x8)) { |
57 | d537cf6c | pbrook | MISC_DPRINTF("Raise IRQ\n");
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58 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
59 | 3475187d | bellard | } else {
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60 | d537cf6c | pbrook | MISC_DPRINTF("Lower IRQ\n");
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61 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
62 | 3475187d | bellard | } |
63 | 3475187d | bellard | } |
64 | 3475187d | bellard | |
65 | 3475187d | bellard | static void slavio_misc_reset(void *opaque) |
66 | 3475187d | bellard | { |
67 | 3475187d | bellard | MiscState *s = opaque; |
68 | 3475187d | bellard | |
69 | 4e3b1ea1 | bellard | // Diagnostic and system control registers not cleared in reset
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70 | 3475187d | bellard | s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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71 | 3475187d | bellard | } |
72 | 3475187d | bellard | |
73 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing) |
74 | 3475187d | bellard | { |
75 | 3475187d | bellard | MiscState *s = opaque; |
76 | 3475187d | bellard | |
77 | 3475187d | bellard | MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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78 | 3475187d | bellard | if (power_failing && (s->config & 0x8)) { |
79 | f930d07e | blueswir1 | s->aux2 |= 0x4;
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80 | 3475187d | bellard | } else {
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81 | f930d07e | blueswir1 | s->aux2 &= ~0x4;
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82 | 3475187d | bellard | } |
83 | 3475187d | bellard | slavio_misc_update_irq(s); |
84 | 3475187d | bellard | } |
85 | 3475187d | bellard | |
86 | 3475187d | bellard | static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
87 | 3475187d | bellard | { |
88 | 3475187d | bellard | MiscState *s = opaque; |
89 | 3475187d | bellard | |
90 | 3475187d | bellard | switch (addr & 0xfff0000) { |
91 | 3475187d | bellard | case 0x1800000: |
92 | f930d07e | blueswir1 | MISC_DPRINTF("Write config %2.2x\n", val & 0xff); |
93 | f930d07e | blueswir1 | s->config = val & 0xff;
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94 | f930d07e | blueswir1 | slavio_misc_update_irq(s); |
95 | f930d07e | blueswir1 | break;
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96 | 3475187d | bellard | case 0x1900000: |
97 | f930d07e | blueswir1 | MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff); |
98 | f930d07e | blueswir1 | s->aux1 = val & 0xff;
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99 | f930d07e | blueswir1 | break;
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100 | 3475187d | bellard | case 0x1910000: |
101 | f930d07e | blueswir1 | val &= 0x3;
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102 | f930d07e | blueswir1 | MISC_DPRINTF("Write aux2 %2.2x\n", val);
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103 | f930d07e | blueswir1 | val |= s->aux2 & 0x4;
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104 | f930d07e | blueswir1 | if (val & 0x2) // Clear Power Fail int |
105 | f930d07e | blueswir1 | val &= 0x1;
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106 | f930d07e | blueswir1 | s->aux2 = val; |
107 | f930d07e | blueswir1 | if (val & 1) |
108 | f930d07e | blueswir1 | qemu_system_shutdown_request(); |
109 | f930d07e | blueswir1 | slavio_misc_update_irq(s); |
110 | f930d07e | blueswir1 | break;
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111 | 3475187d | bellard | case 0x1a00000: |
112 | f930d07e | blueswir1 | MISC_DPRINTF("Write diag %2.2x\n", val & 0xff); |
113 | f930d07e | blueswir1 | s->diag = val & 0xff;
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114 | f930d07e | blueswir1 | break;
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115 | 3475187d | bellard | case 0x1b00000: |
116 | f930d07e | blueswir1 | MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff); |
117 | f930d07e | blueswir1 | s->mctrl = val & 0xff;
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118 | f930d07e | blueswir1 | break;
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119 | 3475187d | bellard | case 0x1f00000: |
120 | f930d07e | blueswir1 | MISC_DPRINTF("Write system control %2.2x\n", val & 0xff); |
121 | f930d07e | blueswir1 | if (val & 1) { |
122 | f930d07e | blueswir1 | s->sysctrl = 0x2;
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123 | f930d07e | blueswir1 | qemu_system_reset_request(); |
124 | f930d07e | blueswir1 | } |
125 | f930d07e | blueswir1 | break;
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126 | 3475187d | bellard | case 0xa000000: |
127 | f930d07e | blueswir1 | MISC_DPRINTF("Write power management %2.2x\n", val & 0xff); |
128 | ba3c64fb | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); |
129 | f930d07e | blueswir1 | break;
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130 | 3475187d | bellard | } |
131 | 3475187d | bellard | } |
132 | 3475187d | bellard | |
133 | 3475187d | bellard | static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr) |
134 | 3475187d | bellard | { |
135 | 3475187d | bellard | MiscState *s = opaque; |
136 | 3475187d | bellard | uint32_t ret = 0;
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137 | 3475187d | bellard | |
138 | 3475187d | bellard | switch (addr & 0xfff0000) { |
139 | 3475187d | bellard | case 0x1800000: |
140 | f930d07e | blueswir1 | ret = s->config; |
141 | f930d07e | blueswir1 | MISC_DPRINTF("Read config %2.2x\n", ret);
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142 | f930d07e | blueswir1 | break;
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143 | 3475187d | bellard | case 0x1900000: |
144 | f930d07e | blueswir1 | ret = s->aux1; |
145 | f930d07e | blueswir1 | MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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146 | f930d07e | blueswir1 | break;
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147 | 3475187d | bellard | case 0x1910000: |
148 | f930d07e | blueswir1 | ret = s->aux2; |
149 | f930d07e | blueswir1 | MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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150 | f930d07e | blueswir1 | break;
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151 | 3475187d | bellard | case 0x1a00000: |
152 | f930d07e | blueswir1 | ret = s->diag; |
153 | f930d07e | blueswir1 | MISC_DPRINTF("Read diag %2.2x\n", ret);
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154 | f930d07e | blueswir1 | break;
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155 | 3475187d | bellard | case 0x1b00000: |
156 | f930d07e | blueswir1 | ret = s->mctrl; |
157 | f930d07e | blueswir1 | MISC_DPRINTF("Read modem control %2.2x\n", ret);
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158 | f930d07e | blueswir1 | break;
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159 | 3475187d | bellard | case 0x1f00000: |
160 | f930d07e | blueswir1 | MISC_DPRINTF("Read system control %2.2x\n", ret);
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161 | f930d07e | blueswir1 | ret = s->sysctrl; |
162 | f930d07e | blueswir1 | break;
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163 | 3475187d | bellard | case 0xa000000: |
164 | f930d07e | blueswir1 | MISC_DPRINTF("Read power management %2.2x\n", ret);
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165 | f930d07e | blueswir1 | break;
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166 | 3475187d | bellard | } |
167 | 3475187d | bellard | return ret;
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168 | 3475187d | bellard | } |
169 | 3475187d | bellard | |
170 | 3475187d | bellard | static CPUReadMemoryFunc *slavio_misc_mem_read[3] = { |
171 | 3475187d | bellard | slavio_misc_mem_readb, |
172 | 3475187d | bellard | slavio_misc_mem_readb, |
173 | 3475187d | bellard | slavio_misc_mem_readb, |
174 | 3475187d | bellard | }; |
175 | 3475187d | bellard | |
176 | 3475187d | bellard | static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = { |
177 | 3475187d | bellard | slavio_misc_mem_writeb, |
178 | 3475187d | bellard | slavio_misc_mem_writeb, |
179 | 3475187d | bellard | slavio_misc_mem_writeb, |
180 | 3475187d | bellard | }; |
181 | 3475187d | bellard | |
182 | 3475187d | bellard | static void slavio_misc_save(QEMUFile *f, void *opaque) |
183 | 3475187d | bellard | { |
184 | 3475187d | bellard | MiscState *s = opaque; |
185 | d537cf6c | pbrook | int tmp;
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186 | 3475187d | bellard | |
187 | d537cf6c | pbrook | tmp = 0;
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188 | d537cf6c | pbrook | qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
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189 | 3475187d | bellard | qemu_put_8s(f, &s->config); |
190 | 3475187d | bellard | qemu_put_8s(f, &s->aux1); |
191 | 3475187d | bellard | qemu_put_8s(f, &s->aux2); |
192 | 3475187d | bellard | qemu_put_8s(f, &s->diag); |
193 | 3475187d | bellard | qemu_put_8s(f, &s->mctrl); |
194 | 4e3b1ea1 | bellard | qemu_put_8s(f, &s->sysctrl); |
195 | 3475187d | bellard | } |
196 | 3475187d | bellard | |
197 | 3475187d | bellard | static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id) |
198 | 3475187d | bellard | { |
199 | 3475187d | bellard | MiscState *s = opaque; |
200 | d537cf6c | pbrook | int tmp;
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201 | 3475187d | bellard | |
202 | 3475187d | bellard | if (version_id != 1) |
203 | 3475187d | bellard | return -EINVAL;
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204 | 3475187d | bellard | |
205 | d537cf6c | pbrook | qemu_get_be32s(f, &tmp); |
206 | 3475187d | bellard | qemu_get_8s(f, &s->config); |
207 | 3475187d | bellard | qemu_get_8s(f, &s->aux1); |
208 | 3475187d | bellard | qemu_get_8s(f, &s->aux2); |
209 | 3475187d | bellard | qemu_get_8s(f, &s->diag); |
210 | 3475187d | bellard | qemu_get_8s(f, &s->mctrl); |
211 | 4e3b1ea1 | bellard | qemu_get_8s(f, &s->sysctrl); |
212 | 3475187d | bellard | return 0; |
213 | 3475187d | bellard | } |
214 | 3475187d | bellard | |
215 | 5dcb6b91 | blueswir1 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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216 | 5dcb6b91 | blueswir1 | qemu_irq irq) |
217 | 3475187d | bellard | { |
218 | 3475187d | bellard | int slavio_misc_io_memory;
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219 | 3475187d | bellard | MiscState *s; |
220 | 3475187d | bellard | |
221 | 3475187d | bellard | s = qemu_mallocz(sizeof(MiscState));
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222 | 3475187d | bellard | if (!s)
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223 | 3475187d | bellard | return NULL; |
224 | 3475187d | bellard | |
225 | 3475187d | bellard | slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);
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226 | 3475187d | bellard | // Slavio control
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227 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1800000, MISC_SIZE,
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228 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
229 | 3475187d | bellard | // AUX 1
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230 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1900000, MISC_SIZE,
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231 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
232 | 3475187d | bellard | // AUX 2
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233 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1910000, MISC_SIZE,
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234 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
235 | 3475187d | bellard | // Diagnostics
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236 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1a00000, MISC_SIZE,
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237 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
238 | 3475187d | bellard | // Modem control
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239 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE,
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240 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
241 | 3475187d | bellard | // System control
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242 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(base + 0x1f00000, MISC_SIZE,
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243 | 5aca8c3b | blueswir1 | slavio_misc_io_memory); |
244 | 3475187d | bellard | // Power management
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245 | 5aca8c3b | blueswir1 | cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory); |
246 | 3475187d | bellard | |
247 | 3475187d | bellard | s->irq = irq; |
248 | 3475187d | bellard | |
249 | 3475187d | bellard | register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s); |
250 | 3475187d | bellard | qemu_register_reset(slavio_misc_reset, s); |
251 | 3475187d | bellard | slavio_misc_reset(s); |
252 | 3475187d | bellard | return s;
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253 | 3475187d | bellard | } |