Revision dc196a57 target-i386/cpu.h

b/target-i386/cpu.h
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/* 16 or 32 segments */
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#define HF_CS32_SHIFT        4
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#define HF_SS32_SHIFT        5
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/* zero base for DS, ES and SS */
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/* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
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#define HF_ADDSEG_SHIFT      6
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/* copy of CR0.PE (protected mode) */
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#define HF_PE_SHIFT          7
......
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        >> (DESC_B_SHIFT - HF_CS32_SHIFT);
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    new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
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        >> (DESC_B_SHIFT - HF_SS32_SHIFT);
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    if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
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    if (!(env->cr[0] & CR0_PE_MASK) ||
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        (env->eflags & VM_MASK) ||
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        !(new_hflags & HF_CS32_MASK)) {
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        /* XXX: try to avoid this test. The problem comes from the
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           fact that is real mode or vm86 mode we only modify the
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           'base' and 'selector' fields of the segment cache to go

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