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#ifndef __SVM_H
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#define __SVM_H
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#define TLB_CONTROL_DO_NOTHING 0 |
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#define TLB_CONTROL_FLUSH_ALL_ASID 1 |
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#define V_TPR_MASK 0x0f |
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#define V_IRQ_SHIFT 8 |
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#define V_IRQ_MASK (1 << V_IRQ_SHIFT) |
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#define V_INTR_PRIO_SHIFT 16 |
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#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) |
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#define V_IGN_TPR_SHIFT 20 |
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#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) |
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#define V_INTR_MASKING_SHIFT 24 |
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#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) |
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#define SVM_INTERRUPT_SHADOW_MASK 1 |
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#define SVM_IOIO_STR_SHIFT 2 |
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#define SVM_IOIO_REP_SHIFT 3 |
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#define SVM_IOIO_SIZE_SHIFT 4 |
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#define SVM_IOIO_ASIZE_SHIFT 7 |
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#define SVM_IOIO_TYPE_MASK 1 |
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#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) |
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#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) |
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#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) |
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#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) |
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#define SVM_EVTINJ_VEC_MASK 0xff |
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#define SVM_EVTINJ_TYPE_SHIFT 8 |
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#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) |
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#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) |
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#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) |
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#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) |
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#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) |
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#define SVM_EVTINJ_VALID (1 << 31) |
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#define SVM_EVTINJ_VALID_ERR (1 << 11) |
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#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
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#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
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#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
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#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
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#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
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#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
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#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
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#define SVM_EXIT_READ_CR0 0x000 |
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#define SVM_EXIT_READ_CR3 0x003 |
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#define SVM_EXIT_READ_CR4 0x004 |
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#define SVM_EXIT_READ_CR8 0x008 |
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#define SVM_EXIT_WRITE_CR0 0x010 |
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#define SVM_EXIT_WRITE_CR3 0x013 |
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#define SVM_EXIT_WRITE_CR4 0x014 |
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#define SVM_EXIT_WRITE_CR8 0x018 |
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#define SVM_EXIT_READ_DR0 0x020 |
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#define SVM_EXIT_READ_DR1 0x021 |
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#define SVM_EXIT_READ_DR2 0x022 |
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#define SVM_EXIT_READ_DR3 0x023 |
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#define SVM_EXIT_READ_DR4 0x024 |
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#define SVM_EXIT_READ_DR5 0x025 |
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#define SVM_EXIT_READ_DR6 0x026 |
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#define SVM_EXIT_READ_DR7 0x027 |
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#define SVM_EXIT_WRITE_DR0 0x030 |
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#define SVM_EXIT_WRITE_DR1 0x031 |
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#define SVM_EXIT_WRITE_DR2 0x032 |
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#define SVM_EXIT_WRITE_DR3 0x033 |
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#define SVM_EXIT_WRITE_DR4 0x034 |
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#define SVM_EXIT_WRITE_DR5 0x035 |
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#define SVM_EXIT_WRITE_DR6 0x036 |
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#define SVM_EXIT_WRITE_DR7 0x037 |
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#define SVM_EXIT_EXCP_BASE 0x040 |
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#define SVM_EXIT_INTR 0x060 |
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#define SVM_EXIT_NMI 0x061 |
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#define SVM_EXIT_SMI 0x062 |
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#define SVM_EXIT_INIT 0x063 |
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#define SVM_EXIT_VINTR 0x064 |
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#define SVM_EXIT_CR0_SEL_WRITE 0x065 |
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#define SVM_EXIT_IDTR_READ 0x066 |
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#define SVM_EXIT_GDTR_READ 0x067 |
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#define SVM_EXIT_LDTR_READ 0x068 |
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#define SVM_EXIT_TR_READ 0x069 |
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#define SVM_EXIT_IDTR_WRITE 0x06a |
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#define SVM_EXIT_GDTR_WRITE 0x06b |
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#define SVM_EXIT_LDTR_WRITE 0x06c |
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#define SVM_EXIT_TR_WRITE 0x06d |
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#define SVM_EXIT_RDTSC 0x06e |
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#define SVM_EXIT_RDPMC 0x06f |
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#define SVM_EXIT_PUSHF 0x070 |
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#define SVM_EXIT_POPF 0x071 |
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#define SVM_EXIT_CPUID 0x072 |
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#define SVM_EXIT_RSM 0x073 |
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#define SVM_EXIT_IRET 0x074 |
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#define SVM_EXIT_SWINT 0x075 |
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#define SVM_EXIT_INVD 0x076 |
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#define SVM_EXIT_PAUSE 0x077 |
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#define SVM_EXIT_HLT 0x078 |
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#define SVM_EXIT_INVLPG 0x079 |
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#define SVM_EXIT_INVLPGA 0x07a |
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#define SVM_EXIT_IOIO 0x07b |
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#define SVM_EXIT_MSR 0x07c |
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#define SVM_EXIT_TASK_SWITCH 0x07d |
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#define SVM_EXIT_FERR_FREEZE 0x07e |
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#define SVM_EXIT_SHUTDOWN 0x07f |
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#define SVM_EXIT_VMRUN 0x080 |
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#define SVM_EXIT_VMMCALL 0x081 |
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#define SVM_EXIT_VMLOAD 0x082 |
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#define SVM_EXIT_VMSAVE 0x083 |
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#define SVM_EXIT_STGI 0x084 |
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#define SVM_EXIT_CLGI 0x085 |
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#define SVM_EXIT_SKINIT 0x086 |
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#define SVM_EXIT_RDTSCP 0x087 |
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#define SVM_EXIT_ICEBP 0x088 |
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#define SVM_EXIT_WBINVD 0x089 |
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/* only included in documentation, maybe wrong */
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#define SVM_EXIT_MONITOR 0x08a |
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#define SVM_EXIT_MWAIT 0x08b |
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#define SVM_EXIT_NPF 0x400 |
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#define SVM_EXIT_ERR -1 |
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#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ |
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struct QEMU_PACKED vmcb_control_area {
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uint16_t intercept_cr_read; |
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uint16_t intercept_cr_write; |
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uint16_t intercept_dr_read; |
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uint16_t intercept_dr_write; |
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uint32_t intercept_exceptions; |
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uint64_t intercept; |
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uint8_t reserved_1[44];
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uint64_t iopm_base_pa; |
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uint64_t msrpm_base_pa; |
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uint64_t tsc_offset; |
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uint32_t asid; |
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uint8_t tlb_ctl; |
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uint8_t reserved_2[3];
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uint32_t int_ctl; |
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uint32_t int_vector; |
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uint32_t int_state; |
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uint8_t reserved_3[4];
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uint64_t exit_code; |
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uint64_t exit_info_1; |
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uint64_t exit_info_2; |
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uint32_t exit_int_info; |
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uint32_t exit_int_info_err; |
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uint64_t nested_ctl; |
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uint8_t reserved_4[16];
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uint32_t event_inj; |
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uint32_t event_inj_err; |
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uint64_t nested_cr3; |
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uint64_t lbr_ctl; |
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uint8_t reserved_5[832];
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}; |
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struct QEMU_PACKED vmcb_seg {
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uint16_t selector; |
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uint16_t attrib; |
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uint32_t limit; |
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uint64_t base; |
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}; |
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struct QEMU_PACKED vmcb_save_area {
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struct vmcb_seg es;
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struct vmcb_seg cs;
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struct vmcb_seg ss;
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struct vmcb_seg ds;
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struct vmcb_seg fs;
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struct vmcb_seg gs;
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struct vmcb_seg gdtr;
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struct vmcb_seg ldtr;
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struct vmcb_seg idtr;
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struct vmcb_seg tr;
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uint8_t reserved_1[43];
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uint8_t cpl; |
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uint8_t reserved_2[4];
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uint64_t efer; |
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uint8_t reserved_3[112];
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uint64_t cr4; |
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uint64_t cr3; |
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uint64_t cr0; |
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uint64_t dr7; |
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uint64_t dr6; |
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uint64_t rflags; |
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uint64_t rip; |
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uint8_t reserved_4[88];
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uint64_t rsp; |
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uint8_t reserved_5[24];
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uint64_t rax; |
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uint64_t star; |
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uint64_t lstar; |
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uint64_t cstar; |
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uint64_t sfmask; |
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uint64_t kernel_gs_base; |
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uint64_t sysenter_cs; |
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uint64_t sysenter_esp; |
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uint64_t sysenter_eip; |
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uint64_t cr2; |
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uint8_t reserved_6[32];
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uint64_t g_pat; |
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uint64_t dbgctl; |
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uint64_t br_from; |
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uint64_t br_to; |
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uint64_t last_excp_from; |
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uint64_t last_excp_to; |
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}; |
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struct QEMU_PACKED vmcb {
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struct vmcb_control_area control;
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struct vmcb_save_area save;
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}; |
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#endif
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