root / hw / i8254.c @ dc5d0b3d
History | View | Annotate | Download (12.6 kB)
1 | 80cabfad | bellard | /*
|
---|---|---|---|
2 | 80cabfad | bellard | * QEMU 8253/8254 interval timer emulation
|
3 | 80cabfad | bellard | *
|
4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
|
5 | 80cabfad | bellard | *
|
6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
|
12 | 80cabfad | bellard | *
|
13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
|
15 | 80cabfad | bellard | *
|
16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 80cabfad | bellard | * THE SOFTWARE.
|
23 | 80cabfad | bellard | */
|
24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | b0a21b53 | bellard | //#define DEBUG_PIT
|
27 | b0a21b53 | bellard | |
28 | ec844b96 | bellard | #define RW_STATE_LSB 1 |
29 | ec844b96 | bellard | #define RW_STATE_MSB 2 |
30 | ec844b96 | bellard | #define RW_STATE_WORD0 3 |
31 | ec844b96 | bellard | #define RW_STATE_WORD1 4 |
32 | 80cabfad | bellard | |
33 | ec844b96 | bellard | typedef struct PITChannelState { |
34 | ec844b96 | bellard | int count; /* can be 65536 */ |
35 | ec844b96 | bellard | uint16_t latched_count; |
36 | ec844b96 | bellard | uint8_t count_latched; |
37 | ec844b96 | bellard | uint8_t status_latched; |
38 | ec844b96 | bellard | uint8_t status; |
39 | ec844b96 | bellard | uint8_t read_state; |
40 | ec844b96 | bellard | uint8_t write_state; |
41 | ec844b96 | bellard | uint8_t write_latch; |
42 | ec844b96 | bellard | uint8_t rw_mode; |
43 | ec844b96 | bellard | uint8_t mode; |
44 | ec844b96 | bellard | uint8_t bcd; /* not supported */
|
45 | ec844b96 | bellard | uint8_t gate; /* timer start */
|
46 | ec844b96 | bellard | int64_t count_load_time; |
47 | ec844b96 | bellard | /* irq handling */
|
48 | ec844b96 | bellard | int64_t next_transition_time; |
49 | ec844b96 | bellard | QEMUTimer *irq_timer; |
50 | ec844b96 | bellard | int irq;
|
51 | ec844b96 | bellard | } PITChannelState; |
52 | ec844b96 | bellard | |
53 | ec844b96 | bellard | struct PITState {
|
54 | ec844b96 | bellard | PITChannelState channels[3];
|
55 | ec844b96 | bellard | }; |
56 | ec844b96 | bellard | |
57 | ec844b96 | bellard | static PITState pit_state;
|
58 | 80cabfad | bellard | |
59 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); |
60 | b0a21b53 | bellard | |
61 | 80cabfad | bellard | static int pit_get_count(PITChannelState *s) |
62 | 80cabfad | bellard | { |
63 | 80cabfad | bellard | uint64_t d; |
64 | 80cabfad | bellard | int counter;
|
65 | 80cabfad | bellard | |
66 | b0a21b53 | bellard | d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec); |
67 | 80cabfad | bellard | switch(s->mode) {
|
68 | 80cabfad | bellard | case 0: |
69 | 80cabfad | bellard | case 1: |
70 | 80cabfad | bellard | case 4: |
71 | 80cabfad | bellard | case 5: |
72 | 80cabfad | bellard | counter = (s->count - d) & 0xffff;
|
73 | 80cabfad | bellard | break;
|
74 | 80cabfad | bellard | case 3: |
75 | 80cabfad | bellard | /* XXX: may be incorrect for odd counts */
|
76 | 80cabfad | bellard | counter = s->count - ((2 * d) % s->count);
|
77 | 80cabfad | bellard | break;
|
78 | 80cabfad | bellard | default:
|
79 | 80cabfad | bellard | counter = s->count - (d % s->count); |
80 | 80cabfad | bellard | break;
|
81 | 80cabfad | bellard | } |
82 | 80cabfad | bellard | return counter;
|
83 | 80cabfad | bellard | } |
84 | 80cabfad | bellard | |
85 | 80cabfad | bellard | /* get pit output bit */
|
86 | ec844b96 | bellard | static int pit_get_out1(PITChannelState *s, int64_t current_time) |
87 | 80cabfad | bellard | { |
88 | 80cabfad | bellard | uint64_t d; |
89 | 80cabfad | bellard | int out;
|
90 | 80cabfad | bellard | |
91 | b0a21b53 | bellard | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); |
92 | 80cabfad | bellard | switch(s->mode) {
|
93 | 80cabfad | bellard | default:
|
94 | 80cabfad | bellard | case 0: |
95 | 80cabfad | bellard | out = (d >= s->count); |
96 | 80cabfad | bellard | break;
|
97 | 80cabfad | bellard | case 1: |
98 | 80cabfad | bellard | out = (d < s->count); |
99 | 80cabfad | bellard | break;
|
100 | 80cabfad | bellard | case 2: |
101 | 80cabfad | bellard | if ((d % s->count) == 0 && d != 0) |
102 | 80cabfad | bellard | out = 1;
|
103 | 80cabfad | bellard | else
|
104 | 80cabfad | bellard | out = 0;
|
105 | 80cabfad | bellard | break;
|
106 | 80cabfad | bellard | case 3: |
107 | 80cabfad | bellard | out = (d % s->count) < ((s->count + 1) >> 1); |
108 | 80cabfad | bellard | break;
|
109 | 80cabfad | bellard | case 4: |
110 | 80cabfad | bellard | case 5: |
111 | 80cabfad | bellard | out = (d == s->count); |
112 | 80cabfad | bellard | break;
|
113 | 80cabfad | bellard | } |
114 | 80cabfad | bellard | return out;
|
115 | 80cabfad | bellard | } |
116 | 80cabfad | bellard | |
117 | ec844b96 | bellard | int pit_get_out(PITState *pit, int channel, int64_t current_time) |
118 | ec844b96 | bellard | { |
119 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
120 | ec844b96 | bellard | return pit_get_out1(s, current_time);
|
121 | ec844b96 | bellard | } |
122 | ec844b96 | bellard | |
123 | b0a21b53 | bellard | /* return -1 if no transition will occur. */
|
124 | b0a21b53 | bellard | static int64_t pit_get_next_transition_time(PITChannelState *s,
|
125 | b0a21b53 | bellard | int64_t current_time) |
126 | 80cabfad | bellard | { |
127 | b0a21b53 | bellard | uint64_t d, next_time, base; |
128 | b0a21b53 | bellard | int period2;
|
129 | 80cabfad | bellard | |
130 | b0a21b53 | bellard | d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec); |
131 | 80cabfad | bellard | switch(s->mode) {
|
132 | 80cabfad | bellard | default:
|
133 | 80cabfad | bellard | case 0: |
134 | 80cabfad | bellard | case 1: |
135 | b0a21b53 | bellard | if (d < s->count)
|
136 | b0a21b53 | bellard | next_time = s->count; |
137 | b0a21b53 | bellard | else
|
138 | b0a21b53 | bellard | return -1; |
139 | 80cabfad | bellard | break;
|
140 | 80cabfad | bellard | case 2: |
141 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
142 | b0a21b53 | bellard | if ((d - base) == 0 && d != 0) |
143 | b0a21b53 | bellard | next_time = base + s->count; |
144 | b0a21b53 | bellard | else
|
145 | b0a21b53 | bellard | next_time = base + s->count + 1;
|
146 | 80cabfad | bellard | break;
|
147 | 80cabfad | bellard | case 3: |
148 | b0a21b53 | bellard | base = (d / s->count) * s->count; |
149 | b0a21b53 | bellard | period2 = ((s->count + 1) >> 1); |
150 | b0a21b53 | bellard | if ((d - base) < period2)
|
151 | b0a21b53 | bellard | next_time = base + period2; |
152 | b0a21b53 | bellard | else
|
153 | b0a21b53 | bellard | next_time = base + s->count; |
154 | 80cabfad | bellard | break;
|
155 | 80cabfad | bellard | case 4: |
156 | 80cabfad | bellard | case 5: |
157 | b0a21b53 | bellard | if (d < s->count)
|
158 | b0a21b53 | bellard | next_time = s->count; |
159 | b0a21b53 | bellard | else if (d == s->count) |
160 | b0a21b53 | bellard | next_time = s->count + 1;
|
161 | 80cabfad | bellard | else
|
162 | b0a21b53 | bellard | return -1; |
163 | 80cabfad | bellard | break;
|
164 | 80cabfad | bellard | } |
165 | b0a21b53 | bellard | /* convert to timer units */
|
166 | b0a21b53 | bellard | next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ); |
167 | 1154e441 | bellard | /* fix potential rounding problems */
|
168 | 1154e441 | bellard | /* XXX: better solution: use a clock at PIT_FREQ Hz */
|
169 | 1154e441 | bellard | if (next_time <= current_time)
|
170 | 1154e441 | bellard | next_time = current_time + 1;
|
171 | b0a21b53 | bellard | return next_time;
|
172 | 80cabfad | bellard | } |
173 | 80cabfad | bellard | |
174 | 80cabfad | bellard | /* val must be 0 or 1 */
|
175 | ec844b96 | bellard | void pit_set_gate(PITState *pit, int channel, int val) |
176 | 80cabfad | bellard | { |
177 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
178 | ec844b96 | bellard | |
179 | 80cabfad | bellard | switch(s->mode) {
|
180 | 80cabfad | bellard | default:
|
181 | 80cabfad | bellard | case 0: |
182 | 80cabfad | bellard | case 4: |
183 | 80cabfad | bellard | /* XXX: just disable/enable counting */
|
184 | 80cabfad | bellard | break;
|
185 | 80cabfad | bellard | case 1: |
186 | 80cabfad | bellard | case 5: |
187 | 80cabfad | bellard | if (s->gate < val) {
|
188 | 80cabfad | bellard | /* restart counting on rising edge */
|
189 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
190 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
191 | 80cabfad | bellard | } |
192 | 80cabfad | bellard | break;
|
193 | 80cabfad | bellard | case 2: |
194 | 80cabfad | bellard | case 3: |
195 | 80cabfad | bellard | if (s->gate < val) {
|
196 | 80cabfad | bellard | /* restart counting on rising edge */
|
197 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
198 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
199 | 80cabfad | bellard | } |
200 | 80cabfad | bellard | /* XXX: disable/enable counting */
|
201 | 80cabfad | bellard | break;
|
202 | 80cabfad | bellard | } |
203 | 80cabfad | bellard | s->gate = val; |
204 | 80cabfad | bellard | } |
205 | 80cabfad | bellard | |
206 | ec844b96 | bellard | int pit_get_gate(PITState *pit, int channel) |
207 | ec844b96 | bellard | { |
208 | ec844b96 | bellard | PITChannelState *s = &pit->channels[channel]; |
209 | ec844b96 | bellard | return s->gate;
|
210 | ec844b96 | bellard | } |
211 | ec844b96 | bellard | |
212 | 80cabfad | bellard | static inline void pit_load_count(PITChannelState *s, int val) |
213 | 80cabfad | bellard | { |
214 | 80cabfad | bellard | if (val == 0) |
215 | 80cabfad | bellard | val = 0x10000;
|
216 | b0a21b53 | bellard | s->count_load_time = qemu_get_clock(vm_clock); |
217 | 80cabfad | bellard | s->count = val; |
218 | b0a21b53 | bellard | pit_irq_timer_update(s, s->count_load_time); |
219 | 80cabfad | bellard | } |
220 | 80cabfad | bellard | |
221 | ec844b96 | bellard | /* if already latched, do not latch again */
|
222 | ec844b96 | bellard | static void pit_latch_count(PITChannelState *s) |
223 | ec844b96 | bellard | { |
224 | ec844b96 | bellard | if (!s->count_latched) {
|
225 | ec844b96 | bellard | s->latched_count = pit_get_count(s); |
226 | ec844b96 | bellard | s->count_latched = s->rw_mode; |
227 | ec844b96 | bellard | } |
228 | ec844b96 | bellard | } |
229 | ec844b96 | bellard | |
230 | b41a2cd1 | bellard | static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
231 | 80cabfad | bellard | { |
232 | ec844b96 | bellard | PITState *pit = opaque; |
233 | 80cabfad | bellard | int channel, access;
|
234 | 80cabfad | bellard | PITChannelState *s; |
235 | 80cabfad | bellard | |
236 | 80cabfad | bellard | addr &= 3;
|
237 | 80cabfad | bellard | if (addr == 3) { |
238 | 80cabfad | bellard | channel = val >> 6;
|
239 | ec844b96 | bellard | if (channel == 3) { |
240 | ec844b96 | bellard | /* read back command */
|
241 | ec844b96 | bellard | for(channel = 0; channel < 3; channel++) { |
242 | ec844b96 | bellard | s = &pit->channels[channel]; |
243 | ec844b96 | bellard | if (val & (2 << channel)) { |
244 | ec844b96 | bellard | if (!(val & 0x20)) { |
245 | ec844b96 | bellard | pit_latch_count(s); |
246 | ec844b96 | bellard | } |
247 | ec844b96 | bellard | if (!(val & 0x10) && !s->status_latched) { |
248 | ec844b96 | bellard | /* status latch */
|
249 | ec844b96 | bellard | /* XXX: add BCD and null count */
|
250 | ec844b96 | bellard | s->status = (pit_get_out1(s, qemu_get_clock(vm_clock)) << 7) |
|
251 | ec844b96 | bellard | (s->rw_mode << 4) |
|
252 | ec844b96 | bellard | (s->mode << 1) |
|
253 | ec844b96 | bellard | s->bcd; |
254 | ec844b96 | bellard | s->status_latched = 1;
|
255 | ec844b96 | bellard | } |
256 | ec844b96 | bellard | } |
257 | ec844b96 | bellard | } |
258 | ec844b96 | bellard | } else {
|
259 | ec844b96 | bellard | s = &pit->channels[channel]; |
260 | ec844b96 | bellard | access = (val >> 4) & 3; |
261 | ec844b96 | bellard | if (access == 0) { |
262 | ec844b96 | bellard | pit_latch_count(s); |
263 | ec844b96 | bellard | } else {
|
264 | ec844b96 | bellard | s->rw_mode = access; |
265 | ec844b96 | bellard | s->read_state = access; |
266 | ec844b96 | bellard | s->write_state = access; |
267 | ec844b96 | bellard | |
268 | ec844b96 | bellard | s->mode = (val >> 1) & 7; |
269 | ec844b96 | bellard | s->bcd = val & 1;
|
270 | ec844b96 | bellard | /* XXX: update irq timer ? */
|
271 | ec844b96 | bellard | } |
272 | 80cabfad | bellard | } |
273 | 80cabfad | bellard | } else {
|
274 | ec844b96 | bellard | s = &pit->channels[addr]; |
275 | ec844b96 | bellard | switch(s->write_state) {
|
276 | ec844b96 | bellard | default:
|
277 | 80cabfad | bellard | case RW_STATE_LSB:
|
278 | 80cabfad | bellard | pit_load_count(s, val); |
279 | 80cabfad | bellard | break;
|
280 | 80cabfad | bellard | case RW_STATE_MSB:
|
281 | 80cabfad | bellard | pit_load_count(s, val << 8);
|
282 | 80cabfad | bellard | break;
|
283 | 80cabfad | bellard | case RW_STATE_WORD0:
|
284 | ec844b96 | bellard | s->write_latch = val; |
285 | ec844b96 | bellard | s->write_state = RW_STATE_WORD1; |
286 | ec844b96 | bellard | break;
|
287 | 80cabfad | bellard | case RW_STATE_WORD1:
|
288 | ec844b96 | bellard | pit_load_count(s, s->write_latch | (val << 8));
|
289 | ec844b96 | bellard | s->write_state = RW_STATE_WORD0; |
290 | 80cabfad | bellard | break;
|
291 | 80cabfad | bellard | } |
292 | 80cabfad | bellard | } |
293 | 80cabfad | bellard | } |
294 | 80cabfad | bellard | |
295 | b41a2cd1 | bellard | static uint32_t pit_ioport_read(void *opaque, uint32_t addr) |
296 | 80cabfad | bellard | { |
297 | ec844b96 | bellard | PITState *pit = opaque; |
298 | 80cabfad | bellard | int ret, count;
|
299 | 80cabfad | bellard | PITChannelState *s; |
300 | 80cabfad | bellard | |
301 | 80cabfad | bellard | addr &= 3;
|
302 | ec844b96 | bellard | s = &pit->channels[addr]; |
303 | ec844b96 | bellard | if (s->status_latched) {
|
304 | ec844b96 | bellard | s->status_latched = 0;
|
305 | ec844b96 | bellard | ret = s->status; |
306 | ec844b96 | bellard | } else if (s->count_latched) { |
307 | ec844b96 | bellard | switch(s->count_latched) {
|
308 | ec844b96 | bellard | default:
|
309 | ec844b96 | bellard | case RW_STATE_LSB:
|
310 | ec844b96 | bellard | ret = s->latched_count & 0xff;
|
311 | ec844b96 | bellard | s->count_latched = 0;
|
312 | ec844b96 | bellard | break;
|
313 | ec844b96 | bellard | case RW_STATE_MSB:
|
314 | 80cabfad | bellard | ret = s->latched_count >> 8;
|
315 | ec844b96 | bellard | s->count_latched = 0;
|
316 | ec844b96 | bellard | break;
|
317 | ec844b96 | bellard | case RW_STATE_WORD0:
|
318 | 80cabfad | bellard | ret = s->latched_count & 0xff;
|
319 | ec844b96 | bellard | s->count_latched = RW_STATE_MSB; |
320 | ec844b96 | bellard | break;
|
321 | ec844b96 | bellard | } |
322 | ec844b96 | bellard | } else {
|
323 | ec844b96 | bellard | switch(s->read_state) {
|
324 | ec844b96 | bellard | default:
|
325 | ec844b96 | bellard | case RW_STATE_LSB:
|
326 | ec844b96 | bellard | count = pit_get_count(s); |
327 | ec844b96 | bellard | ret = count & 0xff;
|
328 | ec844b96 | bellard | break;
|
329 | ec844b96 | bellard | case RW_STATE_MSB:
|
330 | ec844b96 | bellard | count = pit_get_count(s); |
331 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
332 | ec844b96 | bellard | break;
|
333 | ec844b96 | bellard | case RW_STATE_WORD0:
|
334 | ec844b96 | bellard | count = pit_get_count(s); |
335 | ec844b96 | bellard | ret = count & 0xff;
|
336 | ec844b96 | bellard | s->read_state = RW_STATE_WORD1; |
337 | ec844b96 | bellard | break;
|
338 | ec844b96 | bellard | case RW_STATE_WORD1:
|
339 | ec844b96 | bellard | count = pit_get_count(s); |
340 | ec844b96 | bellard | ret = (count >> 8) & 0xff; |
341 | ec844b96 | bellard | s->read_state = RW_STATE_WORD0; |
342 | ec844b96 | bellard | break;
|
343 | ec844b96 | bellard | } |
344 | 80cabfad | bellard | } |
345 | 80cabfad | bellard | return ret;
|
346 | 80cabfad | bellard | } |
347 | 80cabfad | bellard | |
348 | b0a21b53 | bellard | static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) |
349 | b0a21b53 | bellard | { |
350 | b0a21b53 | bellard | int64_t expire_time; |
351 | b0a21b53 | bellard | int irq_level;
|
352 | b0a21b53 | bellard | |
353 | b0a21b53 | bellard | if (!s->irq_timer)
|
354 | b0a21b53 | bellard | return;
|
355 | b0a21b53 | bellard | expire_time = pit_get_next_transition_time(s, current_time); |
356 | ec844b96 | bellard | irq_level = pit_get_out1(s, current_time); |
357 | b0a21b53 | bellard | pic_set_irq(s->irq, irq_level); |
358 | b0a21b53 | bellard | #ifdef DEBUG_PIT
|
359 | b0a21b53 | bellard | printf("irq_level=%d next_delay=%f\n",
|
360 | b0a21b53 | bellard | irq_level, |
361 | b0a21b53 | bellard | (double)(expire_time - current_time) / ticks_per_sec);
|
362 | b0a21b53 | bellard | #endif
|
363 | b0a21b53 | bellard | s->next_transition_time = expire_time; |
364 | b0a21b53 | bellard | if (expire_time != -1) |
365 | b0a21b53 | bellard | qemu_mod_timer(s->irq_timer, expire_time); |
366 | b0a21b53 | bellard | else
|
367 | b0a21b53 | bellard | qemu_del_timer(s->irq_timer); |
368 | b0a21b53 | bellard | } |
369 | b0a21b53 | bellard | |
370 | b0a21b53 | bellard | static void pit_irq_timer(void *opaque) |
371 | b0a21b53 | bellard | { |
372 | b0a21b53 | bellard | PITChannelState *s = opaque; |
373 | b0a21b53 | bellard | |
374 | b0a21b53 | bellard | pit_irq_timer_update(s, s->next_transition_time); |
375 | b0a21b53 | bellard | } |
376 | b0a21b53 | bellard | |
377 | b0a21b53 | bellard | static void pit_save(QEMUFile *f, void *opaque) |
378 | b0a21b53 | bellard | { |
379 | ec844b96 | bellard | PITState *pit = opaque; |
380 | b0a21b53 | bellard | PITChannelState *s; |
381 | b0a21b53 | bellard | int i;
|
382 | b0a21b53 | bellard | |
383 | b0a21b53 | bellard | for(i = 0; i < 3; i++) { |
384 | ec844b96 | bellard | s = &pit->channels[i]; |
385 | b0a21b53 | bellard | qemu_put_be32s(f, &s->count); |
386 | b0a21b53 | bellard | qemu_put_be16s(f, &s->latched_count); |
387 | ec844b96 | bellard | qemu_put_8s(f, &s->count_latched); |
388 | ec844b96 | bellard | qemu_put_8s(f, &s->status_latched); |
389 | ec844b96 | bellard | qemu_put_8s(f, &s->status); |
390 | ec844b96 | bellard | qemu_put_8s(f, &s->read_state); |
391 | ec844b96 | bellard | qemu_put_8s(f, &s->write_state); |
392 | ec844b96 | bellard | qemu_put_8s(f, &s->write_latch); |
393 | ec844b96 | bellard | qemu_put_8s(f, &s->rw_mode); |
394 | b0a21b53 | bellard | qemu_put_8s(f, &s->mode); |
395 | b0a21b53 | bellard | qemu_put_8s(f, &s->bcd); |
396 | b0a21b53 | bellard | qemu_put_8s(f, &s->gate); |
397 | b0a21b53 | bellard | qemu_put_be64s(f, &s->count_load_time); |
398 | b0a21b53 | bellard | if (s->irq_timer) {
|
399 | b0a21b53 | bellard | qemu_put_be64s(f, &s->next_transition_time); |
400 | b0a21b53 | bellard | qemu_put_timer(f, s->irq_timer); |
401 | b0a21b53 | bellard | } |
402 | b0a21b53 | bellard | } |
403 | b0a21b53 | bellard | } |
404 | b0a21b53 | bellard | |
405 | b0a21b53 | bellard | static int pit_load(QEMUFile *f, void *opaque, int version_id) |
406 | b0a21b53 | bellard | { |
407 | ec844b96 | bellard | PITState *pit = opaque; |
408 | b0a21b53 | bellard | PITChannelState *s; |
409 | b0a21b53 | bellard | int i;
|
410 | b0a21b53 | bellard | |
411 | b0a21b53 | bellard | if (version_id != 1) |
412 | b0a21b53 | bellard | return -EINVAL;
|
413 | b0a21b53 | bellard | |
414 | b0a21b53 | bellard | for(i = 0; i < 3; i++) { |
415 | ec844b96 | bellard | s = &pit->channels[i]; |
416 | b0a21b53 | bellard | qemu_get_be32s(f, &s->count); |
417 | b0a21b53 | bellard | qemu_get_be16s(f, &s->latched_count); |
418 | ec844b96 | bellard | qemu_get_8s(f, &s->count_latched); |
419 | ec844b96 | bellard | qemu_get_8s(f, &s->status_latched); |
420 | ec844b96 | bellard | qemu_get_8s(f, &s->status); |
421 | ec844b96 | bellard | qemu_get_8s(f, &s->read_state); |
422 | ec844b96 | bellard | qemu_get_8s(f, &s->write_state); |
423 | ec844b96 | bellard | qemu_get_8s(f, &s->write_latch); |
424 | ec844b96 | bellard | qemu_get_8s(f, &s->rw_mode); |
425 | b0a21b53 | bellard | qemu_get_8s(f, &s->mode); |
426 | b0a21b53 | bellard | qemu_get_8s(f, &s->bcd); |
427 | b0a21b53 | bellard | qemu_get_8s(f, &s->gate); |
428 | b0a21b53 | bellard | qemu_get_be64s(f, &s->count_load_time); |
429 | b0a21b53 | bellard | if (s->irq_timer) {
|
430 | b0a21b53 | bellard | qemu_get_be64s(f, &s->next_transition_time); |
431 | b0a21b53 | bellard | qemu_get_timer(f, s->irq_timer); |
432 | b0a21b53 | bellard | } |
433 | b0a21b53 | bellard | } |
434 | b0a21b53 | bellard | return 0; |
435 | b0a21b53 | bellard | } |
436 | b0a21b53 | bellard | |
437 | d7d02e3c | bellard | static void pit_reset(void *opaque) |
438 | 80cabfad | bellard | { |
439 | d7d02e3c | bellard | PITState *pit = opaque; |
440 | 80cabfad | bellard | PITChannelState *s; |
441 | 80cabfad | bellard | int i;
|
442 | 80cabfad | bellard | |
443 | 80cabfad | bellard | for(i = 0;i < 3; i++) { |
444 | ec844b96 | bellard | s = &pit->channels[i]; |
445 | 80cabfad | bellard | s->mode = 3;
|
446 | 80cabfad | bellard | s->gate = (i != 2);
|
447 | 80cabfad | bellard | pit_load_count(s, 0);
|
448 | 80cabfad | bellard | } |
449 | d7d02e3c | bellard | } |
450 | d7d02e3c | bellard | |
451 | d7d02e3c | bellard | PITState *pit_init(int base, int irq) |
452 | d7d02e3c | bellard | { |
453 | d7d02e3c | bellard | PITState *pit = &pit_state; |
454 | d7d02e3c | bellard | PITChannelState *s; |
455 | d7d02e3c | bellard | |
456 | d7d02e3c | bellard | s = &pit->channels[0];
|
457 | d7d02e3c | bellard | /* the timer 0 is connected to an IRQ */
|
458 | d7d02e3c | bellard | s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); |
459 | d7d02e3c | bellard | s->irq = irq; |
460 | 80cabfad | bellard | |
461 | ec844b96 | bellard | register_savevm("i8254", base, 1, pit_save, pit_load, pit); |
462 | b0a21b53 | bellard | |
463 | d7d02e3c | bellard | qemu_register_reset(pit_reset, pit); |
464 | ec844b96 | bellard | register_ioport_write(base, 4, 1, pit_ioport_write, pit); |
465 | ec844b96 | bellard | register_ioport_read(base, 3, 1, pit_ioport_read, pit); |
466 | d7d02e3c | bellard | |
467 | d7d02e3c | bellard | pit_reset(pit); |
468 | d7d02e3c | bellard | |
469 | ec844b96 | bellard | return pit;
|
470 | 80cabfad | bellard | } |