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1 | b9adb4a6 | bellard | /* ppc-dis.c -- Disassemble PowerPC instructions
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2 | b9adb4a6 | bellard | Copyright 1994 Free Software Foundation, Inc.
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3 | b9adb4a6 | bellard | Written by Ian Lance Taylor, Cygnus Support
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4 | b9adb4a6 | bellard | |
5 | b9adb4a6 | bellard | This file is part of GDB, GAS, and the GNU binutils.
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6 | b9adb4a6 | bellard | |
7 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
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8 | b9adb4a6 | bellard | them and/or modify them under the terms of the GNU General Public
|
9 | b9adb4a6 | bellard | License as published by the Free Software Foundation; either version
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10 | b9adb4a6 | bellard | 2, or (at your option) any later version.
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11 | b9adb4a6 | bellard | |
12 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
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13 | b9adb4a6 | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
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14 | b9adb4a6 | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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15 | b9adb4a6 | bellard | the GNU General Public License for more details.
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16 | b9adb4a6 | bellard | |
17 | b9adb4a6 | bellard | You should have received a copy of the GNU General Public License
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18 | b9adb4a6 | bellard | along with this file; see the file COPYING. If not, write to the Free
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19 | b9adb4a6 | bellard | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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20 | b9adb4a6 | bellard | #include "dis-asm.h" |
21 | b9adb4a6 | bellard | |
22 | b9adb4a6 | bellard | /* ppc.h -- Header file for PowerPC opcode table
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23 | b9adb4a6 | bellard | Copyright 1994 Free Software Foundation, Inc.
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24 | b9adb4a6 | bellard | Written by Ian Lance Taylor, Cygnus Support
|
25 | b9adb4a6 | bellard | |
26 | b9adb4a6 | bellard | This file is part of GDB, GAS, and the GNU binutils.
|
27 | b9adb4a6 | bellard | |
28 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
|
29 | b9adb4a6 | bellard | them and/or modify them under the terms of the GNU General Public
|
30 | b9adb4a6 | bellard | License as published by the Free Software Foundation; either version
|
31 | b9adb4a6 | bellard | 1, or (at your option) any later version.
|
32 | b9adb4a6 | bellard | |
33 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
|
34 | b9adb4a6 | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
35 | b9adb4a6 | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
36 | b9adb4a6 | bellard | the GNU General Public License for more details.
|
37 | b9adb4a6 | bellard | |
38 | b9adb4a6 | bellard | You should have received a copy of the GNU General Public License
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39 | b9adb4a6 | bellard | along with this file; see the file COPYING. If not, write to the Free
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40 | b9adb4a6 | bellard | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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41 | b9adb4a6 | bellard | |
42 | b9adb4a6 | bellard | /* The opcode table is an array of struct powerpc_opcode. */
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43 | b9adb4a6 | bellard | |
44 | b9adb4a6 | bellard | struct powerpc_opcode
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45 | b9adb4a6 | bellard | { |
46 | b9adb4a6 | bellard | /* The opcode name. */
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47 | b9adb4a6 | bellard | const char *name; |
48 | b9adb4a6 | bellard | |
49 | b9adb4a6 | bellard | /* The opcode itself. Those bits which will be filled in with
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50 | b9adb4a6 | bellard | operands are zeroes. */
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51 | 274da6b2 | bellard | uint32_t opcode; |
52 | b9adb4a6 | bellard | |
53 | b9adb4a6 | bellard | /* The opcode mask. This is used by the disassembler. This is a
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54 | b9adb4a6 | bellard | mask containing ones indicating those bits which must match the
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55 | b9adb4a6 | bellard | opcode field, and zeroes indicating those bits which need not
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56 | b9adb4a6 | bellard | match (and are presumably filled in by operands). */
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57 | 274da6b2 | bellard | uint32_t mask; |
58 | b9adb4a6 | bellard | |
59 | b9adb4a6 | bellard | /* One bit flags for the opcode. These are used to indicate which
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60 | b9adb4a6 | bellard | specific processors support the instructions. The defined values
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61 | b9adb4a6 | bellard | are listed below. */
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62 | 274da6b2 | bellard | uint32_t flags; |
63 | b9adb4a6 | bellard | |
64 | b9adb4a6 | bellard | /* An array of operand codes. Each code is an index into the
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65 | b9adb4a6 | bellard | operand table. They appear in the order which the operands must
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66 | b9adb4a6 | bellard | appear in assembly code, and are terminated by a zero. */
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67 | b9adb4a6 | bellard | unsigned char operands[8]; |
68 | b9adb4a6 | bellard | }; |
69 | b9adb4a6 | bellard | |
70 | b9adb4a6 | bellard | /* The table itself is sorted by major opcode number, and is otherwise
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71 | b9adb4a6 | bellard | in the order in which the disassembler should consider
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72 | b9adb4a6 | bellard | instructions. */
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73 | b9adb4a6 | bellard | extern const struct powerpc_opcode powerpc_opcodes[]; |
74 | b9adb4a6 | bellard | extern const int powerpc_num_opcodes; |
75 | b9adb4a6 | bellard | |
76 | b9adb4a6 | bellard | /* Values defined for the flags field of a struct powerpc_opcode. */
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77 | b9adb4a6 | bellard | |
78 | b9adb4a6 | bellard | /* Opcode is defined for the PowerPC architecture. */
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79 | b9adb4a6 | bellard | #define PPC_OPCODE_PPC (01) |
80 | b9adb4a6 | bellard | |
81 | b9adb4a6 | bellard | /* Opcode is defined for the POWER (RS/6000) architecture. */
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82 | b9adb4a6 | bellard | #define PPC_OPCODE_POWER (02) |
83 | b9adb4a6 | bellard | |
84 | b9adb4a6 | bellard | /* Opcode is defined for the POWER2 (Rios 2) architecture. */
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85 | b9adb4a6 | bellard | #define PPC_OPCODE_POWER2 (04) |
86 | b9adb4a6 | bellard | |
87 | b9adb4a6 | bellard | /* Opcode is only defined on 32 bit architectures. */
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88 | b9adb4a6 | bellard | #define PPC_OPCODE_32 (010) |
89 | b9adb4a6 | bellard | |
90 | b9adb4a6 | bellard | /* Opcode is only defined on 64 bit architectures. */
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91 | b9adb4a6 | bellard | #define PPC_OPCODE_64 (020) |
92 | b9adb4a6 | bellard | |
93 | b9adb4a6 | bellard | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
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94 | b9adb4a6 | bellard | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
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95 | b9adb4a6 | bellard | but it also supports many additional POWER instructions. */
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96 | b9adb4a6 | bellard | #define PPC_OPCODE_601 (040) |
97 | b9adb4a6 | bellard | |
98 | b9adb4a6 | bellard | /* A macro to extract the major opcode from an instruction. */
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99 | b9adb4a6 | bellard | #define PPC_OP(i) (((i) >> 26) & 0x3f) |
100 | b9adb4a6 | bellard | |
101 | b9adb4a6 | bellard | /* The operands table is an array of struct powerpc_operand. */
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102 | b9adb4a6 | bellard | |
103 | b9adb4a6 | bellard | struct powerpc_operand
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104 | b9adb4a6 | bellard | { |
105 | b9adb4a6 | bellard | /* The number of bits in the operand. */
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106 | b9adb4a6 | bellard | int bits;
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107 | b9adb4a6 | bellard | |
108 | b9adb4a6 | bellard | /* How far the operand is left shifted in the instruction. */
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109 | b9adb4a6 | bellard | int shift;
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110 | b9adb4a6 | bellard | |
111 | b9adb4a6 | bellard | /* Insertion function. This is used by the assembler. To insert an
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112 | b9adb4a6 | bellard | operand value into an instruction, check this field.
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113 | b9adb4a6 | bellard | |
114 | b9adb4a6 | bellard | If it is NULL, execute
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115 | b9adb4a6 | bellard | i |= (op & ((1 << o->bits) - 1)) << o->shift;
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116 | b9adb4a6 | bellard | (i is the instruction which we are filling in, o is a pointer to
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117 | b9adb4a6 | bellard | this structure, and op is the opcode value; this assumes twos
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118 | b9adb4a6 | bellard | complement arithmetic).
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119 | b9adb4a6 | bellard | |
120 | b9adb4a6 | bellard | If this field is not NULL, then simply call it with the
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121 | b9adb4a6 | bellard | instruction and the operand value. It will return the new value
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122 | b9adb4a6 | bellard | of the instruction. If the ERRMSG argument is not NULL, then if
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123 | b9adb4a6 | bellard | the operand value is illegal, *ERRMSG will be set to a warning
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124 | b9adb4a6 | bellard | string (the operand will be inserted in any case). If the
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125 | b9adb4a6 | bellard | operand value is legal, *ERRMSG will be unchanged (most operands
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126 | b9adb4a6 | bellard | can accept any value). */
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127 | 274da6b2 | bellard | unsigned long (*insert)(uint32_t instruction, int32_t op, |
128 | b9adb4a6 | bellard | const char **errmsg); |
129 | b9adb4a6 | bellard | |
130 | b9adb4a6 | bellard | /* Extraction function. This is used by the disassembler. To
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131 | b9adb4a6 | bellard | extract this operand type from an instruction, check this field.
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132 | b9adb4a6 | bellard | |
133 | b9adb4a6 | bellard | If it is NULL, compute
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134 | b9adb4a6 | bellard | op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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135 | b9adb4a6 | bellard | if ((o->flags & PPC_OPERAND_SIGNED) != 0
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136 | b9adb4a6 | bellard | && (op & (1 << (o->bits - 1))) != 0)
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137 | b9adb4a6 | bellard | op -= 1 << o->bits;
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138 | b9adb4a6 | bellard | (i is the instruction, o is a pointer to this structure, and op
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139 | b9adb4a6 | bellard | is the result; this assumes twos complement arithmetic).
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140 | b9adb4a6 | bellard | |
141 | b9adb4a6 | bellard | If this field is not NULL, then simply call it with the
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142 | b9adb4a6 | bellard | instruction value. It will return the value of the operand. If
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143 | b9adb4a6 | bellard | the INVALID argument is not NULL, *INVALID will be set to
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144 | b9adb4a6 | bellard | non-zero if this operand type can not actually be extracted from
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145 | b9adb4a6 | bellard | this operand (i.e., the instruction does not match). If the
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146 | b9adb4a6 | bellard | operand is valid, *INVALID will not be changed. */
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147 | 274da6b2 | bellard | long (*extract) (uint32_t instruction, int *invalid); |
148 | b9adb4a6 | bellard | |
149 | b9adb4a6 | bellard | /* One bit syntax flags. */
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150 | 274da6b2 | bellard | uint32_t flags; |
151 | b9adb4a6 | bellard | }; |
152 | b9adb4a6 | bellard | |
153 | b9adb4a6 | bellard | /* Elements in the table are retrieved by indexing with values from
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154 | b9adb4a6 | bellard | the operands field of the powerpc_opcodes table. */
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155 | b9adb4a6 | bellard | |
156 | b9adb4a6 | bellard | extern const struct powerpc_operand powerpc_operands[]; |
157 | b9adb4a6 | bellard | |
158 | b9adb4a6 | bellard | /* Values defined for the flags field of a struct powerpc_operand. */
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159 | b9adb4a6 | bellard | |
160 | b9adb4a6 | bellard | /* This operand takes signed values. */
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161 | b9adb4a6 | bellard | #define PPC_OPERAND_SIGNED (01) |
162 | b9adb4a6 | bellard | |
163 | b9adb4a6 | bellard | /* This operand takes signed values, but also accepts a full positive
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164 | b9adb4a6 | bellard | range of values when running in 32 bit mode. That is, if bits is
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165 | b9adb4a6 | bellard | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
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166 | b9adb4a6 | bellard | this flag is ignored. */
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167 | b9adb4a6 | bellard | #define PPC_OPERAND_SIGNOPT (02) |
168 | b9adb4a6 | bellard | |
169 | b9adb4a6 | bellard | /* This operand does not actually exist in the assembler input. This
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170 | b9adb4a6 | bellard | is used to support extended mnemonics such as mr, for which two
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171 | b9adb4a6 | bellard | operands fields are identical. The assembler should call the
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172 | b9adb4a6 | bellard | insert function with any op value. The disassembler should call
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173 | b9adb4a6 | bellard | the extract function, ignore the return value, and check the value
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174 | b9adb4a6 | bellard | placed in the valid argument. */
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175 | b9adb4a6 | bellard | #define PPC_OPERAND_FAKE (04) |
176 | b9adb4a6 | bellard | |
177 | b9adb4a6 | bellard | /* The next operand should be wrapped in parentheses rather than
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178 | b9adb4a6 | bellard | separated from this one by a comma. This is used for the load and
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179 | b9adb4a6 | bellard | store instructions which want their operands to look like
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180 | b9adb4a6 | bellard | reg,displacement(reg)
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181 | b9adb4a6 | bellard | */
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182 | b9adb4a6 | bellard | #define PPC_OPERAND_PARENS (010) |
183 | b9adb4a6 | bellard | |
184 | b9adb4a6 | bellard | /* This operand may use the symbolic names for the CR fields, which
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185 | b9adb4a6 | bellard | are
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186 | b9adb4a6 | bellard | lt 0 gt 1 eq 2 so 3 un 3
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187 | b9adb4a6 | bellard | cr0 0 cr1 1 cr2 2 cr3 3
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188 | b9adb4a6 | bellard | cr4 4 cr5 5 cr6 6 cr7 7
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189 | b9adb4a6 | bellard | These may be combined arithmetically, as in cr2*4+gt. These are
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190 | b9adb4a6 | bellard | only supported on the PowerPC, not the POWER. */
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191 | b9adb4a6 | bellard | #define PPC_OPERAND_CR (020) |
192 | b9adb4a6 | bellard | |
193 | b9adb4a6 | bellard | /* This operand names a register. The disassembler uses this to print
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194 | b9adb4a6 | bellard | register names with a leading 'r'. */
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195 | b9adb4a6 | bellard | #define PPC_OPERAND_GPR (040) |
196 | b9adb4a6 | bellard | |
197 | b9adb4a6 | bellard | /* This operand names a floating point register. The disassembler
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198 | b9adb4a6 | bellard | prints these with a leading 'f'. */
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199 | b9adb4a6 | bellard | #define PPC_OPERAND_FPR (0100) |
200 | b9adb4a6 | bellard | |
201 | b9adb4a6 | bellard | /* This operand is a relative branch displacement. The disassembler
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202 | b9adb4a6 | bellard | prints these symbolically if possible. */
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203 | b9adb4a6 | bellard | #define PPC_OPERAND_RELATIVE (0200) |
204 | b9adb4a6 | bellard | |
205 | b9adb4a6 | bellard | /* This operand is an absolute branch address. The disassembler
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206 | b9adb4a6 | bellard | prints these symbolically if possible. */
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207 | b9adb4a6 | bellard | #define PPC_OPERAND_ABSOLUTE (0400) |
208 | b9adb4a6 | bellard | |
209 | b9adb4a6 | bellard | /* This operand is optional, and is zero if omitted. This is used for
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210 | b9adb4a6 | bellard | the optional BF and L fields in the comparison instructions. The
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211 | b9adb4a6 | bellard | assembler must count the number of operands remaining on the line,
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212 | b9adb4a6 | bellard | and the number of operands remaining for the opcode, and decide
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213 | b9adb4a6 | bellard | whether this operand is present or not. The disassembler should
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214 | b9adb4a6 | bellard | print this operand out only if it is not zero. */
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215 | b9adb4a6 | bellard | #define PPC_OPERAND_OPTIONAL (01000) |
216 | b9adb4a6 | bellard | |
217 | b9adb4a6 | bellard | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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218 | b9adb4a6 | bellard | is omitted, then for the next operand use this operand value plus
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219 | b9adb4a6 | bellard | 1, ignoring the next operand field for the opcode. This wretched
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220 | b9adb4a6 | bellard | hack is needed because the Power rotate instructions can take
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221 | b9adb4a6 | bellard | either 4 or 5 operands. The disassembler should print this operand
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222 | b9adb4a6 | bellard | out regardless of the PPC_OPERAND_OPTIONAL field. */
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223 | b9adb4a6 | bellard | #define PPC_OPERAND_NEXT (02000) |
224 | b9adb4a6 | bellard | |
225 | b9adb4a6 | bellard | /* This operand should be regarded as a negative number for the
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226 | b9adb4a6 | bellard | purposes of overflow checking (i.e., the normal most negative
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227 | b9adb4a6 | bellard | number is disallowed and one more than the normal most positive
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228 | b9adb4a6 | bellard | number is allowed). This flag will only be set for a signed
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229 | b9adb4a6 | bellard | operand. */
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230 | b9adb4a6 | bellard | #define PPC_OPERAND_NEGATIVE (04000) |
231 | b9adb4a6 | bellard | |
232 | b9adb4a6 | bellard | /* The POWER and PowerPC assemblers use a few macros. We keep them
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233 | b9adb4a6 | bellard | with the operands table for simplicity. The macro table is an
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234 | b9adb4a6 | bellard | array of struct powerpc_macro. */
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235 | b9adb4a6 | bellard | |
236 | b9adb4a6 | bellard | struct powerpc_macro
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237 | b9adb4a6 | bellard | { |
238 | b9adb4a6 | bellard | /* The macro name. */
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239 | b9adb4a6 | bellard | const char *name; |
240 | b9adb4a6 | bellard | |
241 | b9adb4a6 | bellard | /* The number of operands the macro takes. */
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242 | b9adb4a6 | bellard | unsigned int operands; |
243 | b9adb4a6 | bellard | |
244 | b9adb4a6 | bellard | /* One bit flags for the opcode. These are used to indicate which
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245 | b9adb4a6 | bellard | specific processors support the instructions. The values are the
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246 | b9adb4a6 | bellard | same as those for the struct powerpc_opcode flags field. */
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247 | 274da6b2 | bellard | uint32_t flags; |
248 | b9adb4a6 | bellard | |
249 | b9adb4a6 | bellard | /* A format string to turn the macro into a normal instruction.
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250 | b9adb4a6 | bellard | Each %N in the string is replaced with operand number N (zero
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251 | b9adb4a6 | bellard | based). */
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252 | b9adb4a6 | bellard | const char *format; |
253 | b9adb4a6 | bellard | }; |
254 | b9adb4a6 | bellard | |
255 | b9adb4a6 | bellard | extern const struct powerpc_macro powerpc_macros[]; |
256 | b9adb4a6 | bellard | extern const int powerpc_num_macros; |
257 | b9adb4a6 | bellard | |
258 | b9adb4a6 | bellard | /* ppc-opc.c -- PowerPC opcode list
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259 | b9adb4a6 | bellard | Copyright 1994 Free Software Foundation, Inc.
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260 | b9adb4a6 | bellard | Written by Ian Lance Taylor, Cygnus Support
|
261 | b9adb4a6 | bellard | |
262 | b9adb4a6 | bellard | This file is part of GDB, GAS, and the GNU binutils.
|
263 | b9adb4a6 | bellard | |
264 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are free software; you can redistribute
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265 | b9adb4a6 | bellard | them and/or modify them under the terms of the GNU General Public
|
266 | b9adb4a6 | bellard | License as published by the Free Software Foundation; either version
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267 | b9adb4a6 | bellard | 2, or (at your option) any later version.
|
268 | b9adb4a6 | bellard | |
269 | b9adb4a6 | bellard | GDB, GAS, and the GNU binutils are distributed in the hope that they
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270 | b9adb4a6 | bellard | will be useful, but WITHOUT ANY WARRANTY; without even the implied
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271 | b9adb4a6 | bellard | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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272 | b9adb4a6 | bellard | the GNU General Public License for more details.
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273 | b9adb4a6 | bellard | |
274 | b9adb4a6 | bellard | You should have received a copy of the GNU General Public License
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275 | b9adb4a6 | bellard | along with this file; see the file COPYING. If not, write to the Free
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276 | b9adb4a6 | bellard | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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277 | b9adb4a6 | bellard | |
278 | b9adb4a6 | bellard | /* This file holds the PowerPC opcode table. The opcode table
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279 | b9adb4a6 | bellard | includes almost all of the extended instruction mnemonics. This
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280 | b9adb4a6 | bellard | permits the disassembler to use them, and simplifies the assembler
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281 | b9adb4a6 | bellard | logic, at the cost of increasing the table size. The table is
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282 | b9adb4a6 | bellard | strictly constant data, so the compiler should be able to put it in
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283 | b9adb4a6 | bellard | the .text section.
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284 | b9adb4a6 | bellard | |
285 | b9adb4a6 | bellard | This file also holds the operand table. All knowledge about
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286 | b9adb4a6 | bellard | inserting operands into instructions and vice-versa is kept in this
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287 | b9adb4a6 | bellard | file. */
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288 | b9adb4a6 | bellard | |
289 | b9adb4a6 | bellard | /* Local insertion and extraction functions. */
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290 | b9adb4a6 | bellard | |
291 | 274da6b2 | bellard | static unsigned long insert_bat (uint32_t, int32_t, const char **); |
292 | 274da6b2 | bellard | static long extract_bat(uint32_t, int *); |
293 | 274da6b2 | bellard | static unsigned long insert_bba(uint32_t, int32_t, const char **); |
294 | 274da6b2 | bellard | static long extract_bba(uint32_t, int *); |
295 | 274da6b2 | bellard | static unsigned long insert_bd(uint32_t, int32_t, const char **); |
296 | 274da6b2 | bellard | static long extract_bd(uint32_t, int *); |
297 | 274da6b2 | bellard | static unsigned long insert_bdm(uint32_t, int32_t, const char **); |
298 | 274da6b2 | bellard | static long extract_bdm(uint32_t, int *); |
299 | 274da6b2 | bellard | static unsigned long insert_bdp(uint32_t, int32_t, const char **); |
300 | 274da6b2 | bellard | static long extract_bdp(uint32_t, int *); |
301 | 274da6b2 | bellard | static unsigned long insert_bo(uint32_t, int32_t, const char **); |
302 | 274da6b2 | bellard | static long extract_bo(uint32_t, int *); |
303 | 274da6b2 | bellard | static unsigned long insert_boe(uint32_t, int32_t, const char **); |
304 | 274da6b2 | bellard | static long extract_boe(uint32_t, int *); |
305 | 274da6b2 | bellard | static unsigned long insert_ds(uint32_t, int32_t, const char **); |
306 | 274da6b2 | bellard | static long extract_ds(uint32_t, int *); |
307 | 274da6b2 | bellard | static unsigned long insert_li(uint32_t, int32_t, const char **); |
308 | 274da6b2 | bellard | static long extract_li(uint32_t, int *); |
309 | 274da6b2 | bellard | static unsigned long insert_mbe(uint32_t, int32_t, const char **); |
310 | 274da6b2 | bellard | static long extract_mbe(uint32_t, int *); |
311 | 274da6b2 | bellard | static unsigned long insert_mb6(uint32_t, int32_t, const char **); |
312 | 274da6b2 | bellard | static long extract_mb6(uint32_t, int *); |
313 | 274da6b2 | bellard | static unsigned long insert_nb(uint32_t, int32_t, const char **); |
314 | 274da6b2 | bellard | static long extract_nb(uint32_t, int *); |
315 | 274da6b2 | bellard | static unsigned long insert_nsi(uint32_t, int32_t, const char **); |
316 | 274da6b2 | bellard | static long extract_nsi(uint32_t, int *); |
317 | 274da6b2 | bellard | static unsigned long insert_ral(uint32_t, int32_t, const char **); |
318 | 274da6b2 | bellard | static unsigned long insert_ram(uint32_t, int32_t, const char **); |
319 | 274da6b2 | bellard | static unsigned long insert_ras(uint32_t, int32_t, const char **); |
320 | 274da6b2 | bellard | static unsigned long insert_rbs(uint32_t, int32_t, const char **); |
321 | 274da6b2 | bellard | static long extract_rbs(uint32_t, int *); |
322 | 274da6b2 | bellard | static unsigned long insert_sh6(uint32_t, int32_t, const char **); |
323 | 274da6b2 | bellard | static long extract_sh6(uint32_t, int *); |
324 | 274da6b2 | bellard | static unsigned long insert_spr(uint32_t, int32_t, const char **); |
325 | 274da6b2 | bellard | static long extract_spr(uint32_t, int *); |
326 | 274da6b2 | bellard | static unsigned long insert_tbr(uint32_t, int32_t, const char **); |
327 | 274da6b2 | bellard | static long extract_tbr(uint32_t, int *); |
328 | b9adb4a6 | bellard | |
329 | b9adb4a6 | bellard | /* The operands table.
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330 | b9adb4a6 | bellard | |
331 | b9adb4a6 | bellard | The fields are bits, shift, signed, insert, extract, flags. */
|
332 | b9adb4a6 | bellard | |
333 | b9adb4a6 | bellard | const struct powerpc_operand powerpc_operands[] = |
334 | b9adb4a6 | bellard | { |
335 | b9adb4a6 | bellard | /* The zero index is used to indicate the end of the list of
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336 | b9adb4a6 | bellard | operands. */
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337 | b9adb4a6 | bellard | #define UNUSED (0) |
338 | b9adb4a6 | bellard | { 0, 0, 0, 0, 0 }, |
339 | b9adb4a6 | bellard | |
340 | b9adb4a6 | bellard | /* The BA field in an XL form instruction. */
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341 | b9adb4a6 | bellard | #define BA (1) |
342 | b9adb4a6 | bellard | #define BA_MASK (0x1f << 16) |
343 | b9adb4a6 | bellard | { 5, 16, 0, 0, PPC_OPERAND_CR }, |
344 | b9adb4a6 | bellard | |
345 | b9adb4a6 | bellard | /* The BA field in an XL form instruction when it must be the same
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346 | b9adb4a6 | bellard | as the BT field in the same instruction. */
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347 | b9adb4a6 | bellard | #define BAT (2) |
348 | b9adb4a6 | bellard | { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, |
349 | b9adb4a6 | bellard | |
350 | b9adb4a6 | bellard | /* The BB field in an XL form instruction. */
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351 | b9adb4a6 | bellard | #define BB (3) |
352 | b9adb4a6 | bellard | #define BB_MASK (0x1f << 11) |
353 | b9adb4a6 | bellard | { 5, 11, 0, 0, PPC_OPERAND_CR }, |
354 | b9adb4a6 | bellard | |
355 | b9adb4a6 | bellard | /* The BB field in an XL form instruction when it must be the same
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356 | b9adb4a6 | bellard | as the BA field in the same instruction. */
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357 | b9adb4a6 | bellard | #define BBA (4) |
358 | b9adb4a6 | bellard | { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, |
359 | b9adb4a6 | bellard | |
360 | b9adb4a6 | bellard | /* The BD field in a B form instruction. The lower two bits are
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361 | b9adb4a6 | bellard | forced to zero. */
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362 | b9adb4a6 | bellard | #define BD (5) |
363 | b9adb4a6 | bellard | { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
364 | b9adb4a6 | bellard | |
365 | b9adb4a6 | bellard | /* The BD field in a B form instruction when absolute addressing is
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366 | b9adb4a6 | bellard | used. */
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367 | b9adb4a6 | bellard | #define BDA (6) |
368 | b9adb4a6 | bellard | { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
369 | b9adb4a6 | bellard | |
370 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the - modifier is used.
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371 | b9adb4a6 | bellard | This sets the y bit of the BO field appropriately. */
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372 | b9adb4a6 | bellard | #define BDM (7) |
373 | b9adb4a6 | bellard | { 16, 0, insert_bdm, extract_bdm, |
374 | b9adb4a6 | bellard | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
375 | b9adb4a6 | bellard | |
376 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the - modifier is used
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377 | b9adb4a6 | bellard | and absolute address is used. */
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378 | b9adb4a6 | bellard | #define BDMA (8) |
379 | b9adb4a6 | bellard | { 16, 0, insert_bdm, extract_bdm, |
380 | b9adb4a6 | bellard | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
381 | b9adb4a6 | bellard | |
382 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the + modifier is used.
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383 | b9adb4a6 | bellard | This sets the y bit of the BO field appropriately. */
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384 | b9adb4a6 | bellard | #define BDP (9) |
385 | b9adb4a6 | bellard | { 16, 0, insert_bdp, extract_bdp, |
386 | b9adb4a6 | bellard | PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
387 | b9adb4a6 | bellard | |
388 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the + modifier is used
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389 | b9adb4a6 | bellard | and absolute addressing is used. */
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390 | b9adb4a6 | bellard | #define BDPA (10) |
391 | b9adb4a6 | bellard | { 16, 0, insert_bdp, extract_bdp, |
392 | b9adb4a6 | bellard | PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
393 | b9adb4a6 | bellard | |
394 | b9adb4a6 | bellard | /* The BF field in an X or XL form instruction. */
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395 | b9adb4a6 | bellard | #define BF (11) |
396 | b9adb4a6 | bellard | { 3, 23, 0, 0, PPC_OPERAND_CR }, |
397 | b9adb4a6 | bellard | |
398 | b9adb4a6 | bellard | /* An optional BF field. This is used for comparison instructions,
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399 | b9adb4a6 | bellard | in which an omitted BF field is taken as zero. */
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400 | b9adb4a6 | bellard | #define OBF (12) |
401 | b9adb4a6 | bellard | { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
402 | b9adb4a6 | bellard | |
403 | b9adb4a6 | bellard | /* The BFA field in an X or XL form instruction. */
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404 | b9adb4a6 | bellard | #define BFA (13) |
405 | b9adb4a6 | bellard | { 3, 18, 0, 0, PPC_OPERAND_CR }, |
406 | b9adb4a6 | bellard | |
407 | b9adb4a6 | bellard | /* The BI field in a B form or XL form instruction. */
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408 | b9adb4a6 | bellard | #define BI (14) |
409 | b9adb4a6 | bellard | #define BI_MASK (0x1f << 16) |
410 | b9adb4a6 | bellard | { 5, 16, 0, 0, PPC_OPERAND_CR }, |
411 | b9adb4a6 | bellard | |
412 | b9adb4a6 | bellard | /* The BO field in a B form instruction. Certain values are
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413 | b9adb4a6 | bellard | illegal. */
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414 | b9adb4a6 | bellard | #define BO (15) |
415 | b9adb4a6 | bellard | #define BO_MASK (0x1f << 21) |
416 | b9adb4a6 | bellard | { 5, 21, insert_bo, extract_bo, 0 }, |
417 | b9adb4a6 | bellard | |
418 | b9adb4a6 | bellard | /* The BO field in a B form instruction when the + or - modifier is
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419 | b9adb4a6 | bellard | used. This is like the BO field, but it must be even. */
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420 | b9adb4a6 | bellard | #define BOE (16) |
421 | b9adb4a6 | bellard | { 5, 21, insert_boe, extract_boe, 0 }, |
422 | b9adb4a6 | bellard | |
423 | b9adb4a6 | bellard | /* The BT field in an X or XL form instruction. */
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424 | b9adb4a6 | bellard | #define BT (17) |
425 | b9adb4a6 | bellard | { 5, 21, 0, 0, PPC_OPERAND_CR }, |
426 | b9adb4a6 | bellard | |
427 | b9adb4a6 | bellard | /* The condition register number portion of the BI field in a B form
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428 | b9adb4a6 | bellard | or XL form instruction. This is used for the extended
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429 | b9adb4a6 | bellard | conditional branch mnemonics, which set the lower two bits of the
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430 | b9adb4a6 | bellard | BI field. This field is optional. */
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431 | b9adb4a6 | bellard | #define CR (18) |
432 | b9adb4a6 | bellard | { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, |
433 | b9adb4a6 | bellard | |
434 | b9adb4a6 | bellard | /* The D field in a D form instruction. This is a displacement off
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435 | b9adb4a6 | bellard | a register, and implies that the next operand is a register in
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436 | b9adb4a6 | bellard | parentheses. */
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437 | b9adb4a6 | bellard | #define D (19) |
438 | b9adb4a6 | bellard | { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
439 | b9adb4a6 | bellard | |
440 | b9adb4a6 | bellard | /* The DS field in a DS form instruction. This is like D, but the
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441 | b9adb4a6 | bellard | lower two bits are forced to zero. */
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442 | b9adb4a6 | bellard | #define DS (20) |
443 | b9adb4a6 | bellard | { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
444 | b9adb4a6 | bellard | |
445 | b9adb4a6 | bellard | /* The FL1 field in a POWER SC form instruction. */
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446 | b9adb4a6 | bellard | #define FL1 (21) |
447 | b9adb4a6 | bellard | { 4, 12, 0, 0, 0 }, |
448 | b9adb4a6 | bellard | |
449 | b9adb4a6 | bellard | /* The FL2 field in a POWER SC form instruction. */
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450 | b9adb4a6 | bellard | #define FL2 (22) |
451 | b9adb4a6 | bellard | { 3, 2, 0, 0, 0 }, |
452 | b9adb4a6 | bellard | |
453 | b9adb4a6 | bellard | /* The FLM field in an XFL form instruction. */
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454 | b9adb4a6 | bellard | #define FLM (23) |
455 | b9adb4a6 | bellard | { 8, 17, 0, 0, 0 }, |
456 | b9adb4a6 | bellard | |
457 | b9adb4a6 | bellard | /* The FRA field in an X or A form instruction. */
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458 | b9adb4a6 | bellard | #define FRA (24) |
459 | b9adb4a6 | bellard | #define FRA_MASK (0x1f << 16) |
460 | b9adb4a6 | bellard | { 5, 16, 0, 0, PPC_OPERAND_FPR }, |
461 | b9adb4a6 | bellard | |
462 | b9adb4a6 | bellard | /* The FRB field in an X or A form instruction. */
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463 | b9adb4a6 | bellard | #define FRB (25) |
464 | b9adb4a6 | bellard | #define FRB_MASK (0x1f << 11) |
465 | b9adb4a6 | bellard | { 5, 11, 0, 0, PPC_OPERAND_FPR }, |
466 | b9adb4a6 | bellard | |
467 | b9adb4a6 | bellard | /* The FRC field in an A form instruction. */
|
468 | b9adb4a6 | bellard | #define FRC (26) |
469 | b9adb4a6 | bellard | #define FRC_MASK (0x1f << 6) |
470 | b9adb4a6 | bellard | { 5, 6, 0, 0, PPC_OPERAND_FPR }, |
471 | b9adb4a6 | bellard | |
472 | b9adb4a6 | bellard | /* The FRS field in an X form instruction or the FRT field in a D, X
|
473 | b9adb4a6 | bellard | or A form instruction. */
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474 | b9adb4a6 | bellard | #define FRS (27) |
475 | b9adb4a6 | bellard | #define FRT (FRS)
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476 | b9adb4a6 | bellard | { 5, 21, 0, 0, PPC_OPERAND_FPR }, |
477 | b9adb4a6 | bellard | |
478 | b9adb4a6 | bellard | /* The FXM field in an XFX instruction. */
|
479 | b9adb4a6 | bellard | #define FXM (28) |
480 | b9adb4a6 | bellard | #define FXM_MASK (0xff << 12) |
481 | b9adb4a6 | bellard | { 8, 12, 0, 0, 0 }, |
482 | b9adb4a6 | bellard | |
483 | b9adb4a6 | bellard | /* The L field in a D or X form instruction. */
|
484 | b9adb4a6 | bellard | #define L (29) |
485 | b9adb4a6 | bellard | { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, |
486 | b9adb4a6 | bellard | |
487 | b9adb4a6 | bellard | /* The LEV field in a POWER SC form instruction. */
|
488 | b9adb4a6 | bellard | #define LEV (30) |
489 | b9adb4a6 | bellard | { 7, 5, 0, 0, 0 }, |
490 | b9adb4a6 | bellard | |
491 | b9adb4a6 | bellard | /* The LI field in an I form instruction. The lower two bits are
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492 | b9adb4a6 | bellard | forced to zero. */
|
493 | b9adb4a6 | bellard | #define LI (31) |
494 | b9adb4a6 | bellard | { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
495 | b9adb4a6 | bellard | |
496 | b9adb4a6 | bellard | /* The LI field in an I form instruction when used as an absolute
|
497 | b9adb4a6 | bellard | address. */
|
498 | b9adb4a6 | bellard | #define LIA (32) |
499 | b9adb4a6 | bellard | { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
500 | b9adb4a6 | bellard | |
501 | b9adb4a6 | bellard | /* The MB field in an M form instruction. */
|
502 | b9adb4a6 | bellard | #define MB (33) |
503 | b9adb4a6 | bellard | #define MB_MASK (0x1f << 6) |
504 | b9adb4a6 | bellard | { 5, 6, 0, 0, 0 }, |
505 | b9adb4a6 | bellard | |
506 | b9adb4a6 | bellard | /* The ME field in an M form instruction. */
|
507 | b9adb4a6 | bellard | #define ME (34) |
508 | b9adb4a6 | bellard | #define ME_MASK (0x1f << 1) |
509 | b9adb4a6 | bellard | { 5, 1, 0, 0, 0 }, |
510 | b9adb4a6 | bellard | |
511 | b9adb4a6 | bellard | /* The MB and ME fields in an M form instruction expressed a single
|
512 | b9adb4a6 | bellard | operand which is a bitmask indicating which bits to select. This
|
513 | b9adb4a6 | bellard | is a two operand form using PPC_OPERAND_NEXT. See the
|
514 | b9adb4a6 | bellard | description in opcode/ppc.h for what this means. */
|
515 | b9adb4a6 | bellard | #define MBE (35) |
516 | b9adb4a6 | bellard | { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
517 | b9adb4a6 | bellard | { 32, 0, insert_mbe, extract_mbe, 0 }, |
518 | b9adb4a6 | bellard | |
519 | b9adb4a6 | bellard | /* The MB or ME field in an MD or MDS form instruction. The high
|
520 | b9adb4a6 | bellard | bit is wrapped to the low end. */
|
521 | b9adb4a6 | bellard | #define MB6 (37) |
522 | b9adb4a6 | bellard | #define ME6 (MB6)
|
523 | b9adb4a6 | bellard | #define MB6_MASK (0x3f << 5) |
524 | b9adb4a6 | bellard | { 6, 5, insert_mb6, extract_mb6, 0 }, |
525 | b9adb4a6 | bellard | |
526 | b9adb4a6 | bellard | /* The NB field in an X form instruction. The value 32 is stored as
|
527 | b9adb4a6 | bellard | 0. */
|
528 | b9adb4a6 | bellard | #define NB (38) |
529 | b9adb4a6 | bellard | { 6, 11, insert_nb, extract_nb, 0 }, |
530 | b9adb4a6 | bellard | |
531 | b9adb4a6 | bellard | /* The NSI field in a D form instruction. This is the same as the
|
532 | b9adb4a6 | bellard | SI field, only negated. */
|
533 | b9adb4a6 | bellard | #define NSI (39) |
534 | b9adb4a6 | bellard | { 16, 0, insert_nsi, extract_nsi, |
535 | b9adb4a6 | bellard | PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
536 | b9adb4a6 | bellard | |
537 | b9adb4a6 | bellard | /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
|
538 | b9adb4a6 | bellard | #define RA (40) |
539 | b9adb4a6 | bellard | #define RA_MASK (0x1f << 16) |
540 | b9adb4a6 | bellard | { 5, 16, 0, 0, PPC_OPERAND_GPR }, |
541 | b9adb4a6 | bellard | |
542 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
543 | b9adb4a6 | bellard | load, which means that the RA field may not be zero and may not
|
544 | b9adb4a6 | bellard | equal the RT field. */
|
545 | b9adb4a6 | bellard | #define RAL (41) |
546 | b9adb4a6 | bellard | { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, |
547 | b9adb4a6 | bellard | |
548 | b9adb4a6 | bellard | /* The RA field in an lmw instruction, which has special value
|
549 | b9adb4a6 | bellard | restrictions. */
|
550 | b9adb4a6 | bellard | #define RAM (42) |
551 | b9adb4a6 | bellard | { 5, 16, insert_ram, 0, PPC_OPERAND_GPR }, |
552 | b9adb4a6 | bellard | |
553 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
554 | b9adb4a6 | bellard | store or an updating floating point load, which means that the RA
|
555 | b9adb4a6 | bellard | field may not be zero. */
|
556 | b9adb4a6 | bellard | #define RAS (43) |
557 | b9adb4a6 | bellard | { 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, |
558 | b9adb4a6 | bellard | |
559 | b9adb4a6 | bellard | /* The RB field in an X, XO, M, or MDS form instruction. */
|
560 | b9adb4a6 | bellard | #define RB (44) |
561 | b9adb4a6 | bellard | #define RB_MASK (0x1f << 11) |
562 | b9adb4a6 | bellard | { 5, 11, 0, 0, PPC_OPERAND_GPR }, |
563 | b9adb4a6 | bellard | |
564 | b9adb4a6 | bellard | /* The RB field in an X form instruction when it must be the same as
|
565 | b9adb4a6 | bellard | the RS field in the instruction. This is used for extended
|
566 | b9adb4a6 | bellard | mnemonics like mr. */
|
567 | b9adb4a6 | bellard | #define RBS (45) |
568 | b9adb4a6 | bellard | { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, |
569 | b9adb4a6 | bellard | |
570 | b9adb4a6 | bellard | /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
|
571 | b9adb4a6 | bellard | instruction or the RT field in a D, DS, X, XFX or XO form
|
572 | b9adb4a6 | bellard | instruction. */
|
573 | b9adb4a6 | bellard | #define RS (46) |
574 | b9adb4a6 | bellard | #define RT (RS)
|
575 | b9adb4a6 | bellard | #define RT_MASK (0x1f << 21) |
576 | b9adb4a6 | bellard | { 5, 21, 0, 0, PPC_OPERAND_GPR }, |
577 | b9adb4a6 | bellard | |
578 | b9adb4a6 | bellard | /* The SH field in an X or M form instruction. */
|
579 | b9adb4a6 | bellard | #define SH (47) |
580 | b9adb4a6 | bellard | #define SH_MASK (0x1f << 11) |
581 | b9adb4a6 | bellard | { 5, 11, 0, 0, 0 }, |
582 | b9adb4a6 | bellard | |
583 | b9adb4a6 | bellard | /* The SH field in an MD form instruction. This is split. */
|
584 | b9adb4a6 | bellard | #define SH6 (48) |
585 | b9adb4a6 | bellard | #define SH6_MASK ((0x1f << 11) | (1 << 1)) |
586 | b9adb4a6 | bellard | { 6, 1, insert_sh6, extract_sh6, 0 }, |
587 | b9adb4a6 | bellard | |
588 | b9adb4a6 | bellard | /* The SI field in a D form instruction. */
|
589 | b9adb4a6 | bellard | #define SI (49) |
590 | b9adb4a6 | bellard | { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, |
591 | b9adb4a6 | bellard | |
592 | b9adb4a6 | bellard | /* The SI field in a D form instruction when we accept a wide range
|
593 | b9adb4a6 | bellard | of positive values. */
|
594 | b9adb4a6 | bellard | #define SISIGNOPT (50) |
595 | b9adb4a6 | bellard | { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
596 | b9adb4a6 | bellard | |
597 | b9adb4a6 | bellard | /* The SPR field in an XFX form instruction. This is flipped--the
|
598 | b9adb4a6 | bellard | lower 5 bits are stored in the upper 5 and vice- versa. */
|
599 | b9adb4a6 | bellard | #define SPR (51) |
600 | b9adb4a6 | bellard | #define SPR_MASK (0x3ff << 11) |
601 | b9adb4a6 | bellard | { 10, 11, insert_spr, extract_spr, 0 }, |
602 | b9adb4a6 | bellard | |
603 | b9adb4a6 | bellard | /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
|
604 | b9adb4a6 | bellard | #define SPRBAT (52) |
605 | b9adb4a6 | bellard | #define SPRBAT_MASK (0x3 << 17) |
606 | b9adb4a6 | bellard | { 2, 17, 0, 0, 0 }, |
607 | b9adb4a6 | bellard | |
608 | b9adb4a6 | bellard | /* The SPRG register number in an XFX form m[ft]sprg instruction. */
|
609 | b9adb4a6 | bellard | #define SPRG (53) |
610 | b9adb4a6 | bellard | #define SPRG_MASK (0x3 << 16) |
611 | b9adb4a6 | bellard | { 2, 16, 0, 0, 0 }, |
612 | b9adb4a6 | bellard | |
613 | b9adb4a6 | bellard | /* The SR field in an X form instruction. */
|
614 | b9adb4a6 | bellard | #define SR (54) |
615 | b9adb4a6 | bellard | { 4, 16, 0, 0, 0 }, |
616 | b9adb4a6 | bellard | |
617 | b9adb4a6 | bellard | /* The SV field in a POWER SC form instruction. */
|
618 | b9adb4a6 | bellard | #define SV (55) |
619 | b9adb4a6 | bellard | { 14, 2, 0, 0, 0 }, |
620 | b9adb4a6 | bellard | |
621 | b9adb4a6 | bellard | /* The TBR field in an XFX form instruction. This is like the SPR
|
622 | b9adb4a6 | bellard | field, but it is optional. */
|
623 | b9adb4a6 | bellard | #define TBR (56) |
624 | b9adb4a6 | bellard | { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, |
625 | b9adb4a6 | bellard | |
626 | b9adb4a6 | bellard | /* The TO field in a D or X form instruction. */
|
627 | b9adb4a6 | bellard | #define TO (57) |
628 | b9adb4a6 | bellard | #define TO_MASK (0x1f << 21) |
629 | b9adb4a6 | bellard | { 5, 21, 0, 0, 0 }, |
630 | b9adb4a6 | bellard | |
631 | b9adb4a6 | bellard | /* The U field in an X form instruction. */
|
632 | b9adb4a6 | bellard | #define U (58) |
633 | b9adb4a6 | bellard | { 4, 12, 0, 0, 0 }, |
634 | b9adb4a6 | bellard | |
635 | b9adb4a6 | bellard | /* The UI field in a D form instruction. */
|
636 | b9adb4a6 | bellard | #define UI (59) |
637 | b9adb4a6 | bellard | { 16, 0, 0, 0, 0 }, |
638 | b9adb4a6 | bellard | }; |
639 | b9adb4a6 | bellard | |
640 | b9adb4a6 | bellard | /* The functions used to insert and extract complicated operands. */
|
641 | b9adb4a6 | bellard | |
642 | b9adb4a6 | bellard | /* The BA field in an XL form instruction when it must be the same as
|
643 | b9adb4a6 | bellard | the BT field in the same instruction. This operand is marked FAKE.
|
644 | b9adb4a6 | bellard | The insertion function just copies the BT field into the BA field,
|
645 | b9adb4a6 | bellard | and the extraction function just checks that the fields are the
|
646 | b9adb4a6 | bellard | same. */
|
647 | b9adb4a6 | bellard | |
648 | b9adb4a6 | bellard | /*ARGSUSED*/
|
649 | b9adb4a6 | bellard | static unsigned long |
650 | b9adb4a6 | bellard | insert_bat (insn, value, errmsg) |
651 | 274da6b2 | bellard | uint32_t insn; |
652 | 274da6b2 | bellard | int32_t value; |
653 | b9adb4a6 | bellard | const char **errmsg; |
654 | b9adb4a6 | bellard | { |
655 | b9adb4a6 | bellard | return insn | (((insn >> 21) & 0x1f) << 16); |
656 | b9adb4a6 | bellard | } |
657 | b9adb4a6 | bellard | |
658 | b9adb4a6 | bellard | static long |
659 | b9adb4a6 | bellard | extract_bat (insn, invalid) |
660 | 274da6b2 | bellard | uint32_t insn; |
661 | b9adb4a6 | bellard | int *invalid;
|
662 | b9adb4a6 | bellard | { |
663 | b9adb4a6 | bellard | if (invalid != (int *) NULL |
664 | b9adb4a6 | bellard | && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) |
665 | b9adb4a6 | bellard | *invalid = 1;
|
666 | b9adb4a6 | bellard | return 0; |
667 | b9adb4a6 | bellard | } |
668 | b9adb4a6 | bellard | |
669 | b9adb4a6 | bellard | /* The BB field in an XL form instruction when it must be the same as
|
670 | b9adb4a6 | bellard | the BA field in the same instruction. This operand is marked FAKE.
|
671 | b9adb4a6 | bellard | The insertion function just copies the BA field into the BB field,
|
672 | b9adb4a6 | bellard | and the extraction function just checks that the fields are the
|
673 | b9adb4a6 | bellard | same. */
|
674 | b9adb4a6 | bellard | |
675 | b9adb4a6 | bellard | /*ARGSUSED*/
|
676 | b9adb4a6 | bellard | static unsigned long |
677 | b9adb4a6 | bellard | insert_bba (insn, value, errmsg) |
678 | 274da6b2 | bellard | uint32_t insn; |
679 | 274da6b2 | bellard | int32_t value; |
680 | b9adb4a6 | bellard | const char **errmsg; |
681 | b9adb4a6 | bellard | { |
682 | b9adb4a6 | bellard | return insn | (((insn >> 16) & 0x1f) << 11); |
683 | b9adb4a6 | bellard | } |
684 | b9adb4a6 | bellard | |
685 | b9adb4a6 | bellard | static long |
686 | b9adb4a6 | bellard | extract_bba (insn, invalid) |
687 | 274da6b2 | bellard | uint32_t insn; |
688 | b9adb4a6 | bellard | int *invalid;
|
689 | b9adb4a6 | bellard | { |
690 | b9adb4a6 | bellard | if (invalid != (int *) NULL |
691 | b9adb4a6 | bellard | && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
692 | b9adb4a6 | bellard | *invalid = 1;
|
693 | b9adb4a6 | bellard | return 0; |
694 | b9adb4a6 | bellard | } |
695 | b9adb4a6 | bellard | |
696 | b9adb4a6 | bellard | /* The BD field in a B form instruction. The lower two bits are
|
697 | b9adb4a6 | bellard | forced to zero. */
|
698 | b9adb4a6 | bellard | |
699 | b9adb4a6 | bellard | /*ARGSUSED*/
|
700 | b9adb4a6 | bellard | static unsigned long |
701 | b9adb4a6 | bellard | insert_bd (insn, value, errmsg) |
702 | 274da6b2 | bellard | uint32_t insn; |
703 | 274da6b2 | bellard | int32_t value; |
704 | b9adb4a6 | bellard | const char **errmsg; |
705 | b9adb4a6 | bellard | { |
706 | b9adb4a6 | bellard | return insn | (value & 0xfffc); |
707 | b9adb4a6 | bellard | } |
708 | b9adb4a6 | bellard | |
709 | b9adb4a6 | bellard | /*ARGSUSED*/
|
710 | b9adb4a6 | bellard | static long |
711 | b9adb4a6 | bellard | extract_bd (insn, invalid) |
712 | 274da6b2 | bellard | uint32_t insn; |
713 | b9adb4a6 | bellard | int *invalid;
|
714 | b9adb4a6 | bellard | { |
715 | b9adb4a6 | bellard | if ((insn & 0x8000) != 0) |
716 | b9adb4a6 | bellard | return (insn & 0xfffc) - 0x10000; |
717 | b9adb4a6 | bellard | else
|
718 | b9adb4a6 | bellard | return insn & 0xfffc; |
719 | b9adb4a6 | bellard | } |
720 | b9adb4a6 | bellard | |
721 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the - modifier is used.
|
722 | b9adb4a6 | bellard | This modifier means that the branch is not expected to be taken.
|
723 | b9adb4a6 | bellard | We must set the y bit of the BO field to 1 if the offset is
|
724 | b9adb4a6 | bellard | negative. When extracting, we require that the y bit be 1 and that
|
725 | b9adb4a6 | bellard | the offset be positive, since if the y bit is 0 we just want to
|
726 | b9adb4a6 | bellard | print the normal form of the instruction. */
|
727 | b9adb4a6 | bellard | |
728 | b9adb4a6 | bellard | /*ARGSUSED*/
|
729 | b9adb4a6 | bellard | static unsigned long |
730 | b9adb4a6 | bellard | insert_bdm (insn, value, errmsg) |
731 | 274da6b2 | bellard | uint32_t insn; |
732 | 274da6b2 | bellard | int32_t value; |
733 | b9adb4a6 | bellard | const char **errmsg; |
734 | b9adb4a6 | bellard | { |
735 | b9adb4a6 | bellard | if ((value & 0x8000) != 0) |
736 | b9adb4a6 | bellard | insn |= 1 << 21; |
737 | b9adb4a6 | bellard | return insn | (value & 0xfffc); |
738 | b9adb4a6 | bellard | } |
739 | b9adb4a6 | bellard | |
740 | b9adb4a6 | bellard | static long |
741 | b9adb4a6 | bellard | extract_bdm (insn, invalid) |
742 | 274da6b2 | bellard | uint32_t insn; |
743 | b9adb4a6 | bellard | int *invalid;
|
744 | b9adb4a6 | bellard | { |
745 | b9adb4a6 | bellard | if (invalid != (int *) NULL |
746 | b9adb4a6 | bellard | && ((insn & (1 << 21)) == 0 |
747 | b9adb4a6 | bellard | || (insn & (1 << 15)) == 0)) |
748 | b9adb4a6 | bellard | *invalid = 1;
|
749 | b9adb4a6 | bellard | if ((insn & 0x8000) != 0) |
750 | b9adb4a6 | bellard | return (insn & 0xfffc) - 0x10000; |
751 | b9adb4a6 | bellard | else
|
752 | b9adb4a6 | bellard | return insn & 0xfffc; |
753 | b9adb4a6 | bellard | } |
754 | b9adb4a6 | bellard | |
755 | b9adb4a6 | bellard | /* The BD field in a B form instruction when the + modifier is used.
|
756 | b9adb4a6 | bellard | This is like BDM, above, except that the branch is expected to be
|
757 | b9adb4a6 | bellard | taken. */
|
758 | b9adb4a6 | bellard | |
759 | b9adb4a6 | bellard | /*ARGSUSED*/
|
760 | b9adb4a6 | bellard | static unsigned long |
761 | b9adb4a6 | bellard | insert_bdp (insn, value, errmsg) |
762 | 274da6b2 | bellard | uint32_t insn; |
763 | 274da6b2 | bellard | int32_t value; |
764 | b9adb4a6 | bellard | const char **errmsg; |
765 | b9adb4a6 | bellard | { |
766 | b9adb4a6 | bellard | if ((value & 0x8000) == 0) |
767 | b9adb4a6 | bellard | insn |= 1 << 21; |
768 | b9adb4a6 | bellard | return insn | (value & 0xfffc); |
769 | b9adb4a6 | bellard | } |
770 | b9adb4a6 | bellard | |
771 | b9adb4a6 | bellard | static long |
772 | b9adb4a6 | bellard | extract_bdp (insn, invalid) |
773 | 274da6b2 | bellard | uint32_t insn; |
774 | b9adb4a6 | bellard | int *invalid;
|
775 | b9adb4a6 | bellard | { |
776 | b9adb4a6 | bellard | if (invalid != (int *) NULL |
777 | b9adb4a6 | bellard | && ((insn & (1 << 21)) == 0 |
778 | b9adb4a6 | bellard | || (insn & (1 << 15)) != 0)) |
779 | b9adb4a6 | bellard | *invalid = 1;
|
780 | b9adb4a6 | bellard | if ((insn & 0x8000) != 0) |
781 | b9adb4a6 | bellard | return (insn & 0xfffc) - 0x10000; |
782 | b9adb4a6 | bellard | else
|
783 | b9adb4a6 | bellard | return insn & 0xfffc; |
784 | b9adb4a6 | bellard | } |
785 | b9adb4a6 | bellard | |
786 | b9adb4a6 | bellard | /* Check for legal values of a BO field. */
|
787 | b9adb4a6 | bellard | |
788 | b9adb4a6 | bellard | static int |
789 | 274da6b2 | bellard | valid_bo (int32_t value) |
790 | b9adb4a6 | bellard | { |
791 | b9adb4a6 | bellard | /* Certain encodings have bits that are required to be zero. These
|
792 | b9adb4a6 | bellard | are (z must be zero, y may be anything):
|
793 | b9adb4a6 | bellard | 001zy
|
794 | b9adb4a6 | bellard | 011zy
|
795 | b9adb4a6 | bellard | 1z00y
|
796 | b9adb4a6 | bellard | 1z01y
|
797 | b9adb4a6 | bellard | 1z1zz
|
798 | b9adb4a6 | bellard | */
|
799 | b9adb4a6 | bellard | switch (value & 0x14) |
800 | b9adb4a6 | bellard | { |
801 | b9adb4a6 | bellard | default:
|
802 | b9adb4a6 | bellard | case 0: |
803 | b9adb4a6 | bellard | return 1; |
804 | b9adb4a6 | bellard | case 0x4: |
805 | b9adb4a6 | bellard | return (value & 0x2) == 0; |
806 | b9adb4a6 | bellard | case 0x10: |
807 | b9adb4a6 | bellard | return (value & 0x8) == 0; |
808 | b9adb4a6 | bellard | case 0x14: |
809 | b9adb4a6 | bellard | return value == 0x14; |
810 | b9adb4a6 | bellard | } |
811 | b9adb4a6 | bellard | } |
812 | b9adb4a6 | bellard | |
813 | b9adb4a6 | bellard | /* The BO field in a B form instruction. Warn about attempts to set
|
814 | b9adb4a6 | bellard | the field to an illegal value. */
|
815 | b9adb4a6 | bellard | |
816 | b9adb4a6 | bellard | static unsigned long |
817 | b9adb4a6 | bellard | insert_bo (insn, value, errmsg) |
818 | 274da6b2 | bellard | uint32_t insn; |
819 | 274da6b2 | bellard | int32_t value; |
820 | b9adb4a6 | bellard | const char **errmsg; |
821 | b9adb4a6 | bellard | { |
822 | b9adb4a6 | bellard | if (errmsg != (const char **) NULL |
823 | b9adb4a6 | bellard | && ! valid_bo (value)) |
824 | b9adb4a6 | bellard | *errmsg = "invalid conditional option";
|
825 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 21); |
826 | b9adb4a6 | bellard | } |
827 | b9adb4a6 | bellard | |
828 | b9adb4a6 | bellard | static long |
829 | b9adb4a6 | bellard | extract_bo (insn, invalid) |
830 | 274da6b2 | bellard | uint32_t insn; |
831 | b9adb4a6 | bellard | int *invalid;
|
832 | b9adb4a6 | bellard | { |
833 | 274da6b2 | bellard | int32_t value; |
834 | b9adb4a6 | bellard | |
835 | b9adb4a6 | bellard | value = (insn >> 21) & 0x1f; |
836 | b9adb4a6 | bellard | if (invalid != (int *) NULL |
837 | b9adb4a6 | bellard | && ! valid_bo (value)) |
838 | b9adb4a6 | bellard | *invalid = 1;
|
839 | b9adb4a6 | bellard | return value;
|
840 | b9adb4a6 | bellard | } |
841 | b9adb4a6 | bellard | |
842 | b9adb4a6 | bellard | /* The BO field in a B form instruction when the + or - modifier is
|
843 | b9adb4a6 | bellard | used. This is like the BO field, but it must be even. When
|
844 | b9adb4a6 | bellard | extracting it, we force it to be even. */
|
845 | b9adb4a6 | bellard | |
846 | b9adb4a6 | bellard | static unsigned long |
847 | b9adb4a6 | bellard | insert_boe (insn, value, errmsg) |
848 | 274da6b2 | bellard | uint32_t insn; |
849 | 274da6b2 | bellard | int32_t value; |
850 | b9adb4a6 | bellard | const char **errmsg; |
851 | b9adb4a6 | bellard | { |
852 | b9adb4a6 | bellard | if (errmsg != (const char **) NULL) |
853 | b9adb4a6 | bellard | { |
854 | b9adb4a6 | bellard | if (! valid_bo (value))
|
855 | b9adb4a6 | bellard | *errmsg = "invalid conditional option";
|
856 | b9adb4a6 | bellard | else if ((value & 1) != 0) |
857 | b9adb4a6 | bellard | *errmsg = "attempt to set y bit when using + or - modifier";
|
858 | b9adb4a6 | bellard | } |
859 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 21); |
860 | b9adb4a6 | bellard | } |
861 | b9adb4a6 | bellard | |
862 | b9adb4a6 | bellard | static long |
863 | b9adb4a6 | bellard | extract_boe (insn, invalid) |
864 | 274da6b2 | bellard | uint32_t insn; |
865 | b9adb4a6 | bellard | int *invalid;
|
866 | b9adb4a6 | bellard | { |
867 | 274da6b2 | bellard | int32_t value; |
868 | b9adb4a6 | bellard | |
869 | b9adb4a6 | bellard | value = (insn >> 21) & 0x1f; |
870 | b9adb4a6 | bellard | if (invalid != (int *) NULL |
871 | b9adb4a6 | bellard | && ! valid_bo (value)) |
872 | b9adb4a6 | bellard | *invalid = 1;
|
873 | b9adb4a6 | bellard | return value & 0x1e; |
874 | b9adb4a6 | bellard | } |
875 | b9adb4a6 | bellard | |
876 | b9adb4a6 | bellard | /* The DS field in a DS form instruction. This is like D, but the
|
877 | b9adb4a6 | bellard | lower two bits are forced to zero. */
|
878 | b9adb4a6 | bellard | |
879 | b9adb4a6 | bellard | /*ARGSUSED*/
|
880 | b9adb4a6 | bellard | static unsigned long |
881 | b9adb4a6 | bellard | insert_ds (insn, value, errmsg) |
882 | 274da6b2 | bellard | uint32_t insn; |
883 | 274da6b2 | bellard | int32_t value; |
884 | b9adb4a6 | bellard | const char **errmsg; |
885 | b9adb4a6 | bellard | { |
886 | b9adb4a6 | bellard | return insn | (value & 0xfffc); |
887 | b9adb4a6 | bellard | } |
888 | b9adb4a6 | bellard | |
889 | b9adb4a6 | bellard | /*ARGSUSED*/
|
890 | b9adb4a6 | bellard | static long |
891 | b9adb4a6 | bellard | extract_ds (insn, invalid) |
892 | 274da6b2 | bellard | uint32_t insn; |
893 | b9adb4a6 | bellard | int *invalid;
|
894 | b9adb4a6 | bellard | { |
895 | b9adb4a6 | bellard | if ((insn & 0x8000) != 0) |
896 | b9adb4a6 | bellard | return (insn & 0xfffc) - 0x10000; |
897 | b9adb4a6 | bellard | else
|
898 | b9adb4a6 | bellard | return insn & 0xfffc; |
899 | b9adb4a6 | bellard | } |
900 | b9adb4a6 | bellard | |
901 | b9adb4a6 | bellard | /* The LI field in an I form instruction. The lower two bits are
|
902 | b9adb4a6 | bellard | forced to zero. */
|
903 | b9adb4a6 | bellard | |
904 | b9adb4a6 | bellard | /*ARGSUSED*/
|
905 | b9adb4a6 | bellard | static unsigned long |
906 | b9adb4a6 | bellard | insert_li (insn, value, errmsg) |
907 | 274da6b2 | bellard | uint32_t insn; |
908 | 274da6b2 | bellard | int32_t value; |
909 | b9adb4a6 | bellard | const char **errmsg; |
910 | b9adb4a6 | bellard | { |
911 | b9adb4a6 | bellard | return insn | (value & 0x3fffffc); |
912 | b9adb4a6 | bellard | } |
913 | b9adb4a6 | bellard | |
914 | b9adb4a6 | bellard | /*ARGSUSED*/
|
915 | b9adb4a6 | bellard | static long |
916 | b9adb4a6 | bellard | extract_li (insn, invalid) |
917 | 274da6b2 | bellard | uint32_t insn; |
918 | b9adb4a6 | bellard | int *invalid;
|
919 | b9adb4a6 | bellard | { |
920 | b9adb4a6 | bellard | if ((insn & 0x2000000) != 0) |
921 | b9adb4a6 | bellard | return (insn & 0x3fffffc) - 0x4000000; |
922 | b9adb4a6 | bellard | else
|
923 | b9adb4a6 | bellard | return insn & 0x3fffffc; |
924 | b9adb4a6 | bellard | } |
925 | b9adb4a6 | bellard | |
926 | b9adb4a6 | bellard | /* The MB and ME fields in an M form instruction expressed as a single
|
927 | b9adb4a6 | bellard | operand which is itself a bitmask. The extraction function always
|
928 | b9adb4a6 | bellard | marks it as invalid, since we never want to recognize an
|
929 | b9adb4a6 | bellard | instruction which uses a field of this type. */
|
930 | b9adb4a6 | bellard | |
931 | b9adb4a6 | bellard | static unsigned long |
932 | b9adb4a6 | bellard | insert_mbe (insn, value, errmsg) |
933 | 274da6b2 | bellard | uint32_t insn; |
934 | 274da6b2 | bellard | int32_t value; |
935 | b9adb4a6 | bellard | const char **errmsg; |
936 | b9adb4a6 | bellard | { |
937 | 274da6b2 | bellard | uint32_t uval; |
938 | b9adb4a6 | bellard | int mb, me;
|
939 | b9adb4a6 | bellard | |
940 | b9adb4a6 | bellard | uval = value; |
941 | b9adb4a6 | bellard | |
942 | b9adb4a6 | bellard | if (uval == 0) |
943 | b9adb4a6 | bellard | { |
944 | b9adb4a6 | bellard | if (errmsg != (const char **) NULL) |
945 | b9adb4a6 | bellard | *errmsg = "illegal bitmask";
|
946 | b9adb4a6 | bellard | return insn;
|
947 | b9adb4a6 | bellard | } |
948 | b9adb4a6 | bellard | |
949 | b9adb4a6 | bellard | me = 31;
|
950 | b9adb4a6 | bellard | while ((uval & 1) == 0) |
951 | b9adb4a6 | bellard | { |
952 | b9adb4a6 | bellard | uval >>= 1;
|
953 | b9adb4a6 | bellard | --me; |
954 | b9adb4a6 | bellard | } |
955 | b9adb4a6 | bellard | |
956 | b9adb4a6 | bellard | mb = me; |
957 | b9adb4a6 | bellard | uval >>= 1;
|
958 | b9adb4a6 | bellard | while ((uval & 1) != 0) |
959 | b9adb4a6 | bellard | { |
960 | b9adb4a6 | bellard | uval >>= 1;
|
961 | b9adb4a6 | bellard | --mb; |
962 | b9adb4a6 | bellard | } |
963 | b9adb4a6 | bellard | |
964 | b9adb4a6 | bellard | if (uval != 0) |
965 | b9adb4a6 | bellard | { |
966 | b9adb4a6 | bellard | if (errmsg != (const char **) NULL) |
967 | b9adb4a6 | bellard | *errmsg = "illegal bitmask";
|
968 | b9adb4a6 | bellard | } |
969 | b9adb4a6 | bellard | |
970 | b9adb4a6 | bellard | return insn | (mb << 6) | (me << 1); |
971 | b9adb4a6 | bellard | } |
972 | b9adb4a6 | bellard | |
973 | b9adb4a6 | bellard | static long |
974 | b9adb4a6 | bellard | extract_mbe (insn, invalid) |
975 | 274da6b2 | bellard | uint32_t insn; |
976 | b9adb4a6 | bellard | int *invalid;
|
977 | b9adb4a6 | bellard | { |
978 | b9adb4a6 | bellard | long ret;
|
979 | b9adb4a6 | bellard | int mb, me;
|
980 | b9adb4a6 | bellard | int i;
|
981 | b9adb4a6 | bellard | |
982 | b9adb4a6 | bellard | if (invalid != (int *) NULL) |
983 | b9adb4a6 | bellard | *invalid = 1;
|
984 | b9adb4a6 | bellard | |
985 | b9adb4a6 | bellard | ret = 0;
|
986 | b9adb4a6 | bellard | mb = (insn >> 6) & 0x1f; |
987 | b9adb4a6 | bellard | me = (insn >> 1) & 0x1f; |
988 | b9adb4a6 | bellard | for (i = mb; i < me; i++)
|
989 | b9adb4a6 | bellard | ret |= 1 << (31 - i); |
990 | b9adb4a6 | bellard | return ret;
|
991 | b9adb4a6 | bellard | } |
992 | b9adb4a6 | bellard | |
993 | b9adb4a6 | bellard | /* The MB or ME field in an MD or MDS form instruction. The high bit
|
994 | b9adb4a6 | bellard | is wrapped to the low end. */
|
995 | b9adb4a6 | bellard | |
996 | b9adb4a6 | bellard | /*ARGSUSED*/
|
997 | b9adb4a6 | bellard | static unsigned long |
998 | b9adb4a6 | bellard | insert_mb6 (insn, value, errmsg) |
999 | 274da6b2 | bellard | uint32_t insn; |
1000 | 274da6b2 | bellard | int32_t value; |
1001 | b9adb4a6 | bellard | const char **errmsg; |
1002 | b9adb4a6 | bellard | { |
1003 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 6) | (value & 0x20); |
1004 | b9adb4a6 | bellard | } |
1005 | b9adb4a6 | bellard | |
1006 | b9adb4a6 | bellard | /*ARGSUSED*/
|
1007 | b9adb4a6 | bellard | static long |
1008 | b9adb4a6 | bellard | extract_mb6 (insn, invalid) |
1009 | 274da6b2 | bellard | uint32_t insn; |
1010 | b9adb4a6 | bellard | int *invalid;
|
1011 | b9adb4a6 | bellard | { |
1012 | b9adb4a6 | bellard | return ((insn >> 6) & 0x1f) | (insn & 0x20); |
1013 | b9adb4a6 | bellard | } |
1014 | b9adb4a6 | bellard | |
1015 | b9adb4a6 | bellard | /* The NB field in an X form instruction. The value 32 is stored as
|
1016 | b9adb4a6 | bellard | 0. */
|
1017 | b9adb4a6 | bellard | |
1018 | b9adb4a6 | bellard | static unsigned long |
1019 | b9adb4a6 | bellard | insert_nb (insn, value, errmsg) |
1020 | 274da6b2 | bellard | uint32_t insn; |
1021 | 274da6b2 | bellard | int32_t value; |
1022 | b9adb4a6 | bellard | const char **errmsg; |
1023 | b9adb4a6 | bellard | { |
1024 | b9adb4a6 | bellard | if (value < 0 || value > 32) |
1025 | b9adb4a6 | bellard | *errmsg = "value out of range";
|
1026 | b9adb4a6 | bellard | if (value == 32) |
1027 | b9adb4a6 | bellard | value = 0;
|
1028 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 11); |
1029 | b9adb4a6 | bellard | } |
1030 | b9adb4a6 | bellard | |
1031 | b9adb4a6 | bellard | /*ARGSUSED*/
|
1032 | b9adb4a6 | bellard | static long |
1033 | b9adb4a6 | bellard | extract_nb (insn, invalid) |
1034 | 274da6b2 | bellard | uint32_t insn; |
1035 | b9adb4a6 | bellard | int *invalid;
|
1036 | b9adb4a6 | bellard | { |
1037 | b9adb4a6 | bellard | long ret;
|
1038 | b9adb4a6 | bellard | |
1039 | b9adb4a6 | bellard | ret = (insn >> 11) & 0x1f; |
1040 | b9adb4a6 | bellard | if (ret == 0) |
1041 | b9adb4a6 | bellard | ret = 32;
|
1042 | b9adb4a6 | bellard | return ret;
|
1043 | b9adb4a6 | bellard | } |
1044 | b9adb4a6 | bellard | |
1045 | b9adb4a6 | bellard | /* The NSI field in a D form instruction. This is the same as the SI
|
1046 | b9adb4a6 | bellard | field, only negated. The extraction function always marks it as
|
1047 | b9adb4a6 | bellard | invalid, since we never want to recognize an instruction which uses
|
1048 | b9adb4a6 | bellard | a field of this type. */
|
1049 | b9adb4a6 | bellard | |
1050 | b9adb4a6 | bellard | /*ARGSUSED*/
|
1051 | b9adb4a6 | bellard | static unsigned long |
1052 | b9adb4a6 | bellard | insert_nsi (insn, value, errmsg) |
1053 | 274da6b2 | bellard | uint32_t insn; |
1054 | 274da6b2 | bellard | int32_t value; |
1055 | b9adb4a6 | bellard | const char **errmsg; |
1056 | b9adb4a6 | bellard | { |
1057 | b9adb4a6 | bellard | return insn | ((- value) & 0xffff); |
1058 | b9adb4a6 | bellard | } |
1059 | b9adb4a6 | bellard | |
1060 | b9adb4a6 | bellard | static long |
1061 | b9adb4a6 | bellard | extract_nsi (insn, invalid) |
1062 | 274da6b2 | bellard | uint32_t insn; |
1063 | b9adb4a6 | bellard | int *invalid;
|
1064 | b9adb4a6 | bellard | { |
1065 | b9adb4a6 | bellard | if (invalid != (int *) NULL) |
1066 | b9adb4a6 | bellard | *invalid = 1;
|
1067 | b9adb4a6 | bellard | if ((insn & 0x8000) != 0) |
1068 | b9adb4a6 | bellard | return - ((insn & 0xffff) - 0x10000); |
1069 | b9adb4a6 | bellard | else
|
1070 | b9adb4a6 | bellard | return - (insn & 0xffff); |
1071 | b9adb4a6 | bellard | } |
1072 | b9adb4a6 | bellard | |
1073 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
1074 | b9adb4a6 | bellard | load, which means that the RA field may not be zero and may not
|
1075 | b9adb4a6 | bellard | equal the RT field. */
|
1076 | b9adb4a6 | bellard | |
1077 | b9adb4a6 | bellard | static unsigned long |
1078 | b9adb4a6 | bellard | insert_ral (insn, value, errmsg) |
1079 | 274da6b2 | bellard | uint32_t insn; |
1080 | 274da6b2 | bellard | int32_t value; |
1081 | b9adb4a6 | bellard | const char **errmsg; |
1082 | b9adb4a6 | bellard | { |
1083 | b9adb4a6 | bellard | if (value == 0 |
1084 | b9adb4a6 | bellard | || value == ((insn >> 21) & 0x1f)) |
1085 | b9adb4a6 | bellard | *errmsg = "invalid register operand when updating";
|
1086 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16); |
1087 | b9adb4a6 | bellard | } |
1088 | b9adb4a6 | bellard | |
1089 | b9adb4a6 | bellard | /* The RA field in an lmw instruction, which has special value
|
1090 | b9adb4a6 | bellard | restrictions. */
|
1091 | b9adb4a6 | bellard | |
1092 | b9adb4a6 | bellard | static unsigned long |
1093 | b9adb4a6 | bellard | insert_ram (insn, value, errmsg) |
1094 | 274da6b2 | bellard | uint32_t insn; |
1095 | 274da6b2 | bellard | int32_t value; |
1096 | b9adb4a6 | bellard | const char **errmsg; |
1097 | b9adb4a6 | bellard | { |
1098 | b9adb4a6 | bellard | if (value >= ((insn >> 21) & 0x1f)) |
1099 | b9adb4a6 | bellard | *errmsg = "index register in load range";
|
1100 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16); |
1101 | b9adb4a6 | bellard | } |
1102 | b9adb4a6 | bellard | |
1103 | b9adb4a6 | bellard | /* The RA field in a D or X form instruction which is an updating
|
1104 | b9adb4a6 | bellard | store or an updating floating point load, which means that the RA
|
1105 | b9adb4a6 | bellard | field may not be zero. */
|
1106 | b9adb4a6 | bellard | |
1107 | b9adb4a6 | bellard | static unsigned long |
1108 | b9adb4a6 | bellard | insert_ras (insn, value, errmsg) |
1109 | 274da6b2 | bellard | uint32_t insn; |
1110 | 274da6b2 | bellard | int32_t value; |
1111 | b9adb4a6 | bellard | const char **errmsg; |
1112 | b9adb4a6 | bellard | { |
1113 | b9adb4a6 | bellard | if (value == 0) |
1114 | b9adb4a6 | bellard | *errmsg = "invalid register operand when updating";
|
1115 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16); |
1116 | b9adb4a6 | bellard | } |
1117 | b9adb4a6 | bellard | |
1118 | b9adb4a6 | bellard | /* The RB field in an X form instruction when it must be the same as
|
1119 | b9adb4a6 | bellard | the RS field in the instruction. This is used for extended
|
1120 | b9adb4a6 | bellard | mnemonics like mr. This operand is marked FAKE. The insertion
|
1121 | b9adb4a6 | bellard | function just copies the BT field into the BA field, and the
|
1122 | b9adb4a6 | bellard | extraction function just checks that the fields are the same. */
|
1123 | b9adb4a6 | bellard | |
1124 | b9adb4a6 | bellard | /*ARGSUSED*/
|
1125 | b9adb4a6 | bellard | static unsigned long |
1126 | b9adb4a6 | bellard | insert_rbs (insn, value, errmsg) |
1127 | 274da6b2 | bellard | uint32_t insn; |
1128 | 274da6b2 | bellard | int32_t value; |
1129 | b9adb4a6 | bellard | const char **errmsg; |
1130 | b9adb4a6 | bellard | { |
1131 | b9adb4a6 | bellard | return insn | (((insn >> 21) & 0x1f) << 11); |
1132 | b9adb4a6 | bellard | } |
1133 | b9adb4a6 | bellard | |
1134 | b9adb4a6 | bellard | static long |
1135 | b9adb4a6 | bellard | extract_rbs (insn, invalid) |
1136 | 274da6b2 | bellard | uint32_t insn; |
1137 | b9adb4a6 | bellard | int *invalid;
|
1138 | b9adb4a6 | bellard | { |
1139 | b9adb4a6 | bellard | if (invalid != (int *) NULL |
1140 | b9adb4a6 | bellard | && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) |
1141 | b9adb4a6 | bellard | *invalid = 1;
|
1142 | b9adb4a6 | bellard | return 0; |
1143 | b9adb4a6 | bellard | } |
1144 | b9adb4a6 | bellard | |
1145 | b9adb4a6 | bellard | /* The SH field in an MD form instruction. This is split. */
|
1146 | b9adb4a6 | bellard | |
1147 | b9adb4a6 | bellard | /*ARGSUSED*/
|
1148 | b9adb4a6 | bellard | static unsigned long |
1149 | b9adb4a6 | bellard | insert_sh6 (insn, value, errmsg) |
1150 | 274da6b2 | bellard | uint32_t insn; |
1151 | 274da6b2 | bellard | int32_t value; |
1152 | b9adb4a6 | bellard | const char **errmsg; |
1153 | b9adb4a6 | bellard | { |
1154 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
1155 | b9adb4a6 | bellard | } |
1156 | b9adb4a6 | bellard | |
1157 | b9adb4a6 | bellard | /*ARGSUSED*/
|
1158 | b9adb4a6 | bellard | static long |
1159 | b9adb4a6 | bellard | extract_sh6 (insn, invalid) |
1160 | 274da6b2 | bellard | uint32_t insn; |
1161 | b9adb4a6 | bellard | int *invalid;
|
1162 | b9adb4a6 | bellard | { |
1163 | b9adb4a6 | bellard | return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
1164 | b9adb4a6 | bellard | } |
1165 | b9adb4a6 | bellard | |
1166 | b9adb4a6 | bellard | /* The SPR field in an XFX form instruction. This is flipped--the
|
1167 | b9adb4a6 | bellard | lower 5 bits are stored in the upper 5 and vice- versa. */
|
1168 | b9adb4a6 | bellard | |
1169 | b9adb4a6 | bellard | static unsigned long |
1170 | b9adb4a6 | bellard | insert_spr (insn, value, errmsg) |
1171 | 274da6b2 | bellard | uint32_t insn; |
1172 | 274da6b2 | bellard | int32_t value; |
1173 | b9adb4a6 | bellard | const char **errmsg; |
1174 | b9adb4a6 | bellard | { |
1175 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
1176 | b9adb4a6 | bellard | } |
1177 | b9adb4a6 | bellard | |
1178 | b9adb4a6 | bellard | static long |
1179 | b9adb4a6 | bellard | extract_spr (insn, invalid) |
1180 | 274da6b2 | bellard | uint32_t insn; |
1181 | b9adb4a6 | bellard | int *invalid;
|
1182 | b9adb4a6 | bellard | { |
1183 | b9adb4a6 | bellard | return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
1184 | b9adb4a6 | bellard | } |
1185 | b9adb4a6 | bellard | |
1186 | b9adb4a6 | bellard | /* The TBR field in an XFX instruction. This is just like SPR, but it
|
1187 | b9adb4a6 | bellard | is optional. When TBR is omitted, it must be inserted as 268 (the
|
1188 | b9adb4a6 | bellard | magic number of the TB register). These functions treat 0
|
1189 | b9adb4a6 | bellard | (indicating an omitted optional operand) as 268. This means that
|
1190 | b9adb4a6 | bellard | ``mftb 4,0'' is not handled correctly. This does not matter very
|
1191 | b9adb4a6 | bellard | much, since the architecture manual does not define mftb as
|
1192 | b9adb4a6 | bellard | accepting any values other than 268 or 269. */
|
1193 | b9adb4a6 | bellard | |
1194 | b9adb4a6 | bellard | #define TB (268) |
1195 | b9adb4a6 | bellard | |
1196 | b9adb4a6 | bellard | static unsigned long |
1197 | b9adb4a6 | bellard | insert_tbr (insn, value, errmsg) |
1198 | 274da6b2 | bellard | uint32_t insn; |
1199 | 274da6b2 | bellard | int32_t value; |
1200 | b9adb4a6 | bellard | const char **errmsg; |
1201 | b9adb4a6 | bellard | { |
1202 | b9adb4a6 | bellard | if (value == 0) |
1203 | b9adb4a6 | bellard | value = TB; |
1204 | b9adb4a6 | bellard | return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
1205 | b9adb4a6 | bellard | } |
1206 | b9adb4a6 | bellard | |
1207 | b9adb4a6 | bellard | static long |
1208 | b9adb4a6 | bellard | extract_tbr (insn, invalid) |
1209 | 274da6b2 | bellard | uint32_t insn; |
1210 | b9adb4a6 | bellard | int *invalid;
|
1211 | b9adb4a6 | bellard | { |
1212 | b9adb4a6 | bellard | long ret;
|
1213 | b9adb4a6 | bellard | |
1214 | b9adb4a6 | bellard | ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
1215 | b9adb4a6 | bellard | if (ret == TB)
|
1216 | b9adb4a6 | bellard | ret = 0;
|
1217 | b9adb4a6 | bellard | return ret;
|
1218 | b9adb4a6 | bellard | } |
1219 | b9adb4a6 | bellard | |
1220 | b9adb4a6 | bellard | /* Macros used to form opcodes. */
|
1221 | b9adb4a6 | bellard | |
1222 | b9adb4a6 | bellard | /* The main opcode. */
|
1223 | b9adb4a6 | bellard | #define OP(x) (((x) & 0x3f) << 26) |
1224 | b9adb4a6 | bellard | #define OP_MASK OP (0x3f) |
1225 | b9adb4a6 | bellard | |
1226 | b9adb4a6 | bellard | /* The main opcode combined with a trap code in the TO field of a D
|
1227 | b9adb4a6 | bellard | form instruction. Used for extended mnemonics for the trap
|
1228 | b9adb4a6 | bellard | instructions. */
|
1229 | b9adb4a6 | bellard | #define OPTO(x,to) (OP (x) | (((to) & 0x1f) << 21)) |
1230 | b9adb4a6 | bellard | #define OPTO_MASK (OP_MASK | TO_MASK)
|
1231 | b9adb4a6 | bellard | |
1232 | b9adb4a6 | bellard | /* The main opcode combined with a comparison size bit in the L field
|
1233 | b9adb4a6 | bellard | of a D form or X form instruction. Used for extended mnemonics for
|
1234 | b9adb4a6 | bellard | the comparison instructions. */
|
1235 | b9adb4a6 | bellard | #define OPL(x,l) (OP (x) | (((l) & 1) << 21)) |
1236 | b9adb4a6 | bellard | #define OPL_MASK OPL (0x3f,1) |
1237 | b9adb4a6 | bellard | |
1238 | b9adb4a6 | bellard | /* An A form instruction. */
|
1239 | b9adb4a6 | bellard | #define A(op, xop, rc) (OP (op) | (((xop) & 0x1f) << 1) | ((rc) & 1)) |
1240 | b9adb4a6 | bellard | #define A_MASK A (0x3f, 0x1f, 1) |
1241 | b9adb4a6 | bellard | |
1242 | b9adb4a6 | bellard | /* An A_MASK with the FRB field fixed. */
|
1243 | b9adb4a6 | bellard | #define AFRB_MASK (A_MASK | FRB_MASK)
|
1244 | b9adb4a6 | bellard | |
1245 | b9adb4a6 | bellard | /* An A_MASK with the FRC field fixed. */
|
1246 | b9adb4a6 | bellard | #define AFRC_MASK (A_MASK | FRC_MASK)
|
1247 | b9adb4a6 | bellard | |
1248 | b9adb4a6 | bellard | /* An A_MASK with the FRA and FRC fields fixed. */
|
1249 | b9adb4a6 | bellard | #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
|
1250 | b9adb4a6 | bellard | |
1251 | b9adb4a6 | bellard | /* A B form instruction. */
|
1252 | b9adb4a6 | bellard | #define B(op, aa, lk) (OP (op) | (((aa) & 1) << 1) | ((lk) & 1)) |
1253 | b9adb4a6 | bellard | #define B_MASK B (0x3f, 1, 1) |
1254 | b9adb4a6 | bellard | |
1255 | b9adb4a6 | bellard | /* A B form instruction setting the BO field. */
|
1256 | b9adb4a6 | bellard | #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | (((bo) & 0x1f) << 21)) |
1257 | b9adb4a6 | bellard | #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
1258 | b9adb4a6 | bellard | |
1259 | b9adb4a6 | bellard | /* A BBO_MASK with the y bit of the BO field removed. This permits
|
1260 | b9adb4a6 | bellard | matching a conditional branch regardless of the setting of the y
|
1261 | b9adb4a6 | bellard | bit. */
|
1262 | b9adb4a6 | bellard | #define Y_MASK (1 << 21) |
1263 | b9adb4a6 | bellard | #define BBOY_MASK (BBO_MASK &~ Y_MASK)
|
1264 | b9adb4a6 | bellard | |
1265 | b9adb4a6 | bellard | /* A B form instruction setting the BO field and the condition bits of
|
1266 | b9adb4a6 | bellard | the BI field. */
|
1267 | b9adb4a6 | bellard | #define BBOCB(op, bo, cb, aa, lk) \
|
1268 | b9adb4a6 | bellard | (BBO ((op), (bo), (aa), (lk)) | (((cb) & 0x3) << 16)) |
1269 | b9adb4a6 | bellard | #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
1270 | b9adb4a6 | bellard | |
1271 | b9adb4a6 | bellard | /* A BBOCB_MASK with the y bit of the BO field removed. */
|
1272 | b9adb4a6 | bellard | #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
|
1273 | b9adb4a6 | bellard | |
1274 | b9adb4a6 | bellard | /* A BBOYCB_MASK in which the BI field is fixed. */
|
1275 | b9adb4a6 | bellard | #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
|
1276 | b9adb4a6 | bellard | |
1277 | b9adb4a6 | bellard | /* The main opcode mask with the RA field clear. */
|
1278 | b9adb4a6 | bellard | #define DRA_MASK (OP_MASK | RA_MASK)
|
1279 | b9adb4a6 | bellard | |
1280 | b9adb4a6 | bellard | /* A DS form instruction. */
|
1281 | b9adb4a6 | bellard | #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) |
1282 | b9adb4a6 | bellard | #define DS_MASK DSO (0x3f, 3) |
1283 | b9adb4a6 | bellard | |
1284 | b9adb4a6 | bellard | /* An M form instruction. */
|
1285 | b9adb4a6 | bellard | #define M(op, rc) (OP (op) | ((rc) & 1)) |
1286 | b9adb4a6 | bellard | #define M_MASK M (0x3f, 1) |
1287 | b9adb4a6 | bellard | |
1288 | b9adb4a6 | bellard | /* An M form instruction with the ME field specified. */
|
1289 | b9adb4a6 | bellard | #define MME(op, me, rc) (M ((op), (rc)) | (((me) & 0x1f) << 1)) |
1290 | b9adb4a6 | bellard | |
1291 | b9adb4a6 | bellard | /* An M_MASK with the MB and ME fields fixed. */
|
1292 | b9adb4a6 | bellard | #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
|
1293 | b9adb4a6 | bellard | |
1294 | b9adb4a6 | bellard | /* An M_MASK with the SH and ME fields fixed. */
|
1295 | b9adb4a6 | bellard | #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
|
1296 | b9adb4a6 | bellard | |
1297 | b9adb4a6 | bellard | /* An MD form instruction. */
|
1298 | b9adb4a6 | bellard | #define MD(op, xop, rc) (OP (op) | (((xop) & 0x7) << 2) | ((rc) & 1)) |
1299 | b9adb4a6 | bellard | #define MD_MASK MD (0x3f, 0x7, 1) |
1300 | b9adb4a6 | bellard | |
1301 | b9adb4a6 | bellard | /* An MD_MASK with the MB field fixed. */
|
1302 | b9adb4a6 | bellard | #define MDMB_MASK (MD_MASK | MB6_MASK)
|
1303 | b9adb4a6 | bellard | |
1304 | b9adb4a6 | bellard | /* An MD_MASK with the SH field fixed. */
|
1305 | b9adb4a6 | bellard | #define MDSH_MASK (MD_MASK | SH6_MASK)
|
1306 | b9adb4a6 | bellard | |
1307 | b9adb4a6 | bellard | /* An MDS form instruction. */
|
1308 | b9adb4a6 | bellard | #define MDS(op, xop, rc) (OP (op) | (((xop) & 0xf) << 1) | ((rc) & 1)) |
1309 | b9adb4a6 | bellard | #define MDS_MASK MDS (0x3f, 0xf, 1) |
1310 | b9adb4a6 | bellard | |
1311 | b9adb4a6 | bellard | /* An MDS_MASK with the MB field fixed. */
|
1312 | b9adb4a6 | bellard | #define MDSMB_MASK (MDS_MASK | MB6_MASK)
|
1313 | b9adb4a6 | bellard | |
1314 | b9adb4a6 | bellard | /* An SC form instruction. */
|
1315 | b9adb4a6 | bellard | #define SC(op, sa, lk) (OP (op) | (((sa) & 1) << 1) | ((lk) & 1)) |
1316 | b9adb4a6 | bellard | #define SC_MASK (OP_MASK | (0x3ff << 16) | (1 << 1) | 1) |
1317 | b9adb4a6 | bellard | |
1318 | b9adb4a6 | bellard | /* An X form instruction. */
|
1319 | b9adb4a6 | bellard | #define X(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) |
1320 | b9adb4a6 | bellard | |
1321 | b9adb4a6 | bellard | /* An X form instruction with the RC bit specified. */
|
1322 | b9adb4a6 | bellard | #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) |
1323 | b9adb4a6 | bellard | |
1324 | b9adb4a6 | bellard | /* The mask for an X form instruction. */
|
1325 | b9adb4a6 | bellard | #define X_MASK XRC (0x3f, 0x3ff, 1) |
1326 | b9adb4a6 | bellard | |
1327 | b9adb4a6 | bellard | /* An X_MASK with the RA field fixed. */
|
1328 | b9adb4a6 | bellard | #define XRA_MASK (X_MASK | RA_MASK)
|
1329 | b9adb4a6 | bellard | |
1330 | b9adb4a6 | bellard | /* An X_MASK with the RB field fixed. */
|
1331 | b9adb4a6 | bellard | #define XRB_MASK (X_MASK | RB_MASK)
|
1332 | b9adb4a6 | bellard | |
1333 | b9adb4a6 | bellard | /* An X_MASK with the RT field fixed. */
|
1334 | b9adb4a6 | bellard | #define XRT_MASK (X_MASK | RT_MASK)
|
1335 | b9adb4a6 | bellard | |
1336 | b9adb4a6 | bellard | /* An X_MASK with the RA and RB fields fixed. */
|
1337 | b9adb4a6 | bellard | #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
|
1338 | b9adb4a6 | bellard | |
1339 | b9adb4a6 | bellard | /* An X_MASK with the RT and RA fields fixed. */
|
1340 | b9adb4a6 | bellard | #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
|
1341 | b9adb4a6 | bellard | |
1342 | b9adb4a6 | bellard | /* An X form comparison instruction. */
|
1343 | b9adb4a6 | bellard | #define XCMPL(op, xop, l) (X ((op), (xop)) | (((l) & 1) << 21)) |
1344 | b9adb4a6 | bellard | |
1345 | b9adb4a6 | bellard | /* The mask for an X form comparison instruction. */
|
1346 | b9adb4a6 | bellard | #define XCMP_MASK (X_MASK | (1 << 22)) |
1347 | b9adb4a6 | bellard | |
1348 | b9adb4a6 | bellard | /* The mask for an X form comparison instruction with the L field
|
1349 | b9adb4a6 | bellard | fixed. */
|
1350 | b9adb4a6 | bellard | #define XCMPL_MASK (XCMP_MASK | (1 << 21)) |
1351 | b9adb4a6 | bellard | |
1352 | b9adb4a6 | bellard | /* An X form trap instruction with the TO field specified. */
|
1353 | b9adb4a6 | bellard | #define XTO(op, xop, to) (X ((op), (xop)) | (((to) & 0x1f) << 21)) |
1354 | b9adb4a6 | bellard | #define XTO_MASK (X_MASK | TO_MASK)
|
1355 | b9adb4a6 | bellard | |
1356 | b9adb4a6 | bellard | /* An XFL form instruction. */
|
1357 | b9adb4a6 | bellard | #define XFL(op, xop, rc) (OP (op) | (((xop) & 0x3ff) << 1) | ((rc) & 1)) |
1358 | b9adb4a6 | bellard | #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (1 << 25) | (1 << 16)) |
1359 | b9adb4a6 | bellard | |
1360 | b9adb4a6 | bellard | /* An XL form instruction with the LK field set to 0. */
|
1361 | b9adb4a6 | bellard | #define XL(op, xop) (OP (op) | (((xop) & 0x3ff) << 1)) |
1362 | b9adb4a6 | bellard | |
1363 | b9adb4a6 | bellard | /* An XL form instruction which uses the LK field. */
|
1364 | b9adb4a6 | bellard | #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) |
1365 | b9adb4a6 | bellard | |
1366 | b9adb4a6 | bellard | /* The mask for an XL form instruction. */
|
1367 | b9adb4a6 | bellard | #define XL_MASK XLLK (0x3f, 0x3ff, 1) |
1368 | b9adb4a6 | bellard | |
1369 | b9adb4a6 | bellard | /* An XL form instruction which explicitly sets the BO field. */
|
1370 | b9adb4a6 | bellard | #define XLO(op, bo, xop, lk) \
|
1371 | b9adb4a6 | bellard | (XLLK ((op), (xop), (lk)) | (((bo) & 0x1f) << 21)) |
1372 | b9adb4a6 | bellard | #define XLO_MASK (XL_MASK | BO_MASK)
|
1373 | b9adb4a6 | bellard | |
1374 | b9adb4a6 | bellard | /* An XL form instruction which explicitly sets the y bit of the BO
|
1375 | b9adb4a6 | bellard | field. */
|
1376 | b9adb4a6 | bellard | #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | (((y) & 1) << 21)) |
1377 | b9adb4a6 | bellard | #define XLYLK_MASK (XL_MASK | Y_MASK)
|
1378 | b9adb4a6 | bellard | |
1379 | b9adb4a6 | bellard | /* An XL form instruction which sets the BO field and the condition
|
1380 | b9adb4a6 | bellard | bits of the BI field. */
|
1381 | b9adb4a6 | bellard | #define XLOCB(op, bo, cb, xop, lk) \
|
1382 | b9adb4a6 | bellard | (XLO ((op), (bo), (xop), (lk)) | (((cb) & 3) << 16)) |
1383 | b9adb4a6 | bellard | #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) |
1384 | b9adb4a6 | bellard | |
1385 | b9adb4a6 | bellard | /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
|
1386 | b9adb4a6 | bellard | #define XLBB_MASK (XL_MASK | BB_MASK)
|
1387 | b9adb4a6 | bellard | #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
|
1388 | b9adb4a6 | bellard | #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
|
1389 | b9adb4a6 | bellard | |
1390 | b9adb4a6 | bellard | /* An XL_MASK with the BO and BB fields fixed. */
|
1391 | b9adb4a6 | bellard | #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
|
1392 | b9adb4a6 | bellard | |
1393 | b9adb4a6 | bellard | /* An XL_MASK with the BO, BI and BB fields fixed. */
|
1394 | b9adb4a6 | bellard | #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
|
1395 | b9adb4a6 | bellard | |
1396 | b9adb4a6 | bellard | /* An XO form instruction. */
|
1397 | b9adb4a6 | bellard | #define XO(op, xop, oe, rc) \
|
1398 | b9adb4a6 | bellard | (OP (op) | (((xop) & 0x1ff) << 1) | (((oe) & 1) << 10) | ((rc) & 1)) |
1399 | b9adb4a6 | bellard | #define XO_MASK XO (0x3f, 0x1ff, 1, 1) |
1400 | b9adb4a6 | bellard | |
1401 | b9adb4a6 | bellard | /* An XO_MASK with the RB field fixed. */
|
1402 | b9adb4a6 | bellard | #define XORB_MASK (XO_MASK | RB_MASK)
|
1403 | b9adb4a6 | bellard | |
1404 | b9adb4a6 | bellard | /* An XS form instruction. */
|
1405 | b9adb4a6 | bellard | #define XS(op, xop, rc) (OP (op) | (((xop) & 0x1ff) << 2) | ((rc) & 1)) |
1406 | b9adb4a6 | bellard | #define XS_MASK XS (0x3f, 0x1ff, 1) |
1407 | b9adb4a6 | bellard | |
1408 | b9adb4a6 | bellard | /* A mask for the FXM version of an XFX form instruction. */
|
1409 | b9adb4a6 | bellard | #define XFXFXM_MASK (X_MASK | (1 << 20) | (1 << 11)) |
1410 | b9adb4a6 | bellard | |
1411 | b9adb4a6 | bellard | /* An XFX form instruction with the FXM field filled in. */
|
1412 | b9adb4a6 | bellard | #define XFXM(op, xop, fxm) \
|
1413 | b9adb4a6 | bellard | (X ((op), (xop)) | (((fxm) & 0xff) << 12)) |
1414 | b9adb4a6 | bellard | |
1415 | b9adb4a6 | bellard | /* An XFX form instruction with the SPR field filled in. */
|
1416 | b9adb4a6 | bellard | #define XSPR(op, xop, spr) \
|
1417 | b9adb4a6 | bellard | (X ((op), (xop)) | (((spr) & 0x1f) << 16) | (((spr) & 0x3e0) << 6)) |
1418 | b9adb4a6 | bellard | #define XSPR_MASK (X_MASK | SPR_MASK)
|
1419 | b9adb4a6 | bellard | |
1420 | b9adb4a6 | bellard | /* An XFX form instruction with the SPR field filled in except for the
|
1421 | b9adb4a6 | bellard | SPRBAT field. */
|
1422 | b9adb4a6 | bellard | #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
|
1423 | b9adb4a6 | bellard | |
1424 | b9adb4a6 | bellard | /* An XFX form instruction with the SPR field filled in except for the
|
1425 | b9adb4a6 | bellard | SPRG field. */
|
1426 | b9adb4a6 | bellard | #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
|
1427 | b9adb4a6 | bellard | |
1428 | b9adb4a6 | bellard | /* The BO encodings used in extended conditional branch mnemonics. */
|
1429 | b9adb4a6 | bellard | #define BODNZF (0x0) |
1430 | b9adb4a6 | bellard | #define BODNZFP (0x1) |
1431 | b9adb4a6 | bellard | #define BODZF (0x2) |
1432 | b9adb4a6 | bellard | #define BODZFP (0x3) |
1433 | b9adb4a6 | bellard | #define BOF (0x4) |
1434 | b9adb4a6 | bellard | #define BOFP (0x5) |
1435 | b9adb4a6 | bellard | #define BODNZT (0x8) |
1436 | b9adb4a6 | bellard | #define BODNZTP (0x9) |
1437 | b9adb4a6 | bellard | #define BODZT (0xa) |
1438 | b9adb4a6 | bellard | #define BODZTP (0xb) |
1439 | b9adb4a6 | bellard | #define BOT (0xc) |
1440 | b9adb4a6 | bellard | #define BOTP (0xd) |
1441 | b9adb4a6 | bellard | #define BODNZ (0x10) |
1442 | b9adb4a6 | bellard | #define BODNZP (0x11) |
1443 | b9adb4a6 | bellard | #define BODZ (0x12) |
1444 | b9adb4a6 | bellard | #define BODZP (0x13) |
1445 | b9adb4a6 | bellard | #define BOU (0x14) |
1446 | b9adb4a6 | bellard | |
1447 | b9adb4a6 | bellard | /* The BI condition bit encodings used in extended conditional branch
|
1448 | b9adb4a6 | bellard | mnemonics. */
|
1449 | b9adb4a6 | bellard | #define CBLT (0) |
1450 | b9adb4a6 | bellard | #define CBGT (1) |
1451 | b9adb4a6 | bellard | #define CBEQ (2) |
1452 | b9adb4a6 | bellard | #define CBSO (3) |
1453 | b9adb4a6 | bellard | |
1454 | b9adb4a6 | bellard | /* The TO encodings used in extended trap mnemonics. */
|
1455 | b9adb4a6 | bellard | #define TOLGT (0x1) |
1456 | b9adb4a6 | bellard | #define TOLLT (0x2) |
1457 | b9adb4a6 | bellard | #define TOEQ (0x4) |
1458 | b9adb4a6 | bellard | #define TOLGE (0x5) |
1459 | b9adb4a6 | bellard | #define TOLNL (0x5) |
1460 | b9adb4a6 | bellard | #define TOLLE (0x6) |
1461 | b9adb4a6 | bellard | #define TOLNG (0x6) |
1462 | b9adb4a6 | bellard | #define TOGT (0x8) |
1463 | b9adb4a6 | bellard | #define TOGE (0xc) |
1464 | b9adb4a6 | bellard | #define TONL (0xc) |
1465 | b9adb4a6 | bellard | #define TOLT (0x10) |
1466 | b9adb4a6 | bellard | #define TOLE (0x14) |
1467 | b9adb4a6 | bellard | #define TONG (0x14) |
1468 | b9adb4a6 | bellard | #define TONE (0x18) |
1469 | b9adb4a6 | bellard | #define TOU (0x1f) |
1470 | b9adb4a6 | bellard | |
1471 | b9adb4a6 | bellard | /* Smaller names for the flags so each entry in the opcodes table will
|
1472 | b9adb4a6 | bellard | fit on a single line. */
|
1473 | b9adb4a6 | bellard | #undef PPC
|
1474 | b9adb4a6 | bellard | #define PPC PPC_OPCODE_PPC
|
1475 | b9adb4a6 | bellard | #define POWER PPC_OPCODE_POWER
|
1476 | b9adb4a6 | bellard | #define POWER2 PPC_OPCODE_POWER2
|
1477 | b9adb4a6 | bellard | #define B32 PPC_OPCODE_32
|
1478 | b9adb4a6 | bellard | #define B64 PPC_OPCODE_64
|
1479 | b9adb4a6 | bellard | #define M601 PPC_OPCODE_601
|
1480 | b9adb4a6 | bellard | |
1481 | b9adb4a6 | bellard | /* The opcode table.
|
1482 | b9adb4a6 | bellard | |
1483 | b9adb4a6 | bellard | The format of the opcode table is:
|
1484 | b9adb4a6 | bellard | |
1485 | b9adb4a6 | bellard | NAME OPCODE MASK FLAGS { OPERANDS }
|
1486 | b9adb4a6 | bellard | |
1487 | b9adb4a6 | bellard | NAME is the name of the instruction.
|
1488 | b9adb4a6 | bellard | OPCODE is the instruction opcode.
|
1489 | b9adb4a6 | bellard | MASK is the opcode mask; this is used to tell the disassembler
|
1490 | b9adb4a6 | bellard | which bits in the actual opcode must match OPCODE.
|
1491 | b9adb4a6 | bellard | FLAGS are flags indicated what processors support the instruction.
|
1492 | b9adb4a6 | bellard | OPERANDS is the list of operands.
|
1493 | b9adb4a6 | bellard | |
1494 | b9adb4a6 | bellard | The disassembler reads the table in order and prints the first
|
1495 | b9adb4a6 | bellard | instruction which matches, so this table is sorted to put more
|
1496 | b9adb4a6 | bellard | specific instructions before more general instructions. It is also
|
1497 | b9adb4a6 | bellard | sorted by major opcode. */
|
1498 | b9adb4a6 | bellard | |
1499 | b9adb4a6 | bellard | const struct powerpc_opcode powerpc_opcodes[] = { |
1500 | b9adb4a6 | bellard | { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC|B64, { RA, SI } }, |
1501 | b9adb4a6 | bellard | { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC|B64, { RA, SI } }, |
1502 | b9adb4a6 | bellard | { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC|B64, { RA, SI } }, |
1503 | b9adb4a6 | bellard | { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC|B64, { RA, SI } }, |
1504 | b9adb4a6 | bellard | { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC|B64, { RA, SI } }, |
1505 | b9adb4a6 | bellard | { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC|B64, { RA, SI } }, |
1506 | b9adb4a6 | bellard | { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC|B64, { RA, SI } }, |
1507 | b9adb4a6 | bellard | { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC|B64, { RA, SI } }, |
1508 | b9adb4a6 | bellard | { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC|B64, { RA, SI } }, |
1509 | b9adb4a6 | bellard | { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC|B64, { RA, SI } }, |
1510 | b9adb4a6 | bellard | { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC|B64, { RA, SI } }, |
1511 | b9adb4a6 | bellard | { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC|B64, { RA, SI } }, |
1512 | b9adb4a6 | bellard | { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC|B64, { RA, SI } }, |
1513 | b9adb4a6 | bellard | { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC|B64, { RA, SI } }, |
1514 | b9adb4a6 | bellard | { "tdi", OP(2), OP_MASK, PPC|B64, { TO, RA, SI } }, |
1515 | b9adb4a6 | bellard | |
1516 | b9adb4a6 | bellard | { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPC, { RA, SI } }, |
1517 | b9adb4a6 | bellard | { "tlgti", OPTO(3,TOLGT), OPTO_MASK, POWER, { RA, SI } }, |
1518 | b9adb4a6 | bellard | { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPC, { RA, SI } }, |
1519 | b9adb4a6 | bellard | { "tllti", OPTO(3,TOLLT), OPTO_MASK, POWER, { RA, SI } }, |
1520 | b9adb4a6 | bellard | { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPC, { RA, SI } }, |
1521 | b9adb4a6 | bellard | { "teqi", OPTO(3,TOEQ), OPTO_MASK, POWER, { RA, SI } }, |
1522 | b9adb4a6 | bellard | { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPC, { RA, SI } }, |
1523 | b9adb4a6 | bellard | { "tlgei", OPTO(3,TOLGE), OPTO_MASK, POWER, { RA, SI } }, |
1524 | b9adb4a6 | bellard | { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPC, { RA, SI } }, |
1525 | b9adb4a6 | bellard | { "tlnli", OPTO(3,TOLNL), OPTO_MASK, POWER, { RA, SI } }, |
1526 | b9adb4a6 | bellard | { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPC, { RA, SI } }, |
1527 | b9adb4a6 | bellard | { "tllei", OPTO(3,TOLLE), OPTO_MASK, POWER, { RA, SI } }, |
1528 | b9adb4a6 | bellard | { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPC, { RA, SI } }, |
1529 | b9adb4a6 | bellard | { "tlngi", OPTO(3,TOLNG), OPTO_MASK, POWER, { RA, SI } }, |
1530 | b9adb4a6 | bellard | { "twgti", OPTO(3,TOGT), OPTO_MASK, PPC, { RA, SI } }, |
1531 | b9adb4a6 | bellard | { "tgti", OPTO(3,TOGT), OPTO_MASK, POWER, { RA, SI } }, |
1532 | b9adb4a6 | bellard | { "twgei", OPTO(3,TOGE), OPTO_MASK, PPC, { RA, SI } }, |
1533 | b9adb4a6 | bellard | { "tgei", OPTO(3,TOGE), OPTO_MASK, POWER, { RA, SI } }, |
1534 | b9adb4a6 | bellard | { "twnli", OPTO(3,TONL), OPTO_MASK, PPC, { RA, SI } }, |
1535 | b9adb4a6 | bellard | { "tnli", OPTO(3,TONL), OPTO_MASK, POWER, { RA, SI } }, |
1536 | b9adb4a6 | bellard | { "twlti", OPTO(3,TOLT), OPTO_MASK, PPC, { RA, SI } }, |
1537 | b9adb4a6 | bellard | { "tlti", OPTO(3,TOLT), OPTO_MASK, POWER, { RA, SI } }, |
1538 | b9adb4a6 | bellard | { "twlei", OPTO(3,TOLE), OPTO_MASK, PPC, { RA, SI } }, |
1539 | b9adb4a6 | bellard | { "tlei", OPTO(3,TOLE), OPTO_MASK, POWER, { RA, SI } }, |
1540 | b9adb4a6 | bellard | { "twngi", OPTO(3,TONG), OPTO_MASK, PPC, { RA, SI } }, |
1541 | b9adb4a6 | bellard | { "tngi", OPTO(3,TONG), OPTO_MASK, POWER, { RA, SI } }, |
1542 | b9adb4a6 | bellard | { "twnei", OPTO(3,TONE), OPTO_MASK, PPC, { RA, SI } }, |
1543 | b9adb4a6 | bellard | { "tnei", OPTO(3,TONE), OPTO_MASK, POWER, { RA, SI } }, |
1544 | b9adb4a6 | bellard | { "twi", OP(3), OP_MASK, PPC, { TO, RA, SI } }, |
1545 | b9adb4a6 | bellard | { "ti", OP(3), OP_MASK, POWER, { TO, RA, SI } }, |
1546 | b9adb4a6 | bellard | |
1547 | b9adb4a6 | bellard | { "mulli", OP(7), OP_MASK, PPC, { RT, RA, SI } }, |
1548 | b9adb4a6 | bellard | { "muli", OP(7), OP_MASK, POWER, { RT, RA, SI } }, |
1549 | b9adb4a6 | bellard | |
1550 | b9adb4a6 | bellard | { "subfic", OP(8), OP_MASK, PPC, { RT, RA, SI } }, |
1551 | b9adb4a6 | bellard | { "sfi", OP(8), OP_MASK, POWER, { RT, RA, SI } }, |
1552 | b9adb4a6 | bellard | |
1553 | b9adb4a6 | bellard | { "dozi", OP(9), OP_MASK, POWER|M601, { RT, RA, SI } }, |
1554 | b9adb4a6 | bellard | |
1555 | b9adb4a6 | bellard | { "cmplwi", OPL(10,0), OPL_MASK, PPC, { OBF, RA, UI } }, |
1556 | b9adb4a6 | bellard | { "cmpldi", OPL(10,1), OPL_MASK, PPC|B64, { OBF, RA, UI } }, |
1557 | b9adb4a6 | bellard | { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, |
1558 | b9adb4a6 | bellard | { "cmpli", OP(10), OP_MASK, POWER, { BF, RA, UI } }, |
1559 | b9adb4a6 | bellard | |
1560 | b9adb4a6 | bellard | { "cmpwi", OPL(11,0), OPL_MASK, PPC, { OBF, RA, SI } }, |
1561 | b9adb4a6 | bellard | { "cmpdi", OPL(11,1), OPL_MASK, PPC|B64, { OBF, RA, SI } }, |
1562 | b9adb4a6 | bellard | { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, |
1563 | b9adb4a6 | bellard | { "cmpi", OP(11), OP_MASK, POWER, { BF, RA, SI } }, |
1564 | b9adb4a6 | bellard | |
1565 | b9adb4a6 | bellard | { "addic", OP(12), OP_MASK, PPC, { RT, RA, SI } }, |
1566 | b9adb4a6 | bellard | { "ai", OP(12), OP_MASK, POWER, { RT, RA, SI } }, |
1567 | b9adb4a6 | bellard | { "subic", OP(12), OP_MASK, PPC, { RT, RA, NSI } }, |
1568 | b9adb4a6 | bellard | |
1569 | b9adb4a6 | bellard | { "addic.", OP(13), OP_MASK, PPC, { RT, RA, SI } }, |
1570 | b9adb4a6 | bellard | { "ai.", OP(13), OP_MASK, POWER, { RT, RA, SI } }, |
1571 | b9adb4a6 | bellard | { "subic.", OP(13), OP_MASK, PPC, { RT, RA, NSI } }, |
1572 | b9adb4a6 | bellard | |
1573 | b9adb4a6 | bellard | { "li", OP(14), DRA_MASK, PPC, { RT, SI } }, |
1574 | b9adb4a6 | bellard | { "lil", OP(14), DRA_MASK, POWER, { RT, SI } }, |
1575 | b9adb4a6 | bellard | { "addi", OP(14), OP_MASK, PPC, { RT, RA, SI } }, |
1576 | b9adb4a6 | bellard | { "cal", OP(14), OP_MASK, POWER, { RT, D, RA } }, |
1577 | b9adb4a6 | bellard | { "subi", OP(14), OP_MASK, PPC, { RT, RA, NSI } }, |
1578 | b9adb4a6 | bellard | { "la", OP(14), OP_MASK, PPC, { RT, D, RA } }, |
1579 | b9adb4a6 | bellard | |
1580 | b9adb4a6 | bellard | { "lis", OP(15), DRA_MASK, PPC, { RT, SISIGNOPT } }, |
1581 | b9adb4a6 | bellard | { "liu", OP(15), DRA_MASK, POWER, { RT, SISIGNOPT } }, |
1582 | b9adb4a6 | bellard | { "addis", OP(15), OP_MASK, PPC, { RT,RA,SISIGNOPT } }, |
1583 | b9adb4a6 | bellard | { "cau", OP(15), OP_MASK, POWER, { RT,RA,SISIGNOPT } }, |
1584 | b9adb4a6 | bellard | { "subis", OP(15), OP_MASK, PPC, { RT, RA, NSI } }, |
1585 | b9adb4a6 | bellard | |
1586 | b9adb4a6 | bellard | { "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDM } }, |
1587 | b9adb4a6 | bellard | { "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BDP } }, |
1588 | b9adb4a6 | bellard | { "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPC, { BD } }, |
1589 | b9adb4a6 | bellard | { "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, POWER, { BD } }, |
1590 | b9adb4a6 | bellard | { "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDM } }, |
1591 | b9adb4a6 | bellard | { "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BDP } }, |
1592 | b9adb4a6 | bellard | { "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPC, { BD } }, |
1593 | b9adb4a6 | bellard | { "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, POWER, { BD } }, |
1594 | b9adb4a6 | bellard | { "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, |
1595 | b9adb4a6 | bellard | { "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, |
1596 | b9adb4a6 | bellard | { "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPC, { BDA } }, |
1597 | b9adb4a6 | bellard | { "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, POWER, { BDA } }, |
1598 | b9adb4a6 | bellard | { "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, |
1599 | b9adb4a6 | bellard | { "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, |
1600 | b9adb4a6 | bellard | { "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPC, { BDA } }, |
1601 | b9adb4a6 | bellard | { "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, POWER, { BDA } }, |
1602 | b9adb4a6 | bellard | { "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDM } }, |
1603 | b9adb4a6 | bellard | { "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC, { BDP } }, |
1604 | b9adb4a6 | bellard | { "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, PPC|POWER, { BD } }, |
1605 | b9adb4a6 | bellard | { "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDM } }, |
1606 | b9adb4a6 | bellard | { "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC, { BDP } }, |
1607 | b9adb4a6 | bellard | { "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, PPC|POWER, { BD } }, |
1608 | b9adb4a6 | bellard | { "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDMA } }, |
1609 | b9adb4a6 | bellard | { "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC, { BDPA } }, |
1610 | b9adb4a6 | bellard | { "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, PPC|POWER, { BDA } }, |
1611 | b9adb4a6 | bellard | { "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDMA } }, |
1612 | b9adb4a6 | bellard | { "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC, { BDPA } }, |
1613 | b9adb4a6 | bellard | { "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, PPC|POWER, { BDA } }, |
1614 | b9adb4a6 | bellard | { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1615 | b9adb4a6 | bellard | { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1616 | b9adb4a6 | bellard | { "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1617 | b9adb4a6 | bellard | { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1618 | b9adb4a6 | bellard | { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1619 | b9adb4a6 | bellard | { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1620 | b9adb4a6 | bellard | { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1621 | b9adb4a6 | bellard | { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1622 | b9adb4a6 | bellard | { "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1623 | b9adb4a6 | bellard | { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1624 | b9adb4a6 | bellard | { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1625 | b9adb4a6 | bellard | { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1626 | b9adb4a6 | bellard | { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1627 | b9adb4a6 | bellard | { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1628 | b9adb4a6 | bellard | { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1629 | b9adb4a6 | bellard | { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1630 | b9adb4a6 | bellard | { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1631 | b9adb4a6 | bellard | { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1632 | b9adb4a6 | bellard | { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1633 | b9adb4a6 | bellard | { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1634 | b9adb4a6 | bellard | { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1635 | b9adb4a6 | bellard | { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1636 | b9adb4a6 | bellard | { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1637 | b9adb4a6 | bellard | { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1638 | b9adb4a6 | bellard | { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1639 | b9adb4a6 | bellard | { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1640 | b9adb4a6 | bellard | { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1641 | b9adb4a6 | bellard | { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1642 | b9adb4a6 | bellard | { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1643 | b9adb4a6 | bellard | { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1644 | b9adb4a6 | bellard | { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1645 | b9adb4a6 | bellard | { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1646 | b9adb4a6 | bellard | { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1647 | b9adb4a6 | bellard | { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1648 | b9adb4a6 | bellard | { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1649 | b9adb4a6 | bellard | { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1650 | b9adb4a6 | bellard | { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1651 | b9adb4a6 | bellard | { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1652 | b9adb4a6 | bellard | { "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1653 | b9adb4a6 | bellard | { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1654 | b9adb4a6 | bellard | { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1655 | b9adb4a6 | bellard | { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1656 | b9adb4a6 | bellard | { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1657 | b9adb4a6 | bellard | { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1658 | b9adb4a6 | bellard | { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1659 | b9adb4a6 | bellard | { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1660 | b9adb4a6 | bellard | { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1661 | b9adb4a6 | bellard | { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1662 | b9adb4a6 | bellard | { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1663 | b9adb4a6 | bellard | { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1664 | b9adb4a6 | bellard | { "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, |
1665 | b9adb4a6 | bellard | { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1666 | b9adb4a6 | bellard | { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1667 | b9adb4a6 | bellard | { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, |
1668 | b9adb4a6 | bellard | { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1669 | b9adb4a6 | bellard | { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1670 | b9adb4a6 | bellard | { "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, |
1671 | b9adb4a6 | bellard | { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1672 | b9adb4a6 | bellard | { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1673 | b9adb4a6 | bellard | { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, |
1674 | b9adb4a6 | bellard | { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1675 | b9adb4a6 | bellard | { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1676 | b9adb4a6 | bellard | { "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1677 | b9adb4a6 | bellard | { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1678 | b9adb4a6 | bellard | { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1679 | b9adb4a6 | bellard | { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1680 | b9adb4a6 | bellard | { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1681 | b9adb4a6 | bellard | { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1682 | b9adb4a6 | bellard | { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1683 | b9adb4a6 | bellard | { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1684 | b9adb4a6 | bellard | { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1685 | b9adb4a6 | bellard | { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1686 | b9adb4a6 | bellard | { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1687 | b9adb4a6 | bellard | { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1688 | b9adb4a6 | bellard | { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1689 | b9adb4a6 | bellard | { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1690 | b9adb4a6 | bellard | { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1691 | b9adb4a6 | bellard | { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1692 | b9adb4a6 | bellard | { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1693 | b9adb4a6 | bellard | { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1694 | b9adb4a6 | bellard | { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1695 | b9adb4a6 | bellard | { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1696 | b9adb4a6 | bellard | { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1697 | b9adb4a6 | bellard | { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1698 | b9adb4a6 | bellard | { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1699 | b9adb4a6 | bellard | { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1700 | b9adb4a6 | bellard | { "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1701 | b9adb4a6 | bellard | { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1702 | b9adb4a6 | bellard | { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1703 | b9adb4a6 | bellard | { "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1704 | b9adb4a6 | bellard | { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1705 | b9adb4a6 | bellard | { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1706 | b9adb4a6 | bellard | { "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1707 | b9adb4a6 | bellard | { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1708 | b9adb4a6 | bellard | { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1709 | b9adb4a6 | bellard | { "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1710 | b9adb4a6 | bellard | { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1711 | b9adb4a6 | bellard | { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1712 | b9adb4a6 | bellard | { "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1713 | b9adb4a6 | bellard | { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1714 | b9adb4a6 | bellard | { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1715 | b9adb4a6 | bellard | { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1716 | b9adb4a6 | bellard | { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1717 | b9adb4a6 | bellard | { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1718 | b9adb4a6 | bellard | { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1719 | b9adb4a6 | bellard | { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1720 | b9adb4a6 | bellard | { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1721 | b9adb4a6 | bellard | { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1722 | b9adb4a6 | bellard | { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1723 | b9adb4a6 | bellard | { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1724 | b9adb4a6 | bellard | { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1725 | b9adb4a6 | bellard | { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1726 | b9adb4a6 | bellard | { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1727 | b9adb4a6 | bellard | { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1728 | b9adb4a6 | bellard | { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1729 | b9adb4a6 | bellard | { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1730 | b9adb4a6 | bellard | { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1731 | b9adb4a6 | bellard | { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1732 | b9adb4a6 | bellard | { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1733 | b9adb4a6 | bellard | { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1734 | b9adb4a6 | bellard | { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1735 | b9adb4a6 | bellard | { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1736 | b9adb4a6 | bellard | { "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1737 | b9adb4a6 | bellard | { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1738 | b9adb4a6 | bellard | { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1739 | b9adb4a6 | bellard | { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC|POWER, { CR, BD } }, |
1740 | b9adb4a6 | bellard | { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1741 | b9adb4a6 | bellard | { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1742 | b9adb4a6 | bellard | { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1743 | b9adb4a6 | bellard | { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1744 | b9adb4a6 | bellard | { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1745 | b9adb4a6 | bellard | { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC|POWER, { CR, BDA } }, |
1746 | b9adb4a6 | bellard | { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDM } }, |
1747 | b9adb4a6 | bellard | { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BDP } }, |
1748 | b9adb4a6 | bellard | { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPC, { CR, BD } }, |
1749 | b9adb4a6 | bellard | { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDM } }, |
1750 | b9adb4a6 | bellard | { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BDP } }, |
1751 | b9adb4a6 | bellard | { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPC, { CR, BD } }, |
1752 | b9adb4a6 | bellard | { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1753 | b9adb4a6 | bellard | { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1754 | b9adb4a6 | bellard | { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPC, { CR, BDA } }, |
1755 | b9adb4a6 | bellard | { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDMA } }, |
1756 | b9adb4a6 | bellard | { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDPA } }, |
1757 | b9adb4a6 | bellard | { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPC, { CR, BDA } }, |
1758 | b9adb4a6 | bellard | { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, |
1759 | b9adb4a6 | bellard | { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, |
1760 | b9adb4a6 | bellard | { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPC, { BI, BD } }, |
1761 | b9adb4a6 | bellard | { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, |
1762 | b9adb4a6 | bellard | { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, |
1763 | b9adb4a6 | bellard | { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPC, { BI, BD } }, |
1764 | b9adb4a6 | bellard | { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, |
1765 | b9adb4a6 | bellard | { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, |
1766 | b9adb4a6 | bellard | { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, |
1767 | b9adb4a6 | bellard | { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, |
1768 | b9adb4a6 | bellard | { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, |
1769 | b9adb4a6 | bellard | { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, |
1770 | b9adb4a6 | bellard | { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, |
1771 | b9adb4a6 | bellard | { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, |
1772 | b9adb4a6 | bellard | { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPC, { BI, BD } }, |
1773 | b9adb4a6 | bellard | { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, |
1774 | b9adb4a6 | bellard | { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, |
1775 | b9adb4a6 | bellard | { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPC, { BI, BD } }, |
1776 | b9adb4a6 | bellard | { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, |
1777 | b9adb4a6 | bellard | { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, |
1778 | b9adb4a6 | bellard | { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, |
1779 | b9adb4a6 | bellard | { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, |
1780 | b9adb4a6 | bellard | { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, |
1781 | b9adb4a6 | bellard | { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, |
1782 | b9adb4a6 | bellard | { "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDM } }, |
1783 | b9adb4a6 | bellard | { "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BDP } }, |
1784 | b9adb4a6 | bellard | { "bt", BBO(16,BOT,0,0), BBOY_MASK, PPC, { BI, BD } }, |
1785 | b9adb4a6 | bellard | { "bbt", BBO(16,BOT,0,0), BBOY_MASK, POWER, { BI, BD } }, |
1786 | b9adb4a6 | bellard | { "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDM } }, |
1787 | b9adb4a6 | bellard | { "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BDP } }, |
1788 | b9adb4a6 | bellard | { "btl", BBO(16,BOT,0,1), BBOY_MASK, PPC, { BI, BD } }, |
1789 | b9adb4a6 | bellard | { "bbtl", BBO(16,BOT,0,1), BBOY_MASK, POWER, { BI, BD } }, |
1790 | b9adb4a6 | bellard | { "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, |
1791 | b9adb4a6 | bellard | { "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, |
1792 | b9adb4a6 | bellard | { "bta", BBO(16,BOT,1,0), BBOY_MASK, PPC, { BI, BDA } }, |
1793 | b9adb4a6 | bellard | { "bbta", BBO(16,BOT,1,0), BBOY_MASK, POWER, { BI, BDA } }, |
1794 | b9adb4a6 | bellard | { "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, |
1795 | b9adb4a6 | bellard | { "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, |
1796 | b9adb4a6 | bellard | { "btla", BBO(16,BOT,1,1), BBOY_MASK, PPC, { BI, BDA } }, |
1797 | b9adb4a6 | bellard | { "bbtla", BBO(16,BOT,1,1), BBOY_MASK, POWER, { BI, BDA } }, |
1798 | b9adb4a6 | bellard | { "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDM } }, |
1799 | b9adb4a6 | bellard | { "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BDP } }, |
1800 | b9adb4a6 | bellard | { "bf", BBO(16,BOF,0,0), BBOY_MASK, PPC, { BI, BD } }, |
1801 | b9adb4a6 | bellard | { "bbf", BBO(16,BOF,0,0), BBOY_MASK, POWER, { BI, BD } }, |
1802 | b9adb4a6 | bellard | { "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDM } }, |
1803 | b9adb4a6 | bellard | { "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BDP } }, |
1804 | b9adb4a6 | bellard | { "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPC, { BI, BD } }, |
1805 | b9adb4a6 | bellard | { "bbfl", BBO(16,BOF,0,1), BBOY_MASK, POWER, { BI, BD } }, |
1806 | b9adb4a6 | bellard | { "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, |
1807 | b9adb4a6 | bellard | { "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, |
1808 | b9adb4a6 | bellard | { "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPC, { BI, BDA } }, |
1809 | b9adb4a6 | bellard | { "bbfa", BBO(16,BOF,1,0), BBOY_MASK, POWER, { BI, BDA } }, |
1810 | b9adb4a6 | bellard | { "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, |
1811 | b9adb4a6 | bellard | { "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, |
1812 | b9adb4a6 | bellard | { "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPC, { BI, BDA } }, |
1813 | b9adb4a6 | bellard | { "bbfla", BBO(16,BOF,1,1), BBOY_MASK, POWER, { BI, BDA } }, |
1814 | b9adb4a6 | bellard | { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDM } }, |
1815 | b9adb4a6 | bellard | { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BDP } }, |
1816 | b9adb4a6 | bellard | { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPC, { BI, BD } }, |
1817 | b9adb4a6 | bellard | { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDM } }, |
1818 | b9adb4a6 | bellard | { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BDP } }, |
1819 | b9adb4a6 | bellard | { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPC, { BI, BD } }, |
1820 | b9adb4a6 | bellard | { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDMA } }, |
1821 | b9adb4a6 | bellard | { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDPA } }, |
1822 | b9adb4a6 | bellard | { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPC, { BI, BDA } }, |
1823 | b9adb4a6 | bellard | { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDMA } }, |
1824 | b9adb4a6 | bellard | { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDPA } }, |
1825 | b9adb4a6 | bellard | { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPC, { BI, BDA } }, |
1826 | b9adb4a6 | bellard | { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDM } }, |
1827 | b9adb4a6 | bellard | { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BDP } }, |
1828 | b9adb4a6 | bellard | { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPC, { BI, BD } }, |
1829 | b9adb4a6 | bellard | { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDM } }, |
1830 | b9adb4a6 | bellard | { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BDP } }, |
1831 | b9adb4a6 | bellard | { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPC, { BI, BD } }, |
1832 | b9adb4a6 | bellard | { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDMA } }, |
1833 | b9adb4a6 | bellard | { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDPA } }, |
1834 | b9adb4a6 | bellard | { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPC, { BI, BDA } }, |
1835 | b9adb4a6 | bellard | { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDMA } }, |
1836 | b9adb4a6 | bellard | { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDPA } }, |
1837 | b9adb4a6 | bellard | { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPC, { BI, BDA } }, |
1838 | b9adb4a6 | bellard | { "bc-", B(16,0,0), B_MASK, PPC, { BOE, BI, BDM } }, |
1839 | b9adb4a6 | bellard | { "bc+", B(16,0,0), B_MASK, PPC, { BOE, BI, BDP } }, |
1840 | b9adb4a6 | bellard | { "bc", B(16,0,0), B_MASK, PPC|POWER, { BO, BI, BD } }, |
1841 | b9adb4a6 | bellard | { "bcl-", B(16,0,1), B_MASK, PPC, { BOE, BI, BDM } }, |
1842 | b9adb4a6 | bellard | { "bcl+", B(16,0,1), B_MASK, PPC, { BOE, BI, BDP } }, |
1843 | b9adb4a6 | bellard | { "bcl", B(16,0,1), B_MASK, PPC|POWER, { BO, BI, BD } }, |
1844 | b9adb4a6 | bellard | { "bca-", B(16,1,0), B_MASK, PPC, { BOE, BI, BDMA } }, |
1845 | b9adb4a6 | bellard | { "bca+", B(16,1,0), B_MASK, PPC, { BOE, BI, BDPA } }, |
1846 | b9adb4a6 | bellard | { "bca", B(16,1,0), B_MASK, PPC|POWER, { BO, BI, BDA } }, |
1847 | b9adb4a6 | bellard | { "bcla-", B(16,1,1), B_MASK, PPC, { BOE, BI, BDMA } }, |
1848 | b9adb4a6 | bellard | { "bcla+", B(16,1,1), B_MASK, PPC, { BOE, BI, BDPA } }, |
1849 | b9adb4a6 | bellard | { "bcla", B(16,1,1), B_MASK, PPC|POWER, { BO, BI, BDA } }, |
1850 | b9adb4a6 | bellard | |
1851 | b9adb4a6 | bellard | { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } }, |
1852 | b9adb4a6 | bellard | { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } }, |
1853 | b9adb4a6 | bellard | { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } }, |
1854 | b9adb4a6 | bellard | { "svca", SC(17,1,0), SC_MASK, POWER, { SV } }, |
1855 | b9adb4a6 | bellard | { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, |
1856 | b9adb4a6 | bellard | |
1857 | b9adb4a6 | bellard | { "b", B(18,0,0), B_MASK, PPC|POWER, { LI } }, |
1858 | b9adb4a6 | bellard | { "bl", B(18,0,1), B_MASK, PPC|POWER, { LI } }, |
1859 | b9adb4a6 | bellard | { "ba", B(18,1,0), B_MASK, PPC|POWER, { LIA } }, |
1860 | b9adb4a6 | bellard | { "bla", B(18,1,1), B_MASK, PPC|POWER, { LIA } }, |
1861 | b9adb4a6 | bellard | |
1862 | b9adb4a6 | bellard | { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, |
1863 | b9adb4a6 | bellard | |
1864 | b9adb4a6 | bellard | { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPC, { 0 } }, |
1865 | b9adb4a6 | bellard | { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, POWER, { 0 } }, |
1866 | b9adb4a6 | bellard | { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPC, { 0 } }, |
1867 | b9adb4a6 | bellard | { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, POWER, { 0 } }, |
1868 | b9adb4a6 | bellard | { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, |
1869 | b9adb4a6 | bellard | { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, |
1870 | b9adb4a6 | bellard | { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, |
1871 | b9adb4a6 | bellard | { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, |
1872 | b9adb4a6 | bellard | { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, |
1873 | b9adb4a6 | bellard | { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, |
1874 | b9adb4a6 | bellard | { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, |
1875 | b9adb4a6 | bellard | { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPC, { 0 } }, |
1876 | b9adb4a6 | bellard | { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPC, { 0 } }, |
1877 | b9adb4a6 | bellard | { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, |
1878 | b9adb4a6 | bellard | { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPC, { 0 } }, |
1879 | b9adb4a6 | bellard | { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPC, { 0 } }, |
1880 | b9adb4a6 | bellard | { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1881 | b9adb4a6 | bellard | { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1882 | b9adb4a6 | bellard | { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1883 | b9adb4a6 | bellard | { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1884 | b9adb4a6 | bellard | { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1885 | b9adb4a6 | bellard | { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1886 | b9adb4a6 | bellard | { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1887 | b9adb4a6 | bellard | { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1888 | b9adb4a6 | bellard | { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1889 | b9adb4a6 | bellard | { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1890 | b9adb4a6 | bellard | { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1891 | b9adb4a6 | bellard | { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1892 | b9adb4a6 | bellard | { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1893 | b9adb4a6 | bellard | { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1894 | b9adb4a6 | bellard | { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1895 | b9adb4a6 | bellard | { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1896 | b9adb4a6 | bellard | { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1897 | b9adb4a6 | bellard | { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1898 | b9adb4a6 | bellard | { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1899 | b9adb4a6 | bellard | { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1900 | b9adb4a6 | bellard | { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1901 | b9adb4a6 | bellard | { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1902 | b9adb4a6 | bellard | { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1903 | b9adb4a6 | bellard | { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1904 | b9adb4a6 | bellard | { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1905 | b9adb4a6 | bellard | { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1906 | b9adb4a6 | bellard | { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1907 | b9adb4a6 | bellard | { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1908 | b9adb4a6 | bellard | { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1909 | b9adb4a6 | bellard | { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1910 | b9adb4a6 | bellard | { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1911 | b9adb4a6 | bellard | { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1912 | b9adb4a6 | bellard | { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1913 | b9adb4a6 | bellard | { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1914 | b9adb4a6 | bellard | { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1915 | b9adb4a6 | bellard | { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1916 | b9adb4a6 | bellard | { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1917 | b9adb4a6 | bellard | { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1918 | b9adb4a6 | bellard | { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1919 | b9adb4a6 | bellard | { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1920 | b9adb4a6 | bellard | { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1921 | b9adb4a6 | bellard | { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1922 | b9adb4a6 | bellard | { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1923 | b9adb4a6 | bellard | { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1924 | b9adb4a6 | bellard | { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1925 | b9adb4a6 | bellard | { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1926 | b9adb4a6 | bellard | { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1927 | b9adb4a6 | bellard | { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1928 | b9adb4a6 | bellard | { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1929 | b9adb4a6 | bellard | { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1930 | b9adb4a6 | bellard | { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1931 | b9adb4a6 | bellard | { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1932 | b9adb4a6 | bellard | { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1933 | b9adb4a6 | bellard | { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1934 | b9adb4a6 | bellard | { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1935 | b9adb4a6 | bellard | { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1936 | b9adb4a6 | bellard | { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1937 | b9adb4a6 | bellard | { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1938 | b9adb4a6 | bellard | { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1939 | b9adb4a6 | bellard | { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1940 | b9adb4a6 | bellard | { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1941 | b9adb4a6 | bellard | { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1942 | b9adb4a6 | bellard | { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1943 | b9adb4a6 | bellard | { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1944 | b9adb4a6 | bellard | { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1945 | b9adb4a6 | bellard | { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1946 | b9adb4a6 | bellard | { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1947 | b9adb4a6 | bellard | { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1948 | b9adb4a6 | bellard | { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1949 | b9adb4a6 | bellard | { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1950 | b9adb4a6 | bellard | { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1951 | b9adb4a6 | bellard | { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1952 | b9adb4a6 | bellard | { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1953 | b9adb4a6 | bellard | { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1954 | b9adb4a6 | bellard | { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1955 | b9adb4a6 | bellard | { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1956 | b9adb4a6 | bellard | { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1957 | b9adb4a6 | bellard | { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1958 | b9adb4a6 | bellard | { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1959 | b9adb4a6 | bellard | { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1960 | b9adb4a6 | bellard | { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1961 | b9adb4a6 | bellard | { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, POWER, { CR } }, |
1962 | b9adb4a6 | bellard | { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1963 | b9adb4a6 | bellard | { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1964 | b9adb4a6 | bellard | { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1965 | b9adb4a6 | bellard | { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, POWER, { CR } }, |
1966 | b9adb4a6 | bellard | { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1967 | b9adb4a6 | bellard | { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1968 | b9adb4a6 | bellard | { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPC, { CR } }, |
1969 | b9adb4a6 | bellard | { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1970 | b9adb4a6 | bellard | { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1971 | b9adb4a6 | bellard | { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPC, { CR } }, |
1972 | b9adb4a6 | bellard | { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, |
1973 | b9adb4a6 | bellard | { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPC, { BI } }, |
1974 | b9adb4a6 | bellard | { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPC, { BI } }, |
1975 | b9adb4a6 | bellard | { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, POWER, { BI } }, |
1976 | b9adb4a6 | bellard | { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, |
1977 | b9adb4a6 | bellard | { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPC, { BI } }, |
1978 | b9adb4a6 | bellard | { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPC, { BI } }, |
1979 | b9adb4a6 | bellard | { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, POWER, { BI } }, |
1980 | b9adb4a6 | bellard | { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, |
1981 | b9adb4a6 | bellard | { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPC, { BI } }, |
1982 | b9adb4a6 | bellard | { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPC, { BI } }, |
1983 | b9adb4a6 | bellard | { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, POWER, { BI } }, |
1984 | b9adb4a6 | bellard | { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, |
1985 | b9adb4a6 | bellard | { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPC, { BI } }, |
1986 | b9adb4a6 | bellard | { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPC, { BI } }, |
1987 | b9adb4a6 | bellard | { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, POWER, { BI } }, |
1988 | b9adb4a6 | bellard | { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, |
1989 | b9adb4a6 | bellard | { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPC, { BI } }, |
1990 | b9adb4a6 | bellard | { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPC, { BI } }, |
1991 | b9adb4a6 | bellard | { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, |
1992 | b9adb4a6 | bellard | { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPC, { BI } }, |
1993 | b9adb4a6 | bellard | { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPC, { BI } }, |
1994 | b9adb4a6 | bellard | { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, |
1995 | b9adb4a6 | bellard | { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPC, { BI } }, |
1996 | b9adb4a6 | bellard | { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPC, { BI } }, |
1997 | b9adb4a6 | bellard | { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, |
1998 | b9adb4a6 | bellard | { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPC, { BI } }, |
1999 | b9adb4a6 | bellard | { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPC, { BI } }, |
2000 | b9adb4a6 | bellard | { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, |
2001 | b9adb4a6 | bellard | { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPC, { BI } }, |
2002 | b9adb4a6 | bellard | { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPC, { BI } }, |
2003 | b9adb4a6 | bellard | { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, |
2004 | b9adb4a6 | bellard | { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPC, { BI } }, |
2005 | b9adb4a6 | bellard | { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPC, { BI } }, |
2006 | b9adb4a6 | bellard | { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, |
2007 | b9adb4a6 | bellard | { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPC, { BI } }, |
2008 | b9adb4a6 | bellard | { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPC, { BI } }, |
2009 | b9adb4a6 | bellard | { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, |
2010 | b9adb4a6 | bellard | { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPC, { BI } }, |
2011 | b9adb4a6 | bellard | { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPC, { BI } }, |
2012 | b9adb4a6 | bellard | { "bclr", XLLK(19,16,0), XLYBB_MASK, PPC, { BO, BI } }, |
2013 | b9adb4a6 | bellard | { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPC, { BO, BI } }, |
2014 | b9adb4a6 | bellard | { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPC, { BOE, BI } }, |
2015 | b9adb4a6 | bellard | { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPC, { BOE, BI } }, |
2016 | b9adb4a6 | bellard | { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPC, { BOE, BI } }, |
2017 | b9adb4a6 | bellard | { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPC, { BOE, BI } }, |
2018 | b9adb4a6 | bellard | { "bcr", XLLK(19,16,0), XLBB_MASK, POWER, { BO, BI } }, |
2019 | b9adb4a6 | bellard | { "bcrl", XLLK(19,16,1), XLBB_MASK, POWER, { BO, BI } }, |
2020 | b9adb4a6 | bellard | |
2021 | b9adb4a6 | bellard | { "crnot", XL(19,33), XL_MASK, PPC, { BT, BA, BBA } }, |
2022 | b9adb4a6 | bellard | { "crnor", XL(19,33), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2023 | b9adb4a6 | bellard | |
2024 | b9adb4a6 | bellard | { "rfi", XL(19,50), 0xffffffff, PPC|POWER, { 0 } }, |
2025 | b9adb4a6 | bellard | { "rfci", XL(19,51), 0xffffffff, PPC, { 0 } }, |
2026 | b9adb4a6 | bellard | |
2027 | b9adb4a6 | bellard | { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, |
2028 | b9adb4a6 | bellard | |
2029 | b9adb4a6 | bellard | { "crandc", XL(19,129), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2030 | b9adb4a6 | bellard | |
2031 | b9adb4a6 | bellard | { "isync", XL(19,150), 0xffffffff, PPC, { 0 } }, |
2032 | b9adb4a6 | bellard | { "ics", XL(19,150), 0xffffffff, POWER, { 0 } }, |
2033 | b9adb4a6 | bellard | |
2034 | b9adb4a6 | bellard | { "crclr", XL(19,193), XL_MASK, PPC, { BT, BAT, BBA } }, |
2035 | b9adb4a6 | bellard | { "crxor", XL(19,193), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2036 | b9adb4a6 | bellard | |
2037 | b9adb4a6 | bellard | { "crnand", XL(19,225), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2038 | b9adb4a6 | bellard | |
2039 | b9adb4a6 | bellard | { "crand", XL(19,257), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2040 | b9adb4a6 | bellard | |
2041 | b9adb4a6 | bellard | { "crset", XL(19,289), XL_MASK, PPC, { BT, BAT, BBA } }, |
2042 | b9adb4a6 | bellard | { "creqv", XL(19,289), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2043 | b9adb4a6 | bellard | |
2044 | b9adb4a6 | bellard | { "crorc", XL(19,417), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2045 | b9adb4a6 | bellard | |
2046 | b9adb4a6 | bellard | { "crmove", XL(19,449), XL_MASK, PPC, { BT, BA, BBA } }, |
2047 | b9adb4a6 | bellard | { "cror", XL(19,449), XL_MASK, PPC|POWER, { BT, BA, BB } }, |
2048 | b9adb4a6 | bellard | |
2049 | b9adb4a6 | bellard | { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, PPC|POWER, { 0 } }, |
2050 | b9adb4a6 | bellard | { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, PPC|POWER, { 0 } }, |
2051 | b9adb4a6 | bellard | { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2052 | b9adb4a6 | bellard | { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2053 | b9adb4a6 | bellard | { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2054 | b9adb4a6 | bellard | { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2055 | b9adb4a6 | bellard | { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2056 | b9adb4a6 | bellard | { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2057 | b9adb4a6 | bellard | { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2058 | b9adb4a6 | bellard | { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2059 | b9adb4a6 | bellard | { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2060 | b9adb4a6 | bellard | { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2061 | b9adb4a6 | bellard | { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2062 | b9adb4a6 | bellard | { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2063 | b9adb4a6 | bellard | { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2064 | b9adb4a6 | bellard | { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2065 | b9adb4a6 | bellard | { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2066 | b9adb4a6 | bellard | { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2067 | b9adb4a6 | bellard | { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2068 | b9adb4a6 | bellard | { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2069 | b9adb4a6 | bellard | { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2070 | b9adb4a6 | bellard | { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2071 | b9adb4a6 | bellard | { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2072 | b9adb4a6 | bellard | { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2073 | b9adb4a6 | bellard | { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2074 | b9adb4a6 | bellard | { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2075 | b9adb4a6 | bellard | { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2076 | b9adb4a6 | bellard | { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2077 | b9adb4a6 | bellard | { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2078 | b9adb4a6 | bellard | { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2079 | b9adb4a6 | bellard | { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2080 | b9adb4a6 | bellard | { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2081 | b9adb4a6 | bellard | { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2082 | b9adb4a6 | bellard | { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2083 | b9adb4a6 | bellard | { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2084 | b9adb4a6 | bellard | { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2085 | b9adb4a6 | bellard | { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2086 | b9adb4a6 | bellard | { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2087 | b9adb4a6 | bellard | { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2088 | b9adb4a6 | bellard | { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2089 | b9adb4a6 | bellard | { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2090 | b9adb4a6 | bellard | { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2091 | b9adb4a6 | bellard | { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2092 | b9adb4a6 | bellard | { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2093 | b9adb4a6 | bellard | { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2094 | b9adb4a6 | bellard | { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2095 | b9adb4a6 | bellard | { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2096 | b9adb4a6 | bellard | { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2097 | b9adb4a6 | bellard | { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2098 | b9adb4a6 | bellard | { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2099 | b9adb4a6 | bellard | { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2100 | b9adb4a6 | bellard | { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2101 | b9adb4a6 | bellard | { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2102 | b9adb4a6 | bellard | { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2103 | b9adb4a6 | bellard | { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2104 | b9adb4a6 | bellard | { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2105 | b9adb4a6 | bellard | { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2106 | b9adb4a6 | bellard | { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2107 | b9adb4a6 | bellard | { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2108 | b9adb4a6 | bellard | { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2109 | b9adb4a6 | bellard | { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2110 | b9adb4a6 | bellard | { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2111 | b9adb4a6 | bellard | { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2112 | b9adb4a6 | bellard | { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2113 | b9adb4a6 | bellard | { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2114 | b9adb4a6 | bellard | { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2115 | b9adb4a6 | bellard | { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2116 | b9adb4a6 | bellard | { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2117 | b9adb4a6 | bellard | { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2118 | b9adb4a6 | bellard | { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2119 | b9adb4a6 | bellard | { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPC, { CR } }, |
2120 | b9adb4a6 | bellard | { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2121 | b9adb4a6 | bellard | { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2122 | b9adb4a6 | bellard | { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPC, { CR } }, |
2123 | b9adb4a6 | bellard | { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, |
2124 | b9adb4a6 | bellard | { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPC, { BI } }, |
2125 | b9adb4a6 | bellard | { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPC, { BI } }, |
2126 | b9adb4a6 | bellard | { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, |
2127 | b9adb4a6 | bellard | { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPC, { BI } }, |
2128 | b9adb4a6 | bellard | { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPC, { BI } }, |
2129 | b9adb4a6 | bellard | { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, |
2130 | b9adb4a6 | bellard | { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPC, { BI } }, |
2131 | b9adb4a6 | bellard | { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPC, { BI } }, |
2132 | b9adb4a6 | bellard | { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, |
2133 | b9adb4a6 | bellard | { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPC, { BI } }, |
2134 | b9adb4a6 | bellard | { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPC, { BI } }, |
2135 | b9adb4a6 | bellard | { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPC, { BO, BI } }, |
2136 | b9adb4a6 | bellard | { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPC, { BOE, BI } }, |
2137 | b9adb4a6 | bellard | { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPC, { BOE, BI } }, |
2138 | b9adb4a6 | bellard | { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPC, { BO, BI } }, |
2139 | b9adb4a6 | bellard | { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPC, { BOE, BI } }, |
2140 | b9adb4a6 | bellard | { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPC, { BOE, BI } }, |
2141 | b9adb4a6 | bellard | { "bcc", XLLK(19,528,0), XLBB_MASK, POWER, { BO, BI } }, |
2142 | b9adb4a6 | bellard | { "bccl", XLLK(19,528,1), XLBB_MASK, POWER, { BO, BI } }, |
2143 | b9adb4a6 | bellard | |
2144 | b9adb4a6 | bellard | { "rlwimi", M(20,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, |
2145 | b9adb4a6 | bellard | { "rlimi", M(20,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, |
2146 | b9adb4a6 | bellard | |
2147 | b9adb4a6 | bellard | { "rlwimi.", M(20,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, |
2148 | b9adb4a6 | bellard | { "rlimi.", M(20,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, |
2149 | b9adb4a6 | bellard | |
2150 | b9adb4a6 | bellard | { "rotlwi", MME(21,31,0), MMBME_MASK, PPC, { RA, RS, SH } }, |
2151 | b9adb4a6 | bellard | { "clrlwi", MME(21,31,0), MSHME_MASK, PPC, { RA, RS, MB } }, |
2152 | b9adb4a6 | bellard | { "rlwinm", M(21,0), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, |
2153 | b9adb4a6 | bellard | { "rlinm", M(21,0), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, |
2154 | b9adb4a6 | bellard | { "rotlwi.", MME(21,31,1), MMBME_MASK, PPC, { RA,RS,SH } }, |
2155 | b9adb4a6 | bellard | { "clrlwi.", MME(21,31,1), MSHME_MASK, PPC, { RA, RS, MB } }, |
2156 | b9adb4a6 | bellard | { "rlwinm.", M(21,1), M_MASK, PPC, { RA,RS,SH,MBE,ME } }, |
2157 | b9adb4a6 | bellard | { "rlinm.", M(21,1), M_MASK, POWER, { RA,RS,SH,MBE,ME } }, |
2158 | b9adb4a6 | bellard | |
2159 | b9adb4a6 | bellard | { "rlmi", M(22,0), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, |
2160 | b9adb4a6 | bellard | { "rlmi.", M(22,1), M_MASK, POWER|M601, { RA,RS,RB,MBE,ME } }, |
2161 | b9adb4a6 | bellard | |
2162 | b9adb4a6 | bellard | { "rotlw", MME(23,31,0), MMBME_MASK, PPC, { RA, RS, RB } }, |
2163 | b9adb4a6 | bellard | { "rlwnm", M(23,0), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, |
2164 | b9adb4a6 | bellard | { "rlnm", M(23,0), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, |
2165 | b9adb4a6 | bellard | { "rotlw.", MME(23,31,1), MMBME_MASK, PPC, { RA, RS, RB } }, |
2166 | b9adb4a6 | bellard | { "rlwnm.", M(23,1), M_MASK, PPC, { RA,RS,RB,MBE,ME } }, |
2167 | b9adb4a6 | bellard | { "rlnm.", M(23,1), M_MASK, POWER, { RA,RS,RB,MBE,ME } }, |
2168 | b9adb4a6 | bellard | |
2169 | b9adb4a6 | bellard | { "nop", OP(24), 0xffffffff, PPC, { 0 } }, |
2170 | b9adb4a6 | bellard | { "ori", OP(24), OP_MASK, PPC, { RA, RS, UI } }, |
2171 | b9adb4a6 | bellard | { "oril", OP(24), OP_MASK, POWER, { RA, RS, UI } }, |
2172 | b9adb4a6 | bellard | |
2173 | b9adb4a6 | bellard | { "oris", OP(25), OP_MASK, PPC, { RA, RS, UI } }, |
2174 | b9adb4a6 | bellard | { "oriu", OP(25), OP_MASK, POWER, { RA, RS, UI } }, |
2175 | b9adb4a6 | bellard | |
2176 | b9adb4a6 | bellard | { "xori", OP(26), OP_MASK, PPC, { RA, RS, UI } }, |
2177 | b9adb4a6 | bellard | { "xoril", OP(26), OP_MASK, POWER, { RA, RS, UI } }, |
2178 | b9adb4a6 | bellard | |
2179 | b9adb4a6 | bellard | { "xoris", OP(27), OP_MASK, PPC, { RA, RS, UI } }, |
2180 | b9adb4a6 | bellard | { "xoriu", OP(27), OP_MASK, POWER, { RA, RS, UI } }, |
2181 | b9adb4a6 | bellard | |
2182 | b9adb4a6 | bellard | { "andi.", OP(28), OP_MASK, PPC, { RA, RS, UI } }, |
2183 | b9adb4a6 | bellard | { "andil.", OP(28), OP_MASK, POWER, { RA, RS, UI } }, |
2184 | b9adb4a6 | bellard | |
2185 | b9adb4a6 | bellard | { "andis.", OP(29), OP_MASK, PPC, { RA, RS, UI } }, |
2186 | b9adb4a6 | bellard | { "andiu.", OP(29), OP_MASK, POWER, { RA, RS, UI } }, |
2187 | b9adb4a6 | bellard | |
2188 | b9adb4a6 | bellard | { "rotldi", MD(30,0,0), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, |
2189 | b9adb4a6 | bellard | { "clrldi", MD(30,0,0), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, |
2190 | b9adb4a6 | bellard | { "rldicl", MD(30,0,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, |
2191 | b9adb4a6 | bellard | { "rotldi.", MD(30,0,1), MDMB_MASK, PPC|B64, { RA, RS, SH6 } }, |
2192 | b9adb4a6 | bellard | { "clrldi.", MD(30,0,1), MDSH_MASK, PPC|B64, { RA, RS, MB6 } }, |
2193 | b9adb4a6 | bellard | { "rldicl.", MD(30,0,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, |
2194 | b9adb4a6 | bellard | |
2195 | b9adb4a6 | bellard | { "rldicr", MD(30,1,0), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, |
2196 | b9adb4a6 | bellard | { "rldicr.", MD(30,1,1), MD_MASK, PPC|B64, { RA, RS, SH6, ME6 } }, |
2197 | b9adb4a6 | bellard | |
2198 | b9adb4a6 | bellard | { "rldic", MD(30,2,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, |
2199 | b9adb4a6 | bellard | { "rldic.", MD(30,2,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, |
2200 | b9adb4a6 | bellard | |
2201 | b9adb4a6 | bellard | { "rldimi", MD(30,3,0), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, |
2202 | b9adb4a6 | bellard | { "rldimi.", MD(30,3,1), MD_MASK, PPC|B64, { RA, RS, SH6, MB6 } }, |
2203 | b9adb4a6 | bellard | |
2204 | b9adb4a6 | bellard | { "rotld", MDS(30,8,0), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, |
2205 | b9adb4a6 | bellard | { "rldcl", MDS(30,8,0), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, |
2206 | b9adb4a6 | bellard | { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC|B64, { RA, RS, RB } }, |
2207 | b9adb4a6 | bellard | { "rldcl.", MDS(30,8,1), MDS_MASK, PPC|B64, { RA, RS, RB, MB6 } }, |
2208 | b9adb4a6 | bellard | |
2209 | b9adb4a6 | bellard | { "rldcr", MDS(30,9,0), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, |
2210 | b9adb4a6 | bellard | { "rldcr.", MDS(30,9,1), MDS_MASK, PPC|B64, { RA, RS, RB, ME6 } }, |
2211 | b9adb4a6 | bellard | |
2212 | b9adb4a6 | bellard | { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, |
2213 | b9adb4a6 | bellard | { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, |
2214 | b9adb4a6 | bellard | { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, |
2215 | b9adb4a6 | bellard | { "cmp", X(31,0), XCMPL_MASK, POWER, { BF, RA, RB } }, |
2216 | b9adb4a6 | bellard | |
2217 | b9adb4a6 | bellard | { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPC, { RA, RB } }, |
2218 | b9adb4a6 | bellard | { "tlgt", XTO(31,4,TOLGT), XTO_MASK, POWER, { RA, RB } }, |
2219 | b9adb4a6 | bellard | { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPC, { RA, RB } }, |
2220 | b9adb4a6 | bellard | { "tllt", XTO(31,4,TOLLT), XTO_MASK, POWER, { RA, RB } }, |
2221 | b9adb4a6 | bellard | { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPC, { RA, RB } }, |
2222 | b9adb4a6 | bellard | { "teq", XTO(31,4,TOEQ), XTO_MASK, POWER, { RA, RB } }, |
2223 | b9adb4a6 | bellard | { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPC, { RA, RB } }, |
2224 | b9adb4a6 | bellard | { "tlge", XTO(31,4,TOLGE), XTO_MASK, POWER, { RA, RB } }, |
2225 | b9adb4a6 | bellard | { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPC, { RA, RB } }, |
2226 | b9adb4a6 | bellard | { "tlnl", XTO(31,4,TOLNL), XTO_MASK, POWER, { RA, RB } }, |
2227 | b9adb4a6 | bellard | { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPC, { RA, RB } }, |
2228 | b9adb4a6 | bellard | { "tlle", XTO(31,4,TOLLE), XTO_MASK, POWER, { RA, RB } }, |
2229 | b9adb4a6 | bellard | { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPC, { RA, RB } }, |
2230 | b9adb4a6 | bellard | { "tlng", XTO(31,4,TOLNG), XTO_MASK, POWER, { RA, RB } }, |
2231 | b9adb4a6 | bellard | { "twgt", XTO(31,4,TOGT), XTO_MASK, PPC, { RA, RB } }, |
2232 | b9adb4a6 | bellard | { "tgt", XTO(31,4,TOGT), XTO_MASK, POWER, { RA, RB } }, |
2233 | b9adb4a6 | bellard | { "twge", XTO(31,4,TOGE), XTO_MASK, PPC, { RA, RB } }, |
2234 | b9adb4a6 | bellard | { "tge", XTO(31,4,TOGE), XTO_MASK, POWER, { RA, RB } }, |
2235 | b9adb4a6 | bellard | { "twnl", XTO(31,4,TONL), XTO_MASK, PPC, { RA, RB } }, |
2236 | b9adb4a6 | bellard | { "tnl", XTO(31,4,TONL), XTO_MASK, POWER, { RA, RB } }, |
2237 | b9adb4a6 | bellard | { "twlt", XTO(31,4,TOLT), XTO_MASK, PPC, { RA, RB } }, |
2238 | b9adb4a6 | bellard | { "tlt", XTO(31,4,TOLT), XTO_MASK, POWER, { RA, RB } }, |
2239 | b9adb4a6 | bellard | { "twle", XTO(31,4,TOLE), XTO_MASK, PPC, { RA, RB } }, |
2240 | b9adb4a6 | bellard | { "tle", XTO(31,4,TOLE), XTO_MASK, POWER, { RA, RB } }, |
2241 | b9adb4a6 | bellard | { "twng", XTO(31,4,TONG), XTO_MASK, PPC, { RA, RB } }, |
2242 | b9adb4a6 | bellard | { "tng", XTO(31,4,TONG), XTO_MASK, POWER, { RA, RB } }, |
2243 | b9adb4a6 | bellard | { "twne", XTO(31,4,TONE), XTO_MASK, PPC, { RA, RB } }, |
2244 | b9adb4a6 | bellard | { "tne", XTO(31,4,TONE), XTO_MASK, POWER, { RA, RB } }, |
2245 | b9adb4a6 | bellard | { "trap", XTO(31,4,TOU), 0xffffffff, PPC, { 0 } }, |
2246 | b9adb4a6 | bellard | { "tw", X(31,4), X_MASK, PPC, { TO, RA, RB } }, |
2247 | b9adb4a6 | bellard | { "t", X(31,4), X_MASK, POWER, { TO, RA, RB } }, |
2248 | b9adb4a6 | bellard | |
2249 | b9adb4a6 | bellard | { "subfc", XO(31,8,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2250 | b9adb4a6 | bellard | { "sf", XO(31,8,0,0), XO_MASK, POWER, { RT, RA, RB } }, |
2251 | b9adb4a6 | bellard | { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
2252 | b9adb4a6 | bellard | { "subfc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2253 | b9adb4a6 | bellard | { "sf.", XO(31,8,0,1), XO_MASK, POWER, { RT, RA, RB } }, |
2254 | b9adb4a6 | bellard | { "subc.", XO(31,8,0,1), XO_MASK, PPC, { RT, RB, RA } }, |
2255 | b9adb4a6 | bellard | { "subfco", XO(31,8,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2256 | b9adb4a6 | bellard | { "sfo", XO(31,8,1,0), XO_MASK, POWER, { RT, RA, RB } }, |
2257 | b9adb4a6 | bellard | { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
2258 | b9adb4a6 | bellard | { "subfco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2259 | b9adb4a6 | bellard | { "sfo.", XO(31,8,1,1), XO_MASK, POWER, { RT, RA, RB } }, |
2260 | b9adb4a6 | bellard | { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
2261 | b9adb4a6 | bellard | |
2262 | b9adb4a6 | bellard | { "mulhdu", XO(31,9,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2263 | b9adb4a6 | bellard | { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2264 | b9adb4a6 | bellard | |
2265 | b9adb4a6 | bellard | { "addc", XO(31,10,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2266 | b9adb4a6 | bellard | { "a", XO(31,10,0,0), XO_MASK, POWER, { RT, RA, RB } }, |
2267 | b9adb4a6 | bellard | { "addc.", XO(31,10,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2268 | b9adb4a6 | bellard | { "a.", XO(31,10,0,1), XO_MASK, POWER, { RT, RA, RB } }, |
2269 | b9adb4a6 | bellard | { "addco", XO(31,10,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2270 | b9adb4a6 | bellard | { "ao", XO(31,10,1,0), XO_MASK, POWER, { RT, RA, RB } }, |
2271 | b9adb4a6 | bellard | { "addco.", XO(31,10,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2272 | b9adb4a6 | bellard | { "ao.", XO(31,10,1,1), XO_MASK, POWER, { RT, RA, RB } }, |
2273 | b9adb4a6 | bellard | |
2274 | b9adb4a6 | bellard | { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2275 | b9adb4a6 | bellard | { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2276 | b9adb4a6 | bellard | |
2277 | b9adb4a6 | bellard | { "mfcr", X(31,19), XRARB_MASK, POWER|PPC, { RT } }, |
2278 | b9adb4a6 | bellard | |
2279 | b9adb4a6 | bellard | { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, |
2280 | b9adb4a6 | bellard | |
2281 | b9adb4a6 | bellard | { "ldx", X(31,21), X_MASK, PPC|B64, { RT, RA, RB } }, |
2282 | b9adb4a6 | bellard | |
2283 | b9adb4a6 | bellard | { "lwzx", X(31,23), X_MASK, PPC, { RT, RA, RB } }, |
2284 | b9adb4a6 | bellard | { "lx", X(31,23), X_MASK, POWER, { RT, RA, RB } }, |
2285 | b9adb4a6 | bellard | |
2286 | b9adb4a6 | bellard | { "slw", XRC(31,24,0), X_MASK, PPC, { RA, RS, RB } }, |
2287 | b9adb4a6 | bellard | { "sl", XRC(31,24,0), X_MASK, POWER, { RA, RS, RB } }, |
2288 | b9adb4a6 | bellard | { "slw.", XRC(31,24,1), X_MASK, PPC, { RA, RS, RB } }, |
2289 | b9adb4a6 | bellard | { "sl.", XRC(31,24,1), X_MASK, POWER, { RA, RS, RB } }, |
2290 | b9adb4a6 | bellard | |
2291 | b9adb4a6 | bellard | { "cntlzw", XRC(31,26,0), XRB_MASK, PPC, { RA, RS } }, |
2292 | b9adb4a6 | bellard | { "cntlz", XRC(31,26,0), XRB_MASK, POWER, { RA, RS } }, |
2293 | b9adb4a6 | bellard | { "cntlzw.", XRC(31,26,1), XRB_MASK, PPC, { RA, RS } }, |
2294 | b9adb4a6 | bellard | { "cntlz.", XRC(31,26,1), XRB_MASK, POWER, { RA, RS } }, |
2295 | b9adb4a6 | bellard | |
2296 | b9adb4a6 | bellard | { "sld", XRC(31,27,0), X_MASK, PPC|B64, { RA, RS, RB } }, |
2297 | b9adb4a6 | bellard | { "sld.", XRC(31,27,1), X_MASK, PPC|B64, { RA, RS, RB } }, |
2298 | b9adb4a6 | bellard | |
2299 | b9adb4a6 | bellard | { "and", XRC(31,28,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2300 | b9adb4a6 | bellard | { "and.", XRC(31,28,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2301 | b9adb4a6 | bellard | |
2302 | b9adb4a6 | bellard | { "maskg", XRC(31,29,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2303 | b9adb4a6 | bellard | { "maskg.", XRC(31,29,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2304 | b9adb4a6 | bellard | |
2305 | b9adb4a6 | bellard | { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPC, { OBF, RA, RB } }, |
2306 | b9adb4a6 | bellard | { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC|B64, { OBF, RA, RB } }, |
2307 | b9adb4a6 | bellard | { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, |
2308 | b9adb4a6 | bellard | { "cmpl", X(31,32), XCMPL_MASK, POWER, { BF, RA, RB } }, |
2309 | b9adb4a6 | bellard | |
2310 | b9adb4a6 | bellard | { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2311 | b9adb4a6 | bellard | { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, |
2312 | b9adb4a6 | bellard | { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2313 | b9adb4a6 | bellard | { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, |
2314 | b9adb4a6 | bellard | { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2315 | b9adb4a6 | bellard | { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, |
2316 | b9adb4a6 | bellard | { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2317 | b9adb4a6 | bellard | { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, |
2318 | b9adb4a6 | bellard | |
2319 | b9adb4a6 | bellard | { "ldux", X(31,53), X_MASK, PPC|B64, { RT, RAL, RB } }, |
2320 | b9adb4a6 | bellard | |
2321 | b9adb4a6 | bellard | { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, |
2322 | b9adb4a6 | bellard | |
2323 | b9adb4a6 | bellard | { "lwzux", X(31,55), X_MASK, PPC, { RT, RAL, RB } }, |
2324 | b9adb4a6 | bellard | { "lux", X(31,55), X_MASK, POWER, { RT, RA, RB } }, |
2325 | b9adb4a6 | bellard | |
2326 | b9adb4a6 | bellard | { "cntlzd", XRC(31,58,0), XRB_MASK, PPC|B64, { RA, RS } }, |
2327 | b9adb4a6 | bellard | { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC|B64, { RA, RS } }, |
2328 | b9adb4a6 | bellard | |
2329 | b9adb4a6 | bellard | { "andc", XRC(31,60,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2330 | b9adb4a6 | bellard | { "andc.", XRC(31,60,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2331 | b9adb4a6 | bellard | |
2332 | b9adb4a6 | bellard | { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC|B64, { RA, RB } }, |
2333 | b9adb4a6 | bellard | { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC|B64, { RA, RB } }, |
2334 | b9adb4a6 | bellard | { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC|B64, { RA, RB } }, |
2335 | b9adb4a6 | bellard | { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC|B64, { RA, RB } }, |
2336 | b9adb4a6 | bellard | { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC|B64, { RA, RB } }, |
2337 | b9adb4a6 | bellard | { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC|B64, { RA, RB } }, |
2338 | b9adb4a6 | bellard | { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC|B64, { RA, RB } }, |
2339 | b9adb4a6 | bellard | { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC|B64, { RA, RB } }, |
2340 | b9adb4a6 | bellard | { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC|B64, { RA, RB } }, |
2341 | b9adb4a6 | bellard | { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC|B64, { RA, RB } }, |
2342 | b9adb4a6 | bellard | { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC|B64, { RA, RB } }, |
2343 | b9adb4a6 | bellard | { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC|B64, { RA, RB } }, |
2344 | b9adb4a6 | bellard | { "tdng", XTO(31,68,TONG), XTO_MASK, PPC|B64, { RA, RB } }, |
2345 | b9adb4a6 | bellard | { "tdne", XTO(31,68,TONE), XTO_MASK, PPC|B64, { RA, RB } }, |
2346 | b9adb4a6 | bellard | { "td", X(31,68), X_MASK, PPC|B64, { TO, RA, RB } }, |
2347 | b9adb4a6 | bellard | |
2348 | b9adb4a6 | bellard | { "mulhd", XO(31,73,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2349 | b9adb4a6 | bellard | { "mulhd.", XO(31,73,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2350 | b9adb4a6 | bellard | |
2351 | b9adb4a6 | bellard | { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2352 | b9adb4a6 | bellard | { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2353 | b9adb4a6 | bellard | |
2354 | b9adb4a6 | bellard | { "mfmsr", X(31,83), XRARB_MASK, PPC|POWER, { RT } }, |
2355 | b9adb4a6 | bellard | |
2356 | b9adb4a6 | bellard | { "ldarx", X(31,84), X_MASK, PPC|B64, { RT, RA, RB } }, |
2357 | b9adb4a6 | bellard | |
2358 | b9adb4a6 | bellard | { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, |
2359 | b9adb4a6 | bellard | |
2360 | b9adb4a6 | bellard | { "lbzx", X(31,87), X_MASK, PPC|POWER, { RT, RA, RB } }, |
2361 | b9adb4a6 | bellard | |
2362 | b9adb4a6 | bellard | { "neg", XO(31,104,0,0), XORB_MASK, PPC|POWER, { RT, RA } }, |
2363 | b9adb4a6 | bellard | { "neg.", XO(31,104,0,1), XORB_MASK, PPC|POWER, { RT, RA } }, |
2364 | b9adb4a6 | bellard | { "nego", XO(31,104,1,0), XORB_MASK, PPC|POWER, { RT, RA } }, |
2365 | b9adb4a6 | bellard | { "nego.", XO(31,104,1,1), XORB_MASK, PPC|POWER, { RT, RA } }, |
2366 | b9adb4a6 | bellard | |
2367 | b9adb4a6 | bellard | { "mul", XO(31,107,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2368 | b9adb4a6 | bellard | { "mul.", XO(31,107,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2369 | b9adb4a6 | bellard | { "mulo", XO(31,107,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2370 | b9adb4a6 | bellard | { "mulo.", XO(31,107,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2371 | b9adb4a6 | bellard | |
2372 | b9adb4a6 | bellard | { "clf", X(31,118), XRB_MASK, POWER, { RT, RA } }, |
2373 | b9adb4a6 | bellard | |
2374 | b9adb4a6 | bellard | { "lbzux", X(31,119), X_MASK, PPC|POWER, { RT, RAL, RB } }, |
2375 | b9adb4a6 | bellard | |
2376 | b9adb4a6 | bellard | { "not", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, |
2377 | b9adb4a6 | bellard | { "nor", XRC(31,124,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2378 | b9adb4a6 | bellard | { "not.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, |
2379 | b9adb4a6 | bellard | { "nor.", XRC(31,124,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2380 | b9adb4a6 | bellard | |
2381 | b9adb4a6 | bellard | { "subfe", XO(31,136,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2382 | b9adb4a6 | bellard | { "sfe", XO(31,136,0,0), XO_MASK, POWER, { RT, RA, RB } }, |
2383 | b9adb4a6 | bellard | { "subfe.", XO(31,136,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2384 | b9adb4a6 | bellard | { "sfe.", XO(31,136,0,1), XO_MASK, POWER, { RT, RA, RB } }, |
2385 | b9adb4a6 | bellard | { "subfeo", XO(31,136,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2386 | b9adb4a6 | bellard | { "sfeo", XO(31,136,1,0), XO_MASK, POWER, { RT, RA, RB } }, |
2387 | b9adb4a6 | bellard | { "subfeo.", XO(31,136,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2388 | b9adb4a6 | bellard | { "sfeo.", XO(31,136,1,1), XO_MASK, POWER, { RT, RA, RB } }, |
2389 | b9adb4a6 | bellard | |
2390 | b9adb4a6 | bellard | { "adde", XO(31,138,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2391 | b9adb4a6 | bellard | { "ae", XO(31,138,0,0), XO_MASK, POWER, { RT, RA, RB } }, |
2392 | b9adb4a6 | bellard | { "adde.", XO(31,138,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2393 | b9adb4a6 | bellard | { "ae.", XO(31,138,0,1), XO_MASK, POWER, { RT, RA, RB } }, |
2394 | b9adb4a6 | bellard | { "addeo", XO(31,138,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2395 | b9adb4a6 | bellard | { "aeo", XO(31,138,1,0), XO_MASK, POWER, { RT, RA, RB } }, |
2396 | b9adb4a6 | bellard | { "addeo.", XO(31,138,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2397 | b9adb4a6 | bellard | { "aeo.", XO(31,138,1,1), XO_MASK, POWER, { RT, RA, RB } }, |
2398 | b9adb4a6 | bellard | |
2399 | b9adb4a6 | bellard | { "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, PPC|POWER, { RS }}, |
2400 | b9adb4a6 | bellard | { "mtcrf", X(31,144), XFXFXM_MASK, PPC|POWER, { FXM, RS } }, |
2401 | b9adb4a6 | bellard | |
2402 | b9adb4a6 | bellard | { "mtmsr", X(31,146), XRARB_MASK, PPC|POWER, { RS } }, |
2403 | b9adb4a6 | bellard | |
2404 | b9adb4a6 | bellard | { "stdx", X(31,149), X_MASK, PPC|B64, { RS, RA, RB } }, |
2405 | b9adb4a6 | bellard | |
2406 | b9adb4a6 | bellard | { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, |
2407 | b9adb4a6 | bellard | |
2408 | b9adb4a6 | bellard | { "stwx", X(31,151), X_MASK, PPC, { RS, RA, RB } }, |
2409 | b9adb4a6 | bellard | { "stx", X(31,151), X_MASK, POWER, { RS, RA, RB } }, |
2410 | b9adb4a6 | bellard | |
2411 | b9adb4a6 | bellard | { "slq", XRC(31,152,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2412 | b9adb4a6 | bellard | { "slq.", XRC(31,152,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2413 | b9adb4a6 | bellard | |
2414 | b9adb4a6 | bellard | { "sle", XRC(31,153,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2415 | b9adb4a6 | bellard | { "sle.", XRC(31,153,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2416 | b9adb4a6 | bellard | |
2417 | b9adb4a6 | bellard | { "stdux", X(31,181), X_MASK, PPC|B64, { RS, RAS, RB } }, |
2418 | b9adb4a6 | bellard | |
2419 | b9adb4a6 | bellard | { "stwux", X(31,183), X_MASK, PPC, { RS, RAS, RB } }, |
2420 | b9adb4a6 | bellard | { "stux", X(31,183), X_MASK, POWER, { RS, RA, RB } }, |
2421 | b9adb4a6 | bellard | |
2422 | b9adb4a6 | bellard | { "sliq", XRC(31,184,0), X_MASK, POWER|M601, { RA, RS, SH } }, |
2423 | b9adb4a6 | bellard | { "sliq.", XRC(31,184,1), X_MASK, POWER|M601, { RA, RS, SH } }, |
2424 | b9adb4a6 | bellard | |
2425 | b9adb4a6 | bellard | { "subfze", XO(31,200,0,0), XORB_MASK, PPC, { RT, RA } }, |
2426 | b9adb4a6 | bellard | { "sfze", XO(31,200,0,0), XORB_MASK, POWER, { RT, RA } }, |
2427 | b9adb4a6 | bellard | { "subfze.", XO(31,200,0,1), XORB_MASK, PPC, { RT, RA } }, |
2428 | b9adb4a6 | bellard | { "sfze.", XO(31,200,0,1), XORB_MASK, POWER, { RT, RA } }, |
2429 | b9adb4a6 | bellard | { "subfzeo", XO(31,200,1,0), XORB_MASK, PPC, { RT, RA } }, |
2430 | b9adb4a6 | bellard | { "sfzeo", XO(31,200,1,0), XORB_MASK, POWER, { RT, RA } }, |
2431 | b9adb4a6 | bellard | { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPC, { RT, RA } }, |
2432 | b9adb4a6 | bellard | { "sfzeo.", XO(31,200,1,1), XORB_MASK, POWER, { RT, RA } }, |
2433 | b9adb4a6 | bellard | |
2434 | b9adb4a6 | bellard | { "addze", XO(31,202,0,0), XORB_MASK, PPC, { RT, RA } }, |
2435 | b9adb4a6 | bellard | { "aze", XO(31,202,0,0), XORB_MASK, POWER, { RT, RA } }, |
2436 | b9adb4a6 | bellard | { "addze.", XO(31,202,0,1), XORB_MASK, PPC, { RT, RA } }, |
2437 | b9adb4a6 | bellard | { "aze.", XO(31,202,0,1), XORB_MASK, POWER, { RT, RA } }, |
2438 | b9adb4a6 | bellard | { "addzeo", XO(31,202,1,0), XORB_MASK, PPC, { RT, RA } }, |
2439 | b9adb4a6 | bellard | { "azeo", XO(31,202,1,0), XORB_MASK, POWER, { RT, RA } }, |
2440 | b9adb4a6 | bellard | { "addzeo.", XO(31,202,1,1), XORB_MASK, PPC, { RT, RA } }, |
2441 | b9adb4a6 | bellard | { "azeo.", XO(31,202,1,1), XORB_MASK, POWER, { RT, RA } }, |
2442 | b9adb4a6 | bellard | |
2443 | b9adb4a6 | bellard | { "mtsr", X(31,210), XRB_MASK|(1<<20), PPC|POWER|B32, { SR, RS } }, |
2444 | b9adb4a6 | bellard | |
2445 | b9adb4a6 | bellard | { "stdcx.", XRC(31,214,1), X_MASK, PPC|B64, { RS, RA, RB } }, |
2446 | b9adb4a6 | bellard | |
2447 | b9adb4a6 | bellard | { "stbx", X(31,215), X_MASK, PPC|POWER, { RS, RA, RB } }, |
2448 | b9adb4a6 | bellard | |
2449 | b9adb4a6 | bellard | { "sllq", XRC(31,216,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2450 | b9adb4a6 | bellard | { "sllq.", XRC(31,216,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2451 | b9adb4a6 | bellard | |
2452 | b9adb4a6 | bellard | { "sleq", XRC(31,217,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2453 | b9adb4a6 | bellard | { "sleq.", XRC(31,217,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2454 | b9adb4a6 | bellard | |
2455 | b9adb4a6 | bellard | { "subfme", XO(31,232,0,0), XORB_MASK, PPC, { RT, RA } }, |
2456 | b9adb4a6 | bellard | { "sfme", XO(31,232,0,0), XORB_MASK, POWER, { RT, RA } }, |
2457 | b9adb4a6 | bellard | { "subfme.", XO(31,232,0,1), XORB_MASK, PPC, { RT, RA } }, |
2458 | b9adb4a6 | bellard | { "sfme.", XO(31,232,0,1), XORB_MASK, POWER, { RT, RA } }, |
2459 | b9adb4a6 | bellard | { "subfmeo", XO(31,232,1,0), XORB_MASK, PPC, { RT, RA } }, |
2460 | b9adb4a6 | bellard | { "sfmeo", XO(31,232,1,0), XORB_MASK, POWER, { RT, RA } }, |
2461 | b9adb4a6 | bellard | { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPC, { RT, RA } }, |
2462 | b9adb4a6 | bellard | { "sfmeo.", XO(31,232,1,1), XORB_MASK, POWER, { RT, RA } }, |
2463 | b9adb4a6 | bellard | |
2464 | b9adb4a6 | bellard | { "mulld", XO(31,233,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2465 | b9adb4a6 | bellard | { "mulld.", XO(31,233,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2466 | b9adb4a6 | bellard | { "mulldo", XO(31,233,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2467 | b9adb4a6 | bellard | { "mulldo.", XO(31,233,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2468 | b9adb4a6 | bellard | |
2469 | b9adb4a6 | bellard | { "addme", XO(31,234,0,0), XORB_MASK, PPC, { RT, RA } }, |
2470 | b9adb4a6 | bellard | { "ame", XO(31,234,0,0), XORB_MASK, POWER, { RT, RA } }, |
2471 | b9adb4a6 | bellard | { "addme.", XO(31,234,0,1), XORB_MASK, PPC, { RT, RA } }, |
2472 | b9adb4a6 | bellard | { "ame.", XO(31,234,0,1), XORB_MASK, POWER, { RT, RA } }, |
2473 | b9adb4a6 | bellard | { "addmeo", XO(31,234,1,0), XORB_MASK, PPC, { RT, RA } }, |
2474 | b9adb4a6 | bellard | { "ameo", XO(31,234,1,0), XORB_MASK, POWER, { RT, RA } }, |
2475 | b9adb4a6 | bellard | { "addmeo.", XO(31,234,1,1), XORB_MASK, PPC, { RT, RA } }, |
2476 | b9adb4a6 | bellard | { "ameo.", XO(31,234,1,1), XORB_MASK, POWER, { RT, RA } }, |
2477 | b9adb4a6 | bellard | |
2478 | b9adb4a6 | bellard | { "mullw", XO(31,235,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2479 | b9adb4a6 | bellard | { "muls", XO(31,235,0,0), XO_MASK, POWER, { RT, RA, RB } }, |
2480 | b9adb4a6 | bellard | { "mullw.", XO(31,235,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2481 | b9adb4a6 | bellard | { "muls.", XO(31,235,0,1), XO_MASK, POWER, { RT, RA, RB } }, |
2482 | b9adb4a6 | bellard | { "mullwo", XO(31,235,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2483 | b9adb4a6 | bellard | { "mulso", XO(31,235,1,0), XO_MASK, POWER, { RT, RA, RB } }, |
2484 | b9adb4a6 | bellard | { "mullwo.", XO(31,235,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2485 | b9adb4a6 | bellard | { "mulso.", XO(31,235,1,1), XO_MASK, POWER, { RT, RA, RB } }, |
2486 | b9adb4a6 | bellard | |
2487 | b9adb4a6 | bellard | { "mtsrin", X(31,242), XRA_MASK, PPC|B32, { RS, RB } }, |
2488 | b9adb4a6 | bellard | { "mtsri", X(31,242), XRA_MASK, POWER|B32, { RS, RB } }, |
2489 | b9adb4a6 | bellard | |
2490 | b9adb4a6 | bellard | { "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } }, |
2491 | b9adb4a6 | bellard | |
2492 | b9adb4a6 | bellard | { "stbux", X(31,247), X_MASK, PPC|POWER, { RS, RAS, RB } }, |
2493 | b9adb4a6 | bellard | |
2494 | b9adb4a6 | bellard | { "slliq", XRC(31,248,0), X_MASK, POWER|M601, { RA, RS, SH } }, |
2495 | b9adb4a6 | bellard | { "slliq.", XRC(31,248,1), X_MASK, POWER|M601, { RA, RS, SH } }, |
2496 | b9adb4a6 | bellard | |
2497 | b9adb4a6 | bellard | { "doz", XO(31,264,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2498 | b9adb4a6 | bellard | { "doz.", XO(31,264,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2499 | b9adb4a6 | bellard | { "dozo", XO(31,264,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2500 | b9adb4a6 | bellard | { "dozo.", XO(31,264,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2501 | b9adb4a6 | bellard | |
2502 | b9adb4a6 | bellard | { "add", XO(31,266,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2503 | b9adb4a6 | bellard | { "cax", XO(31,266,0,0), XO_MASK, POWER, { RT, RA, RB } }, |
2504 | b9adb4a6 | bellard | { "add.", XO(31,266,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2505 | b9adb4a6 | bellard | { "cax.", XO(31,266,0,1), XO_MASK, POWER, { RT, RA, RB } }, |
2506 | b9adb4a6 | bellard | { "addo", XO(31,266,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2507 | b9adb4a6 | bellard | { "caxo", XO(31,266,1,0), XO_MASK, POWER, { RT, RA, RB } }, |
2508 | b9adb4a6 | bellard | { "addo.", XO(31,266,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2509 | b9adb4a6 | bellard | { "caxo.", XO(31,266,1,1), XO_MASK, POWER, { RT, RA, RB } }, |
2510 | b9adb4a6 | bellard | |
2511 | b9adb4a6 | bellard | { "lscbx", XRC(31,277,0), X_MASK, POWER|M601, { RT, RA, RB } }, |
2512 | b9adb4a6 | bellard | { "lscbx.", XRC(31,277,1), X_MASK, POWER|M601, { RT, RA, RB } }, |
2513 | b9adb4a6 | bellard | |
2514 | b9adb4a6 | bellard | { "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } }, |
2515 | b9adb4a6 | bellard | |
2516 | b9adb4a6 | bellard | { "lhzx", X(31,279), X_MASK, PPC|POWER, { RT, RA, RB } }, |
2517 | b9adb4a6 | bellard | |
2518 | b9adb4a6 | bellard | { "icbt", X(31,262), XRT_MASK, PPC, { RA, RB } }, |
2519 | b9adb4a6 | bellard | |
2520 | b9adb4a6 | bellard | { "eqv", XRC(31,284,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2521 | b9adb4a6 | bellard | { "eqv.", XRC(31,284,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2522 | b9adb4a6 | bellard | |
2523 | b9adb4a6 | bellard | { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } }, |
2524 | b9adb4a6 | bellard | { "tlbi", X(31,306), XRTRA_MASK, POWER, { RB } }, |
2525 | b9adb4a6 | bellard | |
2526 | b9adb4a6 | bellard | { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, |
2527 | b9adb4a6 | bellard | |
2528 | b9adb4a6 | bellard | { "lhzux", X(31,311), X_MASK, PPC|POWER, { RT, RAL, RB } }, |
2529 | b9adb4a6 | bellard | |
2530 | b9adb4a6 | bellard | { "xor", XRC(31,316,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2531 | b9adb4a6 | bellard | { "xor.", XRC(31,316,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2532 | b9adb4a6 | bellard | |
2533 | b9adb4a6 | bellard | { "mfdcr", X(31,323), X_MASK, PPC, { RT, SPR } }, |
2534 | b9adb4a6 | bellard | |
2535 | b9adb4a6 | bellard | { "div", XO(31,331,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2536 | b9adb4a6 | bellard | { "div.", XO(31,331,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2537 | b9adb4a6 | bellard | { "divo", XO(31,331,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2538 | b9adb4a6 | bellard | { "divo.", XO(31,331,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2539 | b9adb4a6 | bellard | |
2540 | b9adb4a6 | bellard | { "mfmq", XSPR(31,339,0), XSPR_MASK, POWER|M601, { RT } }, |
2541 | b9adb4a6 | bellard | { "mfxer", XSPR(31,339,1), XSPR_MASK, PPC|POWER, { RT } }, |
2542 | b9adb4a6 | bellard | { "mfrtcu", XSPR(31,339,4), XSPR_MASK, PPC|POWER, { RT } }, |
2543 | b9adb4a6 | bellard | { "mfrtcl", XSPR(31,339,5), XSPR_MASK, PPC|POWER, { RT } }, |
2544 | b9adb4a6 | bellard | { "mfdec", XSPR(31,339,6), XSPR_MASK, POWER|M601, { RT } }, |
2545 | b9adb4a6 | bellard | { "mflr", XSPR(31,339,8), XSPR_MASK, PPC|POWER, { RT } }, |
2546 | b9adb4a6 | bellard | { "mfctr", XSPR(31,339,9), XSPR_MASK, PPC|POWER, { RT } }, |
2547 | b9adb4a6 | bellard | { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, |
2548 | b9adb4a6 | bellard | { "mfdsisr", XSPR(31,339,18), XSPR_MASK, PPC|POWER, { RT } }, |
2549 | b9adb4a6 | bellard | { "mfdar", XSPR(31,339,19), XSPR_MASK, PPC|POWER, { RT } }, |
2550 | b9adb4a6 | bellard | { "mfdec", XSPR(31,339,22), XSPR_MASK, PPC, { RT } }, |
2551 | b9adb4a6 | bellard | { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, |
2552 | b9adb4a6 | bellard | { "mfsdr1", XSPR(31,339,25), XSPR_MASK, PPC|POWER, { RT } }, |
2553 | b9adb4a6 | bellard | { "mfsrr0", XSPR(31,339,26), XSPR_MASK, PPC|POWER, { RT } }, |
2554 | b9adb4a6 | bellard | { "mfsrr1", XSPR(31,339,27), XSPR_MASK, PPC|POWER, { RT } }, |
2555 | b9adb4a6 | bellard | { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, |
2556 | b9adb4a6 | bellard | { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC|B64, { RT } }, |
2557 | b9adb4a6 | bellard | { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, |
2558 | b9adb4a6 | bellard | { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, |
2559 | b9adb4a6 | bellard | { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
2560 | b9adb4a6 | bellard | { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
2561 | b9adb4a6 | bellard | { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
2562 | b9adb4a6 | bellard | { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, |
2563 | b9adb4a6 | bellard | { "mfspr", X(31,339), X_MASK, PPC|POWER, { RT, SPR } }, |
2564 | b9adb4a6 | bellard | |
2565 | b9adb4a6 | bellard | { "lwax", X(31,341), X_MASK, PPC|B64, { RT, RA, RB } }, |
2566 | b9adb4a6 | bellard | |
2567 | b9adb4a6 | bellard | { "lhax", X(31,343), X_MASK, PPC|POWER, { RT, RA, RB } }, |
2568 | b9adb4a6 | bellard | |
2569 | b9adb4a6 | bellard | { "dccci", X(31,454), XRT_MASK, PPC, { RA, RB } }, |
2570 | b9adb4a6 | bellard | |
2571 | b9adb4a6 | bellard | { "abs", XO(31,360,0,0), XORB_MASK, POWER|M601, { RT, RA } }, |
2572 | b9adb4a6 | bellard | { "abs.", XO(31,360,0,1), XORB_MASK, POWER|M601, { RT, RA } }, |
2573 | b9adb4a6 | bellard | { "abso", XO(31,360,1,0), XORB_MASK, POWER|M601, { RT, RA } }, |
2574 | b9adb4a6 | bellard | { "abso.", XO(31,360,1,1), XORB_MASK, POWER|M601, { RT, RA } }, |
2575 | b9adb4a6 | bellard | |
2576 | b9adb4a6 | bellard | { "divs", XO(31,363,0,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2577 | b9adb4a6 | bellard | { "divs.", XO(31,363,0,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2578 | b9adb4a6 | bellard | { "divso", XO(31,363,1,0), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2579 | b9adb4a6 | bellard | { "divso.", XO(31,363,1,1), XO_MASK, POWER|M601, { RT, RA, RB } }, |
2580 | b9adb4a6 | bellard | |
2581 | b9adb4a6 | bellard | { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, |
2582 | b9adb4a6 | bellard | |
2583 | b9adb4a6 | bellard | { "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, |
2584 | b9adb4a6 | bellard | { "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, |
2585 | b9adb4a6 | bellard | |
2586 | b9adb4a6 | bellard | { "lwaux", X(31,373), X_MASK, PPC|B64, { RT, RAL, RB } }, |
2587 | b9adb4a6 | bellard | |
2588 | b9adb4a6 | bellard | { "lhaux", X(31,375), X_MASK, PPC|POWER, { RT, RAL, RB } }, |
2589 | b9adb4a6 | bellard | |
2590 | b9adb4a6 | bellard | { "sthx", X(31,407), X_MASK, PPC|POWER, { RS, RA, RB } }, |
2591 | b9adb4a6 | bellard | |
2592 | b9adb4a6 | bellard | { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, |
2593 | b9adb4a6 | bellard | |
2594 | b9adb4a6 | bellard | { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, |
2595 | b9adb4a6 | bellard | |
2596 | b9adb4a6 | bellard | { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, |
2597 | b9adb4a6 | bellard | |
2598 | b9adb4a6 | bellard | { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, |
2599 | b9adb4a6 | bellard | |
2600 | b9adb4a6 | bellard | { "orc", XRC(31,412,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2601 | b9adb4a6 | bellard | { "orc.", XRC(31,412,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2602 | b9adb4a6 | bellard | |
2603 | b9adb4a6 | bellard | { "sradi", XS(31,413,0), XS_MASK, PPC|B64, { RA, RS, SH6 } }, |
2604 | b9adb4a6 | bellard | { "sradi.", XS(31,413,1), XS_MASK, PPC|B64, { RA, RS, SH6 } }, |
2605 | b9adb4a6 | bellard | |
2606 | b9adb4a6 | bellard | { "slbie", X(31,434), XRTRA_MASK, PPC|B64, { RB } }, |
2607 | b9adb4a6 | bellard | |
2608 | b9adb4a6 | bellard | { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, |
2609 | b9adb4a6 | bellard | |
2610 | b9adb4a6 | bellard | { "sthux", X(31,439), X_MASK, PPC|POWER, { RS, RAS, RB } }, |
2611 | b9adb4a6 | bellard | |
2612 | b9adb4a6 | bellard | { "mr", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RBS } }, |
2613 | b9adb4a6 | bellard | { "or", XRC(31,444,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2614 | b9adb4a6 | bellard | { "mr.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RBS } }, |
2615 | b9adb4a6 | bellard | { "or.", XRC(31,444,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2616 | b9adb4a6 | bellard | |
2617 | b9adb4a6 | bellard | { "mtdcr", X(31,451), X_MASK, PPC, { SPR, RS } }, |
2618 | b9adb4a6 | bellard | |
2619 | b9adb4a6 | bellard | { "divdu", XO(31,457,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2620 | b9adb4a6 | bellard | { "divdu.", XO(31,457,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2621 | b9adb4a6 | bellard | { "divduo", XO(31,457,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2622 | b9adb4a6 | bellard | { "divduo.", XO(31,457,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2623 | b9adb4a6 | bellard | |
2624 | b9adb4a6 | bellard | { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2625 | b9adb4a6 | bellard | { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2626 | b9adb4a6 | bellard | { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2627 | b9adb4a6 | bellard | { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2628 | b9adb4a6 | bellard | |
2629 | b9adb4a6 | bellard | { "mtmq", XSPR(31,467,0), XSPR_MASK, POWER|M601, { RS } }, |
2630 | b9adb4a6 | bellard | { "mtxer", XSPR(31,467,1), XSPR_MASK, PPC|POWER, { RS } }, |
2631 | b9adb4a6 | bellard | { "mtlr", XSPR(31,467,8), XSPR_MASK, PPC|POWER, { RS } }, |
2632 | b9adb4a6 | bellard | { "mtctr", XSPR(31,467,9), XSPR_MASK, PPC|POWER, { RS } }, |
2633 | b9adb4a6 | bellard | { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, |
2634 | b9adb4a6 | bellard | { "mtdsisr", XSPR(31,467,18), XSPR_MASK, PPC|POWER, { RS } }, |
2635 | b9adb4a6 | bellard | { "mtdar", XSPR(31,467,19), XSPR_MASK, PPC|POWER, { RS } }, |
2636 | b9adb4a6 | bellard | { "mtrtcu", XSPR(31,467,20), XSPR_MASK, PPC|POWER, { RS } }, |
2637 | b9adb4a6 | bellard | { "mtrtcl", XSPR(31,467,21), XSPR_MASK, PPC|POWER, { RS } }, |
2638 | b9adb4a6 | bellard | { "mtdec", XSPR(31,467,22), XSPR_MASK, PPC|POWER, { RS } }, |
2639 | b9adb4a6 | bellard | { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, |
2640 | b9adb4a6 | bellard | { "mtsdr1", XSPR(31,467,25), XSPR_MASK, PPC|POWER, { RS } }, |
2641 | b9adb4a6 | bellard | { "mtsrr0", XSPR(31,467,26), XSPR_MASK, PPC|POWER, { RS } }, |
2642 | b9adb4a6 | bellard | { "mtsrr1", XSPR(31,467,27), XSPR_MASK, PPC|POWER, { RS } }, |
2643 | b9adb4a6 | bellard | { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, |
2644 | b9adb4a6 | bellard | { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC|B64, { RS } }, |
2645 | b9adb4a6 | bellard | { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, |
2646 | b9adb4a6 | bellard | { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, |
2647 | b9adb4a6 | bellard | { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, |
2648 | b9adb4a6 | bellard | { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
2649 | b9adb4a6 | bellard | { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
2650 | b9adb4a6 | bellard | { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
2651 | b9adb4a6 | bellard | { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, |
2652 | b9adb4a6 | bellard | { "mtspr", X(31,467), X_MASK, PPC|POWER, { SPR, RS } }, |
2653 | b9adb4a6 | bellard | |
2654 | b9adb4a6 | bellard | { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, |
2655 | b9adb4a6 | bellard | |
2656 | b9adb4a6 | bellard | { "nand", XRC(31,476,0), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2657 | b9adb4a6 | bellard | { "nand.", XRC(31,476,1), X_MASK, PPC|POWER, { RA, RS, RB } }, |
2658 | b9adb4a6 | bellard | |
2659 | b9adb4a6 | bellard | { "nabs", XO(31,488,0,0), XORB_MASK, POWER|M601, { RT, RA } }, |
2660 | b9adb4a6 | bellard | { "nabs.", XO(31,488,0,1), XORB_MASK, POWER|M601, { RT, RA } }, |
2661 | b9adb4a6 | bellard | { "nabso", XO(31,488,1,0), XORB_MASK, POWER|M601, { RT, RA } }, |
2662 | b9adb4a6 | bellard | { "nabso.", XO(31,488,1,1), XORB_MASK, POWER|M601, { RT, RA } }, |
2663 | b9adb4a6 | bellard | |
2664 | b9adb4a6 | bellard | { "divd", XO(31,489,0,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2665 | b9adb4a6 | bellard | { "divd.", XO(31,489,0,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2666 | b9adb4a6 | bellard | { "divdo", XO(31,489,1,0), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2667 | b9adb4a6 | bellard | { "divdo.", XO(31,489,1,1), XO_MASK, PPC|B64, { RT, RA, RB } }, |
2668 | b9adb4a6 | bellard | |
2669 | b9adb4a6 | bellard | { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, |
2670 | b9adb4a6 | bellard | { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, |
2671 | b9adb4a6 | bellard | { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, |
2672 | b9adb4a6 | bellard | { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, |
2673 | b9adb4a6 | bellard | |
2674 | b9adb4a6 | bellard | { "slbia", X(31,498), 0xffffffff, PPC|B64, { 0 } }, |
2675 | b9adb4a6 | bellard | |
2676 | b9adb4a6 | bellard | { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, |
2677 | b9adb4a6 | bellard | |
2678 | b9adb4a6 | bellard | { "mcrxr", X(31,512), XRARB_MASK|(3<<21), PPC|POWER, { BF } }, |
2679 | b9adb4a6 | bellard | |
2680 | b9adb4a6 | bellard | { "clcs", X(31,531), XRB_MASK, POWER|M601, { RT, RA } }, |
2681 | b9adb4a6 | bellard | |
2682 | b9adb4a6 | bellard | { "lswx", X(31,533), X_MASK, PPC, { RT, RA, RB } }, |
2683 | b9adb4a6 | bellard | { "lsx", X(31,533), X_MASK, POWER, { RT, RA, RB } }, |
2684 | b9adb4a6 | bellard | |
2685 | b9adb4a6 | bellard | { "lwbrx", X(31,534), X_MASK, PPC, { RT, RA, RB } }, |
2686 | b9adb4a6 | bellard | { "lbrx", X(31,534), X_MASK, POWER, { RT, RA, RB } }, |
2687 | b9adb4a6 | bellard | |
2688 | b9adb4a6 | bellard | { "lfsx", X(31,535), X_MASK, PPC|POWER, { FRT, RA, RB } }, |
2689 | b9adb4a6 | bellard | |
2690 | b9adb4a6 | bellard | { "srw", XRC(31,536,0), X_MASK, PPC, { RA, RS, RB } }, |
2691 | b9adb4a6 | bellard | { "sr", XRC(31,536,0), X_MASK, POWER, { RA, RS, RB } }, |
2692 | b9adb4a6 | bellard | { "srw.", XRC(31,536,1), X_MASK, PPC, { RA, RS, RB } }, |
2693 | b9adb4a6 | bellard | { "sr.", XRC(31,536,1), X_MASK, POWER, { RA, RS, RB } }, |
2694 | b9adb4a6 | bellard | |
2695 | b9adb4a6 | bellard | { "rrib", XRC(31,537,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2696 | b9adb4a6 | bellard | { "rrib.", XRC(31,537,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2697 | b9adb4a6 | bellard | |
2698 | b9adb4a6 | bellard | { "srd", XRC(31,539,0), X_MASK, PPC|B64, { RA, RS, RB } }, |
2699 | b9adb4a6 | bellard | { "srd.", XRC(31,539,1), X_MASK, PPC|B64, { RA, RS, RB } }, |
2700 | b9adb4a6 | bellard | |
2701 | b9adb4a6 | bellard | { "maskir", XRC(31,541,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2702 | b9adb4a6 | bellard | { "maskir.", XRC(31,541,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2703 | b9adb4a6 | bellard | |
2704 | b9adb4a6 | bellard | { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, |
2705 | b9adb4a6 | bellard | |
2706 | b9adb4a6 | bellard | { "lfsux", X(31,567), X_MASK, PPC|POWER, { FRT, RAS, RB } }, |
2707 | b9adb4a6 | bellard | |
2708 | b9adb4a6 | bellard | { "mfsr", X(31,595), XRB_MASK|(1<<20), PPC|POWER|B32, { RT, SR } }, |
2709 | b9adb4a6 | bellard | |
2710 | b9adb4a6 | bellard | { "lswi", X(31,597), X_MASK, PPC, { RT, RA, NB } }, |
2711 | b9adb4a6 | bellard | { "lsi", X(31,597), X_MASK, POWER, { RT, RA, NB } }, |
2712 | b9adb4a6 | bellard | |
2713 | b9adb4a6 | bellard | { "sync", X(31,598), 0xffffffff, PPC, { 0 } }, |
2714 | b9adb4a6 | bellard | { "dcs", X(31,598), 0xffffffff, POWER, { 0 } }, |
2715 | b9adb4a6 | bellard | |
2716 | b9adb4a6 | bellard | { "lfdx", X(31,599), X_MASK, PPC|POWER, { FRT, RA, RB } }, |
2717 | b9adb4a6 | bellard | |
2718 | b9adb4a6 | bellard | { "mfsri", X(31,627), X_MASK, POWER, { RT, RA, RB } }, |
2719 | b9adb4a6 | bellard | |
2720 | b9adb4a6 | bellard | { "dclst", X(31,630), XRB_MASK, POWER, { RS, RA } }, |
2721 | b9adb4a6 | bellard | |
2722 | b9adb4a6 | bellard | { "lfdux", X(31,631), X_MASK, PPC|POWER, { FRT, RAS, RB } }, |
2723 | b9adb4a6 | bellard | |
2724 | b9adb4a6 | bellard | { "mfsrin", X(31,659), XRA_MASK, PPC|B32, { RT, RB } }, |
2725 | b9adb4a6 | bellard | |
2726 | b9adb4a6 | bellard | { "stswx", X(31,661), X_MASK, PPC, { RS, RA, RB } }, |
2727 | b9adb4a6 | bellard | { "stsx", X(31,661), X_MASK, POWER, { RS, RA, RB } }, |
2728 | b9adb4a6 | bellard | |
2729 | b9adb4a6 | bellard | { "stwbrx", X(31,662), X_MASK, PPC, { RS, RA, RB } }, |
2730 | b9adb4a6 | bellard | { "stbrx", X(31,662), X_MASK, POWER, { RS, RA, RB } }, |
2731 | b9adb4a6 | bellard | |
2732 | b9adb4a6 | bellard | { "stfsx", X(31,663), X_MASK, PPC|POWER, { FRS, RA, RB } }, |
2733 | b9adb4a6 | bellard | |
2734 | b9adb4a6 | bellard | { "srq", XRC(31,664,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2735 | b9adb4a6 | bellard | { "srq.", XRC(31,664,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2736 | b9adb4a6 | bellard | |
2737 | b9adb4a6 | bellard | { "sre", XRC(31,665,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2738 | b9adb4a6 | bellard | { "sre.", XRC(31,665,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2739 | b9adb4a6 | bellard | |
2740 | b9adb4a6 | bellard | { "stfsux", X(31,695), X_MASK, PPC|POWER, { FRS, RAS, RB } }, |
2741 | b9adb4a6 | bellard | |
2742 | b9adb4a6 | bellard | { "sriq", XRC(31,696,0), X_MASK, POWER|M601, { RA, RS, SH } }, |
2743 | b9adb4a6 | bellard | { "sriq.", XRC(31,696,1), X_MASK, POWER|M601, { RA, RS, SH } }, |
2744 | b9adb4a6 | bellard | |
2745 | b9adb4a6 | bellard | { "stswi", X(31,725), X_MASK, PPC, { RS, RA, NB } }, |
2746 | b9adb4a6 | bellard | { "stsi", X(31,725), X_MASK, POWER, { RS, RA, NB } }, |
2747 | b9adb4a6 | bellard | |
2748 | b9adb4a6 | bellard | { "stfdx", X(31,727), X_MASK, PPC|POWER, { FRS, RA, RB } }, |
2749 | b9adb4a6 | bellard | |
2750 | b9adb4a6 | bellard | { "srlq", XRC(31,728,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2751 | b9adb4a6 | bellard | { "srlq.", XRC(31,728,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2752 | b9adb4a6 | bellard | |
2753 | b9adb4a6 | bellard | { "sreq", XRC(31,729,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2754 | b9adb4a6 | bellard | { "sreq.", XRC(31,729,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2755 | b9adb4a6 | bellard | |
2756 | b9adb4a6 | bellard | { "stfdux", X(31,759), X_MASK, PPC|POWER, { FRS, RAS, RB } }, |
2757 | b9adb4a6 | bellard | |
2758 | b9adb4a6 | bellard | { "srliq", XRC(31,760,0), X_MASK, POWER|M601, { RA, RS, SH } }, |
2759 | b9adb4a6 | bellard | { "srliq.", XRC(31,760,1), X_MASK, POWER|M601, { RA, RS, SH } }, |
2760 | b9adb4a6 | bellard | |
2761 | b9adb4a6 | bellard | { "lhbrx", X(31,790), X_MASK, PPC|POWER, { RT, RA, RB } }, |
2762 | b9adb4a6 | bellard | |
2763 | b9adb4a6 | bellard | { "sraw", XRC(31,792,0), X_MASK, PPC, { RA, RS, RB } }, |
2764 | b9adb4a6 | bellard | { "sra", XRC(31,792,0), X_MASK, POWER, { RA, RS, RB } }, |
2765 | b9adb4a6 | bellard | { "sraw.", XRC(31,792,1), X_MASK, PPC, { RA, RS, RB } }, |
2766 | b9adb4a6 | bellard | { "sra.", XRC(31,792,1), X_MASK, POWER, { RA, RS, RB } }, |
2767 | b9adb4a6 | bellard | |
2768 | b9adb4a6 | bellard | { "srad", XRC(31,794,0), X_MASK, PPC|B64, { RA, RS, RB } }, |
2769 | b9adb4a6 | bellard | { "srad.", XRC(31,794,1), X_MASK, PPC|B64, { RA, RS, RB } }, |
2770 | b9adb4a6 | bellard | |
2771 | b9adb4a6 | bellard | { "rac", X(31,818), X_MASK, POWER, { RT, RA, RB } }, |
2772 | b9adb4a6 | bellard | |
2773 | b9adb4a6 | bellard | { "srawi", XRC(31,824,0), X_MASK, PPC, { RA, RS, SH } }, |
2774 | b9adb4a6 | bellard | { "srai", XRC(31,824,0), X_MASK, POWER, { RA, RS, SH } }, |
2775 | b9adb4a6 | bellard | { "srawi.", XRC(31,824,1), X_MASK, PPC, { RA, RS, SH } }, |
2776 | b9adb4a6 | bellard | { "srai.", XRC(31,824,1), X_MASK, POWER, { RA, RS, SH } }, |
2777 | b9adb4a6 | bellard | |
2778 | b9adb4a6 | bellard | { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, |
2779 | b9adb4a6 | bellard | |
2780 | b9adb4a6 | bellard | { "sthbrx", X(31,918), X_MASK, PPC|POWER, { RS, RA, RB } }, |
2781 | b9adb4a6 | bellard | |
2782 | b9adb4a6 | bellard | { "sraq", XRC(31,920,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2783 | b9adb4a6 | bellard | { "sraq.", XRC(31,920,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2784 | b9adb4a6 | bellard | |
2785 | b9adb4a6 | bellard | { "srea", XRC(31,921,0), X_MASK, POWER|M601, { RA, RS, RB } }, |
2786 | b9adb4a6 | bellard | { "srea.", XRC(31,921,1), X_MASK, POWER|M601, { RA, RS, RB } }, |
2787 | b9adb4a6 | bellard | |
2788 | b9adb4a6 | bellard | { "extsh", XRC(31,922,0), XRB_MASK, PPC, { RA, RS } }, |
2789 | b9adb4a6 | bellard | { "exts", XRC(31,922,0), XRB_MASK, POWER, { RA, RS } }, |
2790 | b9adb4a6 | bellard | { "extsh.", XRC(31,922,1), XRB_MASK, PPC, { RA, RS } }, |
2791 | b9adb4a6 | bellard | { "exts.", XRC(31,922,1), XRB_MASK, POWER, { RA, RS } }, |
2792 | b9adb4a6 | bellard | |
2793 | b9adb4a6 | bellard | { "sraiq", XRC(31,952,0), X_MASK, POWER|M601, { RA, RS, SH } }, |
2794 | b9adb4a6 | bellard | { "sraiq.", XRC(31,952,1), X_MASK, POWER|M601, { RA, RS, SH } }, |
2795 | b9adb4a6 | bellard | |
2796 | b9adb4a6 | bellard | { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, |
2797 | b9adb4a6 | bellard | { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, |
2798 | b9adb4a6 | bellard | |
2799 | b9adb4a6 | bellard | { "iccci", X(31,966), XRT_MASK, PPC, { RA, RB } }, |
2800 | b9adb4a6 | bellard | |
2801 | b9adb4a6 | bellard | { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, |
2802 | b9adb4a6 | bellard | |
2803 | b9adb4a6 | bellard | { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, |
2804 | b9adb4a6 | bellard | |
2805 | b9adb4a6 | bellard | { "extsw", XRC(31,986,0), XRB_MASK, PPC, { RA, RS } }, |
2806 | b9adb4a6 | bellard | { "extsw.", XRC(31,986,1), XRB_MASK, PPC, { RA, RS } }, |
2807 | b9adb4a6 | bellard | |
2808 | b9adb4a6 | bellard | { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
2809 | b9adb4a6 | bellard | { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, |
2810 | b9adb4a6 | bellard | |
2811 | b9adb4a6 | bellard | { "lwz", OP(32), OP_MASK, PPC, { RT, D, RA } }, |
2812 | b9adb4a6 | bellard | { "l", OP(32), OP_MASK, POWER, { RT, D, RA } }, |
2813 | b9adb4a6 | bellard | |
2814 | b9adb4a6 | bellard | { "lwzu", OP(33), OP_MASK, PPC, { RT, D, RAL } }, |
2815 | b9adb4a6 | bellard | { "lu", OP(33), OP_MASK, POWER, { RT, D, RA } }, |
2816 | b9adb4a6 | bellard | |
2817 | b9adb4a6 | bellard | { "lbz", OP(34), OP_MASK, PPC|POWER, { RT, D, RA } }, |
2818 | b9adb4a6 | bellard | |
2819 | b9adb4a6 | bellard | { "lbzu", OP(35), OP_MASK, PPC|POWER, { RT, D, RAL } }, |
2820 | b9adb4a6 | bellard | |
2821 | b9adb4a6 | bellard | { "stw", OP(36), OP_MASK, PPC, { RS, D, RA } }, |
2822 | b9adb4a6 | bellard | { "st", OP(36), OP_MASK, POWER, { RS, D, RA } }, |
2823 | b9adb4a6 | bellard | |
2824 | b9adb4a6 | bellard | { "stwu", OP(37), OP_MASK, PPC, { RS, D, RAS } }, |
2825 | b9adb4a6 | bellard | { "stu", OP(37), OP_MASK, POWER, { RS, D, RA } }, |
2826 | b9adb4a6 | bellard | |
2827 | b9adb4a6 | bellard | { "stb", OP(38), OP_MASK, PPC|POWER, { RS, D, RA } }, |
2828 | b9adb4a6 | bellard | |
2829 | b9adb4a6 | bellard | { "stbu", OP(39), OP_MASK, PPC|POWER, { RS, D, RAS } }, |
2830 | b9adb4a6 | bellard | |
2831 | b9adb4a6 | bellard | { "lhz", OP(40), OP_MASK, PPC|POWER, { RT, D, RA } }, |
2832 | b9adb4a6 | bellard | |
2833 | b9adb4a6 | bellard | { "lhzu", OP(41), OP_MASK, PPC|POWER, { RT, D, RAL } }, |
2834 | b9adb4a6 | bellard | |
2835 | b9adb4a6 | bellard | { "lha", OP(42), OP_MASK, PPC|POWER, { RT, D, RA } }, |
2836 | b9adb4a6 | bellard | |
2837 | b9adb4a6 | bellard | { "lhau", OP(43), OP_MASK, PPC|POWER, { RT, D, RAL } }, |
2838 | b9adb4a6 | bellard | |
2839 | b9adb4a6 | bellard | { "sth", OP(44), OP_MASK, PPC|POWER, { RS, D, RA } }, |
2840 | b9adb4a6 | bellard | |
2841 | b9adb4a6 | bellard | { "sthu", OP(45), OP_MASK, PPC|POWER, { RS, D, RAS } }, |
2842 | b9adb4a6 | bellard | |
2843 | b9adb4a6 | bellard | { "lmw", OP(46), OP_MASK, PPC, { RT, D, RAM } }, |
2844 | b9adb4a6 | bellard | { "lm", OP(46), OP_MASK, POWER, { RT, D, RA } }, |
2845 | b9adb4a6 | bellard | |
2846 | b9adb4a6 | bellard | { "stmw", OP(47), OP_MASK, PPC, { RS, D, RA } }, |
2847 | b9adb4a6 | bellard | { "stm", OP(47), OP_MASK, POWER, { RS, D, RA } }, |
2848 | b9adb4a6 | bellard | |
2849 | b9adb4a6 | bellard | { "lfs", OP(48), OP_MASK, PPC|POWER, { FRT, D, RA } }, |
2850 | b9adb4a6 | bellard | |
2851 | b9adb4a6 | bellard | { "lfsu", OP(49), OP_MASK, PPC|POWER, { FRT, D, RAS } }, |
2852 | b9adb4a6 | bellard | |
2853 | b9adb4a6 | bellard | { "lfd", OP(50), OP_MASK, PPC|POWER, { FRT, D, RA } }, |
2854 | b9adb4a6 | bellard | |
2855 | b9adb4a6 | bellard | { "lfdu", OP(51), OP_MASK, PPC|POWER, { FRT, D, RAS } }, |
2856 | b9adb4a6 | bellard | |
2857 | b9adb4a6 | bellard | { "stfs", OP(52), OP_MASK, PPC|POWER, { FRS, D, RA } }, |
2858 | b9adb4a6 | bellard | |
2859 | b9adb4a6 | bellard | { "stfsu", OP(53), OP_MASK, PPC|POWER, { FRS, D, RAS } }, |
2860 | b9adb4a6 | bellard | |
2861 | b9adb4a6 | bellard | { "stfd", OP(54), OP_MASK, PPC|POWER, { FRS, D, RA } }, |
2862 | b9adb4a6 | bellard | |
2863 | b9adb4a6 | bellard | { "stfdu", OP(55), OP_MASK, PPC|POWER, { FRS, D, RAS } }, |
2864 | b9adb4a6 | bellard | |
2865 | b9adb4a6 | bellard | { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, |
2866 | b9adb4a6 | bellard | |
2867 | b9adb4a6 | bellard | { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, |
2868 | b9adb4a6 | bellard | |
2869 | b9adb4a6 | bellard | { "ld", DSO(58,0), DS_MASK, PPC|B64, { RT, DS, RA } }, |
2870 | b9adb4a6 | bellard | |
2871 | b9adb4a6 | bellard | { "ldu", DSO(58,1), DS_MASK, PPC|B64, { RT, DS, RAL } }, |
2872 | b9adb4a6 | bellard | |
2873 | b9adb4a6 | bellard | { "lwa", DSO(58,2), DS_MASK, PPC|B64, { RT, DS, RA } }, |
2874 | b9adb4a6 | bellard | |
2875 | b9adb4a6 | bellard | { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2876 | b9adb4a6 | bellard | { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2877 | b9adb4a6 | bellard | |
2878 | b9adb4a6 | bellard | { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2879 | b9adb4a6 | bellard | { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2880 | b9adb4a6 | bellard | |
2881 | b9adb4a6 | bellard | { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2882 | b9adb4a6 | bellard | { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2883 | b9adb4a6 | bellard | |
2884 | b9adb4a6 | bellard | { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
2885 | b9adb4a6 | bellard | { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
2886 | b9adb4a6 | bellard | |
2887 | b9adb4a6 | bellard | { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
2888 | b9adb4a6 | bellard | { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
2889 | b9adb4a6 | bellard | |
2890 | b9adb4a6 | bellard | { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
2891 | b9adb4a6 | bellard | { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
2892 | b9adb4a6 | bellard | |
2893 | b9adb4a6 | bellard | { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2894 | b9adb4a6 | bellard | { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2895 | b9adb4a6 | bellard | |
2896 | b9adb4a6 | bellard | { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2897 | b9adb4a6 | bellard | { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2898 | b9adb4a6 | bellard | |
2899 | b9adb4a6 | bellard | { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2900 | b9adb4a6 | bellard | { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2901 | b9adb4a6 | bellard | |
2902 | b9adb4a6 | bellard | { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2903 | b9adb4a6 | bellard | { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2904 | b9adb4a6 | bellard | |
2905 | b9adb4a6 | bellard | { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, |
2906 | b9adb4a6 | bellard | |
2907 | b9adb4a6 | bellard | { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, |
2908 | b9adb4a6 | bellard | |
2909 | b9adb4a6 | bellard | { "std", DSO(62,0), DS_MASK, PPC|B64, { RS, DS, RA } }, |
2910 | b9adb4a6 | bellard | |
2911 | b9adb4a6 | bellard | { "stdu", DSO(62,1), DS_MASK, PPC|B64, { RS, DS, RAS } }, |
2912 | b9adb4a6 | bellard | |
2913 | b9adb4a6 | bellard | { "fcmpu", X(63,0), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, |
2914 | b9adb4a6 | bellard | |
2915 | b9adb4a6 | bellard | { "frsp", XRC(63,12,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2916 | b9adb4a6 | bellard | { "frsp.", XRC(63,12,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2917 | b9adb4a6 | bellard | |
2918 | b9adb4a6 | bellard | { "fctiw", XRC(63,14,0), XRA_MASK, PPC, { FRT, FRB } }, |
2919 | b9adb4a6 | bellard | { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, |
2920 | b9adb4a6 | bellard | { "fctiw.", XRC(63,14,1), XRA_MASK, PPC, { FRT, FRB } }, |
2921 | b9adb4a6 | bellard | { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, |
2922 | b9adb4a6 | bellard | |
2923 | b9adb4a6 | bellard | { "fctiwz", XRC(63,15,0), XRA_MASK, PPC, { FRT, FRB } }, |
2924 | b9adb4a6 | bellard | { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, |
2925 | b9adb4a6 | bellard | { "fctiwz.", XRC(63,15,1), XRA_MASK, PPC, { FRT, FRB } }, |
2926 | b9adb4a6 | bellard | { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, |
2927 | b9adb4a6 | bellard | |
2928 | b9adb4a6 | bellard | { "fdiv", A(63,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2929 | b9adb4a6 | bellard | { "fd", A(63,18,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, |
2930 | b9adb4a6 | bellard | { "fdiv.", A(63,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2931 | b9adb4a6 | bellard | { "fd.", A(63,18,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, |
2932 | b9adb4a6 | bellard | |
2933 | b9adb4a6 | bellard | { "fsub", A(63,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2934 | b9adb4a6 | bellard | { "fs", A(63,20,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, |
2935 | b9adb4a6 | bellard | { "fsub.", A(63,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2936 | b9adb4a6 | bellard | { "fs.", A(63,20,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, |
2937 | b9adb4a6 | bellard | |
2938 | b9adb4a6 | bellard | { "fadd", A(63,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2939 | b9adb4a6 | bellard | { "fa", A(63,21,0), AFRC_MASK, POWER, { FRT, FRA, FRB } }, |
2940 | b9adb4a6 | bellard | { "fadd.", A(63,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, |
2941 | b9adb4a6 | bellard | { "fa.", A(63,21,1), AFRC_MASK, POWER, { FRT, FRA, FRB } }, |
2942 | b9adb4a6 | bellard | |
2943 | b9adb4a6 | bellard | { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, |
2944 | b9adb4a6 | bellard | { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPC|POWER2, { FRT, FRB } }, |
2945 | b9adb4a6 | bellard | |
2946 | b9adb4a6 | bellard | { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2947 | b9adb4a6 | bellard | { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2948 | b9adb4a6 | bellard | |
2949 | b9adb4a6 | bellard | { "fmul", A(63,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
2950 | b9adb4a6 | bellard | { "fm", A(63,25,0), AFRB_MASK, POWER, { FRT, FRA, FRC } }, |
2951 | b9adb4a6 | bellard | { "fmul.", A(63,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, |
2952 | b9adb4a6 | bellard | { "fm.", A(63,25,1), AFRB_MASK, POWER, { FRT, FRA, FRC } }, |
2953 | b9adb4a6 | bellard | |
2954 | b9adb4a6 | bellard | { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
2955 | b9adb4a6 | bellard | { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, |
2956 | b9adb4a6 | bellard | |
2957 | b9adb4a6 | bellard | { "fmsub", A(63,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2958 | b9adb4a6 | bellard | { "fms", A(63,28,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2959 | b9adb4a6 | bellard | { "fmsub.", A(63,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2960 | b9adb4a6 | bellard | { "fms.", A(63,28,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2961 | b9adb4a6 | bellard | |
2962 | b9adb4a6 | bellard | { "fmadd", A(63,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2963 | b9adb4a6 | bellard | { "fma", A(63,29,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2964 | b9adb4a6 | bellard | { "fmadd.", A(63,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2965 | b9adb4a6 | bellard | { "fma.", A(63,29,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2966 | b9adb4a6 | bellard | |
2967 | b9adb4a6 | bellard | { "fnmsub", A(63,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2968 | b9adb4a6 | bellard | { "fnms", A(63,30,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2969 | b9adb4a6 | bellard | { "fnmsub.", A(63,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2970 | b9adb4a6 | bellard | { "fnms.", A(63,30,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2971 | b9adb4a6 | bellard | |
2972 | b9adb4a6 | bellard | { "fnmadd", A(63,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2973 | b9adb4a6 | bellard | { "fnma", A(63,31,0), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2974 | b9adb4a6 | bellard | { "fnmadd.", A(63,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, |
2975 | b9adb4a6 | bellard | { "fnma.", A(63,31,1), A_MASK, POWER, { FRT,FRA,FRC,FRB } }, |
2976 | b9adb4a6 | bellard | |
2977 | b9adb4a6 | bellard | { "fcmpo", X(63,30), X_MASK|(3<<21), PPC|POWER, { BF, FRA, FRB } }, |
2978 | b9adb4a6 | bellard | |
2979 | b9adb4a6 | bellard | { "mtfsb1", XRC(63,38,0), XRARB_MASK, PPC|POWER, { BT } }, |
2980 | b9adb4a6 | bellard | { "mtfsb1.", XRC(63,38,1), XRARB_MASK, PPC|POWER, { BT } }, |
2981 | b9adb4a6 | bellard | |
2982 | b9adb4a6 | bellard | { "fneg", XRC(63,40,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2983 | b9adb4a6 | bellard | { "fneg.", XRC(63,40,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2984 | b9adb4a6 | bellard | |
2985 | b9adb4a6 | bellard | { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), PPC|POWER, { BF, BFA } }, |
2986 | b9adb4a6 | bellard | |
2987 | b9adb4a6 | bellard | { "mtfsb0", XRC(63,70,0), XRARB_MASK, PPC|POWER, { BT } }, |
2988 | b9adb4a6 | bellard | { "mtfsb0.", XRC(63,70,1), XRARB_MASK, PPC|POWER, { BT } }, |
2989 | b9adb4a6 | bellard | |
2990 | b9adb4a6 | bellard | { "fmr", XRC(63,72,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2991 | b9adb4a6 | bellard | { "fmr.", XRC(63,72,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2992 | b9adb4a6 | bellard | |
2993 | b9adb4a6 | bellard | { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, |
2994 | b9adb4a6 | bellard | { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), PPC|POWER, { BF, U } }, |
2995 | b9adb4a6 | bellard | |
2996 | b9adb4a6 | bellard | { "fnabs", XRC(63,136,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2997 | b9adb4a6 | bellard | { "fnabs.", XRC(63,136,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
2998 | b9adb4a6 | bellard | |
2999 | b9adb4a6 | bellard | { "fabs", XRC(63,264,0), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
3000 | b9adb4a6 | bellard | { "fabs.", XRC(63,264,1), XRA_MASK, PPC|POWER, { FRT, FRB } }, |
3001 | b9adb4a6 | bellard | |
3002 | b9adb4a6 | bellard | { "mffs", XRC(63,583,0), XRARB_MASK, PPC|POWER, { FRT } }, |
3003 | b9adb4a6 | bellard | { "mffs.", XRC(63,583,1), XRARB_MASK, PPC|POWER, { FRT } }, |
3004 | b9adb4a6 | bellard | |
3005 | b9adb4a6 | bellard | { "mtfsf", XFL(63,711,0), XFL_MASK, PPC|POWER, { FLM, FRB } }, |
3006 | b9adb4a6 | bellard | { "mtfsf.", XFL(63,711,1), XFL_MASK, PPC|POWER, { FLM, FRB } }, |
3007 | b9adb4a6 | bellard | |
3008 | b9adb4a6 | bellard | { "fctid", XRC(63,814,0), XRA_MASK, PPC|B64, { FRT, FRB } }, |
3009 | b9adb4a6 | bellard | { "fctid.", XRC(63,814,1), XRA_MASK, PPC|B64, { FRT, FRB } }, |
3010 | b9adb4a6 | bellard | |
3011 | b9adb4a6 | bellard | { "fctidz", XRC(63,815,0), XRA_MASK, PPC|B64, { FRT, FRB } }, |
3012 | b9adb4a6 | bellard | { "fctidz.", XRC(63,815,1), XRA_MASK, PPC|B64, { FRT, FRB } }, |
3013 | b9adb4a6 | bellard | |
3014 | b9adb4a6 | bellard | { "fcfid", XRC(63,846,0), XRA_MASK, PPC|B64, { FRT, FRB } }, |
3015 | b9adb4a6 | bellard | { "fcfid.", XRC(63,846,1), XRA_MASK, PPC|B64, { FRT, FRB } }, |
3016 | b9adb4a6 | bellard | |
3017 | b9adb4a6 | bellard | }; |
3018 | b9adb4a6 | bellard | |
3019 | b9adb4a6 | bellard | const int powerpc_num_opcodes = |
3020 | b9adb4a6 | bellard | sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); |
3021 | b9adb4a6 | bellard | |
3022 | b9adb4a6 | bellard | /* The macro table. This is only used by the assembler. */
|
3023 | b9adb4a6 | bellard | |
3024 | b9adb4a6 | bellard | const struct powerpc_macro powerpc_macros[] = { |
3025 | b9adb4a6 | bellard | { "extldi", 4, PPC|B64, "rldicr %0,%1,%3,(%2)-1" }, |
3026 | b9adb4a6 | bellard | { "extldi.", 4, PPC|B64, "rldicr. %0,%1,%3,(%2)-1" }, |
3027 | b9adb4a6 | bellard | { "extrdi", 4, PPC|B64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, |
3028 | b9adb4a6 | bellard | { "extrdi.", 4, PPC|B64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, |
3029 | b9adb4a6 | bellard | { "insrdi", 4, PPC|B64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, |
3030 | b9adb4a6 | bellard | { "insrdi.", 4, PPC|B64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, |
3031 | b9adb4a6 | bellard | { "rotrdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),0" }, |
3032 | b9adb4a6 | bellard | { "rotrdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),0" }, |
3033 | b9adb4a6 | bellard | { "sldi", 3, PPC|B64, "rldicr %0,%1,%2,63-(%2)" }, |
3034 | b9adb4a6 | bellard | { "sldi.", 3, PPC|B64, "rldicr. %0,%1,%2,63-(%2)" }, |
3035 | b9adb4a6 | bellard | { "srdi", 3, PPC|B64, "rldicl %0,%1,64-(%2),%2" }, |
3036 | b9adb4a6 | bellard | { "srdi.", 3, PPC|B64, "rldicl. %0,%1,64-(%2),%2" }, |
3037 | b9adb4a6 | bellard | { "clrrdi", 3, PPC|B64, "rldicr %0,%1,0,63-(%2)" }, |
3038 | b9adb4a6 | bellard | { "clrrdi.", 3, PPC|B64, "rldicr. %0,%1,0,63-(%2)" }, |
3039 | b9adb4a6 | bellard | { "clrlsldi",4, PPC|B64, "rldic %0,%1,%3,(%2)-(%3)" }, |
3040 | b9adb4a6 | bellard | { "clrlsldi.",4, PPC|B64, "rldic. %0,%1,%3,(%2)-(%3)" }, |
3041 | b9adb4a6 | bellard | |
3042 | b9adb4a6 | bellard | { "extlwi", 4, PPC, "rlwinm %0,%1,%3,0,(%2)-1" }, |
3043 | b9adb4a6 | bellard | { "extlwi.", 4, PPC, "rlwinm. %0,%1,%3,0,(%2)-1" }, |
3044 | b9adb4a6 | bellard | { "extrwi", 4, PPC, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, |
3045 | b9adb4a6 | bellard | { "extrwi.", 4, PPC, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, |
3046 | b9adb4a6 | bellard | { "inslwi", 4, PPC, "rlwimi %0,%1,32-(%3),%3,(%2)+(%3)-1" }, |
3047 | b9adb4a6 | bellard | { "inslwi.", 4, PPC, "rlwimi. %0,%1,32-(%3),%3,(%2)+(%3)-1" }, |
3048 | b9adb4a6 | bellard | { "insrwi", 4, PPC, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, |
3049 | b9adb4a6 | bellard | { "insrwi.", 4, PPC, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, |
3050 | b9adb4a6 | bellard | { "rotrwi", 3, PPC, "rlwinm %0,%1,32-(%2),0,31" }, |
3051 | b9adb4a6 | bellard | { "rotrwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),0,31" }, |
3052 | b9adb4a6 | bellard | { "slwi", 3, PPC, "rlwinm %0,%1,%2,0,31-(%2)" }, |
3053 | b9adb4a6 | bellard | { "sli", 3, POWER, "rlinm %0,%1,%2,0,31-(%2)" }, |
3054 | b9adb4a6 | bellard | { "slwi.", 3, PPC, "rlwinm. %0,%1,%2,0,31-(%2)" }, |
3055 | b9adb4a6 | bellard | { "sli.", 3, POWER, "rlinm. %0,%1,%2,0,31-(%2)" }, |
3056 | b9adb4a6 | bellard | { "srwi", 3, PPC, "rlwinm %0,%1,32-(%2),%2,31" }, |
3057 | b9adb4a6 | bellard | { "sri", 3, POWER, "rlinm %0,%1,32-(%2),%2,31" }, |
3058 | b9adb4a6 | bellard | { "srwi.", 3, PPC, "rlwinm. %0,%1,32-(%2),%2,31" }, |
3059 | b9adb4a6 | bellard | { "sri.", 3, POWER, "rlinm. %0,%1,32-(%2),%2,31" }, |
3060 | b9adb4a6 | bellard | { "clrrwi", 3, PPC, "rlwinm %0,%1,0,0,31-(%2)" }, |
3061 | b9adb4a6 | bellard | { "clrrwi.", 3, PPC, "rlwinm. %0,%1,0,0,31-(%2)" }, |
3062 | b9adb4a6 | bellard | { "clrlslwi",4, PPC, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, |
3063 | b9adb4a6 | bellard | { "clrlslwi.",4, PPC, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, |
3064 | b9adb4a6 | bellard | |
3065 | b9adb4a6 | bellard | }; |
3066 | b9adb4a6 | bellard | |
3067 | b9adb4a6 | bellard | const int powerpc_num_macros = |
3068 | b9adb4a6 | bellard | sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); |
3069 | b9adb4a6 | bellard | |
3070 | 274da6b2 | bellard | static int print_insn_powerpc(FILE *, uint32_t insn, unsigned memaddr, int dialect); |
3071 | b9adb4a6 | bellard | |
3072 | b9adb4a6 | bellard | /* Print a big endian PowerPC instruction. For convenience, also
|
3073 | b9adb4a6 | bellard | disassemble instructions supported by the Motorola PowerPC 601. */
|
3074 | 274da6b2 | bellard | #include "cpu.h" |
3075 | b9adb4a6 | bellard | |
3076 | b9adb4a6 | bellard | int print_insn_ppc (bfd_vma pc, disassemble_info *info)
|
3077 | b9adb4a6 | bellard | { |
3078 | 274da6b2 | bellard | uint32_t opc; |
3079 | 274da6b2 | bellard | |
3080 | 274da6b2 | bellard | (*info->read_memory_func)(pc, (bfd_byte *)(&opc), 4, info);
|
3081 | 274da6b2 | bellard | return print_insn_powerpc (info->stream, tswap32(opc), pc,
|
3082 | 274da6b2 | bellard | PPC | B32 | M601); |
3083 | b9adb4a6 | bellard | } |
3084 | b9adb4a6 | bellard | |
3085 | b9adb4a6 | bellard | /* Print a PowerPC or POWER instruction. */
|
3086 | b9adb4a6 | bellard | |
3087 | 274da6b2 | bellard | int
|
3088 | 274da6b2 | bellard | print_insn_powerpc (FILE *out, uint32_t insn, unsigned memaddr,
|
3089 | b9adb4a6 | bellard | int dialect)
|
3090 | b9adb4a6 | bellard | { |
3091 | b9adb4a6 | bellard | const struct powerpc_opcode *opcode; |
3092 | b9adb4a6 | bellard | const struct powerpc_opcode *opcode_end; |
3093 | 274da6b2 | bellard | uint32_t op; |
3094 | b9adb4a6 | bellard | |
3095 | b9adb4a6 | bellard | /* Get the major opcode of the instruction. */
|
3096 | b9adb4a6 | bellard | op = PPC_OP (insn); |
3097 | b9adb4a6 | bellard | |
3098 | b9adb4a6 | bellard | /* Find the first match in the opcode table. We could speed this up
|
3099 | b9adb4a6 | bellard | a bit by doing a binary search on the major opcode. */
|
3100 | b9adb4a6 | bellard | opcode_end = powerpc_opcodes + powerpc_num_opcodes; |
3101 | b9adb4a6 | bellard | for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
|
3102 | b9adb4a6 | bellard | { |
3103 | 274da6b2 | bellard | uint32_t table_op; |
3104 | b9adb4a6 | bellard | const unsigned char *opindex; |
3105 | b9adb4a6 | bellard | const struct powerpc_operand *operand; |
3106 | b9adb4a6 | bellard | int invalid;
|
3107 | b9adb4a6 | bellard | int need_comma;
|
3108 | b9adb4a6 | bellard | int need_paren;
|
3109 | b9adb4a6 | bellard | |
3110 | b9adb4a6 | bellard | table_op = PPC_OP (opcode->opcode); |
3111 | b9adb4a6 | bellard | if (op < table_op)
|
3112 | b9adb4a6 | bellard | break;
|
3113 | b9adb4a6 | bellard | if (op > table_op)
|
3114 | b9adb4a6 | bellard | continue;
|
3115 | b9adb4a6 | bellard | |
3116 | b9adb4a6 | bellard | if ((insn & opcode->mask) != opcode->opcode
|
3117 | b9adb4a6 | bellard | || (opcode->flags & dialect) == 0)
|
3118 | b9adb4a6 | bellard | continue;
|
3119 | b9adb4a6 | bellard | |
3120 | b9adb4a6 | bellard | /* Make two passes over the operands. First see if any of them
|
3121 | b9adb4a6 | bellard | have extraction functions, and, if they do, make sure the
|
3122 | b9adb4a6 | bellard | instruction is valid. */
|
3123 | b9adb4a6 | bellard | invalid = 0;
|
3124 | b9adb4a6 | bellard | for (opindex = opcode->operands; *opindex != 0; opindex++) |
3125 | b9adb4a6 | bellard | { |
3126 | b9adb4a6 | bellard | operand = powerpc_operands + *opindex; |
3127 | b9adb4a6 | bellard | if (operand->extract)
|
3128 | b9adb4a6 | bellard | (*operand->extract) (insn, &invalid); |
3129 | b9adb4a6 | bellard | } |
3130 | b9adb4a6 | bellard | if (invalid)
|
3131 | b9adb4a6 | bellard | continue;
|
3132 | b9adb4a6 | bellard | |
3133 | b9adb4a6 | bellard | /* The instruction is valid. */
|
3134 | b9adb4a6 | bellard | fprintf(out, "%s", opcode->name);
|
3135 | b9adb4a6 | bellard | if (opcode->operands[0] != 0) |
3136 | b9adb4a6 | bellard | fprintf(out, "\t");
|
3137 | b9adb4a6 | bellard | |
3138 | b9adb4a6 | bellard | /* Now extract and print the operands. */
|
3139 | b9adb4a6 | bellard | need_comma = 0;
|
3140 | b9adb4a6 | bellard | need_paren = 0;
|
3141 | b9adb4a6 | bellard | for (opindex = opcode->operands; *opindex != 0; opindex++) |
3142 | b9adb4a6 | bellard | { |
3143 | 274da6b2 | bellard | int32_t value; |
3144 | b9adb4a6 | bellard | |
3145 | b9adb4a6 | bellard | operand = powerpc_operands + *opindex; |
3146 | b9adb4a6 | bellard | |
3147 | b9adb4a6 | bellard | /* Operands that are marked FAKE are simply ignored. We
|
3148 | b9adb4a6 | bellard | already made sure that the extract function considered
|
3149 | b9adb4a6 | bellard | the instruction to be valid. */
|
3150 | b9adb4a6 | bellard | if ((operand->flags & PPC_OPERAND_FAKE) != 0) |
3151 | b9adb4a6 | bellard | continue;
|
3152 | b9adb4a6 | bellard | |
3153 | b9adb4a6 | bellard | /* Extract the value from the instruction. */
|
3154 | b9adb4a6 | bellard | if (operand->extract)
|
3155 | b9adb4a6 | bellard | value = (*operand->extract) (insn, (int *) 0); |
3156 | b9adb4a6 | bellard | else
|
3157 | b9adb4a6 | bellard | { |
3158 | b9adb4a6 | bellard | value = (insn >> operand->shift) & ((1 << operand->bits) - 1); |
3159 | b9adb4a6 | bellard | if ((operand->flags & PPC_OPERAND_SIGNED) != 0 |
3160 | b9adb4a6 | bellard | && (value & (1 << (operand->bits - 1))) != 0) |
3161 | b9adb4a6 | bellard | value -= 1 << operand->bits;
|
3162 | b9adb4a6 | bellard | } |
3163 | b9adb4a6 | bellard | |
3164 | b9adb4a6 | bellard | /* If the operand is optional, and the value is zero, don't
|
3165 | b9adb4a6 | bellard | print anything. */
|
3166 | b9adb4a6 | bellard | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
3167 | b9adb4a6 | bellard | && (operand->flags & PPC_OPERAND_NEXT) == 0
|
3168 | b9adb4a6 | bellard | && value == 0)
|
3169 | b9adb4a6 | bellard | continue;
|
3170 | b9adb4a6 | bellard | |
3171 | b9adb4a6 | bellard | if (need_comma)
|
3172 | b9adb4a6 | bellard | { |
3173 | b9adb4a6 | bellard | fprintf(out, ",");
|
3174 | b9adb4a6 | bellard | need_comma = 0;
|
3175 | b9adb4a6 | bellard | } |
3176 | b9adb4a6 | bellard | |
3177 | b9adb4a6 | bellard | /* Print the operand as directed by the flags. */
|
3178 | b9adb4a6 | bellard | if ((operand->flags & PPC_OPERAND_GPR) != 0) |
3179 | 274da6b2 | bellard | fprintf(out, "r%d", value);
|
3180 | b9adb4a6 | bellard | else if ((operand->flags & PPC_OPERAND_FPR) != 0) |
3181 | 274da6b2 | bellard | fprintf(out, "f%d", value);
|
3182 | b9adb4a6 | bellard | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) |
3183 | 274da6b2 | bellard | fprintf(out, "%08X", memaddr + value);
|
3184 | b9adb4a6 | bellard | else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) |
3185 | 274da6b2 | bellard | fprintf(out, "%08X", value & 0xffffffff); |
3186 | b9adb4a6 | bellard | else if ((operand->flags & PPC_OPERAND_CR) == 0 |
3187 | b9adb4a6 | bellard | || (dialect & PPC_OPCODE_PPC) == 0)
|
3188 | 274da6b2 | bellard | fprintf(out, "%d", value);
|
3189 | b9adb4a6 | bellard | else
|
3190 | b9adb4a6 | bellard | { |
3191 | b9adb4a6 | bellard | if (operand->bits == 3) |
3192 | 274da6b2 | bellard | fprintf(out, "cr%d", value);
|
3193 | b9adb4a6 | bellard | else
|
3194 | b9adb4a6 | bellard | { |
3195 | b9adb4a6 | bellard | static const char *cbnames[4] = { "lt", "gt", "eq", "so" }; |
3196 | b9adb4a6 | bellard | int cr;
|
3197 | b9adb4a6 | bellard | int cc;
|
3198 | b9adb4a6 | bellard | |
3199 | b9adb4a6 | bellard | cr = value >> 2;
|
3200 | b9adb4a6 | bellard | if (cr != 0) |
3201 | b9adb4a6 | bellard | fprintf(out, "4*cr%d", cr);
|
3202 | b9adb4a6 | bellard | cc = value & 3;
|
3203 | b9adb4a6 | bellard | if (cc != 0) |
3204 | b9adb4a6 | bellard | { |
3205 | b9adb4a6 | bellard | if (cr != 0) |
3206 | b9adb4a6 | bellard | fprintf(out, "+");
|
3207 | b9adb4a6 | bellard | fprintf(out, "%s", cbnames[cc]);
|
3208 | b9adb4a6 | bellard | } |
3209 | b9adb4a6 | bellard | } |
3210 | b9adb4a6 | bellard | } |
3211 | b9adb4a6 | bellard | |
3212 | b9adb4a6 | bellard | if (need_paren)
|
3213 | b9adb4a6 | bellard | { |
3214 | b9adb4a6 | bellard | fprintf(out, ")");
|
3215 | b9adb4a6 | bellard | need_paren = 0;
|
3216 | b9adb4a6 | bellard | } |
3217 | b9adb4a6 | bellard | |
3218 | b9adb4a6 | bellard | if ((operand->flags & PPC_OPERAND_PARENS) == 0) |
3219 | b9adb4a6 | bellard | need_comma = 1;
|
3220 | b9adb4a6 | bellard | else
|
3221 | b9adb4a6 | bellard | { |
3222 | b9adb4a6 | bellard | fprintf(out, "(");
|
3223 | b9adb4a6 | bellard | need_paren = 1;
|
3224 | b9adb4a6 | bellard | } |
3225 | b9adb4a6 | bellard | } |
3226 | b9adb4a6 | bellard | |
3227 | b9adb4a6 | bellard | /* We have found and printed an instruction; return. */
|
3228 | b9adb4a6 | bellard | return 4; |
3229 | b9adb4a6 | bellard | } |
3230 | b9adb4a6 | bellard | |
3231 | b9adb4a6 | bellard | /* We could not find a match. */
|
3232 | 274da6b2 | bellard | fprintf(out, ".long 0x%x", insn);
|
3233 | b9adb4a6 | bellard | |
3234 | b9adb4a6 | bellard | return 4; |
3235 | b9adb4a6 | bellard | } |