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1 | 79aceca5 | bellard | /*
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2 | 79aceca5 | bellard | * PPC emulation micro-operations for qemu.
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3 | 79aceca5 | bellard | *
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4 | 79aceca5 | bellard | * Copyright (c) 2003 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | |
21 | a541f297 | bellard | //#define DEBUG_OP
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22 | a541f297 | bellard | |
23 | 79aceca5 | bellard | #include "config.h" |
24 | 79aceca5 | bellard | #include "exec.h" |
25 | 79aceca5 | bellard | |
26 | 79aceca5 | bellard | #define regs (env)
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27 | 79aceca5 | bellard | #define Ts0 (int32_t)T0
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28 | 79aceca5 | bellard | #define Ts1 (int32_t)T1
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29 | 79aceca5 | bellard | #define Ts2 (int32_t)T2
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30 | 79aceca5 | bellard | |
31 | 28b6751f | bellard | #define FT0 (env->ft0)
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32 | fb0eaffc | bellard | #define FT1 (env->ft1)
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33 | fb0eaffc | bellard | #define FT2 (env->ft2)
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34 | fb0eaffc | bellard | |
35 | fb0eaffc | bellard | #define FTS0 ((float)env->ft0) |
36 | fb0eaffc | bellard | #define FTS1 ((float)env->ft1) |
37 | fb0eaffc | bellard | #define FTS2 ((float)env->ft2) |
38 | 79aceca5 | bellard | |
39 | 9a64fbe4 | bellard | #define PPC_OP(name) void glue(op_, name)(void) |
40 | 79aceca5 | bellard | |
41 | 28b6751f | bellard | #define REG 0 |
42 | 28b6751f | bellard | #include "op_template.h" |
43 | 28b6751f | bellard | |
44 | 28b6751f | bellard | #define REG 1 |
45 | 28b6751f | bellard | #include "op_template.h" |
46 | 28b6751f | bellard | |
47 | 28b6751f | bellard | #define REG 2 |
48 | 28b6751f | bellard | #include "op_template.h" |
49 | 28b6751f | bellard | |
50 | 28b6751f | bellard | #define REG 3 |
51 | 28b6751f | bellard | #include "op_template.h" |
52 | 28b6751f | bellard | |
53 | 28b6751f | bellard | #define REG 4 |
54 | 28b6751f | bellard | #include "op_template.h" |
55 | 28b6751f | bellard | |
56 | 28b6751f | bellard | #define REG 5 |
57 | 28b6751f | bellard | #include "op_template.h" |
58 | 28b6751f | bellard | |
59 | 28b6751f | bellard | #define REG 6 |
60 | 28b6751f | bellard | #include "op_template.h" |
61 | 28b6751f | bellard | |
62 | 28b6751f | bellard | #define REG 7 |
63 | 28b6751f | bellard | #include "op_template.h" |
64 | 28b6751f | bellard | |
65 | 28b6751f | bellard | #define REG 8 |
66 | 28b6751f | bellard | #include "op_template.h" |
67 | 28b6751f | bellard | |
68 | 28b6751f | bellard | #define REG 9 |
69 | 28b6751f | bellard | #include "op_template.h" |
70 | 28b6751f | bellard | |
71 | 28b6751f | bellard | #define REG 10 |
72 | 28b6751f | bellard | #include "op_template.h" |
73 | 28b6751f | bellard | |
74 | 28b6751f | bellard | #define REG 11 |
75 | 28b6751f | bellard | #include "op_template.h" |
76 | 28b6751f | bellard | |
77 | 28b6751f | bellard | #define REG 12 |
78 | 28b6751f | bellard | #include "op_template.h" |
79 | 28b6751f | bellard | |
80 | 28b6751f | bellard | #define REG 13 |
81 | 28b6751f | bellard | #include "op_template.h" |
82 | 28b6751f | bellard | |
83 | 28b6751f | bellard | #define REG 14 |
84 | 28b6751f | bellard | #include "op_template.h" |
85 | 28b6751f | bellard | |
86 | 28b6751f | bellard | #define REG 15 |
87 | 28b6751f | bellard | #include "op_template.h" |
88 | 28b6751f | bellard | |
89 | 28b6751f | bellard | #define REG 16 |
90 | 28b6751f | bellard | #include "op_template.h" |
91 | 28b6751f | bellard | |
92 | 28b6751f | bellard | #define REG 17 |
93 | 28b6751f | bellard | #include "op_template.h" |
94 | 28b6751f | bellard | |
95 | 28b6751f | bellard | #define REG 18 |
96 | 28b6751f | bellard | #include "op_template.h" |
97 | 28b6751f | bellard | |
98 | 28b6751f | bellard | #define REG 19 |
99 | 28b6751f | bellard | #include "op_template.h" |
100 | 28b6751f | bellard | |
101 | 28b6751f | bellard | #define REG 20 |
102 | 28b6751f | bellard | #include "op_template.h" |
103 | 28b6751f | bellard | |
104 | 28b6751f | bellard | #define REG 21 |
105 | 28b6751f | bellard | #include "op_template.h" |
106 | 28b6751f | bellard | |
107 | 28b6751f | bellard | #define REG 22 |
108 | 28b6751f | bellard | #include "op_template.h" |
109 | 28b6751f | bellard | |
110 | 28b6751f | bellard | #define REG 23 |
111 | 28b6751f | bellard | #include "op_template.h" |
112 | 28b6751f | bellard | |
113 | 28b6751f | bellard | #define REG 24 |
114 | 28b6751f | bellard | #include "op_template.h" |
115 | 28b6751f | bellard | |
116 | 28b6751f | bellard | #define REG 25 |
117 | 28b6751f | bellard | #include "op_template.h" |
118 | 28b6751f | bellard | |
119 | 28b6751f | bellard | #define REG 26 |
120 | 28b6751f | bellard | #include "op_template.h" |
121 | 28b6751f | bellard | |
122 | 28b6751f | bellard | #define REG 27 |
123 | 28b6751f | bellard | #include "op_template.h" |
124 | 28b6751f | bellard | |
125 | 28b6751f | bellard | #define REG 28 |
126 | 28b6751f | bellard | #include "op_template.h" |
127 | 28b6751f | bellard | |
128 | 28b6751f | bellard | #define REG 29 |
129 | 28b6751f | bellard | #include "op_template.h" |
130 | 28b6751f | bellard | |
131 | 28b6751f | bellard | #define REG 30 |
132 | 28b6751f | bellard | #include "op_template.h" |
133 | 28b6751f | bellard | |
134 | 28b6751f | bellard | #define REG 31 |
135 | 28b6751f | bellard | #include "op_template.h" |
136 | 28b6751f | bellard | |
137 | 79aceca5 | bellard | /* PPC state maintenance operations */
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138 | 79aceca5 | bellard | /* set_Rc0 */
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139 | 79aceca5 | bellard | PPC_OP(set_Rc0) |
140 | 79aceca5 | bellard | { |
141 | 79aceca5 | bellard | uint32_t tmp; |
142 | 79aceca5 | bellard | |
143 | 79aceca5 | bellard | if (Ts0 < 0) { |
144 | 79aceca5 | bellard | tmp = 0x08;
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145 | 79aceca5 | bellard | } else if (Ts0 > 0) { |
146 | 79aceca5 | bellard | tmp = 0x04;
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147 | 79aceca5 | bellard | } else {
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148 | 79aceca5 | bellard | tmp = 0x02;
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149 | 79aceca5 | bellard | } |
150 | 9a64fbe4 | bellard | env->crf[0] = tmp;
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151 | 79aceca5 | bellard | RETURN(); |
152 | 79aceca5 | bellard | } |
153 | 79aceca5 | bellard | |
154 | 79aceca5 | bellard | PPC_OP(set_Rc0_ov) |
155 | 79aceca5 | bellard | { |
156 | 79aceca5 | bellard | uint32_t tmp; |
157 | 79aceca5 | bellard | |
158 | 79aceca5 | bellard | if (Ts0 < 0) { |
159 | 79aceca5 | bellard | tmp = 0x08;
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160 | 79aceca5 | bellard | } else if (Ts0 > 0) { |
161 | 79aceca5 | bellard | tmp = 0x04;
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162 | 79aceca5 | bellard | } else {
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163 | 79aceca5 | bellard | tmp = 0x02;
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164 | 79aceca5 | bellard | } |
165 | 79aceca5 | bellard | tmp |= xer_ov; |
166 | 9a64fbe4 | bellard | env->crf[0] = tmp;
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167 | 79aceca5 | bellard | RETURN(); |
168 | 79aceca5 | bellard | } |
169 | 79aceca5 | bellard | |
170 | 79aceca5 | bellard | /* reset_Rc0 */
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171 | 79aceca5 | bellard | PPC_OP(reset_Rc0) |
172 | 79aceca5 | bellard | { |
173 | 9a64fbe4 | bellard | env->crf[0] = 0x02 | xer_ov; |
174 | 79aceca5 | bellard | RETURN(); |
175 | 79aceca5 | bellard | } |
176 | 79aceca5 | bellard | |
177 | 79aceca5 | bellard | /* set_Rc0_1 */
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178 | 79aceca5 | bellard | PPC_OP(set_Rc0_1) |
179 | 79aceca5 | bellard | { |
180 | 9a64fbe4 | bellard | env->crf[0] = 0x04 | xer_ov; |
181 | 79aceca5 | bellard | RETURN(); |
182 | 79aceca5 | bellard | } |
183 | 79aceca5 | bellard | |
184 | fb0eaffc | bellard | /* Set Rc1 (for floating point arithmetic) */
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185 | fb0eaffc | bellard | PPC_OP(set_Rc1) |
186 | fb0eaffc | bellard | { |
187 | fb0eaffc | bellard | env->crf[1] = regs->fpscr[7]; |
188 | fb0eaffc | bellard | RETURN(); |
189 | fb0eaffc | bellard | } |
190 | fb0eaffc | bellard | |
191 | 9a64fbe4 | bellard | /* Constants load */
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192 | 79aceca5 | bellard | PPC_OP(set_T0) |
193 | 79aceca5 | bellard | { |
194 | 79aceca5 | bellard | T0 = PARAM(1);
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195 | 79aceca5 | bellard | RETURN(); |
196 | 79aceca5 | bellard | } |
197 | 79aceca5 | bellard | |
198 | 79aceca5 | bellard | PPC_OP(set_T1) |
199 | 79aceca5 | bellard | { |
200 | 79aceca5 | bellard | T1 = PARAM(1);
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201 | 79aceca5 | bellard | RETURN(); |
202 | 79aceca5 | bellard | } |
203 | 79aceca5 | bellard | |
204 | 79aceca5 | bellard | PPC_OP(set_T2) |
205 | 79aceca5 | bellard | { |
206 | 79aceca5 | bellard | T2 = PARAM(1);
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207 | 79aceca5 | bellard | RETURN(); |
208 | 79aceca5 | bellard | } |
209 | 79aceca5 | bellard | |
210 | 9a64fbe4 | bellard | /* Generate exceptions */
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211 | 9fddaa0c | bellard | PPC_OP(raise_exception_err) |
212 | 79aceca5 | bellard | { |
213 | 9fddaa0c | bellard | do_raise_exception_err(PARAM(1), PARAM(2)); |
214 | 9a64fbe4 | bellard | } |
215 | 9a64fbe4 | bellard | |
216 | 9fddaa0c | bellard | PPC_OP(raise_exception) |
217 | 9a64fbe4 | bellard | { |
218 | 9fddaa0c | bellard | do_raise_exception(PARAM(1));
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219 | 9a64fbe4 | bellard | } |
220 | 9a64fbe4 | bellard | |
221 | 9fddaa0c | bellard | PPC_OP(update_nip) |
222 | 9a64fbe4 | bellard | { |
223 | 004bc62c | bellard | env->nip = PARAM(1);
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224 | 9a64fbe4 | bellard | } |
225 | 9a64fbe4 | bellard | |
226 | a541f297 | bellard | PPC_OP(debug) |
227 | a541f297 | bellard | { |
228 | a541f297 | bellard | env->nip = PARAM(1);
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229 | a541f297 | bellard | #if defined (DEBUG_OP)
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230 | a541f297 | bellard | dump_state(); |
231 | a541f297 | bellard | #endif
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232 | 9fddaa0c | bellard | do_raise_exception(EXCP_DEBUG); |
233 | a541f297 | bellard | RETURN(); |
234 | a541f297 | bellard | } |
235 | a541f297 | bellard | |
236 | 9a64fbe4 | bellard | /* Segment registers load and store with immediate index */
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237 | 9a64fbe4 | bellard | PPC_OP(load_srin) |
238 | 9a64fbe4 | bellard | { |
239 | 9a64fbe4 | bellard | T0 = regs->sr[T1 >> 28];
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240 | 9a64fbe4 | bellard | RETURN(); |
241 | 9a64fbe4 | bellard | } |
242 | 9a64fbe4 | bellard | |
243 | 9a64fbe4 | bellard | PPC_OP(store_srin) |
244 | 9a64fbe4 | bellard | { |
245 | 4b3686fa | bellard | do_store_sr(T1 >> 28);
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246 | 9a64fbe4 | bellard | RETURN(); |
247 | 9a64fbe4 | bellard | } |
248 | 9a64fbe4 | bellard | |
249 | 9a64fbe4 | bellard | PPC_OP(load_sdr1) |
250 | 9a64fbe4 | bellard | { |
251 | 9a64fbe4 | bellard | T0 = regs->sdr1; |
252 | 79aceca5 | bellard | RETURN(); |
253 | 79aceca5 | bellard | } |
254 | 79aceca5 | bellard | |
255 | 9a64fbe4 | bellard | PPC_OP(store_sdr1) |
256 | 79aceca5 | bellard | { |
257 | 9a64fbe4 | bellard | regs->sdr1 = T0; |
258 | 79aceca5 | bellard | RETURN(); |
259 | 79aceca5 | bellard | } |
260 | 79aceca5 | bellard | |
261 | 79aceca5 | bellard | PPC_OP(exit_tb) |
262 | 79aceca5 | bellard | { |
263 | 79aceca5 | bellard | EXIT_TB(); |
264 | 79aceca5 | bellard | } |
265 | 79aceca5 | bellard | |
266 | 9a64fbe4 | bellard | /* Load/store special registers */
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267 | 79aceca5 | bellard | PPC_OP(load_cr) |
268 | 79aceca5 | bellard | { |
269 | 9a64fbe4 | bellard | do_load_cr(); |
270 | 79aceca5 | bellard | RETURN(); |
271 | 79aceca5 | bellard | } |
272 | 79aceca5 | bellard | |
273 | 79aceca5 | bellard | PPC_OP(store_cr) |
274 | 79aceca5 | bellard | { |
275 | 9a64fbe4 | bellard | do_store_cr(PARAM(1));
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276 | 79aceca5 | bellard | RETURN(); |
277 | 79aceca5 | bellard | } |
278 | 79aceca5 | bellard | |
279 | 79aceca5 | bellard | PPC_OP(load_xer_cr) |
280 | 79aceca5 | bellard | { |
281 | 79aceca5 | bellard | T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1); |
282 | 79aceca5 | bellard | RETURN(); |
283 | 79aceca5 | bellard | } |
284 | 79aceca5 | bellard | |
285 | 79aceca5 | bellard | PPC_OP(clear_xer_cr) |
286 | 79aceca5 | bellard | { |
287 | 79aceca5 | bellard | xer_so = 0;
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288 | 79aceca5 | bellard | xer_ov = 0;
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289 | 79aceca5 | bellard | xer_ca = 0;
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290 | 79aceca5 | bellard | RETURN(); |
291 | 79aceca5 | bellard | } |
292 | 79aceca5 | bellard | |
293 | 79aceca5 | bellard | PPC_OP(load_xer_bc) |
294 | 79aceca5 | bellard | { |
295 | 9a64fbe4 | bellard | T1 = xer_bc; |
296 | 79aceca5 | bellard | RETURN(); |
297 | 79aceca5 | bellard | } |
298 | 79aceca5 | bellard | |
299 | 79aceca5 | bellard | PPC_OP(load_xer) |
300 | 79aceca5 | bellard | { |
301 | 9a64fbe4 | bellard | do_load_xer(); |
302 | 79aceca5 | bellard | RETURN(); |
303 | 79aceca5 | bellard | } |
304 | 79aceca5 | bellard | |
305 | 79aceca5 | bellard | PPC_OP(store_xer) |
306 | 79aceca5 | bellard | { |
307 | 9a64fbe4 | bellard | do_store_xer(); |
308 | 79aceca5 | bellard | RETURN(); |
309 | 79aceca5 | bellard | } |
310 | 79aceca5 | bellard | |
311 | 79aceca5 | bellard | PPC_OP(load_msr) |
312 | 79aceca5 | bellard | { |
313 | 9a64fbe4 | bellard | do_load_msr(); |
314 | 79aceca5 | bellard | RETURN(); |
315 | 79aceca5 | bellard | } |
316 | 79aceca5 | bellard | |
317 | 79aceca5 | bellard | PPC_OP(store_msr) |
318 | 79aceca5 | bellard | { |
319 | 9a64fbe4 | bellard | do_store_msr(); |
320 | 9a64fbe4 | bellard | RETURN(); |
321 | 9a64fbe4 | bellard | } |
322 | 9a64fbe4 | bellard | |
323 | 9a64fbe4 | bellard | /* SPR */
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324 | 9a64fbe4 | bellard | PPC_OP(load_spr) |
325 | 9a64fbe4 | bellard | { |
326 | 9a64fbe4 | bellard | T0 = regs->spr[PARAM(1)];
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327 | 9a64fbe4 | bellard | RETURN(); |
328 | 9a64fbe4 | bellard | } |
329 | 9a64fbe4 | bellard | |
330 | 9a64fbe4 | bellard | PPC_OP(store_spr) |
331 | 9a64fbe4 | bellard | { |
332 | 9a64fbe4 | bellard | regs->spr[PARAM(1)] = T0;
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333 | 79aceca5 | bellard | RETURN(); |
334 | 79aceca5 | bellard | } |
335 | 79aceca5 | bellard | |
336 | 79aceca5 | bellard | PPC_OP(load_lr) |
337 | 79aceca5 | bellard | { |
338 | 9a64fbe4 | bellard | T0 = regs->lr; |
339 | 9a64fbe4 | bellard | RETURN(); |
340 | 9a64fbe4 | bellard | } |
341 | 9a64fbe4 | bellard | |
342 | 9a64fbe4 | bellard | PPC_OP(store_lr) |
343 | 9a64fbe4 | bellard | { |
344 | 9a64fbe4 | bellard | regs->lr = T0; |
345 | 9a64fbe4 | bellard | RETURN(); |
346 | 9a64fbe4 | bellard | } |
347 | 9a64fbe4 | bellard | |
348 | 9a64fbe4 | bellard | PPC_OP(load_ctr) |
349 | 9a64fbe4 | bellard | { |
350 | 9a64fbe4 | bellard | T0 = regs->ctr; |
351 | 9a64fbe4 | bellard | RETURN(); |
352 | 9a64fbe4 | bellard | } |
353 | 9a64fbe4 | bellard | |
354 | 9a64fbe4 | bellard | PPC_OP(store_ctr) |
355 | 9a64fbe4 | bellard | { |
356 | 9a64fbe4 | bellard | regs->ctr = T0; |
357 | 9a64fbe4 | bellard | RETURN(); |
358 | 9a64fbe4 | bellard | } |
359 | 9a64fbe4 | bellard | |
360 | 9fddaa0c | bellard | PPC_OP(load_tbl) |
361 | 9a64fbe4 | bellard | { |
362 | 9fddaa0c | bellard | T0 = cpu_ppc_load_tbl(regs); |
363 | 9a64fbe4 | bellard | RETURN(); |
364 | 9a64fbe4 | bellard | } |
365 | 9a64fbe4 | bellard | |
366 | 9fddaa0c | bellard | PPC_OP(load_tbu) |
367 | 9a64fbe4 | bellard | { |
368 | 9fddaa0c | bellard | T0 = cpu_ppc_load_tbu(regs); |
369 | 9a64fbe4 | bellard | RETURN(); |
370 | 9a64fbe4 | bellard | } |
371 | 9a64fbe4 | bellard | |
372 | 9fddaa0c | bellard | PPC_OP(store_tbl) |
373 | 9a64fbe4 | bellard | { |
374 | 9fddaa0c | bellard | cpu_ppc_store_tbl(regs, T0); |
375 | 79aceca5 | bellard | RETURN(); |
376 | 79aceca5 | bellard | } |
377 | 79aceca5 | bellard | |
378 | 9fddaa0c | bellard | PPC_OP(store_tbu) |
379 | 9a64fbe4 | bellard | { |
380 | 9fddaa0c | bellard | cpu_ppc_store_tbu(regs, T0); |
381 | 9a64fbe4 | bellard | RETURN(); |
382 | 9a64fbe4 | bellard | } |
383 | 9a64fbe4 | bellard | |
384 | 9fddaa0c | bellard | PPC_OP(load_decr) |
385 | 9a64fbe4 | bellard | { |
386 | 9fddaa0c | bellard | T0 = cpu_ppc_load_decr(regs); |
387 | 9a64fbe4 | bellard | } |
388 | 9fddaa0c | bellard | |
389 | 9fddaa0c | bellard | PPC_OP(store_decr) |
390 | 9fddaa0c | bellard | { |
391 | 9fddaa0c | bellard | cpu_ppc_store_decr(regs, T0); |
392 | 9a64fbe4 | bellard | RETURN(); |
393 | 9a64fbe4 | bellard | } |
394 | 9a64fbe4 | bellard | |
395 | 9a64fbe4 | bellard | PPC_OP(load_ibat) |
396 | 9a64fbe4 | bellard | { |
397 | 9a64fbe4 | bellard | T0 = regs->IBAT[PARAM(1)][PARAM(2)]; |
398 | 9a64fbe4 | bellard | } |
399 | 9a64fbe4 | bellard | |
400 | 9a64fbe4 | bellard | PPC_OP(store_ibat) |
401 | 9a64fbe4 | bellard | { |
402 | 4b3686fa | bellard | do_store_ibat(PARAM(1), PARAM(2)); |
403 | 9a64fbe4 | bellard | } |
404 | 9a64fbe4 | bellard | |
405 | 9a64fbe4 | bellard | PPC_OP(load_dbat) |
406 | 9a64fbe4 | bellard | { |
407 | 9a64fbe4 | bellard | T0 = regs->DBAT[PARAM(1)][PARAM(2)]; |
408 | 9a64fbe4 | bellard | } |
409 | 9a64fbe4 | bellard | |
410 | 9a64fbe4 | bellard | PPC_OP(store_dbat) |
411 | 9a64fbe4 | bellard | { |
412 | 4b3686fa | bellard | do_store_dbat(PARAM(1), PARAM(2)); |
413 | 9a64fbe4 | bellard | } |
414 | 9a64fbe4 | bellard | |
415 | fb0eaffc | bellard | /* FPSCR */
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416 | fb0eaffc | bellard | PPC_OP(load_fpscr) |
417 | fb0eaffc | bellard | { |
418 | fb0eaffc | bellard | do_load_fpscr(); |
419 | fb0eaffc | bellard | RETURN(); |
420 | fb0eaffc | bellard | } |
421 | fb0eaffc | bellard | |
422 | fb0eaffc | bellard | PPC_OP(store_fpscr) |
423 | fb0eaffc | bellard | { |
424 | fb0eaffc | bellard | do_store_fpscr(PARAM(1));
|
425 | fb0eaffc | bellard | RETURN(); |
426 | fb0eaffc | bellard | } |
427 | fb0eaffc | bellard | |
428 | fb0eaffc | bellard | PPC_OP(reset_scrfx) |
429 | fb0eaffc | bellard | { |
430 | fb0eaffc | bellard | regs->fpscr[7] &= ~0x8; |
431 | fb0eaffc | bellard | RETURN(); |
432 | fb0eaffc | bellard | } |
433 | fb0eaffc | bellard | |
434 | 79aceca5 | bellard | /* crf operations */
|
435 | 79aceca5 | bellard | PPC_OP(getbit_T0) |
436 | 79aceca5 | bellard | { |
437 | 79aceca5 | bellard | T0 = (T0 >> PARAM(1)) & 1; |
438 | 79aceca5 | bellard | RETURN(); |
439 | 79aceca5 | bellard | } |
440 | 79aceca5 | bellard | |
441 | 79aceca5 | bellard | PPC_OP(getbit_T1) |
442 | 79aceca5 | bellard | { |
443 | 79aceca5 | bellard | T1 = (T1 >> PARAM(1)) & 1; |
444 | 79aceca5 | bellard | RETURN(); |
445 | 79aceca5 | bellard | } |
446 | 79aceca5 | bellard | |
447 | 79aceca5 | bellard | PPC_OP(setcrfbit) |
448 | 79aceca5 | bellard | { |
449 | 79aceca5 | bellard | T1 = (T1 & PARAM(1)) | (T0 << PARAM(2)); |
450 | 79aceca5 | bellard | RETURN(); |
451 | 79aceca5 | bellard | } |
452 | 79aceca5 | bellard | |
453 | 79aceca5 | bellard | /* Branch */
|
454 | 9a64fbe4 | bellard | #define EIP regs->nip
|
455 | 9a64fbe4 | bellard | |
456 | e98a6e40 | bellard | PPC_OP(setlr) |
457 | e98a6e40 | bellard | { |
458 | e98a6e40 | bellard | regs->lr = PARAM1; |
459 | e98a6e40 | bellard | } |
460 | e98a6e40 | bellard | |
461 | e98a6e40 | bellard | PPC_OP(b) |
462 | e98a6e40 | bellard | { |
463 | e98a6e40 | bellard | JUMP_TB(b1, PARAM1, 0, PARAM2);
|
464 | e98a6e40 | bellard | } |
465 | e98a6e40 | bellard | |
466 | e98a6e40 | bellard | PPC_OP(b_T1) |
467 | e98a6e40 | bellard | { |
468 | e98a6e40 | bellard | regs->nip = T1; |
469 | e98a6e40 | bellard | } |
470 | e98a6e40 | bellard | |
471 | e98a6e40 | bellard | PPC_OP(btest) |
472 | e98a6e40 | bellard | { |
473 | e98a6e40 | bellard | if (T0) {
|
474 | e98a6e40 | bellard | JUMP_TB(btest, PARAM1, 0, PARAM2);
|
475 | e98a6e40 | bellard | } else {
|
476 | e98a6e40 | bellard | JUMP_TB(btest, PARAM1, 1, PARAM3);
|
477 | e98a6e40 | bellard | } |
478 | e98a6e40 | bellard | RETURN(); |
479 | e98a6e40 | bellard | } |
480 | e98a6e40 | bellard | |
481 | e98a6e40 | bellard | PPC_OP(btest_T1) |
482 | e98a6e40 | bellard | { |
483 | e98a6e40 | bellard | if (T0) {
|
484 | e98a6e40 | bellard | regs->nip = T1 & ~3;
|
485 | e98a6e40 | bellard | } else {
|
486 | e98a6e40 | bellard | regs->nip = PARAM1; |
487 | e98a6e40 | bellard | } |
488 | e98a6e40 | bellard | RETURN(); |
489 | e98a6e40 | bellard | } |
490 | e98a6e40 | bellard | |
491 | e98a6e40 | bellard | PPC_OP(movl_T1_ctr) |
492 | e98a6e40 | bellard | { |
493 | e98a6e40 | bellard | T1 = regs->ctr; |
494 | e98a6e40 | bellard | } |
495 | e98a6e40 | bellard | |
496 | e98a6e40 | bellard | PPC_OP(movl_T1_lr) |
497 | e98a6e40 | bellard | { |
498 | e98a6e40 | bellard | T1 = regs->lr; |
499 | e98a6e40 | bellard | } |
500 | e98a6e40 | bellard | |
501 | e98a6e40 | bellard | /* tests with result in T0 */
|
502 | e98a6e40 | bellard | |
503 | e98a6e40 | bellard | PPC_OP(test_ctr) |
504 | e98a6e40 | bellard | { |
505 | b88e4a9a | bellard | T0 = regs->ctr; |
506 | e98a6e40 | bellard | } |
507 | e98a6e40 | bellard | |
508 | e98a6e40 | bellard | PPC_OP(test_ctr_true) |
509 | e98a6e40 | bellard | { |
510 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0); |
511 | e98a6e40 | bellard | } |
512 | e98a6e40 | bellard | |
513 | e98a6e40 | bellard | PPC_OP(test_ctr_false) |
514 | e98a6e40 | bellard | { |
515 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0); |
516 | e98a6e40 | bellard | } |
517 | e98a6e40 | bellard | |
518 | e98a6e40 | bellard | PPC_OP(test_ctrz) |
519 | e98a6e40 | bellard | { |
520 | e98a6e40 | bellard | T0 = (regs->ctr == 0);
|
521 | e98a6e40 | bellard | } |
522 | e98a6e40 | bellard | |
523 | e98a6e40 | bellard | PPC_OP(test_ctrz_true) |
524 | e98a6e40 | bellard | { |
525 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0); |
526 | e98a6e40 | bellard | } |
527 | e98a6e40 | bellard | |
528 | e98a6e40 | bellard | PPC_OP(test_ctrz_false) |
529 | e98a6e40 | bellard | { |
530 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0); |
531 | e98a6e40 | bellard | } |
532 | e98a6e40 | bellard | |
533 | e98a6e40 | bellard | PPC_OP(test_true) |
534 | e98a6e40 | bellard | { |
535 | b88e4a9a | bellard | T0 = (T0 & PARAM(1));
|
536 | e98a6e40 | bellard | } |
537 | e98a6e40 | bellard | |
538 | e98a6e40 | bellard | PPC_OP(test_false) |
539 | e98a6e40 | bellard | { |
540 | e98a6e40 | bellard | T0 = ((T0 & PARAM(1)) == 0); |
541 | e98a6e40 | bellard | } |
542 | 79aceca5 | bellard | |
543 | 79aceca5 | bellard | /* CTR maintenance */
|
544 | 79aceca5 | bellard | PPC_OP(dec_ctr) |
545 | 79aceca5 | bellard | { |
546 | 9a64fbe4 | bellard | regs->ctr--; |
547 | 79aceca5 | bellard | RETURN(); |
548 | 79aceca5 | bellard | } |
549 | 79aceca5 | bellard | |
550 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
551 | 79aceca5 | bellard | /* add */
|
552 | 79aceca5 | bellard | PPC_OP(add) |
553 | 79aceca5 | bellard | { |
554 | 79aceca5 | bellard | T0 += T1; |
555 | 79aceca5 | bellard | RETURN(); |
556 | 79aceca5 | bellard | } |
557 | 79aceca5 | bellard | |
558 | 79aceca5 | bellard | PPC_OP(addo) |
559 | 79aceca5 | bellard | { |
560 | 79aceca5 | bellard | T2 = T0; |
561 | 79aceca5 | bellard | T0 += T1; |
562 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
563 | 79aceca5 | bellard | xer_so = 1;
|
564 | 79aceca5 | bellard | xer_ov = 1;
|
565 | 79aceca5 | bellard | } else {
|
566 | 79aceca5 | bellard | xer_ov = 0;
|
567 | 79aceca5 | bellard | } |
568 | 79aceca5 | bellard | RETURN(); |
569 | 79aceca5 | bellard | } |
570 | 79aceca5 | bellard | |
571 | 79aceca5 | bellard | /* add carrying */
|
572 | 79aceca5 | bellard | PPC_OP(addc) |
573 | 79aceca5 | bellard | { |
574 | 79aceca5 | bellard | T2 = T0; |
575 | 79aceca5 | bellard | T0 += T1; |
576 | 79aceca5 | bellard | if (T0 < T2) {
|
577 | 79aceca5 | bellard | xer_ca = 1;
|
578 | 79aceca5 | bellard | } else {
|
579 | 79aceca5 | bellard | xer_ca = 0;
|
580 | 79aceca5 | bellard | } |
581 | 79aceca5 | bellard | RETURN(); |
582 | 79aceca5 | bellard | } |
583 | 79aceca5 | bellard | |
584 | 79aceca5 | bellard | PPC_OP(addco) |
585 | 79aceca5 | bellard | { |
586 | 79aceca5 | bellard | T2 = T0; |
587 | 79aceca5 | bellard | T0 += T1; |
588 | 79aceca5 | bellard | if (T0 < T2) {
|
589 | 79aceca5 | bellard | xer_ca = 1;
|
590 | 79aceca5 | bellard | } else {
|
591 | 79aceca5 | bellard | xer_ca = 0;
|
592 | 79aceca5 | bellard | } |
593 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
594 | 79aceca5 | bellard | xer_so = 1;
|
595 | 79aceca5 | bellard | xer_ov = 1;
|
596 | 79aceca5 | bellard | } else {
|
597 | 79aceca5 | bellard | xer_ov = 0;
|
598 | 79aceca5 | bellard | } |
599 | 79aceca5 | bellard | RETURN(); |
600 | 79aceca5 | bellard | } |
601 | 79aceca5 | bellard | |
602 | 79aceca5 | bellard | /* add extended */
|
603 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
604 | 79aceca5 | bellard | PPC_OP(adde) |
605 | 79aceca5 | bellard | { |
606 | 79aceca5 | bellard | T2 = T0; |
607 | 79aceca5 | bellard | T0 += T1 + xer_ca; |
608 | 79aceca5 | bellard | if (T0 < T2 || (xer_ca == 1 && T0 == T2)) { |
609 | 79aceca5 | bellard | xer_ca = 1;
|
610 | 79aceca5 | bellard | } else {
|
611 | 79aceca5 | bellard | xer_ca = 0;
|
612 | 79aceca5 | bellard | } |
613 | 79aceca5 | bellard | RETURN(); |
614 | 79aceca5 | bellard | } |
615 | 79aceca5 | bellard | |
616 | 79aceca5 | bellard | PPC_OP(addeo) |
617 | 79aceca5 | bellard | { |
618 | 79aceca5 | bellard | T2 = T0; |
619 | 79aceca5 | bellard | T0 += T1 + xer_ca; |
620 | 79aceca5 | bellard | if (T0 < T2 || (xer_ca == 1 && T0 == T2)) { |
621 | 79aceca5 | bellard | xer_ca = 1;
|
622 | 79aceca5 | bellard | } else {
|
623 | 79aceca5 | bellard | xer_ca = 0;
|
624 | 79aceca5 | bellard | } |
625 | 79aceca5 | bellard | if ((T2 ^ T1 ^ (-1)) & (T2 ^ T0) & (1 << 31)) { |
626 | 79aceca5 | bellard | xer_so = 1;
|
627 | 79aceca5 | bellard | xer_ov = 1;
|
628 | 79aceca5 | bellard | } else {
|
629 | 79aceca5 | bellard | xer_ov = 0;
|
630 | 79aceca5 | bellard | } |
631 | 79aceca5 | bellard | RETURN(); |
632 | 79aceca5 | bellard | } |
633 | 79aceca5 | bellard | |
634 | 79aceca5 | bellard | /* add immediate */
|
635 | 79aceca5 | bellard | PPC_OP(addi) |
636 | 79aceca5 | bellard | { |
637 | 79aceca5 | bellard | T0 += PARAM(1);
|
638 | 79aceca5 | bellard | RETURN(); |
639 | 79aceca5 | bellard | } |
640 | 79aceca5 | bellard | |
641 | 79aceca5 | bellard | /* add immediate carrying */
|
642 | 79aceca5 | bellard | PPC_OP(addic) |
643 | 79aceca5 | bellard | { |
644 | 79aceca5 | bellard | T1 = T0; |
645 | 79aceca5 | bellard | T0 += PARAM(1);
|
646 | 79aceca5 | bellard | if (T0 < T1) {
|
647 | 79aceca5 | bellard | xer_ca = 1;
|
648 | 79aceca5 | bellard | } else {
|
649 | 79aceca5 | bellard | xer_ca = 0;
|
650 | 79aceca5 | bellard | } |
651 | 79aceca5 | bellard | RETURN(); |
652 | 79aceca5 | bellard | } |
653 | 79aceca5 | bellard | |
654 | 79aceca5 | bellard | /* add to minus one extended */
|
655 | 79aceca5 | bellard | PPC_OP(addme) |
656 | 79aceca5 | bellard | { |
657 | 79aceca5 | bellard | T1 = T0; |
658 | 79aceca5 | bellard | T0 += xer_ca + (-1);
|
659 | 79aceca5 | bellard | if (T1 != 0) |
660 | 79aceca5 | bellard | xer_ca = 1;
|
661 | 79aceca5 | bellard | RETURN(); |
662 | 79aceca5 | bellard | } |
663 | 79aceca5 | bellard | |
664 | 79aceca5 | bellard | PPC_OP(addmeo) |
665 | 79aceca5 | bellard | { |
666 | 79aceca5 | bellard | T1 = T0; |
667 | 79aceca5 | bellard | T0 += xer_ca + (-1);
|
668 | 79aceca5 | bellard | if (T1 & (T1 ^ T0) & (1 << 31)) { |
669 | 79aceca5 | bellard | xer_so = 1;
|
670 | 79aceca5 | bellard | xer_ov = 1;
|
671 | 79aceca5 | bellard | } else {
|
672 | 79aceca5 | bellard | xer_ov = 0;
|
673 | 79aceca5 | bellard | } |
674 | 79aceca5 | bellard | if (T1 != 0) |
675 | 79aceca5 | bellard | xer_ca = 1;
|
676 | 79aceca5 | bellard | RETURN(); |
677 | 79aceca5 | bellard | } |
678 | 79aceca5 | bellard | |
679 | 79aceca5 | bellard | /* add to zero extended */
|
680 | 79aceca5 | bellard | PPC_OP(addze) |
681 | 79aceca5 | bellard | { |
682 | 79aceca5 | bellard | T1 = T0; |
683 | 79aceca5 | bellard | T0 += xer_ca; |
684 | 79aceca5 | bellard | if (T0 < T1) {
|
685 | 79aceca5 | bellard | xer_ca = 1;
|
686 | 79aceca5 | bellard | } else {
|
687 | 79aceca5 | bellard | xer_ca = 0;
|
688 | 79aceca5 | bellard | } |
689 | 79aceca5 | bellard | RETURN(); |
690 | 79aceca5 | bellard | } |
691 | 79aceca5 | bellard | |
692 | 79aceca5 | bellard | PPC_OP(addzeo) |
693 | 79aceca5 | bellard | { |
694 | 79aceca5 | bellard | T1 = T0; |
695 | 79aceca5 | bellard | T0 += xer_ca; |
696 | 79aceca5 | bellard | if ((T1 ^ (-1)) & (T1 ^ T0) & (1 << 31)) { |
697 | 79aceca5 | bellard | xer_so = 1;
|
698 | 79aceca5 | bellard | xer_ov = 1;
|
699 | 79aceca5 | bellard | } else {
|
700 | 79aceca5 | bellard | xer_ov = 0;
|
701 | 79aceca5 | bellard | } |
702 | 79aceca5 | bellard | if (T0 < T1) {
|
703 | 79aceca5 | bellard | xer_ca = 1;
|
704 | 79aceca5 | bellard | } else {
|
705 | 79aceca5 | bellard | xer_ca = 0;
|
706 | 79aceca5 | bellard | } |
707 | 79aceca5 | bellard | RETURN(); |
708 | 79aceca5 | bellard | } |
709 | 79aceca5 | bellard | |
710 | 79aceca5 | bellard | /* divide word */
|
711 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
712 | 79aceca5 | bellard | PPC_OP(divw) |
713 | 79aceca5 | bellard | { |
714 | 79aceca5 | bellard | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { |
715 | 79aceca5 | bellard | Ts0 = (-1) * (T0 >> 31); |
716 | 79aceca5 | bellard | } else {
|
717 | 79aceca5 | bellard | Ts0 /= Ts1; |
718 | 79aceca5 | bellard | } |
719 | 79aceca5 | bellard | RETURN(); |
720 | 79aceca5 | bellard | } |
721 | 79aceca5 | bellard | |
722 | 79aceca5 | bellard | PPC_OP(divwo) |
723 | 79aceca5 | bellard | { |
724 | 79aceca5 | bellard | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { |
725 | 79aceca5 | bellard | xer_so = 1;
|
726 | 79aceca5 | bellard | xer_ov = 1;
|
727 | 79aceca5 | bellard | T0 = (-1) * (T0 >> 31); |
728 | 79aceca5 | bellard | } else {
|
729 | 79aceca5 | bellard | xer_ov = 0;
|
730 | 79aceca5 | bellard | Ts0 /= Ts1; |
731 | 79aceca5 | bellard | } |
732 | 79aceca5 | bellard | RETURN(); |
733 | 79aceca5 | bellard | } |
734 | 79aceca5 | bellard | |
735 | 79aceca5 | bellard | /* divide word unsigned */
|
736 | 79aceca5 | bellard | PPC_OP(divwu) |
737 | 79aceca5 | bellard | { |
738 | 79aceca5 | bellard | if (T1 == 0) { |
739 | 79aceca5 | bellard | T0 = 0;
|
740 | 79aceca5 | bellard | } else {
|
741 | 79aceca5 | bellard | T0 /= T1; |
742 | 79aceca5 | bellard | } |
743 | 79aceca5 | bellard | RETURN(); |
744 | 79aceca5 | bellard | } |
745 | 79aceca5 | bellard | |
746 | 79aceca5 | bellard | PPC_OP(divwuo) |
747 | 79aceca5 | bellard | { |
748 | 79aceca5 | bellard | if (T1 == 0) { |
749 | 79aceca5 | bellard | xer_so = 1;
|
750 | 79aceca5 | bellard | xer_ov = 1;
|
751 | 79aceca5 | bellard | T0 = 0;
|
752 | 79aceca5 | bellard | } else {
|
753 | 79aceca5 | bellard | xer_ov = 0;
|
754 | 79aceca5 | bellard | T0 /= T1; |
755 | 79aceca5 | bellard | } |
756 | 79aceca5 | bellard | RETURN(); |
757 | 79aceca5 | bellard | } |
758 | 79aceca5 | bellard | |
759 | 79aceca5 | bellard | /* multiply high word */
|
760 | 79aceca5 | bellard | PPC_OP(mulhw) |
761 | 79aceca5 | bellard | { |
762 | 79aceca5 | bellard | Ts0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32;
|
763 | 79aceca5 | bellard | RETURN(); |
764 | 79aceca5 | bellard | } |
765 | 79aceca5 | bellard | |
766 | 79aceca5 | bellard | /* multiply high word unsigned */
|
767 | 79aceca5 | bellard | PPC_OP(mulhwu) |
768 | 79aceca5 | bellard | { |
769 | 79aceca5 | bellard | T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32;
|
770 | 79aceca5 | bellard | RETURN(); |
771 | 79aceca5 | bellard | } |
772 | 79aceca5 | bellard | |
773 | 79aceca5 | bellard | /* multiply low immediate */
|
774 | 79aceca5 | bellard | PPC_OP(mulli) |
775 | 79aceca5 | bellard | { |
776 | 79aceca5 | bellard | Ts0 *= SPARAM(1);
|
777 | 79aceca5 | bellard | RETURN(); |
778 | 79aceca5 | bellard | } |
779 | 79aceca5 | bellard | |
780 | 79aceca5 | bellard | /* multiply low word */
|
781 | 79aceca5 | bellard | PPC_OP(mullw) |
782 | 79aceca5 | bellard | { |
783 | 79aceca5 | bellard | T0 *= T1; |
784 | 79aceca5 | bellard | RETURN(); |
785 | 79aceca5 | bellard | } |
786 | 79aceca5 | bellard | |
787 | 79aceca5 | bellard | PPC_OP(mullwo) |
788 | 79aceca5 | bellard | { |
789 | 79aceca5 | bellard | int64_t res = (int64_t)Ts0 * (int64_t)Ts1; |
790 | 79aceca5 | bellard | |
791 | 79aceca5 | bellard | if ((int32_t)res != res) {
|
792 | 79aceca5 | bellard | xer_ov = 1;
|
793 | 79aceca5 | bellard | xer_so = 1;
|
794 | 79aceca5 | bellard | } else {
|
795 | 79aceca5 | bellard | xer_ov = 0;
|
796 | 79aceca5 | bellard | } |
797 | 79aceca5 | bellard | Ts0 = res; |
798 | 79aceca5 | bellard | RETURN(); |
799 | 79aceca5 | bellard | } |
800 | 79aceca5 | bellard | |
801 | 79aceca5 | bellard | /* negate */
|
802 | 79aceca5 | bellard | PPC_OP(neg) |
803 | 79aceca5 | bellard | { |
804 | 79aceca5 | bellard | if (T0 != 0x80000000) { |
805 | 79aceca5 | bellard | Ts0 = -Ts0; |
806 | 79aceca5 | bellard | } |
807 | 79aceca5 | bellard | RETURN(); |
808 | 79aceca5 | bellard | } |
809 | 79aceca5 | bellard | |
810 | 79aceca5 | bellard | PPC_OP(nego) |
811 | 79aceca5 | bellard | { |
812 | 79aceca5 | bellard | if (T0 == 0x80000000) { |
813 | 79aceca5 | bellard | xer_ov = 1;
|
814 | 79aceca5 | bellard | xer_so = 1;
|
815 | 79aceca5 | bellard | } else {
|
816 | 79aceca5 | bellard | xer_ov = 0;
|
817 | 79aceca5 | bellard | Ts0 = -Ts0; |
818 | 79aceca5 | bellard | } |
819 | 79aceca5 | bellard | RETURN(); |
820 | 79aceca5 | bellard | } |
821 | 79aceca5 | bellard | |
822 | 79aceca5 | bellard | /* substract from */
|
823 | 79aceca5 | bellard | PPC_OP(subf) |
824 | 79aceca5 | bellard | { |
825 | 79aceca5 | bellard | T0 = T1 - T0; |
826 | 79aceca5 | bellard | RETURN(); |
827 | 79aceca5 | bellard | } |
828 | 79aceca5 | bellard | |
829 | 79aceca5 | bellard | PPC_OP(subfo) |
830 | 79aceca5 | bellard | { |
831 | 79aceca5 | bellard | T2 = T0; |
832 | 79aceca5 | bellard | T0 = T1 - T0; |
833 | 79aceca5 | bellard | if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) { |
834 | 79aceca5 | bellard | xer_so = 1;
|
835 | 79aceca5 | bellard | xer_ov = 1;
|
836 | 79aceca5 | bellard | } else {
|
837 | 79aceca5 | bellard | xer_ov = 0;
|
838 | 79aceca5 | bellard | } |
839 | 79aceca5 | bellard | RETURN(); |
840 | 79aceca5 | bellard | } |
841 | 79aceca5 | bellard | |
842 | 79aceca5 | bellard | /* substract from carrying */
|
843 | 79aceca5 | bellard | PPC_OP(subfc) |
844 | 79aceca5 | bellard | { |
845 | 79aceca5 | bellard | T0 = T1 - T0; |
846 | 79aceca5 | bellard | if (T0 <= T1) {
|
847 | 79aceca5 | bellard | xer_ca = 1;
|
848 | 79aceca5 | bellard | } else {
|
849 | 79aceca5 | bellard | xer_ca = 0;
|
850 | 79aceca5 | bellard | } |
851 | 79aceca5 | bellard | RETURN(); |
852 | 79aceca5 | bellard | } |
853 | 79aceca5 | bellard | |
854 | 79aceca5 | bellard | PPC_OP(subfco) |
855 | 79aceca5 | bellard | { |
856 | 79aceca5 | bellard | T2 = T0; |
857 | 79aceca5 | bellard | T0 = T1 - T0; |
858 | 79aceca5 | bellard | if (T0 <= T1) {
|
859 | 79aceca5 | bellard | xer_ca = 1;
|
860 | 79aceca5 | bellard | } else {
|
861 | 79aceca5 | bellard | xer_ca = 0;
|
862 | 79aceca5 | bellard | } |
863 | 79aceca5 | bellard | if (((~T2) ^ T1 ^ (-1)) & ((~T2) ^ T0) & (1 << 31)) { |
864 | 79aceca5 | bellard | xer_so = 1;
|
865 | 79aceca5 | bellard | xer_ov = 1;
|
866 | 79aceca5 | bellard | } else {
|
867 | 79aceca5 | bellard | xer_ov = 0;
|
868 | 79aceca5 | bellard | } |
869 | 79aceca5 | bellard | RETURN(); |
870 | 79aceca5 | bellard | } |
871 | 79aceca5 | bellard | |
872 | 79aceca5 | bellard | /* substract from extended */
|
873 | 79aceca5 | bellard | /* candidate for helper (too long) */
|
874 | 79aceca5 | bellard | PPC_OP(subfe) |
875 | 79aceca5 | bellard | { |
876 | 79aceca5 | bellard | T0 = T1 + ~T0 + xer_ca; |
877 | 79aceca5 | bellard | if (T0 < T1 || (xer_ca == 1 && T0 == T1)) { |
878 | 79aceca5 | bellard | xer_ca = 1;
|
879 | 79aceca5 | bellard | } else {
|
880 | 79aceca5 | bellard | xer_ca = 0;
|
881 | 79aceca5 | bellard | } |
882 | 79aceca5 | bellard | RETURN(); |
883 | 79aceca5 | bellard | } |
884 | 79aceca5 | bellard | |
885 | 79aceca5 | bellard | PPC_OP(subfeo) |
886 | 79aceca5 | bellard | { |
887 | 79aceca5 | bellard | T2 = T0; |
888 | 79aceca5 | bellard | T0 = T1 + ~T0 + xer_ca; |
889 | 79aceca5 | bellard | if ((~T2 ^ T1 ^ (-1)) & (~T2 ^ T0) & (1 << 31)) { |
890 | 79aceca5 | bellard | xer_so = 1;
|
891 | 79aceca5 | bellard | xer_ov = 1;
|
892 | 79aceca5 | bellard | } else {
|
893 | 79aceca5 | bellard | xer_ov = 0;
|
894 | 79aceca5 | bellard | } |
895 | 79aceca5 | bellard | if (T0 < T1 || (xer_ca == 1 && T0 == T1)) { |
896 | 79aceca5 | bellard | xer_ca = 1;
|
897 | 79aceca5 | bellard | } else {
|
898 | 79aceca5 | bellard | xer_ca = 0;
|
899 | 79aceca5 | bellard | } |
900 | 79aceca5 | bellard | RETURN(); |
901 | 79aceca5 | bellard | } |
902 | 79aceca5 | bellard | |
903 | 79aceca5 | bellard | /* substract from immediate carrying */
|
904 | 79aceca5 | bellard | PPC_OP(subfic) |
905 | 79aceca5 | bellard | { |
906 | 79aceca5 | bellard | T0 = PARAM(1) + ~T0 + 1; |
907 | 79aceca5 | bellard | if (T0 <= PARAM(1)) { |
908 | 79aceca5 | bellard | xer_ca = 1;
|
909 | 79aceca5 | bellard | } else {
|
910 | 79aceca5 | bellard | xer_ca = 0;
|
911 | 79aceca5 | bellard | } |
912 | 79aceca5 | bellard | RETURN(); |
913 | 79aceca5 | bellard | } |
914 | 79aceca5 | bellard | |
915 | 79aceca5 | bellard | /* substract from minus one extended */
|
916 | 79aceca5 | bellard | PPC_OP(subfme) |
917 | 79aceca5 | bellard | { |
918 | 79aceca5 | bellard | T0 = ~T0 + xer_ca - 1;
|
919 | 79aceca5 | bellard | |
920 | 79aceca5 | bellard | if (T0 != -1) |
921 | 79aceca5 | bellard | xer_ca = 1;
|
922 | 79aceca5 | bellard | RETURN(); |
923 | 79aceca5 | bellard | } |
924 | 79aceca5 | bellard | |
925 | 79aceca5 | bellard | PPC_OP(subfmeo) |
926 | 79aceca5 | bellard | { |
927 | 79aceca5 | bellard | T1 = T0; |
928 | 79aceca5 | bellard | T0 = ~T0 + xer_ca - 1;
|
929 | 79aceca5 | bellard | if (~T1 & (~T1 ^ T0) & (1 << 31)) { |
930 | 79aceca5 | bellard | xer_so = 1;
|
931 | 79aceca5 | bellard | xer_ov = 1;
|
932 | 79aceca5 | bellard | } else {
|
933 | 79aceca5 | bellard | xer_ov = 0;
|
934 | 79aceca5 | bellard | } |
935 | 79aceca5 | bellard | if (T1 != -1) |
936 | 79aceca5 | bellard | xer_ca = 1;
|
937 | 79aceca5 | bellard | RETURN(); |
938 | 79aceca5 | bellard | } |
939 | 79aceca5 | bellard | |
940 | 79aceca5 | bellard | /* substract from zero extended */
|
941 | 79aceca5 | bellard | PPC_OP(subfze) |
942 | 79aceca5 | bellard | { |
943 | 79aceca5 | bellard | T1 = ~T0; |
944 | 79aceca5 | bellard | T0 = T1 + xer_ca; |
945 | 79aceca5 | bellard | if (T0 < T1) {
|
946 | 79aceca5 | bellard | xer_ca = 1;
|
947 | 79aceca5 | bellard | } else {
|
948 | 79aceca5 | bellard | xer_ca = 0;
|
949 | 79aceca5 | bellard | } |
950 | 79aceca5 | bellard | RETURN(); |
951 | 79aceca5 | bellard | } |
952 | 79aceca5 | bellard | |
953 | 79aceca5 | bellard | PPC_OP(subfzeo) |
954 | 79aceca5 | bellard | { |
955 | 79aceca5 | bellard | T1 = T0; |
956 | 79aceca5 | bellard | T0 = ~T0 + xer_ca; |
957 | 79aceca5 | bellard | if ((~T1 ^ (-1)) & ((~T1) ^ T0) & (1 << 31)) { |
958 | 79aceca5 | bellard | xer_ov = 1;
|
959 | 79aceca5 | bellard | xer_so = 1;
|
960 | 79aceca5 | bellard | } else {
|
961 | 79aceca5 | bellard | xer_ov = 0;
|
962 | 79aceca5 | bellard | } |
963 | 79aceca5 | bellard | if (T0 < ~T1) {
|
964 | 79aceca5 | bellard | xer_ca = 1;
|
965 | 79aceca5 | bellard | } else {
|
966 | 79aceca5 | bellard | xer_ca = 0;
|
967 | 79aceca5 | bellard | } |
968 | 79aceca5 | bellard | RETURN(); |
969 | 79aceca5 | bellard | } |
970 | 79aceca5 | bellard | |
971 | 79aceca5 | bellard | /*** Integer comparison ***/
|
972 | 79aceca5 | bellard | /* compare */
|
973 | 79aceca5 | bellard | PPC_OP(cmp) |
974 | 79aceca5 | bellard | { |
975 | 79aceca5 | bellard | if (Ts0 < Ts1) {
|
976 | 79aceca5 | bellard | T0 = 0x08;
|
977 | 79aceca5 | bellard | } else if (Ts0 > Ts1) { |
978 | 79aceca5 | bellard | T0 = 0x04;
|
979 | 79aceca5 | bellard | } else {
|
980 | 79aceca5 | bellard | T0 = 0x02;
|
981 | 79aceca5 | bellard | } |
982 | 79aceca5 | bellard | RETURN(); |
983 | 79aceca5 | bellard | } |
984 | 79aceca5 | bellard | |
985 | 79aceca5 | bellard | /* compare immediate */
|
986 | 79aceca5 | bellard | PPC_OP(cmpi) |
987 | 79aceca5 | bellard | { |
988 | 79aceca5 | bellard | if (Ts0 < SPARAM(1)) { |
989 | 79aceca5 | bellard | T0 = 0x08;
|
990 | 79aceca5 | bellard | } else if (Ts0 > SPARAM(1)) { |
991 | 79aceca5 | bellard | T0 = 0x04;
|
992 | 79aceca5 | bellard | } else {
|
993 | 79aceca5 | bellard | T0 = 0x02;
|
994 | 79aceca5 | bellard | } |
995 | 79aceca5 | bellard | RETURN(); |
996 | 79aceca5 | bellard | } |
997 | 79aceca5 | bellard | |
998 | 79aceca5 | bellard | /* compare logical */
|
999 | 79aceca5 | bellard | PPC_OP(cmpl) |
1000 | 79aceca5 | bellard | { |
1001 | 79aceca5 | bellard | if (T0 < T1) {
|
1002 | 79aceca5 | bellard | T0 = 0x08;
|
1003 | 79aceca5 | bellard | } else if (T0 > T1) { |
1004 | 79aceca5 | bellard | T0 = 0x04;
|
1005 | 79aceca5 | bellard | } else {
|
1006 | 79aceca5 | bellard | T0 = 0x02;
|
1007 | 79aceca5 | bellard | } |
1008 | 79aceca5 | bellard | RETURN(); |
1009 | 79aceca5 | bellard | } |
1010 | 79aceca5 | bellard | |
1011 | 79aceca5 | bellard | /* compare logical immediate */
|
1012 | 79aceca5 | bellard | PPC_OP(cmpli) |
1013 | 79aceca5 | bellard | { |
1014 | 79aceca5 | bellard | if (T0 < PARAM(1)) { |
1015 | 79aceca5 | bellard | T0 = 0x08;
|
1016 | 79aceca5 | bellard | } else if (T0 > PARAM(1)) { |
1017 | 79aceca5 | bellard | T0 = 0x04;
|
1018 | 79aceca5 | bellard | } else {
|
1019 | 79aceca5 | bellard | T0 = 0x02;
|
1020 | 79aceca5 | bellard | } |
1021 | 79aceca5 | bellard | RETURN(); |
1022 | 79aceca5 | bellard | } |
1023 | 79aceca5 | bellard | |
1024 | 79aceca5 | bellard | /*** Integer logical ***/
|
1025 | 79aceca5 | bellard | /* and */
|
1026 | 79aceca5 | bellard | PPC_OP(and) |
1027 | 79aceca5 | bellard | { |
1028 | 79aceca5 | bellard | T0 &= T1; |
1029 | 79aceca5 | bellard | RETURN(); |
1030 | 79aceca5 | bellard | } |
1031 | 79aceca5 | bellard | |
1032 | 79aceca5 | bellard | /* andc */
|
1033 | 79aceca5 | bellard | PPC_OP(andc) |
1034 | 79aceca5 | bellard | { |
1035 | 79aceca5 | bellard | T0 &= ~T1; |
1036 | 79aceca5 | bellard | RETURN(); |
1037 | 79aceca5 | bellard | } |
1038 | 79aceca5 | bellard | |
1039 | 79aceca5 | bellard | /* andi. */
|
1040 | 79aceca5 | bellard | PPC_OP(andi_) |
1041 | 79aceca5 | bellard | { |
1042 | 79aceca5 | bellard | T0 &= PARAM(1);
|
1043 | 79aceca5 | bellard | RETURN(); |
1044 | 79aceca5 | bellard | } |
1045 | 79aceca5 | bellard | |
1046 | 79aceca5 | bellard | /* count leading zero */
|
1047 | 79aceca5 | bellard | PPC_OP(cntlzw) |
1048 | 79aceca5 | bellard | { |
1049 | 79aceca5 | bellard | T1 = T0; |
1050 | 79aceca5 | bellard | for (T0 = 32; T1 > 0; T0--) |
1051 | 79aceca5 | bellard | T1 = T1 >> 1;
|
1052 | 79aceca5 | bellard | RETURN(); |
1053 | 79aceca5 | bellard | } |
1054 | 79aceca5 | bellard | |
1055 | 79aceca5 | bellard | /* eqv */
|
1056 | 79aceca5 | bellard | PPC_OP(eqv) |
1057 | 79aceca5 | bellard | { |
1058 | 79aceca5 | bellard | T0 = ~(T0 ^ T1); |
1059 | 79aceca5 | bellard | RETURN(); |
1060 | 79aceca5 | bellard | } |
1061 | 79aceca5 | bellard | |
1062 | 79aceca5 | bellard | /* extend sign byte */
|
1063 | 79aceca5 | bellard | PPC_OP(extsb) |
1064 | 79aceca5 | bellard | { |
1065 | 79aceca5 | bellard | Ts0 = s_ext8(Ts0); |
1066 | 79aceca5 | bellard | RETURN(); |
1067 | 79aceca5 | bellard | } |
1068 | 79aceca5 | bellard | |
1069 | 79aceca5 | bellard | /* extend sign half word */
|
1070 | 79aceca5 | bellard | PPC_OP(extsh) |
1071 | 79aceca5 | bellard | { |
1072 | 79aceca5 | bellard | Ts0 = s_ext16(Ts0); |
1073 | 79aceca5 | bellard | RETURN(); |
1074 | 79aceca5 | bellard | } |
1075 | 79aceca5 | bellard | |
1076 | 79aceca5 | bellard | /* nand */
|
1077 | 79aceca5 | bellard | PPC_OP(nand) |
1078 | 79aceca5 | bellard | { |
1079 | 79aceca5 | bellard | T0 = ~(T0 & T1); |
1080 | 79aceca5 | bellard | RETURN(); |
1081 | 79aceca5 | bellard | } |
1082 | 79aceca5 | bellard | |
1083 | 79aceca5 | bellard | /* nor */
|
1084 | 79aceca5 | bellard | PPC_OP(nor) |
1085 | 79aceca5 | bellard | { |
1086 | 79aceca5 | bellard | T0 = ~(T0 | T1); |
1087 | 79aceca5 | bellard | RETURN(); |
1088 | 79aceca5 | bellard | } |
1089 | 79aceca5 | bellard | |
1090 | 79aceca5 | bellard | /* or */
|
1091 | 79aceca5 | bellard | PPC_OP(or) |
1092 | 79aceca5 | bellard | { |
1093 | 79aceca5 | bellard | T0 |= T1; |
1094 | 79aceca5 | bellard | RETURN(); |
1095 | 79aceca5 | bellard | } |
1096 | 79aceca5 | bellard | |
1097 | 79aceca5 | bellard | /* orc */
|
1098 | 79aceca5 | bellard | PPC_OP(orc) |
1099 | 79aceca5 | bellard | { |
1100 | 79aceca5 | bellard | T0 |= ~T1; |
1101 | 79aceca5 | bellard | RETURN(); |
1102 | 79aceca5 | bellard | } |
1103 | 79aceca5 | bellard | |
1104 | 79aceca5 | bellard | /* ori */
|
1105 | 79aceca5 | bellard | PPC_OP(ori) |
1106 | 79aceca5 | bellard | { |
1107 | 79aceca5 | bellard | T0 |= PARAM(1);
|
1108 | 79aceca5 | bellard | RETURN(); |
1109 | 79aceca5 | bellard | } |
1110 | 79aceca5 | bellard | |
1111 | 79aceca5 | bellard | /* xor */
|
1112 | 79aceca5 | bellard | PPC_OP(xor) |
1113 | 79aceca5 | bellard | { |
1114 | 79aceca5 | bellard | T0 ^= T1; |
1115 | 79aceca5 | bellard | RETURN(); |
1116 | 79aceca5 | bellard | } |
1117 | 79aceca5 | bellard | |
1118 | 79aceca5 | bellard | /* xori */
|
1119 | 79aceca5 | bellard | PPC_OP(xori) |
1120 | 79aceca5 | bellard | { |
1121 | 79aceca5 | bellard | T0 ^= PARAM(1);
|
1122 | 79aceca5 | bellard | RETURN(); |
1123 | 79aceca5 | bellard | } |
1124 | 79aceca5 | bellard | |
1125 | 79aceca5 | bellard | /*** Integer rotate ***/
|
1126 | 79aceca5 | bellard | /* rotate left word immediate then mask insert */
|
1127 | 79aceca5 | bellard | PPC_OP(rlwimi) |
1128 | 79aceca5 | bellard | { |
1129 | fb0eaffc | bellard | T0 = (rotl(T0, PARAM(1)) & PARAM(2)) | (T1 & PARAM(3)); |
1130 | 79aceca5 | bellard | RETURN(); |
1131 | 79aceca5 | bellard | } |
1132 | 79aceca5 | bellard | |
1133 | 79aceca5 | bellard | /* rotate left immediate then and with mask insert */
|
1134 | 79aceca5 | bellard | PPC_OP(rotlwi) |
1135 | 79aceca5 | bellard | { |
1136 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1));
|
1137 | 79aceca5 | bellard | RETURN(); |
1138 | 79aceca5 | bellard | } |
1139 | 79aceca5 | bellard | |
1140 | 79aceca5 | bellard | PPC_OP(slwi) |
1141 | 79aceca5 | bellard | { |
1142 | 79aceca5 | bellard | T0 = T0 << PARAM(1);
|
1143 | 79aceca5 | bellard | RETURN(); |
1144 | 79aceca5 | bellard | } |
1145 | 79aceca5 | bellard | |
1146 | 79aceca5 | bellard | PPC_OP(srwi) |
1147 | 79aceca5 | bellard | { |
1148 | 79aceca5 | bellard | T0 = T0 >> PARAM(1);
|
1149 | 79aceca5 | bellard | RETURN(); |
1150 | 79aceca5 | bellard | } |
1151 | 79aceca5 | bellard | |
1152 | 79aceca5 | bellard | /* rotate left word then and with mask insert */
|
1153 | 79aceca5 | bellard | PPC_OP(rlwinm) |
1154 | 79aceca5 | bellard | { |
1155 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1)) & PARAM(2); |
1156 | 79aceca5 | bellard | RETURN(); |
1157 | 79aceca5 | bellard | } |
1158 | 79aceca5 | bellard | |
1159 | 79aceca5 | bellard | PPC_OP(rotl) |
1160 | 79aceca5 | bellard | { |
1161 | 79aceca5 | bellard | T0 = rotl(T0, T1); |
1162 | 79aceca5 | bellard | RETURN(); |
1163 | 79aceca5 | bellard | } |
1164 | 79aceca5 | bellard | |
1165 | 79aceca5 | bellard | PPC_OP(rlwnm) |
1166 | 79aceca5 | bellard | { |
1167 | 79aceca5 | bellard | T0 = rotl(T0, T1) & PARAM(1);
|
1168 | 79aceca5 | bellard | RETURN(); |
1169 | 79aceca5 | bellard | } |
1170 | 79aceca5 | bellard | |
1171 | 79aceca5 | bellard | /*** Integer shift ***/
|
1172 | 79aceca5 | bellard | /* shift left word */
|
1173 | 79aceca5 | bellard | PPC_OP(slw) |
1174 | 79aceca5 | bellard | { |
1175 | 79aceca5 | bellard | if (T1 & 0x20) { |
1176 | 79aceca5 | bellard | T0 = 0;
|
1177 | 79aceca5 | bellard | } else {
|
1178 | 79aceca5 | bellard | T0 = T0 << T1; |
1179 | 79aceca5 | bellard | } |
1180 | 79aceca5 | bellard | RETURN(); |
1181 | 79aceca5 | bellard | } |
1182 | 79aceca5 | bellard | |
1183 | 79aceca5 | bellard | /* shift right algebraic word */
|
1184 | 79aceca5 | bellard | PPC_OP(sraw) |
1185 | 79aceca5 | bellard | { |
1186 | 9a64fbe4 | bellard | do_sraw(); |
1187 | 79aceca5 | bellard | RETURN(); |
1188 | 79aceca5 | bellard | } |
1189 | 79aceca5 | bellard | |
1190 | 79aceca5 | bellard | /* shift right algebraic word immediate */
|
1191 | 79aceca5 | bellard | PPC_OP(srawi) |
1192 | 79aceca5 | bellard | { |
1193 | 79aceca5 | bellard | Ts1 = Ts0; |
1194 | 79aceca5 | bellard | Ts0 = Ts0 >> PARAM(1);
|
1195 | 79aceca5 | bellard | if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) { |
1196 | 79aceca5 | bellard | xer_ca = 1;
|
1197 | 79aceca5 | bellard | } else {
|
1198 | 79aceca5 | bellard | xer_ca = 0;
|
1199 | 79aceca5 | bellard | } |
1200 | 79aceca5 | bellard | RETURN(); |
1201 | 79aceca5 | bellard | } |
1202 | 79aceca5 | bellard | |
1203 | 79aceca5 | bellard | /* shift right word */
|
1204 | 79aceca5 | bellard | PPC_OP(srw) |
1205 | 79aceca5 | bellard | { |
1206 | 79aceca5 | bellard | if (T1 & 0x20) { |
1207 | 79aceca5 | bellard | T0 = 0;
|
1208 | 79aceca5 | bellard | } else {
|
1209 | 79aceca5 | bellard | T0 = T0 >> T1; |
1210 | 79aceca5 | bellard | } |
1211 | 79aceca5 | bellard | RETURN(); |
1212 | 79aceca5 | bellard | } |
1213 | 79aceca5 | bellard | |
1214 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
1215 | 9a64fbe4 | bellard | /* fadd - fadd. */
|
1216 | 9a64fbe4 | bellard | PPC_OP(fadd) |
1217 | 79aceca5 | bellard | { |
1218 | 9a64fbe4 | bellard | FT0 += FT1; |
1219 | 79aceca5 | bellard | RETURN(); |
1220 | 79aceca5 | bellard | } |
1221 | 79aceca5 | bellard | |
1222 | 9a64fbe4 | bellard | /* fadds - fadds. */
|
1223 | 9a64fbe4 | bellard | PPC_OP(fadds) |
1224 | 79aceca5 | bellard | { |
1225 | 9a64fbe4 | bellard | FTS0 += FTS1; |
1226 | 79aceca5 | bellard | RETURN(); |
1227 | 79aceca5 | bellard | } |
1228 | 79aceca5 | bellard | |
1229 | 9a64fbe4 | bellard | /* fsub - fsub. */
|
1230 | 9a64fbe4 | bellard | PPC_OP(fsub) |
1231 | 79aceca5 | bellard | { |
1232 | 9a64fbe4 | bellard | FT0 -= FT1; |
1233 | 79aceca5 | bellard | RETURN(); |
1234 | 79aceca5 | bellard | } |
1235 | 79aceca5 | bellard | |
1236 | 9a64fbe4 | bellard | /* fsubs - fsubs. */
|
1237 | 9a64fbe4 | bellard | PPC_OP(fsubs) |
1238 | 79aceca5 | bellard | { |
1239 | 9a64fbe4 | bellard | FTS0 -= FTS1; |
1240 | 79aceca5 | bellard | RETURN(); |
1241 | 79aceca5 | bellard | } |
1242 | 79aceca5 | bellard | |
1243 | 9a64fbe4 | bellard | /* fmul - fmul. */
|
1244 | 9a64fbe4 | bellard | PPC_OP(fmul) |
1245 | 79aceca5 | bellard | { |
1246 | 9a64fbe4 | bellard | FT0 *= FT1; |
1247 | 79aceca5 | bellard | RETURN(); |
1248 | 79aceca5 | bellard | } |
1249 | 79aceca5 | bellard | |
1250 | 9a64fbe4 | bellard | /* fmuls - fmuls. */
|
1251 | 9a64fbe4 | bellard | PPC_OP(fmuls) |
1252 | 79aceca5 | bellard | { |
1253 | 9a64fbe4 | bellard | FTS0 *= FTS1; |
1254 | 79aceca5 | bellard | RETURN(); |
1255 | 79aceca5 | bellard | } |
1256 | 79aceca5 | bellard | |
1257 | 9a64fbe4 | bellard | /* fdiv - fdiv. */
|
1258 | 9a64fbe4 | bellard | PPC_OP(fdiv) |
1259 | 79aceca5 | bellard | { |
1260 | 9a64fbe4 | bellard | FT0 /= FT1; |
1261 | 79aceca5 | bellard | RETURN(); |
1262 | 79aceca5 | bellard | } |
1263 | 79aceca5 | bellard | |
1264 | 9a64fbe4 | bellard | /* fdivs - fdivs. */
|
1265 | 9a64fbe4 | bellard | PPC_OP(fdivs) |
1266 | 79aceca5 | bellard | { |
1267 | 9a64fbe4 | bellard | FTS0 /= FTS1; |
1268 | 79aceca5 | bellard | RETURN(); |
1269 | 79aceca5 | bellard | } |
1270 | 28b6751f | bellard | |
1271 | 9a64fbe4 | bellard | /* fsqrt - fsqrt. */
|
1272 | 9a64fbe4 | bellard | PPC_OP(fsqrt) |
1273 | 28b6751f | bellard | { |
1274 | 9a64fbe4 | bellard | do_fsqrt(); |
1275 | 9a64fbe4 | bellard | RETURN(); |
1276 | 28b6751f | bellard | } |
1277 | 28b6751f | bellard | |
1278 | 9a64fbe4 | bellard | /* fsqrts - fsqrts. */
|
1279 | 9a64fbe4 | bellard | PPC_OP(fsqrts) |
1280 | 28b6751f | bellard | { |
1281 | 9a64fbe4 | bellard | do_fsqrts(); |
1282 | 9a64fbe4 | bellard | RETURN(); |
1283 | 28b6751f | bellard | } |
1284 | 28b6751f | bellard | |
1285 | 9a64fbe4 | bellard | /* fres - fres. */
|
1286 | 9a64fbe4 | bellard | PPC_OP(fres) |
1287 | 28b6751f | bellard | { |
1288 | 9a64fbe4 | bellard | do_fres(); |
1289 | 9a64fbe4 | bellard | RETURN(); |
1290 | 28b6751f | bellard | } |
1291 | 28b6751f | bellard | |
1292 | 9a64fbe4 | bellard | /* frsqrte - frsqrte. */
|
1293 | 9a64fbe4 | bellard | PPC_OP(frsqrte) |
1294 | 28b6751f | bellard | { |
1295 | 9a64fbe4 | bellard | do_fsqrte(); |
1296 | 9a64fbe4 | bellard | RETURN(); |
1297 | 28b6751f | bellard | } |
1298 | 28b6751f | bellard | |
1299 | 9a64fbe4 | bellard | /* fsel - fsel. */
|
1300 | 9a64fbe4 | bellard | PPC_OP(fsel) |
1301 | 28b6751f | bellard | { |
1302 | 9a64fbe4 | bellard | do_fsel(); |
1303 | 9a64fbe4 | bellard | RETURN(); |
1304 | 28b6751f | bellard | } |
1305 | 28b6751f | bellard | |
1306 | 9a64fbe4 | bellard | /*** Floating-Point multiply-and-add ***/
|
1307 | 9a64fbe4 | bellard | /* fmadd - fmadd. */
|
1308 | 9a64fbe4 | bellard | PPC_OP(fmadd) |
1309 | 28b6751f | bellard | { |
1310 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) + FT2; |
1311 | 9a64fbe4 | bellard | RETURN(); |
1312 | 28b6751f | bellard | } |
1313 | 28b6751f | bellard | |
1314 | 9a64fbe4 | bellard | /* fmadds - fmadds. */
|
1315 | 9a64fbe4 | bellard | PPC_OP(fmadds) |
1316 | 28b6751f | bellard | { |
1317 | 9a64fbe4 | bellard | FTS0 = (FTS0 * FTS1) + FTS2; |
1318 | 9a64fbe4 | bellard | RETURN(); |
1319 | 28b6751f | bellard | } |
1320 | 28b6751f | bellard | |
1321 | 9a64fbe4 | bellard | /* fmsub - fmsub. */
|
1322 | 9a64fbe4 | bellard | PPC_OP(fmsub) |
1323 | 28b6751f | bellard | { |
1324 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) - FT2; |
1325 | 9a64fbe4 | bellard | RETURN(); |
1326 | 28b6751f | bellard | } |
1327 | 28b6751f | bellard | |
1328 | 9a64fbe4 | bellard | /* fmsubs - fmsubs. */
|
1329 | 9a64fbe4 | bellard | PPC_OP(fmsubs) |
1330 | 28b6751f | bellard | { |
1331 | 9a64fbe4 | bellard | FTS0 = (FTS0 * FTS1) - FTS2; |
1332 | 9a64fbe4 | bellard | RETURN(); |
1333 | 28b6751f | bellard | } |
1334 | 28b6751f | bellard | |
1335 | 9a64fbe4 | bellard | /* fnmadd - fnmadd. - fnmadds - fnmadds. */
|
1336 | 9a64fbe4 | bellard | PPC_OP(fnmadd) |
1337 | 28b6751f | bellard | { |
1338 | 4b3686fa | bellard | do_fnmadd(); |
1339 | 9a64fbe4 | bellard | RETURN(); |
1340 | 28b6751f | bellard | } |
1341 | 28b6751f | bellard | |
1342 | 9a64fbe4 | bellard | /* fnmadds - fnmadds. */
|
1343 | 9a64fbe4 | bellard | PPC_OP(fnmadds) |
1344 | 28b6751f | bellard | { |
1345 | 1ef59d0a | bellard | do_fnmadds(); |
1346 | 9a64fbe4 | bellard | RETURN(); |
1347 | 28b6751f | bellard | } |
1348 | 28b6751f | bellard | |
1349 | 9a64fbe4 | bellard | /* fnmsub - fnmsub. */
|
1350 | 9a64fbe4 | bellard | PPC_OP(fnmsub) |
1351 | 28b6751f | bellard | { |
1352 | 4b3686fa | bellard | do_fnmsub(); |
1353 | 9a64fbe4 | bellard | RETURN(); |
1354 | 28b6751f | bellard | } |
1355 | 28b6751f | bellard | |
1356 | 9a64fbe4 | bellard | /* fnmsubs - fnmsubs. */
|
1357 | 9a64fbe4 | bellard | PPC_OP(fnmsubs) |
1358 | 28b6751f | bellard | { |
1359 | 1ef59d0a | bellard | do_fnmsubs(); |
1360 | 9a64fbe4 | bellard | RETURN(); |
1361 | 28b6751f | bellard | } |
1362 | 28b6751f | bellard | |
1363 | 9a64fbe4 | bellard | /*** Floating-Point round & convert ***/
|
1364 | 9a64fbe4 | bellard | /* frsp - frsp. */
|
1365 | 9a64fbe4 | bellard | PPC_OP(frsp) |
1366 | 28b6751f | bellard | { |
1367 | 9a64fbe4 | bellard | FT0 = FTS0; |
1368 | 9a64fbe4 | bellard | RETURN(); |
1369 | 28b6751f | bellard | } |
1370 | 28b6751f | bellard | |
1371 | 9a64fbe4 | bellard | /* fctiw - fctiw. */
|
1372 | 9a64fbe4 | bellard | PPC_OP(fctiw) |
1373 | 28b6751f | bellard | { |
1374 | 9a64fbe4 | bellard | do_fctiw(); |
1375 | 9a64fbe4 | bellard | RETURN(); |
1376 | 28b6751f | bellard | } |
1377 | 28b6751f | bellard | |
1378 | 9a64fbe4 | bellard | /* fctiwz - fctiwz. */
|
1379 | 9a64fbe4 | bellard | PPC_OP(fctiwz) |
1380 | 28b6751f | bellard | { |
1381 | 9a64fbe4 | bellard | do_fctiwz(); |
1382 | 9a64fbe4 | bellard | RETURN(); |
1383 | 28b6751f | bellard | } |
1384 | 28b6751f | bellard | |
1385 | 9a64fbe4 | bellard | |
1386 | 9a64fbe4 | bellard | /*** Floating-Point compare ***/
|
1387 | 9a64fbe4 | bellard | /* fcmpu */
|
1388 | 9a64fbe4 | bellard | PPC_OP(fcmpu) |
1389 | 28b6751f | bellard | { |
1390 | 9a64fbe4 | bellard | do_fcmpu(); |
1391 | 9a64fbe4 | bellard | RETURN(); |
1392 | 28b6751f | bellard | } |
1393 | 28b6751f | bellard | |
1394 | 9a64fbe4 | bellard | /* fcmpo */
|
1395 | 9a64fbe4 | bellard | PPC_OP(fcmpo) |
1396 | 28b6751f | bellard | { |
1397 | 9a64fbe4 | bellard | do_fcmpo(); |
1398 | 9a64fbe4 | bellard | RETURN(); |
1399 | fb0eaffc | bellard | } |
1400 | fb0eaffc | bellard | |
1401 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
1402 | 9a64fbe4 | bellard | /* fabs */
|
1403 | 9a64fbe4 | bellard | PPC_OP(fabs) |
1404 | fb0eaffc | bellard | { |
1405 | 9a64fbe4 | bellard | do_fabs(); |
1406 | fb0eaffc | bellard | RETURN(); |
1407 | fb0eaffc | bellard | } |
1408 | fb0eaffc | bellard | |
1409 | 9a64fbe4 | bellard | /* fnabs */
|
1410 | 9a64fbe4 | bellard | PPC_OP(fnabs) |
1411 | fb0eaffc | bellard | { |
1412 | 9a64fbe4 | bellard | do_fnabs(); |
1413 | fb0eaffc | bellard | RETURN(); |
1414 | fb0eaffc | bellard | } |
1415 | fb0eaffc | bellard | |
1416 | 9a64fbe4 | bellard | /* fneg */
|
1417 | 9a64fbe4 | bellard | PPC_OP(fneg) |
1418 | fb0eaffc | bellard | { |
1419 | 9a64fbe4 | bellard | FT0 = -FT0; |
1420 | fb0eaffc | bellard | RETURN(); |
1421 | fb0eaffc | bellard | } |
1422 | fb0eaffc | bellard | |
1423 | 9a64fbe4 | bellard | /* Load and store */
|
1424 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
|
1425 | 9a64fbe4 | bellard | #include "op_mem.h" |
1426 | a541f297 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1427 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
|
1428 | 9a64fbe4 | bellard | #include "op_mem.h" |
1429 | 9a64fbe4 | bellard | |
1430 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
|
1431 | 9a64fbe4 | bellard | #include "op_mem.h" |
1432 | 9a64fbe4 | bellard | #endif
|
1433 | 9a64fbe4 | bellard | |
1434 | 4b3686fa | bellard | /* Special op to check and maybe clear reservation */
|
1435 | 4b3686fa | bellard | PPC_OP(check_reservation) |
1436 | 4b3686fa | bellard | { |
1437 | 4b3686fa | bellard | do_check_reservation(); |
1438 | 4b3686fa | bellard | RETURN(); |
1439 | 4b3686fa | bellard | } |
1440 | 4b3686fa | bellard | |
1441 | 9a64fbe4 | bellard | /* Return from interrupt */
|
1442 | 9a64fbe4 | bellard | PPC_OP(rfi) |
1443 | fb0eaffc | bellard | { |
1444 | 9fddaa0c | bellard | regs->nip = regs->spr[SRR0] & ~0x00000003;
|
1445 | 4b3686fa | bellard | #if 1 // TRY |
1446 | 4b3686fa | bellard | T0 = regs->spr[SRR1] & ~0xFFF00000;
|
1447 | 4b3686fa | bellard | #else
|
1448 | 9a64fbe4 | bellard | T0 = regs->spr[SRR1] & ~0xFFFF0000;
|
1449 | 4b3686fa | bellard | #endif
|
1450 | 9a64fbe4 | bellard | do_store_msr(); |
1451 | a541f297 | bellard | #if defined (DEBUG_OP)
|
1452 | 9a64fbe4 | bellard | dump_rfi(); |
1453 | a541f297 | bellard | #endif
|
1454 | 9fddaa0c | bellard | // do_tlbia();
|
1455 | 9fddaa0c | bellard | do_raise_exception(EXCP_RFI); |
1456 | fb0eaffc | bellard | RETURN(); |
1457 | fb0eaffc | bellard | } |
1458 | fb0eaffc | bellard | |
1459 | 9a64fbe4 | bellard | /* Trap word */
|
1460 | 9a64fbe4 | bellard | PPC_OP(tw) |
1461 | fb0eaffc | bellard | { |
1462 | 9a64fbe4 | bellard | if ((Ts0 < Ts1 && (PARAM(1) & 0x10)) || |
1463 | 9a64fbe4 | bellard | (Ts0 > Ts1 && (PARAM(1) & 0x08)) || |
1464 | 9a64fbe4 | bellard | (Ts0 == Ts1 && (PARAM(1) & 0x04)) || |
1465 | 9a64fbe4 | bellard | (T0 < T1 && (PARAM(1) & 0x02)) || |
1466 | 9a64fbe4 | bellard | (T0 > T1 && (PARAM(1) & 0x01))) |
1467 | 9fddaa0c | bellard | do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP); |
1468 | fb0eaffc | bellard | RETURN(); |
1469 | fb0eaffc | bellard | } |
1470 | fb0eaffc | bellard | |
1471 | 9a64fbe4 | bellard | PPC_OP(twi) |
1472 | fb0eaffc | bellard | { |
1473 | 9a64fbe4 | bellard | if ((Ts0 < SPARAM(1) && (PARAM(2) & 0x10)) || |
1474 | 9a64fbe4 | bellard | (Ts0 > SPARAM(1) && (PARAM(2) & 0x08)) || |
1475 | 9a64fbe4 | bellard | (Ts0 == SPARAM(1) && (PARAM(2) & 0x04)) || |
1476 | 9a64fbe4 | bellard | (T0 < (uint32_t)SPARAM(1) && (PARAM(2) & 0x02)) || |
1477 | 9a64fbe4 | bellard | (T0 > (uint32_t)SPARAM(1) && (PARAM(2) & 0x01))) |
1478 | 9fddaa0c | bellard | do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP); |
1479 | fb0eaffc | bellard | RETURN(); |
1480 | fb0eaffc | bellard | } |
1481 | fb0eaffc | bellard | |
1482 | fb0eaffc | bellard | /* Instruction cache block invalidate */
|
1483 | 9a64fbe4 | bellard | PPC_OP(icbi) |
1484 | fb0eaffc | bellard | { |
1485 | fb0eaffc | bellard | do_icbi(); |
1486 | fb0eaffc | bellard | RETURN(); |
1487 | fb0eaffc | bellard | } |
1488 | fb0eaffc | bellard | |
1489 | 9a64fbe4 | bellard | /* tlbia */
|
1490 | 9a64fbe4 | bellard | PPC_OP(tlbia) |
1491 | fb0eaffc | bellard | { |
1492 | 9a64fbe4 | bellard | do_tlbia(); |
1493 | 9a64fbe4 | bellard | RETURN(); |
1494 | 9a64fbe4 | bellard | } |
1495 | 9a64fbe4 | bellard | |
1496 | 9a64fbe4 | bellard | /* tlbie */
|
1497 | 9a64fbe4 | bellard | PPC_OP(tlbie) |
1498 | 9a64fbe4 | bellard | { |
1499 | 9a64fbe4 | bellard | do_tlbie(); |
1500 | fb0eaffc | bellard | RETURN(); |
1501 | 28b6751f | bellard | } |