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1 | 2055283b | Peter Maydell | /*
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2 | 2055283b | Peter Maydell | * ARM Versatile Express emulation.
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3 | 2055283b | Peter Maydell | *
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4 | 2055283b | Peter Maydell | * Copyright (c) 2010 - 2011 B Labs Ltd.
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5 | 2055283b | Peter Maydell | * Copyright (c) 2011 Linaro Limited
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6 | 2055283b | Peter Maydell | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
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7 | 2055283b | Peter Maydell | *
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8 | 2055283b | Peter Maydell | * This program is free software; you can redistribute it and/or modify
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9 | 2055283b | Peter Maydell | * it under the terms of the GNU General Public License version 2 as
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10 | 2055283b | Peter Maydell | * published by the Free Software Foundation.
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11 | 2055283b | Peter Maydell | *
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12 | 2055283b | Peter Maydell | * This program is distributed in the hope that it will be useful,
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13 | 2055283b | Peter Maydell | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 2055283b | Peter Maydell | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 | 2055283b | Peter Maydell | * GNU General Public License for more details.
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16 | 2055283b | Peter Maydell | *
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17 | 2055283b | Peter Maydell | * You should have received a copy of the GNU General Public License along
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18 | 2055283b | Peter Maydell | * with this program; if not, see <http://www.gnu.org/licenses/>.
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19 | 6b620ca3 | Paolo Bonzini | *
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20 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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21 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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22 | 2055283b | Peter Maydell | */
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23 | 2055283b | Peter Maydell | |
24 | 83c9f4ca | Paolo Bonzini | #include "hw/sysbus.h" |
25 | bd2be150 | Peter Maydell | #include "hw/arm/arm.h" |
26 | 0d09e41a | Paolo Bonzini | #include "hw/arm/primecell.h" |
27 | bd2be150 | Peter Maydell | #include "hw/devices.h" |
28 | 1422e32d | Paolo Bonzini | #include "net/net.h" |
29 | 9c17d615 | Paolo Bonzini | #include "sysemu/sysemu.h" |
30 | 83c9f4ca | Paolo Bonzini | #include "hw/boards.h" |
31 | 022c62cb | Paolo Bonzini | #include "exec/address-spaces.h" |
32 | 9c17d615 | Paolo Bonzini | #include "sysemu/blockdev.h" |
33 | 0d09e41a | Paolo Bonzini | #include "hw/block/flash.h" |
34 | 2055283b | Peter Maydell | |
35 | 2055283b | Peter Maydell | #define VEXPRESS_BOARD_ID 0x8e0 |
36 | 3dc3e7dd | Francesco Lavra | #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) |
37 | 3dc3e7dd | Francesco Lavra | #define VEXPRESS_FLASH_SECT_SIZE (256 * 1024) |
38 | 2055283b | Peter Maydell | |
39 | aac1e02c | Peter Maydell | static struct arm_boot_info vexpress_binfo; |
40 | 2558e0a6 | Peter Maydell | |
41 | 2558e0a6 | Peter Maydell | /* Address maps for peripherals:
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42 | 2558e0a6 | Peter Maydell | * the Versatile Express motherboard has two possible maps,
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43 | 2558e0a6 | Peter Maydell | * the "legacy" one (used for A9) and the "Cortex-A Series"
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44 | 2558e0a6 | Peter Maydell | * map (used for newer cores).
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45 | 2558e0a6 | Peter Maydell | * Individual daughterboards can also have different maps for
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46 | 2558e0a6 | Peter Maydell | * their peripherals.
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47 | 2558e0a6 | Peter Maydell | */
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48 | 2558e0a6 | Peter Maydell | |
49 | 2558e0a6 | Peter Maydell | enum {
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50 | 2558e0a6 | Peter Maydell | VE_SYSREGS, |
51 | 2558e0a6 | Peter Maydell | VE_SP810, |
52 | 2558e0a6 | Peter Maydell | VE_SERIALPCI, |
53 | 2558e0a6 | Peter Maydell | VE_PL041, |
54 | 2558e0a6 | Peter Maydell | VE_MMCI, |
55 | 2558e0a6 | Peter Maydell | VE_KMI0, |
56 | 2558e0a6 | Peter Maydell | VE_KMI1, |
57 | 2558e0a6 | Peter Maydell | VE_UART0, |
58 | 2558e0a6 | Peter Maydell | VE_UART1, |
59 | 2558e0a6 | Peter Maydell | VE_UART2, |
60 | 2558e0a6 | Peter Maydell | VE_UART3, |
61 | 2558e0a6 | Peter Maydell | VE_WDT, |
62 | 2558e0a6 | Peter Maydell | VE_TIMER01, |
63 | 2558e0a6 | Peter Maydell | VE_TIMER23, |
64 | 2558e0a6 | Peter Maydell | VE_SERIALDVI, |
65 | 2558e0a6 | Peter Maydell | VE_RTC, |
66 | 2558e0a6 | Peter Maydell | VE_COMPACTFLASH, |
67 | 2558e0a6 | Peter Maydell | VE_CLCD, |
68 | 2558e0a6 | Peter Maydell | VE_NORFLASH0, |
69 | 2558e0a6 | Peter Maydell | VE_NORFLASH1, |
70 | 2558e0a6 | Peter Maydell | VE_SRAM, |
71 | 2558e0a6 | Peter Maydell | VE_VIDEORAM, |
72 | 2558e0a6 | Peter Maydell | VE_ETHERNET, |
73 | 2558e0a6 | Peter Maydell | VE_USB, |
74 | 2558e0a6 | Peter Maydell | VE_DAPROM, |
75 | 2558e0a6 | Peter Maydell | }; |
76 | 2558e0a6 | Peter Maydell | |
77 | a8170e5e | Avi Kivity | static hwaddr motherboard_legacy_map[] = {
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78 | 2558e0a6 | Peter Maydell | /* CS7: 0x10000000 .. 0x10020000 */
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79 | 2558e0a6 | Peter Maydell | [VE_SYSREGS] = 0x10000000,
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80 | 2558e0a6 | Peter Maydell | [VE_SP810] = 0x10001000,
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81 | 2558e0a6 | Peter Maydell | [VE_SERIALPCI] = 0x10002000,
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82 | 2558e0a6 | Peter Maydell | [VE_PL041] = 0x10004000,
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83 | 2558e0a6 | Peter Maydell | [VE_MMCI] = 0x10005000,
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84 | 2558e0a6 | Peter Maydell | [VE_KMI0] = 0x10006000,
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85 | 2558e0a6 | Peter Maydell | [VE_KMI1] = 0x10007000,
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86 | 2558e0a6 | Peter Maydell | [VE_UART0] = 0x10009000,
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87 | 2558e0a6 | Peter Maydell | [VE_UART1] = 0x1000a000,
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88 | 2558e0a6 | Peter Maydell | [VE_UART2] = 0x1000b000,
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89 | 2558e0a6 | Peter Maydell | [VE_UART3] = 0x1000c000,
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90 | 2558e0a6 | Peter Maydell | [VE_WDT] = 0x1000f000,
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91 | 2558e0a6 | Peter Maydell | [VE_TIMER01] = 0x10011000,
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92 | 2558e0a6 | Peter Maydell | [VE_TIMER23] = 0x10012000,
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93 | 2558e0a6 | Peter Maydell | [VE_SERIALDVI] = 0x10016000,
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94 | 2558e0a6 | Peter Maydell | [VE_RTC] = 0x10017000,
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95 | 2558e0a6 | Peter Maydell | [VE_COMPACTFLASH] = 0x1001a000,
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96 | 2558e0a6 | Peter Maydell | [VE_CLCD] = 0x1001f000,
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97 | 2558e0a6 | Peter Maydell | /* CS0: 0x40000000 .. 0x44000000 */
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98 | 2558e0a6 | Peter Maydell | [VE_NORFLASH0] = 0x40000000,
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99 | 2558e0a6 | Peter Maydell | /* CS1: 0x44000000 .. 0x48000000 */
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100 | 2558e0a6 | Peter Maydell | [VE_NORFLASH1] = 0x44000000,
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101 | 2558e0a6 | Peter Maydell | /* CS2: 0x48000000 .. 0x4a000000 */
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102 | 2558e0a6 | Peter Maydell | [VE_SRAM] = 0x48000000,
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103 | 2558e0a6 | Peter Maydell | /* CS3: 0x4c000000 .. 0x50000000 */
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104 | 2558e0a6 | Peter Maydell | [VE_VIDEORAM] = 0x4c000000,
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105 | 2558e0a6 | Peter Maydell | [VE_ETHERNET] = 0x4e000000,
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106 | 2558e0a6 | Peter Maydell | [VE_USB] = 0x4f000000,
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107 | 2055283b | Peter Maydell | }; |
108 | 2055283b | Peter Maydell | |
109 | a8170e5e | Avi Kivity | static hwaddr motherboard_aseries_map[] = {
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110 | 661bafb3 | Francesco Lavra | /* CS0: 0x08000000 .. 0x0c000000 */
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111 | 661bafb3 | Francesco Lavra | [VE_NORFLASH0] = 0x08000000,
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112 | 961f195e | Peter Maydell | /* CS4: 0x0c000000 .. 0x10000000 */
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113 | 961f195e | Peter Maydell | [VE_NORFLASH1] = 0x0c000000,
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114 | 961f195e | Peter Maydell | /* CS5: 0x10000000 .. 0x14000000 */
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115 | 961f195e | Peter Maydell | /* CS1: 0x14000000 .. 0x18000000 */
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116 | 961f195e | Peter Maydell | [VE_SRAM] = 0x14000000,
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117 | 961f195e | Peter Maydell | /* CS2: 0x18000000 .. 0x1c000000 */
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118 | 961f195e | Peter Maydell | [VE_VIDEORAM] = 0x18000000,
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119 | 961f195e | Peter Maydell | [VE_ETHERNET] = 0x1a000000,
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120 | 961f195e | Peter Maydell | [VE_USB] = 0x1b000000,
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121 | 961f195e | Peter Maydell | /* CS3: 0x1c000000 .. 0x20000000 */
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122 | 961f195e | Peter Maydell | [VE_DAPROM] = 0x1c000000,
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123 | 961f195e | Peter Maydell | [VE_SYSREGS] = 0x1c010000,
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124 | 961f195e | Peter Maydell | [VE_SP810] = 0x1c020000,
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125 | 961f195e | Peter Maydell | [VE_SERIALPCI] = 0x1c030000,
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126 | 961f195e | Peter Maydell | [VE_PL041] = 0x1c040000,
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127 | 961f195e | Peter Maydell | [VE_MMCI] = 0x1c050000,
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128 | 961f195e | Peter Maydell | [VE_KMI0] = 0x1c060000,
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129 | 961f195e | Peter Maydell | [VE_KMI1] = 0x1c070000,
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130 | 961f195e | Peter Maydell | [VE_UART0] = 0x1c090000,
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131 | 961f195e | Peter Maydell | [VE_UART1] = 0x1c0a0000,
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132 | 961f195e | Peter Maydell | [VE_UART2] = 0x1c0b0000,
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133 | 961f195e | Peter Maydell | [VE_UART3] = 0x1c0c0000,
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134 | 961f195e | Peter Maydell | [VE_WDT] = 0x1c0f0000,
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135 | 961f195e | Peter Maydell | [VE_TIMER01] = 0x1c110000,
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136 | 961f195e | Peter Maydell | [VE_TIMER23] = 0x1c120000,
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137 | 961f195e | Peter Maydell | [VE_SERIALDVI] = 0x1c160000,
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138 | 961f195e | Peter Maydell | [VE_RTC] = 0x1c170000,
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139 | 961f195e | Peter Maydell | [VE_COMPACTFLASH] = 0x1c1a0000,
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140 | 961f195e | Peter Maydell | [VE_CLCD] = 0x1c1f0000,
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141 | 961f195e | Peter Maydell | }; |
142 | 961f195e | Peter Maydell | |
143 | 4c3b29b8 | Peter Maydell | /* Structure defining the peculiarities of a specific daughterboard */
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144 | 4c3b29b8 | Peter Maydell | |
145 | 4c3b29b8 | Peter Maydell | typedef struct VEDBoardInfo VEDBoardInfo; |
146 | 4c3b29b8 | Peter Maydell | |
147 | 4c3b29b8 | Peter Maydell | typedef void DBoardInitFn(const VEDBoardInfo *daughterboard, |
148 | 4c3b29b8 | Peter Maydell | ram_addr_t ram_size, |
149 | 4c3b29b8 | Peter Maydell | const char *cpu_model, |
150 | cdef10bb | Peter Maydell | qemu_irq *pic); |
151 | 4c3b29b8 | Peter Maydell | |
152 | 4c3b29b8 | Peter Maydell | struct VEDBoardInfo {
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153 | a8170e5e | Avi Kivity | const hwaddr *motherboard_map;
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154 | a8170e5e | Avi Kivity | hwaddr loader_start; |
155 | a8170e5e | Avi Kivity | const hwaddr gic_cpu_if_addr;
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156 | cdef10bb | Peter Maydell | uint32_t proc_id; |
157 | 31410948 | Peter Maydell | uint32_t num_voltage_sensors; |
158 | 31410948 | Peter Maydell | const uint32_t *voltages;
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159 | 9c7d4893 | Peter Maydell | uint32_t num_clocks; |
160 | 9c7d4893 | Peter Maydell | const uint32_t *clocks;
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161 | 4c3b29b8 | Peter Maydell | DBoardInitFn *init; |
162 | 4c3b29b8 | Peter Maydell | }; |
163 | 4c3b29b8 | Peter Maydell | |
164 | 4c3b29b8 | Peter Maydell | static void a9_daughterboard_init(const VEDBoardInfo *daughterboard, |
165 | 4c3b29b8 | Peter Maydell | ram_addr_t ram_size, |
166 | 4c3b29b8 | Peter Maydell | const char *cpu_model, |
167 | cdef10bb | Peter Maydell | qemu_irq *pic) |
168 | 2055283b | Peter Maydell | { |
169 | e6d17b05 | Avi Kivity | MemoryRegion *sysmem = get_system_memory(); |
170 | e6d17b05 | Avi Kivity | MemoryRegion *ram = g_new(MemoryRegion, 1);
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171 | e6d17b05 | Avi Kivity | MemoryRegion *lowram = g_new(MemoryRegion, 1);
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172 | 4c3b29b8 | Peter Maydell | DeviceState *dev; |
173 | 2055283b | Peter Maydell | SysBusDevice *busdev; |
174 | 2055283b | Peter Maydell | qemu_irq *irqp; |
175 | 2055283b | Peter Maydell | int n;
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176 | 2055283b | Peter Maydell | qemu_irq cpu_irq[4];
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177 | 4c3b29b8 | Peter Maydell | ram_addr_t low_ram_size; |
178 | 2055283b | Peter Maydell | |
179 | 2055283b | Peter Maydell | if (!cpu_model) {
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180 | 2055283b | Peter Maydell | cpu_model = "cortex-a9";
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181 | 2055283b | Peter Maydell | } |
182 | 2055283b | Peter Maydell | |
183 | 2055283b | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
184 | 64c9e297 | Andreas Färber | ARMCPU *cpu = cpu_arm_init(cpu_model); |
185 | 64c9e297 | Andreas Färber | if (!cpu) {
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186 | 2055283b | Peter Maydell | fprintf(stderr, "Unable to find CPU definition\n");
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187 | 2055283b | Peter Maydell | exit(1);
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188 | 2055283b | Peter Maydell | } |
189 | 4bd74661 | Andreas Färber | irqp = arm_pic_init_cpu(cpu); |
190 | 2055283b | Peter Maydell | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
191 | 2055283b | Peter Maydell | } |
192 | 2055283b | Peter Maydell | |
193 | 2055283b | Peter Maydell | if (ram_size > 0x40000000) { |
194 | 2055283b | Peter Maydell | /* 1GB is the maximum the address space permits */
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195 | 4c3b29b8 | Peter Maydell | fprintf(stderr, "vexpress-a9: cannot model more than 1GB RAM\n");
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196 | 2055283b | Peter Maydell | exit(1);
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197 | 2055283b | Peter Maydell | } |
198 | 2055283b | Peter Maydell | |
199 | c5705a77 | Avi Kivity | memory_region_init_ram(ram, "vexpress.highmem", ram_size);
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200 | c5705a77 | Avi Kivity | vmstate_register_ram_global(ram); |
201 | 2055283b | Peter Maydell | low_ram_size = ram_size; |
202 | 2055283b | Peter Maydell | if (low_ram_size > 0x4000000) { |
203 | 2055283b | Peter Maydell | low_ram_size = 0x4000000;
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204 | 2055283b | Peter Maydell | } |
205 | 2055283b | Peter Maydell | /* RAM is from 0x60000000 upwards. The bottom 64MB of the
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206 | 2055283b | Peter Maydell | * address space should in theory be remappable to various
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207 | 2055283b | Peter Maydell | * things including ROM or RAM; we always map the RAM there.
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208 | 2055283b | Peter Maydell | */
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209 | e6d17b05 | Avi Kivity | memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size); |
210 | e6d17b05 | Avi Kivity | memory_region_add_subregion(sysmem, 0x0, lowram);
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211 | e6d17b05 | Avi Kivity | memory_region_add_subregion(sysmem, 0x60000000, ram);
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212 | 2055283b | Peter Maydell | |
213 | 2055283b | Peter Maydell | /* 0x1e000000 A9MPCore (SCU) private memory region */
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214 | 2055283b | Peter Maydell | dev = qdev_create(NULL, "a9mpcore_priv"); |
215 | 2055283b | Peter Maydell | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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216 | 2055283b | Peter Maydell | qdev_init_nofail(dev); |
217 | 1356b98d | Andreas Färber | busdev = SYS_BUS_DEVICE(dev); |
218 | 96eacf64 | Peter Maydell | sysbus_mmio_map(busdev, 0, 0x1e000000); |
219 | 2055283b | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
220 | 2055283b | Peter Maydell | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
221 | 2055283b | Peter Maydell | } |
222 | 2055283b | Peter Maydell | /* Interrupts [42:0] are from the motherboard;
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223 | 2055283b | Peter Maydell | * [47:43] are reserved; [63:48] are daughterboard
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224 | 2055283b | Peter Maydell | * peripherals. Note that some documentation numbers
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225 | 2055283b | Peter Maydell | * external interrupts starting from 32 (because the
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226 | 2055283b | Peter Maydell | * A9MP has internal interrupts 0..31).
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227 | 2055283b | Peter Maydell | */
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228 | 2055283b | Peter Maydell | for (n = 0; n < 64; n++) { |
229 | 2055283b | Peter Maydell | pic[n] = qdev_get_gpio_in(dev, n); |
230 | 2055283b | Peter Maydell | } |
231 | 2055283b | Peter Maydell | |
232 | 4c3b29b8 | Peter Maydell | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
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233 | 4c3b29b8 | Peter Maydell | |
234 | 4c3b29b8 | Peter Maydell | /* 0x10020000 PL111 CLCD (daughterboard) */
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235 | 4c3b29b8 | Peter Maydell | sysbus_create_simple("pl111", 0x10020000, pic[44]); |
236 | 4c3b29b8 | Peter Maydell | |
237 | 4c3b29b8 | Peter Maydell | /* 0x10060000 AXI RAM */
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238 | 4c3b29b8 | Peter Maydell | /* 0x100e0000 PL341 Dynamic Memory Controller */
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239 | 4c3b29b8 | Peter Maydell | /* 0x100e1000 PL354 Static Memory Controller */
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240 | 4c3b29b8 | Peter Maydell | /* 0x100e2000 System Configuration Controller */
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241 | 4c3b29b8 | Peter Maydell | |
242 | 4c3b29b8 | Peter Maydell | sysbus_create_simple("sp804", 0x100e4000, pic[48]); |
243 | 4c3b29b8 | Peter Maydell | /* 0x100e5000 SP805 Watchdog module */
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244 | 4c3b29b8 | Peter Maydell | /* 0x100e6000 BP147 TrustZone Protection Controller */
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245 | 4c3b29b8 | Peter Maydell | /* 0x100e9000 PL301 'Fast' AXI matrix */
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246 | 4c3b29b8 | Peter Maydell | /* 0x100ea000 PL301 'Slow' AXI matrix */
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247 | 4c3b29b8 | Peter Maydell | /* 0x100ec000 TrustZone Address Space Controller */
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248 | 4c3b29b8 | Peter Maydell | /* 0x10200000 CoreSight debug APB */
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249 | 4c3b29b8 | Peter Maydell | /* 0x1e00a000 PL310 L2 Cache Controller */
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250 | 4c3b29b8 | Peter Maydell | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); |
251 | 4c3b29b8 | Peter Maydell | } |
252 | 4c3b29b8 | Peter Maydell | |
253 | 31410948 | Peter Maydell | /* Voltage values for SYS_CFG_VOLT daughterboard registers;
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254 | 31410948 | Peter Maydell | * values are in microvolts.
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255 | 31410948 | Peter Maydell | */
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256 | 31410948 | Peter Maydell | static const uint32_t a9_voltages[] = { |
257 | 31410948 | Peter Maydell | 1000000, /* VD10 : 1.0V : SoC internal logic voltage */ |
258 | 31410948 | Peter Maydell | 1000000, /* VD10_S2 : 1.0V : PL310, L2 cache, RAM, non-PL310 logic */ |
259 | 31410948 | Peter Maydell | 1000000, /* VD10_S3 : 1.0V : Cortex-A9, cores, MPEs, SCU, PL310 logic */ |
260 | 31410948 | Peter Maydell | 1800000, /* VCC1V8 : 1.8V : DDR2 SDRAM, test chip DDR2 I/O supply */ |
261 | 31410948 | Peter Maydell | 900000, /* DDR2VTT : 0.9V : DDR2 SDRAM VTT termination voltage */ |
262 | 31410948 | Peter Maydell | 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ |
263 | 31410948 | Peter Maydell | }; |
264 | 31410948 | Peter Maydell | |
265 | 9c7d4893 | Peter Maydell | /* Reset values for daughterboard oscillators (in Hz) */
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266 | 9c7d4893 | Peter Maydell | static const uint32_t a9_clocks[] = { |
267 | 9c7d4893 | Peter Maydell | 45000000, /* AMBA AXI ACLK: 45MHz */ |
268 | 9c7d4893 | Peter Maydell | 23750000, /* daughterboard CLCD clock: 23.75MHz */ |
269 | 9c7d4893 | Peter Maydell | 66670000, /* Test chip reference clock: 66.67MHz */ |
270 | 9c7d4893 | Peter Maydell | }; |
271 | 9c7d4893 | Peter Maydell | |
272 | 4c3b29b8 | Peter Maydell | static const VEDBoardInfo a9_daughterboard = { |
273 | 4c3b29b8 | Peter Maydell | .motherboard_map = motherboard_legacy_map, |
274 | 4c3b29b8 | Peter Maydell | .loader_start = 0x60000000,
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275 | 96eacf64 | Peter Maydell | .gic_cpu_if_addr = 0x1e000100,
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276 | cdef10bb | Peter Maydell | .proc_id = 0x0c000191,
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277 | 31410948 | Peter Maydell | .num_voltage_sensors = ARRAY_SIZE(a9_voltages), |
278 | 31410948 | Peter Maydell | .voltages = a9_voltages, |
279 | 9c7d4893 | Peter Maydell | .num_clocks = ARRAY_SIZE(a9_clocks), |
280 | 9c7d4893 | Peter Maydell | .clocks = a9_clocks, |
281 | 4c3b29b8 | Peter Maydell | .init = a9_daughterboard_init, |
282 | 4c3b29b8 | Peter Maydell | }; |
283 | 4c3b29b8 | Peter Maydell | |
284 | 961f195e | Peter Maydell | static void a15_daughterboard_init(const VEDBoardInfo *daughterboard, |
285 | 961f195e | Peter Maydell | ram_addr_t ram_size, |
286 | 961f195e | Peter Maydell | const char *cpu_model, |
287 | cdef10bb | Peter Maydell | qemu_irq *pic) |
288 | 961f195e | Peter Maydell | { |
289 | 961f195e | Peter Maydell | int n;
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290 | 961f195e | Peter Maydell | MemoryRegion *sysmem = get_system_memory(); |
291 | 961f195e | Peter Maydell | MemoryRegion *ram = g_new(MemoryRegion, 1);
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292 | 961f195e | Peter Maydell | MemoryRegion *sram = g_new(MemoryRegion, 1);
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293 | 961f195e | Peter Maydell | qemu_irq cpu_irq[4];
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294 | 961f195e | Peter Maydell | DeviceState *dev; |
295 | 961f195e | Peter Maydell | SysBusDevice *busdev; |
296 | 961f195e | Peter Maydell | |
297 | 961f195e | Peter Maydell | if (!cpu_model) {
|
298 | 961f195e | Peter Maydell | cpu_model = "cortex-a15";
|
299 | 961f195e | Peter Maydell | } |
300 | 961f195e | Peter Maydell | |
301 | 961f195e | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
302 | 64c9e297 | Andreas Färber | ARMCPU *cpu; |
303 | 961f195e | Peter Maydell | qemu_irq *irqp; |
304 | 64c9e297 | Andreas Färber | |
305 | 64c9e297 | Andreas Färber | cpu = cpu_arm_init(cpu_model); |
306 | 64c9e297 | Andreas Färber | if (!cpu) {
|
307 | 961f195e | Peter Maydell | fprintf(stderr, "Unable to find CPU definition\n");
|
308 | 961f195e | Peter Maydell | exit(1);
|
309 | 961f195e | Peter Maydell | } |
310 | 4bd74661 | Andreas Färber | irqp = arm_pic_init_cpu(cpu); |
311 | 961f195e | Peter Maydell | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; |
312 | 961f195e | Peter Maydell | } |
313 | 961f195e | Peter Maydell | |
314 | 25d71699 | Peter Maydell | { |
315 | 25d71699 | Peter Maydell | /* We have to use a separate 64 bit variable here to avoid the gcc
|
316 | 25d71699 | Peter Maydell | * "comparison is always false due to limited range of data type"
|
317 | 25d71699 | Peter Maydell | * warning if we are on a host where ram_addr_t is 32 bits.
|
318 | 25d71699 | Peter Maydell | */
|
319 | 25d71699 | Peter Maydell | uint64_t rsz = ram_size; |
320 | 25d71699 | Peter Maydell | if (rsz > (30ULL * 1024 * 1024 * 1024)) { |
321 | 25d71699 | Peter Maydell | fprintf(stderr, "vexpress-a15: cannot model more than 30GB RAM\n");
|
322 | 25d71699 | Peter Maydell | exit(1);
|
323 | 25d71699 | Peter Maydell | } |
324 | 961f195e | Peter Maydell | } |
325 | 961f195e | Peter Maydell | |
326 | 961f195e | Peter Maydell | memory_region_init_ram(ram, "vexpress.highmem", ram_size);
|
327 | 961f195e | Peter Maydell | vmstate_register_ram_global(ram); |
328 | 961f195e | Peter Maydell | /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */
|
329 | 961f195e | Peter Maydell | memory_region_add_subregion(sysmem, 0x80000000, ram);
|
330 | 961f195e | Peter Maydell | |
331 | 961f195e | Peter Maydell | /* 0x2c000000 A15MPCore private memory region (GIC) */
|
332 | 961f195e | Peter Maydell | dev = qdev_create(NULL, "a15mpcore_priv"); |
333 | 961f195e | Peter Maydell | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
|
334 | 961f195e | Peter Maydell | qdev_init_nofail(dev); |
335 | 1356b98d | Andreas Färber | busdev = SYS_BUS_DEVICE(dev); |
336 | 961f195e | Peter Maydell | sysbus_mmio_map(busdev, 0, 0x2c000000); |
337 | 961f195e | Peter Maydell | for (n = 0; n < smp_cpus; n++) { |
338 | 961f195e | Peter Maydell | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
339 | 961f195e | Peter Maydell | } |
340 | 961f195e | Peter Maydell | /* Interrupts [42:0] are from the motherboard;
|
341 | 961f195e | Peter Maydell | * [47:43] are reserved; [63:48] are daughterboard
|
342 | 961f195e | Peter Maydell | * peripherals. Note that some documentation numbers
|
343 | 961f195e | Peter Maydell | * external interrupts starting from 32 (because there
|
344 | 961f195e | Peter Maydell | * are internal interrupts 0..31).
|
345 | 961f195e | Peter Maydell | */
|
346 | 961f195e | Peter Maydell | for (n = 0; n < 64; n++) { |
347 | 961f195e | Peter Maydell | pic[n] = qdev_get_gpio_in(dev, n); |
348 | 961f195e | Peter Maydell | } |
349 | 961f195e | Peter Maydell | |
350 | 961f195e | Peter Maydell | /* A15 daughterboard peripherals: */
|
351 | 961f195e | Peter Maydell | |
352 | 961f195e | Peter Maydell | /* 0x20000000: CoreSight interfaces: not modelled */
|
353 | 961f195e | Peter Maydell | /* 0x2a000000: PL301 AXI interconnect: not modelled */
|
354 | 961f195e | Peter Maydell | /* 0x2a420000: SCC: not modelled */
|
355 | 961f195e | Peter Maydell | /* 0x2a430000: system counter: not modelled */
|
356 | 961f195e | Peter Maydell | /* 0x2b000000: HDLCD controller: not modelled */
|
357 | 961f195e | Peter Maydell | /* 0x2b060000: SP805 watchdog: not modelled */
|
358 | 961f195e | Peter Maydell | /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */
|
359 | 961f195e | Peter Maydell | /* 0x2e000000: system SRAM */
|
360 | 961f195e | Peter Maydell | memory_region_init_ram(sram, "vexpress.a15sram", 0x10000); |
361 | 961f195e | Peter Maydell | vmstate_register_ram_global(sram); |
362 | 961f195e | Peter Maydell | memory_region_add_subregion(sysmem, 0x2e000000, sram);
|
363 | 961f195e | Peter Maydell | |
364 | 961f195e | Peter Maydell | /* 0x7ffb0000: DMA330 DMA controller: not modelled */
|
365 | 961f195e | Peter Maydell | /* 0x7ffd0000: PL354 static memory controller: not modelled */
|
366 | 961f195e | Peter Maydell | } |
367 | 961f195e | Peter Maydell | |
368 | 31410948 | Peter Maydell | static const uint32_t a15_voltages[] = { |
369 | 31410948 | Peter Maydell | 900000, /* Vcore: 0.9V : CPU core voltage */ |
370 | 31410948 | Peter Maydell | }; |
371 | 31410948 | Peter Maydell | |
372 | 9c7d4893 | Peter Maydell | static const uint32_t a15_clocks[] = { |
373 | 9c7d4893 | Peter Maydell | 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ |
374 | 9c7d4893 | Peter Maydell | 0, /* OSCCLK1: reserved */ |
375 | 9c7d4893 | Peter Maydell | 0, /* OSCCLK2: reserved */ |
376 | 9c7d4893 | Peter Maydell | 0, /* OSCCLK3: reserved */ |
377 | 9c7d4893 | Peter Maydell | 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ |
378 | 9c7d4893 | Peter Maydell | 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ |
379 | 9c7d4893 | Peter Maydell | 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ |
380 | 9c7d4893 | Peter Maydell | 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ |
381 | 9c7d4893 | Peter Maydell | 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ |
382 | 9c7d4893 | Peter Maydell | }; |
383 | 9c7d4893 | Peter Maydell | |
384 | 961f195e | Peter Maydell | static const VEDBoardInfo a15_daughterboard = { |
385 | 961f195e | Peter Maydell | .motherboard_map = motherboard_aseries_map, |
386 | 961f195e | Peter Maydell | .loader_start = 0x80000000,
|
387 | 961f195e | Peter Maydell | .gic_cpu_if_addr = 0x2c002000,
|
388 | cdef10bb | Peter Maydell | .proc_id = 0x14000237,
|
389 | 31410948 | Peter Maydell | .num_voltage_sensors = ARRAY_SIZE(a15_voltages), |
390 | 31410948 | Peter Maydell | .voltages = a15_voltages, |
391 | 9c7d4893 | Peter Maydell | .num_clocks = ARRAY_SIZE(a15_clocks), |
392 | 9c7d4893 | Peter Maydell | .clocks = a15_clocks, |
393 | 961f195e | Peter Maydell | .init = a15_daughterboard_init, |
394 | 961f195e | Peter Maydell | }; |
395 | 961f195e | Peter Maydell | |
396 | 4c3b29b8 | Peter Maydell | static void vexpress_common_init(const VEDBoardInfo *daughterboard, |
397 | f3cdbc32 | Peter Maydell | QEMUMachineInitArgs *args) |
398 | 4c3b29b8 | Peter Maydell | { |
399 | 4c3b29b8 | Peter Maydell | DeviceState *dev, *sysctl, *pl041; |
400 | 4c3b29b8 | Peter Maydell | qemu_irq pic[64];
|
401 | 4c3b29b8 | Peter Maydell | uint32_t sys_id; |
402 | 3dc3e7dd | Francesco Lavra | DriveInfo *dinfo; |
403 | 4c3b29b8 | Peter Maydell | ram_addr_t vram_size, sram_size; |
404 | 4c3b29b8 | Peter Maydell | MemoryRegion *sysmem = get_system_memory(); |
405 | 4c3b29b8 | Peter Maydell | MemoryRegion *vram = g_new(MemoryRegion, 1);
|
406 | 4c3b29b8 | Peter Maydell | MemoryRegion *sram = g_new(MemoryRegion, 1);
|
407 | a8170e5e | Avi Kivity | const hwaddr *map = daughterboard->motherboard_map;
|
408 | 31410948 | Peter Maydell | int i;
|
409 | 4c3b29b8 | Peter Maydell | |
410 | cdef10bb | Peter Maydell | daughterboard->init(daughterboard, args->ram_size, args->cpu_model, pic); |
411 | 4c3b29b8 | Peter Maydell | |
412 | 2558e0a6 | Peter Maydell | /* Motherboard peripherals: the wiring is the same but the
|
413 | 2558e0a6 | Peter Maydell | * addresses vary between the legacy and A-Series memory maps.
|
414 | 2558e0a6 | Peter Maydell | */
|
415 | 2558e0a6 | Peter Maydell | |
416 | 2055283b | Peter Maydell | sys_id = 0x1190f500;
|
417 | 2055283b | Peter Maydell | |
418 | 2055283b | Peter Maydell | sysctl = qdev_create(NULL, "realview_sysctl"); |
419 | 2055283b | Peter Maydell | qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
|
420 | cdef10bb | Peter Maydell | qdev_prop_set_uint32(sysctl, "proc_id", daughterboard->proc_id);
|
421 | 31410948 | Peter Maydell | qdev_prop_set_uint32(sysctl, "len-db-voltage",
|
422 | 31410948 | Peter Maydell | daughterboard->num_voltage_sensors); |
423 | 31410948 | Peter Maydell | for (i = 0; i < daughterboard->num_voltage_sensors; i++) { |
424 | 31410948 | Peter Maydell | char *propname = g_strdup_printf("db-voltage[%d]", i); |
425 | 31410948 | Peter Maydell | qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); |
426 | 31410948 | Peter Maydell | g_free(propname); |
427 | 31410948 | Peter Maydell | } |
428 | 9c7d4893 | Peter Maydell | qdev_prop_set_uint32(sysctl, "len-db-clock",
|
429 | 9c7d4893 | Peter Maydell | daughterboard->num_clocks); |
430 | 9c7d4893 | Peter Maydell | for (i = 0; i < daughterboard->num_clocks; i++) { |
431 | 9c7d4893 | Peter Maydell | char *propname = g_strdup_printf("db-clock[%d]", i); |
432 | 9c7d4893 | Peter Maydell | qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); |
433 | 9c7d4893 | Peter Maydell | g_free(propname); |
434 | 9c7d4893 | Peter Maydell | } |
435 | 7a65c8cc | Peter Maydell | qdev_init_nofail(sysctl); |
436 | 1356b98d | Andreas Färber | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);
|
437 | 2558e0a6 | Peter Maydell | |
438 | 2558e0a6 | Peter Maydell | /* VE_SP810: not modelled */
|
439 | 2558e0a6 | Peter Maydell | /* VE_SERIALPCI: not modelled */
|
440 | 2055283b | Peter Maydell | |
441 | 03a0e944 | Peter Maydell | pl041 = qdev_create(NULL, "pl041"); |
442 | 03a0e944 | Peter Maydell | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); |
443 | 03a0e944 | Peter Maydell | qdev_init_nofail(pl041); |
444 | 1356b98d | Andreas Färber | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, map[VE_PL041]);
|
445 | 1356b98d | Andreas Färber | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[11]); |
446 | 2055283b | Peter Maydell | |
447 | 2558e0a6 | Peter Maydell | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
448 | 2055283b | Peter Maydell | /* Wire up MMC card detect and read-only signals */
|
449 | 2055283b | Peter Maydell | qdev_connect_gpio_out(dev, 0,
|
450 | 2055283b | Peter Maydell | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); |
451 | 2055283b | Peter Maydell | qdev_connect_gpio_out(dev, 1,
|
452 | 2055283b | Peter Maydell | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); |
453 | 2055283b | Peter Maydell | |
454 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
455 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); |
456 | 2055283b | Peter Maydell | |
457 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART0], pic[5]); |
458 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART1], pic[6]); |
459 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART2], pic[7]); |
460 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl011", map[VE_UART3], pic[8]); |
461 | 2055283b | Peter Maydell | |
462 | 2558e0a6 | Peter Maydell | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
463 | 2558e0a6 | Peter Maydell | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); |
464 | 2055283b | Peter Maydell | |
465 | 2558e0a6 | Peter Maydell | /* VE_SERIALDVI: not modelled */
|
466 | 2055283b | Peter Maydell | |
467 | 2558e0a6 | Peter Maydell | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
468 | 2055283b | Peter Maydell | |
469 | 2558e0a6 | Peter Maydell | /* VE_COMPACTFLASH: not modelled */
|
470 | 2055283b | Peter Maydell | |
471 | b7206878 | Peter Maydell | sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); |
472 | 2055283b | Peter Maydell | |
473 | 3dc3e7dd | Francesco Lavra | dinfo = drive_get_next(IF_PFLASH); |
474 | 3dc3e7dd | Francesco Lavra | if (!pflash_cfi01_register(map[VE_NORFLASH0], NULL, "vexpress.flash0", |
475 | 3dc3e7dd | Francesco Lavra | VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
|
476 | 3dc3e7dd | Francesco Lavra | VEXPRESS_FLASH_SECT_SIZE, |
477 | 3dc3e7dd | Francesco Lavra | VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
|
478 | 3dc3e7dd | Francesco Lavra | 0x00, 0x89, 0x00, 0x18, 0)) { |
479 | 3dc3e7dd | Francesco Lavra | fprintf(stderr, "vexpress: error registering flash 0.\n");
|
480 | 3dc3e7dd | Francesco Lavra | exit(1);
|
481 | 3dc3e7dd | Francesco Lavra | } |
482 | 3dc3e7dd | Francesco Lavra | |
483 | 3dc3e7dd | Francesco Lavra | dinfo = drive_get_next(IF_PFLASH); |
484 | 3dc3e7dd | Francesco Lavra | if (!pflash_cfi01_register(map[VE_NORFLASH1], NULL, "vexpress.flash1", |
485 | 3dc3e7dd | Francesco Lavra | VEXPRESS_FLASH_SIZE, dinfo ? dinfo->bdrv : NULL,
|
486 | 3dc3e7dd | Francesco Lavra | VEXPRESS_FLASH_SECT_SIZE, |
487 | 3dc3e7dd | Francesco Lavra | VEXPRESS_FLASH_SIZE / VEXPRESS_FLASH_SECT_SIZE, 4,
|
488 | 3dc3e7dd | Francesco Lavra | 0x00, 0x89, 0x00, 0x18, 0)) { |
489 | 3dc3e7dd | Francesco Lavra | fprintf(stderr, "vexpress: error registering flash 1.\n");
|
490 | 3dc3e7dd | Francesco Lavra | exit(1);
|
491 | 3dc3e7dd | Francesco Lavra | } |
492 | 2558e0a6 | Peter Maydell | |
493 | 2055283b | Peter Maydell | sram_size = 0x2000000;
|
494 | c5705a77 | Avi Kivity | memory_region_init_ram(sram, "vexpress.sram", sram_size);
|
495 | c5705a77 | Avi Kivity | vmstate_register_ram_global(sram); |
496 | 2558e0a6 | Peter Maydell | memory_region_add_subregion(sysmem, map[VE_SRAM], sram); |
497 | 2055283b | Peter Maydell | |
498 | 2055283b | Peter Maydell | vram_size = 0x800000;
|
499 | c5705a77 | Avi Kivity | memory_region_init_ram(vram, "vexpress.vram", vram_size);
|
500 | c5705a77 | Avi Kivity | vmstate_register_ram_global(vram); |
501 | 2558e0a6 | Peter Maydell | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); |
502 | 2055283b | Peter Maydell | |
503 | 2055283b | Peter Maydell | /* 0x4e000000 LAN9118 Ethernet */
|
504 | a005d073 | Stefan Hajnoczi | if (nd_table[0].used) { |
505 | 2558e0a6 | Peter Maydell | lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); |
506 | 2055283b | Peter Maydell | } |
507 | 2055283b | Peter Maydell | |
508 | 2558e0a6 | Peter Maydell | /* VE_USB: not modelled */
|
509 | 2558e0a6 | Peter Maydell | |
510 | 2558e0a6 | Peter Maydell | /* VE_DAPROM: not modelled */
|
511 | 2055283b | Peter Maydell | |
512 | f3cdbc32 | Peter Maydell | vexpress_binfo.ram_size = args->ram_size; |
513 | f3cdbc32 | Peter Maydell | vexpress_binfo.kernel_filename = args->kernel_filename; |
514 | f3cdbc32 | Peter Maydell | vexpress_binfo.kernel_cmdline = args->kernel_cmdline; |
515 | f3cdbc32 | Peter Maydell | vexpress_binfo.initrd_filename = args->initrd_filename; |
516 | 2055283b | Peter Maydell | vexpress_binfo.nb_cpus = smp_cpus; |
517 | 2055283b | Peter Maydell | vexpress_binfo.board_id = VEXPRESS_BOARD_ID; |
518 | 4c3b29b8 | Peter Maydell | vexpress_binfo.loader_start = daughterboard->loader_start; |
519 | aac1e02c | Peter Maydell | vexpress_binfo.smp_loader_start = map[VE_SRAM]; |
520 | 2558e0a6 | Peter Maydell | vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30;
|
521 | 96eacf64 | Peter Maydell | vexpress_binfo.gic_cpu_if_addr = daughterboard->gic_cpu_if_addr; |
522 | 3aaa8dfa | Andreas Färber | arm_load_kernel(arm_env_get_cpu(first_cpu), &vexpress_binfo); |
523 | 2055283b | Peter Maydell | } |
524 | 2055283b | Peter Maydell | |
525 | 5f072e1f | Eduardo Habkost | static void vexpress_a9_init(QEMUMachineInitArgs *args) |
526 | 4c3b29b8 | Peter Maydell | { |
527 | f3cdbc32 | Peter Maydell | vexpress_common_init(&a9_daughterboard, args); |
528 | 4c3b29b8 | Peter Maydell | } |
529 | 2055283b | Peter Maydell | |
530 | 5f072e1f | Eduardo Habkost | static void vexpress_a15_init(QEMUMachineInitArgs *args) |
531 | 961f195e | Peter Maydell | { |
532 | f3cdbc32 | Peter Maydell | vexpress_common_init(&a15_daughterboard, args); |
533 | 961f195e | Peter Maydell | } |
534 | 961f195e | Peter Maydell | |
535 | 2055283b | Peter Maydell | static QEMUMachine vexpress_a9_machine = {
|
536 | 2055283b | Peter Maydell | .name = "vexpress-a9",
|
537 | 2055283b | Peter Maydell | .desc = "ARM Versatile Express for Cortex-A9",
|
538 | 2055283b | Peter Maydell | .init = vexpress_a9_init, |
539 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
540 | 2055283b | Peter Maydell | .max_cpus = 4,
|
541 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
542 | 2055283b | Peter Maydell | }; |
543 | 2055283b | Peter Maydell | |
544 | 961f195e | Peter Maydell | static QEMUMachine vexpress_a15_machine = {
|
545 | 961f195e | Peter Maydell | .name = "vexpress-a15",
|
546 | 961f195e | Peter Maydell | .desc = "ARM Versatile Express for Cortex-A15",
|
547 | 961f195e | Peter Maydell | .init = vexpress_a15_init, |
548 | 2d0d2837 | Christian Borntraeger | .block_default_type = IF_SCSI, |
549 | 961f195e | Peter Maydell | .max_cpus = 4,
|
550 | e4ada29e | Avik Sil | DEFAULT_MACHINE_OPTIONS, |
551 | 961f195e | Peter Maydell | }; |
552 | 961f195e | Peter Maydell | |
553 | 2055283b | Peter Maydell | static void vexpress_machine_init(void) |
554 | 2055283b | Peter Maydell | { |
555 | 2055283b | Peter Maydell | qemu_register_machine(&vexpress_a9_machine); |
556 | 961f195e | Peter Maydell | qemu_register_machine(&vexpress_a15_machine); |
557 | 2055283b | Peter Maydell | } |
558 | 2055283b | Peter Maydell | |
559 | 2055283b | Peter Maydell | machine_init(vexpress_machine_init); |