root / hw / sparc32_dma.c @ dd4239d6
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1 | 67e999be | bellard | /*
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2 | 67e999be | bellard | * QEMU Sparc32 DMA controller emulation
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3 | 67e999be | bellard | *
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4 | 67e999be | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 67e999be | bellard | *
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6 | 67e999be | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 67e999be | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 67e999be | bellard | * in the Software without restriction, including without limitation the rights
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9 | 67e999be | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 67e999be | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 67e999be | bellard | * furnished to do so, subject to the following conditions:
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12 | 67e999be | bellard | *
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13 | 67e999be | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 67e999be | bellard | * all copies or substantial portions of the Software.
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15 | 67e999be | bellard | *
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16 | 67e999be | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 67e999be | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 67e999be | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 67e999be | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 67e999be | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 67e999be | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 67e999be | bellard | * THE SOFTWARE.
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23 | 67e999be | bellard | */
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24 | 6f6260c7 | Blue Swirl | |
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 87ecb68b | pbrook | #include "sparc32_dma.h" |
27 | 87ecb68b | pbrook | #include "sun4m.h" |
28 | 6f6260c7 | Blue Swirl | #include "sysbus.h" |
29 | 67e999be | bellard | |
30 | 67e999be | bellard | /* debug DMA */
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31 | 67e999be | bellard | //#define DEBUG_DMA
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32 | 67e999be | bellard | |
33 | 67e999be | bellard | /*
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34 | 67e999be | bellard | * This is the DMA controller part of chip STP2000 (Master I/O), also
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35 | 67e999be | bellard | * produced as NCR89C100. See
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36 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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37 | 67e999be | bellard | * and
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38 | 67e999be | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
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39 | 67e999be | bellard | */
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40 | 67e999be | bellard | |
41 | 67e999be | bellard | #ifdef DEBUG_DMA
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42 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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43 | 001faf32 | Blue Swirl | do { printf("DMA: " fmt , ## __VA_ARGS__); } while (0) |
44 | 67e999be | bellard | #else
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45 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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46 | 67e999be | bellard | #endif
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47 | 67e999be | bellard | |
48 | 5aca8c3b | blueswir1 | #define DMA_REGS 4 |
49 | 5aca8c3b | blueswir1 | #define DMA_SIZE (4 * sizeof(uint32_t)) |
50 | 09723aa1 | blueswir1 | /* We need the mask, because one instance of the device is not page
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51 | 09723aa1 | blueswir1 | aligned (ledma, start address 0x0010) */
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52 | 09723aa1 | blueswir1 | #define DMA_MASK (DMA_SIZE - 1) |
53 | 67e999be | bellard | |
54 | 67e999be | bellard | #define DMA_VER 0xa0000000 |
55 | 67e999be | bellard | #define DMA_INTR 1 |
56 | 67e999be | bellard | #define DMA_INTREN 0x10 |
57 | 67e999be | bellard | #define DMA_WRITE_MEM 0x100 |
58 | 67e999be | bellard | #define DMA_LOADED 0x04000000 |
59 | 5aca8c3b | blueswir1 | #define DMA_DRAIN_FIFO 0x40 |
60 | 67e999be | bellard | #define DMA_RESET 0x80 |
61 | 67e999be | bellard | |
62 | 67e999be | bellard | typedef struct DMAState DMAState; |
63 | 67e999be | bellard | |
64 | 67e999be | bellard | struct DMAState {
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65 | 6f6260c7 | Blue Swirl | SysBusDevice busdev; |
66 | 67e999be | bellard | uint32_t dmaregs[DMA_REGS]; |
67 | 5aca8c3b | blueswir1 | qemu_irq irq; |
68 | 2d069bab | blueswir1 | void *iommu;
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69 | 2d069bab | blueswir1 | qemu_irq dev_reset; |
70 | 67e999be | bellard | }; |
71 | 67e999be | bellard | |
72 | 9b94dc32 | bellard | /* Note: on sparc, the lance 16 bit bus is swapped */
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73 | c227f099 | Anthony Liguori | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
74 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
75 | 67e999be | bellard | { |
76 | 67e999be | bellard | DMAState *s = opaque; |
77 | 9b94dc32 | bellard | int i;
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78 | 67e999be | bellard | |
79 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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80 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
81 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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82 | 9b94dc32 | bellard | if (do_bswap) {
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83 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
84 | 9b94dc32 | bellard | } else {
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85 | 9b94dc32 | bellard | addr &= ~1;
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86 | 9b94dc32 | bellard | len &= ~1;
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87 | 9b94dc32 | bellard | sparc_iommu_memory_read(s->iommu, addr, buf, len); |
88 | 9b94dc32 | bellard | for(i = 0; i < len; i += 2) { |
89 | 9b94dc32 | bellard | bswap16s((uint16_t *)(buf + i)); |
90 | 9b94dc32 | bellard | } |
91 | 9b94dc32 | bellard | } |
92 | 67e999be | bellard | } |
93 | 67e999be | bellard | |
94 | c227f099 | Anthony Liguori | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
95 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap) |
96 | 67e999be | bellard | { |
97 | 67e999be | bellard | DMAState *s = opaque; |
98 | 9b94dc32 | bellard | int l, i;
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99 | 9b94dc32 | bellard | uint16_t tmp_buf[32];
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100 | 67e999be | bellard | |
101 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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102 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
103 | 5aca8c3b | blueswir1 | addr |= s->dmaregs[3];
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104 | 9b94dc32 | bellard | if (do_bswap) {
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105 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, buf, len); |
106 | 9b94dc32 | bellard | } else {
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107 | 9b94dc32 | bellard | addr &= ~1;
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108 | 9b94dc32 | bellard | len &= ~1;
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109 | 9b94dc32 | bellard | while (len > 0) { |
110 | 9b94dc32 | bellard | l = len; |
111 | 9b94dc32 | bellard | if (l > sizeof(tmp_buf)) |
112 | 9b94dc32 | bellard | l = sizeof(tmp_buf);
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113 | 9b94dc32 | bellard | for(i = 0; i < l; i += 2) { |
114 | 9b94dc32 | bellard | tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
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115 | 9b94dc32 | bellard | } |
116 | 9b94dc32 | bellard | sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l); |
117 | 9b94dc32 | bellard | len -= l; |
118 | 9b94dc32 | bellard | buf += l; |
119 | 9b94dc32 | bellard | addr += l; |
120 | 9b94dc32 | bellard | } |
121 | 9b94dc32 | bellard | } |
122 | 67e999be | bellard | } |
123 | 67e999be | bellard | |
124 | 70c0de96 | blueswir1 | static void dma_set_irq(void *opaque, int irq, int level) |
125 | 67e999be | bellard | { |
126 | 67e999be | bellard | DMAState *s = opaque; |
127 | 70c0de96 | blueswir1 | if (level) {
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128 | 9b5207aa | blueswir1 | DPRINTF("Raise IRQ\n");
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129 | 70c0de96 | blueswir1 | s->dmaregs[0] |= DMA_INTR;
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130 | 70c0de96 | blueswir1 | qemu_irq_raise(s->irq); |
131 | 70c0de96 | blueswir1 | } else {
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132 | 70c0de96 | blueswir1 | s->dmaregs[0] &= ~DMA_INTR;
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133 | 9b5207aa | blueswir1 | DPRINTF("Lower IRQ\n");
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134 | 70c0de96 | blueswir1 | qemu_irq_lower(s->irq); |
135 | 70c0de96 | blueswir1 | } |
136 | 67e999be | bellard | } |
137 | 67e999be | bellard | |
138 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
139 | 67e999be | bellard | { |
140 | 67e999be | bellard | DMAState *s = opaque; |
141 | 67e999be | bellard | |
142 | 67e999be | bellard | DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
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143 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
144 | 67e999be | bellard | sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
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145 | 67e999be | bellard | s->dmaregs[0] |= DMA_INTR;
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146 | 67e999be | bellard | s->dmaregs[1] += len;
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147 | 67e999be | bellard | } |
148 | 67e999be | bellard | |
149 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len) |
150 | 67e999be | bellard | { |
151 | 67e999be | bellard | DMAState *s = opaque; |
152 | 67e999be | bellard | |
153 | 67e999be | bellard | DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
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154 | 67e999be | bellard | s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]); |
155 | 67e999be | bellard | sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
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156 | 67e999be | bellard | s->dmaregs[0] |= DMA_INTR;
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157 | 67e999be | bellard | s->dmaregs[1] += len;
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158 | 67e999be | bellard | } |
159 | 67e999be | bellard | |
160 | c227f099 | Anthony Liguori | static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr) |
161 | 67e999be | bellard | { |
162 | 67e999be | bellard | DMAState *s = opaque; |
163 | 67e999be | bellard | uint32_t saddr; |
164 | 67e999be | bellard | |
165 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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166 | 5aca8c3b | blueswir1 | DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr, |
167 | 5aca8c3b | blueswir1 | s->dmaregs[saddr]); |
168 | 67e999be | bellard | |
169 | 67e999be | bellard | return s->dmaregs[saddr];
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170 | 67e999be | bellard | } |
171 | 67e999be | bellard | |
172 | c227f099 | Anthony Liguori | static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
173 | 67e999be | bellard | { |
174 | 67e999be | bellard | DMAState *s = opaque; |
175 | 67e999be | bellard | uint32_t saddr; |
176 | 67e999be | bellard | |
177 | 09723aa1 | blueswir1 | saddr = (addr & DMA_MASK) >> 2;
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178 | 5aca8c3b | blueswir1 | DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr, |
179 | 5aca8c3b | blueswir1 | s->dmaregs[saddr], val); |
180 | 67e999be | bellard | switch (saddr) {
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181 | 67e999be | bellard | case 0: |
182 | d537cf6c | pbrook | if (!(val & DMA_INTREN)) {
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183 | 5aca8c3b | blueswir1 | DPRINTF("Lower IRQ\n");
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184 | 5aca8c3b | blueswir1 | qemu_irq_lower(s->irq); |
185 | d537cf6c | pbrook | } |
186 | 67e999be | bellard | if (val & DMA_RESET) {
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187 | 2d069bab | blueswir1 | qemu_irq_raise(s->dev_reset); |
188 | 2d069bab | blueswir1 | qemu_irq_lower(s->dev_reset); |
189 | 5aca8c3b | blueswir1 | } else if (val & DMA_DRAIN_FIFO) { |
190 | 5aca8c3b | blueswir1 | val &= ~DMA_DRAIN_FIFO; |
191 | 67e999be | bellard | } else if (val == 0) |
192 | 5aca8c3b | blueswir1 | val = DMA_DRAIN_FIFO; |
193 | 67e999be | bellard | val &= 0x0fffffff;
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194 | 67e999be | bellard | val |= DMA_VER; |
195 | 67e999be | bellard | break;
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196 | 67e999be | bellard | case 1: |
197 | 67e999be | bellard | s->dmaregs[0] |= DMA_LOADED;
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198 | 67e999be | bellard | break;
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199 | 67e999be | bellard | default:
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200 | 67e999be | bellard | break;
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201 | 67e999be | bellard | } |
202 | 67e999be | bellard | s->dmaregs[saddr] = val; |
203 | 67e999be | bellard | } |
204 | 67e999be | bellard | |
205 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const dma_mem_read[3] = { |
206 | 7c560456 | blueswir1 | NULL,
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207 | 7c560456 | blueswir1 | NULL,
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208 | 67e999be | bellard | dma_mem_readl, |
209 | 67e999be | bellard | }; |
210 | 67e999be | bellard | |
211 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const dma_mem_write[3] = { |
212 | 7c560456 | blueswir1 | NULL,
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213 | 7c560456 | blueswir1 | NULL,
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214 | 67e999be | bellard | dma_mem_writel, |
215 | 67e999be | bellard | }; |
216 | 67e999be | bellard | |
217 | 49ef6c90 | Blue Swirl | static void dma_reset(DeviceState *d) |
218 | 67e999be | bellard | { |
219 | 49ef6c90 | Blue Swirl | DMAState *s = container_of(d, DMAState, busdev.qdev); |
220 | 67e999be | bellard | |
221 | 5aca8c3b | blueswir1 | memset(s->dmaregs, 0, DMA_SIZE);
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222 | 67e999be | bellard | s->dmaregs[0] = DMA_VER;
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223 | 67e999be | bellard | } |
224 | 67e999be | bellard | |
225 | 75c497dc | Blue Swirl | static const VMStateDescription vmstate_dma = { |
226 | 75c497dc | Blue Swirl | .name ="sparc32_dma",
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227 | 75c497dc | Blue Swirl | .version_id = 2,
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228 | 75c497dc | Blue Swirl | .minimum_version_id = 2,
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229 | 75c497dc | Blue Swirl | .minimum_version_id_old = 2,
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230 | 75c497dc | Blue Swirl | .fields = (VMStateField []) { |
231 | 75c497dc | Blue Swirl | VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS), |
232 | 75c497dc | Blue Swirl | VMSTATE_END_OF_LIST() |
233 | 75c497dc | Blue Swirl | } |
234 | 75c497dc | Blue Swirl | }; |
235 | 67e999be | bellard | |
236 | 81a322d4 | Gerd Hoffmann | static int sparc32_dma_init1(SysBusDevice *dev) |
237 | 6f6260c7 | Blue Swirl | { |
238 | 6f6260c7 | Blue Swirl | DMAState *s = FROM_SYSBUS(DMAState, dev); |
239 | 6f6260c7 | Blue Swirl | int dma_io_memory;
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240 | 67e999be | bellard | |
241 | 6f6260c7 | Blue Swirl | sysbus_init_irq(dev, &s->irq); |
242 | 67e999be | bellard | |
243 | 1eed09cb | Avi Kivity | dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s); |
244 | 6f6260c7 | Blue Swirl | sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory); |
245 | 67e999be | bellard | |
246 | 6f6260c7 | Blue Swirl | qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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247 | 74ff8d90 | Blue Swirl | qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1);
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248 | 49ef6c90 | Blue Swirl | |
249 | 81a322d4 | Gerd Hoffmann | return 0; |
250 | 6f6260c7 | Blue Swirl | } |
251 | 67e999be | bellard | |
252 | 6f6260c7 | Blue Swirl | static SysBusDeviceInfo sparc32_dma_info = {
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253 | 6f6260c7 | Blue Swirl | .init = sparc32_dma_init1, |
254 | 6f6260c7 | Blue Swirl | .qdev.name = "sparc32_dma",
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255 | 6f6260c7 | Blue Swirl | .qdev.size = sizeof(DMAState),
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256 | 49ef6c90 | Blue Swirl | .qdev.vmsd = &vmstate_dma, |
257 | 49ef6c90 | Blue Swirl | .qdev.reset = dma_reset, |
258 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
259 | 3180d772 | Gerd Hoffmann | DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),
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260 | 3180d772 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
261 | 6f6260c7 | Blue Swirl | } |
262 | 6f6260c7 | Blue Swirl | }; |
263 | 6f6260c7 | Blue Swirl | |
264 | 6f6260c7 | Blue Swirl | static void sparc32_dma_register_devices(void) |
265 | 6f6260c7 | Blue Swirl | { |
266 | 6f6260c7 | Blue Swirl | sysbus_register_withprop(&sparc32_dma_info); |
267 | 67e999be | bellard | } |
268 | 6f6260c7 | Blue Swirl | |
269 | 6f6260c7 | Blue Swirl | device_init(sparc32_dma_register_devices) |