root / hw / mcf_intc.c @ dd4239d6
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/*
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* ColdFire Interrupt Controller emulation.
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*
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* Copyright (c) 2007 CodeSourcery.
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*
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* This code is licenced under the GPL
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*/
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#include "hw.h" |
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#include "mcf.h" |
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typedef struct { |
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uint64_t ipr; |
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uint64_t imr; |
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uint64_t ifr; |
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uint64_t enabled; |
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uint8_t icr[64];
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CPUState *env; |
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int active_vector;
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} mcf_intc_state; |
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static void mcf_intc_update(mcf_intc_state *s) |
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{ |
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uint64_t active; |
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int i;
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int best;
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int best_level;
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active = (s->ipr | s->ifr) & s->enabled & ~s->imr; |
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best_level = 0;
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best = 64;
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if (active) {
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for (i = 0; i < 64; i++) { |
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if ((active & 1) != 0 && s->icr[i] >= best_level) { |
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best_level = s->icr[i]; |
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best = i; |
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} |
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active >>= 1;
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} |
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} |
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s->active_vector = ((best == 64) ? 24 : (best + 64)); |
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m68k_set_irq_level(s->env, best_level, s->active_vector); |
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} |
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static uint32_t mcf_intc_read(void *opaque, target_phys_addr_t addr) |
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{ |
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int offset;
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mcf_intc_state *s = (mcf_intc_state *)opaque; |
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offset = addr & 0xff;
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if (offset >= 0x40 && offset < 0x80) { |
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return s->icr[offset - 0x40]; |
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} |
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switch (offset) {
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case 0x00: |
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return (uint32_t)(s->ipr >> 32); |
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case 0x04: |
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return (uint32_t)s->ipr;
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case 0x08: |
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return (uint32_t)(s->imr >> 32); |
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case 0x0c: |
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return (uint32_t)s->imr;
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case 0x10: |
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return (uint32_t)(s->ifr >> 32); |
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case 0x14: |
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return (uint32_t)s->ifr;
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case 0xe0: /* SWIACK. */ |
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return s->active_vector;
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case 0xe1: case 0xe2: case 0xe3: case 0xe4: |
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case 0xe5: case 0xe6: case 0xe7: |
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/* LnIACK */
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hw_error("mcf_intc_read: LnIACK not implemented\n");
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default:
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return 0; |
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} |
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} |
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static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val) |
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{ |
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int offset;
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mcf_intc_state *s = (mcf_intc_state *)opaque; |
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offset = addr & 0xff;
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if (offset >= 0x40 && offset < 0x80) { |
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int n = offset - 0x40; |
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s->icr[n] = val; |
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if (val == 0) |
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s->enabled &= ~(1ull << n);
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else
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s->enabled |= (1ull << n);
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mcf_intc_update(s); |
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return;
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} |
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switch (offset) {
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case 0x00: case 0x04: |
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/* Ignore IPR writes. */
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return;
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case 0x08: |
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s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32); |
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break;
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case 0x0c: |
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s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;
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break;
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default:
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hw_error("mcf_intc_write: Bad write offset %d\n", offset);
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break;
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} |
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mcf_intc_update(s); |
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} |
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static void mcf_intc_set_irq(void *opaque, int irq, int level) |
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{ |
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mcf_intc_state *s = (mcf_intc_state *)opaque; |
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if (irq >= 64) |
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return;
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if (level)
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s->ipr |= 1ull << irq;
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else
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s->ipr &= ~(1ull << irq);
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mcf_intc_update(s); |
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} |
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static void mcf_intc_reset(mcf_intc_state *s) |
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{ |
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s->imr = ~0ull;
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s->ipr = 0;
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s->ifr = 0;
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s->enabled = 0;
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memset(s->icr, 0, 64); |
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s->active_vector = 24;
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} |
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static CPUReadMemoryFunc * const mcf_intc_readfn[] = { |
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mcf_intc_read, |
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mcf_intc_read, |
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mcf_intc_read |
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}; |
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static CPUWriteMemoryFunc * const mcf_intc_writefn[] = { |
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mcf_intc_write, |
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mcf_intc_write, |
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mcf_intc_write |
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}; |
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qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env) |
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{ |
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mcf_intc_state *s; |
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int iomemtype;
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s = qemu_mallocz(sizeof(mcf_intc_state));
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s->env = env; |
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mcf_intc_reset(s); |
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iomemtype = cpu_register_io_memory(mcf_intc_readfn, |
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mcf_intc_writefn, s); |
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cpu_register_physical_memory(base, 0x100, iomemtype);
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return qemu_allocate_irqs(mcf_intc_set_irq, s, 64); |
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} |