root / hw / pci.c @ dd4239d6
History | View | Annotate | Download (43.3 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU PCI bus manager
|
| 3 |
*
|
| 4 |
* Copyright (c) 2004 Fabrice Bellard
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
#include "hw.h" |
| 25 |
#include "pci.h" |
| 26 |
#include "pci_host.h" |
| 27 |
#include "monitor.h" |
| 28 |
#include "net.h" |
| 29 |
#include "sysemu.h" |
| 30 |
|
| 31 |
//#define DEBUG_PCI
|
| 32 |
#ifdef DEBUG_PCI
|
| 33 |
# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
| 34 |
#else
|
| 35 |
# define PCI_DPRINTF(format, ...) do { } while (0) |
| 36 |
#endif
|
| 37 |
|
| 38 |
struct PCIBus {
|
| 39 |
BusState qbus; |
| 40 |
int devfn_min;
|
| 41 |
pci_set_irq_fn set_irq; |
| 42 |
pci_map_irq_fn map_irq; |
| 43 |
pci_hotplug_fn hotplug; |
| 44 |
uint32_t config_reg; /* XXX: suppress */
|
| 45 |
void *irq_opaque;
|
| 46 |
PCIDevice *devices[256];
|
| 47 |
PCIDevice *parent_dev; |
| 48 |
|
| 49 |
QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
|
| 50 |
QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
|
| 51 |
|
| 52 |
/* The bus IRQ state is the logical OR of the connected devices.
|
| 53 |
Keep a count of the number of devices with raised IRQs. */
|
| 54 |
int nirq;
|
| 55 |
int *irq_count;
|
| 56 |
}; |
| 57 |
|
| 58 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
| 59 |
|
| 60 |
static struct BusInfo pci_bus_info = { |
| 61 |
.name = "PCI",
|
| 62 |
.size = sizeof(PCIBus),
|
| 63 |
.print_dev = pcibus_dev_print, |
| 64 |
.props = (Property[]) {
|
| 65 |
DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
| 66 |
DEFINE_PROP_END_OF_LIST() |
| 67 |
} |
| 68 |
}; |
| 69 |
|
| 70 |
static void pci_update_mappings(PCIDevice *d); |
| 71 |
static void pci_set_irq(void *opaque, int irq_num, int level); |
| 72 |
|
| 73 |
target_phys_addr_t pci_mem_base; |
| 74 |
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
|
| 75 |
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
|
| 76 |
|
| 77 |
struct PCIHostBus {
|
| 78 |
int domain;
|
| 79 |
struct PCIBus *bus;
|
| 80 |
QLIST_ENTRY(PCIHostBus) next; |
| 81 |
}; |
| 82 |
static QLIST_HEAD(, PCIHostBus) host_buses;
|
| 83 |
|
| 84 |
static const VMStateDescription vmstate_pcibus = { |
| 85 |
.name = "PCIBUS",
|
| 86 |
.version_id = 1,
|
| 87 |
.minimum_version_id = 1,
|
| 88 |
.minimum_version_id_old = 1,
|
| 89 |
.fields = (VMStateField []) {
|
| 90 |
VMSTATE_INT32_EQUAL(nirq, PCIBus), |
| 91 |
VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
|
| 92 |
VMSTATE_END_OF_LIST() |
| 93 |
} |
| 94 |
}; |
| 95 |
|
| 96 |
static int pci_bar(PCIDevice *d, int reg) |
| 97 |
{
|
| 98 |
uint8_t type; |
| 99 |
|
| 100 |
if (reg != PCI_ROM_SLOT)
|
| 101 |
return PCI_BASE_ADDRESS_0 + reg * 4; |
| 102 |
|
| 103 |
type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
| 104 |
return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
|
| 105 |
} |
| 106 |
|
| 107 |
static void pci_device_reset(PCIDevice *dev) |
| 108 |
{
|
| 109 |
int r;
|
| 110 |
|
| 111 |
memset(dev->irq_state, 0, sizeof dev->irq_state); |
| 112 |
dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 113 |
PCI_COMMAND_MASTER); |
| 114 |
dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
|
| 115 |
dev->config[PCI_INTERRUPT_LINE] = 0x0;
|
| 116 |
for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
| 117 |
if (!dev->io_regions[r].size) {
|
| 118 |
continue;
|
| 119 |
} |
| 120 |
pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type); |
| 121 |
} |
| 122 |
pci_update_mappings(dev); |
| 123 |
} |
| 124 |
|
| 125 |
static void pci_bus_reset(void *opaque) |
| 126 |
{
|
| 127 |
PCIBus *bus = opaque; |
| 128 |
int i;
|
| 129 |
|
| 130 |
for (i = 0; i < bus->nirq; i++) { |
| 131 |
bus->irq_count[i] = 0;
|
| 132 |
} |
| 133 |
for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
| 134 |
if (bus->devices[i]) {
|
| 135 |
pci_device_reset(bus->devices[i]); |
| 136 |
} |
| 137 |
} |
| 138 |
} |
| 139 |
|
| 140 |
static void pci_host_bus_register(int domain, PCIBus *bus) |
| 141 |
{
|
| 142 |
struct PCIHostBus *host;
|
| 143 |
host = qemu_mallocz(sizeof(*host));
|
| 144 |
host->domain = domain; |
| 145 |
host->bus = bus; |
| 146 |
QLIST_INSERT_HEAD(&host_buses, host, next); |
| 147 |
} |
| 148 |
|
| 149 |
PCIBus *pci_find_host_bus(int domain)
|
| 150 |
{
|
| 151 |
struct PCIHostBus *host;
|
| 152 |
|
| 153 |
QLIST_FOREACH(host, &host_buses, next) {
|
| 154 |
if (host->domain == domain) {
|
| 155 |
return host->bus;
|
| 156 |
} |
| 157 |
} |
| 158 |
|
| 159 |
return NULL; |
| 160 |
} |
| 161 |
|
| 162 |
void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
|
| 163 |
const char *name, int devfn_min) |
| 164 |
{
|
| 165 |
static int nbus = 0; |
| 166 |
|
| 167 |
qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name); |
| 168 |
bus->devfn_min = devfn_min; |
| 169 |
|
| 170 |
/* host bridge */
|
| 171 |
QLIST_INIT(&bus->child); |
| 172 |
pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ |
| 173 |
|
| 174 |
vmstate_register(nbus++, &vmstate_pcibus, bus); |
| 175 |
qemu_register_reset(pci_bus_reset, bus); |
| 176 |
} |
| 177 |
|
| 178 |
PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min) |
| 179 |
{
|
| 180 |
PCIBus *bus; |
| 181 |
|
| 182 |
bus = qemu_mallocz(sizeof(*bus));
|
| 183 |
bus->qbus.qdev_allocated = 1;
|
| 184 |
pci_bus_new_inplace(bus, parent, name, devfn_min); |
| 185 |
return bus;
|
| 186 |
} |
| 187 |
|
| 188 |
void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
|
| 189 |
void *irq_opaque, int nirq) |
| 190 |
{
|
| 191 |
bus->set_irq = set_irq; |
| 192 |
bus->map_irq = map_irq; |
| 193 |
bus->irq_opaque = irq_opaque; |
| 194 |
bus->nirq = nirq; |
| 195 |
bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0])); |
| 196 |
} |
| 197 |
|
| 198 |
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
|
| 199 |
{
|
| 200 |
bus->qbus.allow_hotplug = 1;
|
| 201 |
bus->hotplug = hotplug; |
| 202 |
} |
| 203 |
|
| 204 |
PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
| 205 |
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
| 206 |
void *irq_opaque, int devfn_min, int nirq) |
| 207 |
{
|
| 208 |
PCIBus *bus; |
| 209 |
|
| 210 |
bus = pci_bus_new(parent, name, devfn_min); |
| 211 |
pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
| 212 |
return bus;
|
| 213 |
} |
| 214 |
|
| 215 |
static void pci_register_secondary_bus(PCIBus *parent, |
| 216 |
PCIBus *bus, |
| 217 |
PCIDevice *dev, |
| 218 |
pci_map_irq_fn map_irq, |
| 219 |
const char *name) |
| 220 |
{
|
| 221 |
qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name); |
| 222 |
bus->map_irq = map_irq; |
| 223 |
bus->parent_dev = dev; |
| 224 |
|
| 225 |
QLIST_INIT(&bus->child); |
| 226 |
QLIST_INSERT_HEAD(&parent->child, bus, sibling); |
| 227 |
} |
| 228 |
|
| 229 |
static void pci_unregister_secondary_bus(PCIBus *bus) |
| 230 |
{
|
| 231 |
assert(QLIST_EMPTY(&bus->child)); |
| 232 |
QLIST_REMOVE(bus, sibling); |
| 233 |
} |
| 234 |
|
| 235 |
int pci_bus_num(PCIBus *s)
|
| 236 |
{
|
| 237 |
if (!s->parent_dev)
|
| 238 |
return 0; /* pci host bridge */ |
| 239 |
return s->parent_dev->config[PCI_SECONDARY_BUS];
|
| 240 |
} |
| 241 |
|
| 242 |
static uint8_t pci_sub_bus(PCIBus *s)
|
| 243 |
{
|
| 244 |
if (!s->parent_dev)
|
| 245 |
return 255; /* pci host bridge */ |
| 246 |
return s->parent_dev->config[PCI_SUBORDINATE_BUS];
|
| 247 |
} |
| 248 |
|
| 249 |
static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
| 250 |
{
|
| 251 |
PCIDevice *s = container_of(pv, PCIDevice, config); |
| 252 |
uint8_t *config; |
| 253 |
int i;
|
| 254 |
|
| 255 |
assert(size == pci_config_size(s)); |
| 256 |
config = qemu_malloc(size); |
| 257 |
|
| 258 |
qemu_get_buffer(f, config, size); |
| 259 |
for (i = 0; i < size; ++i) { |
| 260 |
if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
|
| 261 |
qemu_free(config); |
| 262 |
return -EINVAL;
|
| 263 |
} |
| 264 |
} |
| 265 |
memcpy(s->config, config, size); |
| 266 |
|
| 267 |
pci_update_mappings(s); |
| 268 |
|
| 269 |
qemu_free(config); |
| 270 |
return 0; |
| 271 |
} |
| 272 |
|
| 273 |
/* just put buffer */
|
| 274 |
static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
| 275 |
{
|
| 276 |
const uint8_t **v = pv;
|
| 277 |
assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
| 278 |
qemu_put_buffer(f, *v, size); |
| 279 |
} |
| 280 |
|
| 281 |
static VMStateInfo vmstate_info_pci_config = {
|
| 282 |
.name = "pci config",
|
| 283 |
.get = get_pci_config_device, |
| 284 |
.put = put_pci_config_device, |
| 285 |
}; |
| 286 |
|
| 287 |
const VMStateDescription vmstate_pci_device = {
|
| 288 |
.name = "PCIDevice",
|
| 289 |
.version_id = 2,
|
| 290 |
.minimum_version_id = 1,
|
| 291 |
.minimum_version_id_old = 1,
|
| 292 |
.fields = (VMStateField []) {
|
| 293 |
VMSTATE_INT32_LE(version_id, PCIDevice), |
| 294 |
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
| 295 |
vmstate_info_pci_config, |
| 296 |
PCI_CONFIG_SPACE_SIZE), |
| 297 |
VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
|
| 298 |
VMSTATE_END_OF_LIST() |
| 299 |
} |
| 300 |
}; |
| 301 |
|
| 302 |
const VMStateDescription vmstate_pcie_device = {
|
| 303 |
.name = "PCIDevice",
|
| 304 |
.version_id = 2,
|
| 305 |
.minimum_version_id = 1,
|
| 306 |
.minimum_version_id_old = 1,
|
| 307 |
.fields = (VMStateField []) {
|
| 308 |
VMSTATE_INT32_LE(version_id, PCIDevice), |
| 309 |
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
| 310 |
vmstate_info_pci_config, |
| 311 |
PCIE_CONFIG_SPACE_SIZE), |
| 312 |
VMSTATE_INT32_ARRAY_V(irq_state, PCIDevice, PCI_NUM_PINS, 2),
|
| 313 |
VMSTATE_END_OF_LIST() |
| 314 |
} |
| 315 |
}; |
| 316 |
|
| 317 |
static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
| 318 |
{
|
| 319 |
return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
|
| 320 |
} |
| 321 |
|
| 322 |
void pci_device_save(PCIDevice *s, QEMUFile *f)
|
| 323 |
{
|
| 324 |
vmstate_save_state(f, pci_get_vmstate(s), s); |
| 325 |
} |
| 326 |
|
| 327 |
int pci_device_load(PCIDevice *s, QEMUFile *f)
|
| 328 |
{
|
| 329 |
return vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
|
| 330 |
} |
| 331 |
|
| 332 |
static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
| 333 |
{
|
| 334 |
uint16_t *id; |
| 335 |
|
| 336 |
id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
|
| 337 |
id[0] = cpu_to_le16(pci_default_sub_vendor_id);
|
| 338 |
id[1] = cpu_to_le16(pci_default_sub_device_id);
|
| 339 |
return 0; |
| 340 |
} |
| 341 |
|
| 342 |
/*
|
| 343 |
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
|
| 344 |
*/
|
| 345 |
static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
| 346 |
{
|
| 347 |
const char *p; |
| 348 |
char *e;
|
| 349 |
unsigned long val; |
| 350 |
unsigned long dom = 0, bus = 0; |
| 351 |
unsigned slot = 0; |
| 352 |
|
| 353 |
p = addr; |
| 354 |
val = strtoul(p, &e, 16);
|
| 355 |
if (e == p)
|
| 356 |
return -1; |
| 357 |
if (*e == ':') { |
| 358 |
bus = val; |
| 359 |
p = e + 1;
|
| 360 |
val = strtoul(p, &e, 16);
|
| 361 |
if (e == p)
|
| 362 |
return -1; |
| 363 |
if (*e == ':') { |
| 364 |
dom = bus; |
| 365 |
bus = val; |
| 366 |
p = e + 1;
|
| 367 |
val = strtoul(p, &e, 16);
|
| 368 |
if (e == p)
|
| 369 |
return -1; |
| 370 |
} |
| 371 |
} |
| 372 |
|
| 373 |
if (dom > 0xffff || bus > 0xff || val > 0x1f) |
| 374 |
return -1; |
| 375 |
|
| 376 |
slot = val; |
| 377 |
|
| 378 |
if (*e)
|
| 379 |
return -1; |
| 380 |
|
| 381 |
/* Note: QEMU doesn't implement domains other than 0 */
|
| 382 |
if (!pci_find_bus(pci_find_host_bus(dom), bus))
|
| 383 |
return -1; |
| 384 |
|
| 385 |
*domp = dom; |
| 386 |
*busp = bus; |
| 387 |
*slotp = slot; |
| 388 |
return 0; |
| 389 |
} |
| 390 |
|
| 391 |
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
| 392 |
unsigned *slotp)
|
| 393 |
{
|
| 394 |
/* strip legacy tag */
|
| 395 |
if (!strncmp(addr, "pci_addr=", 9)) { |
| 396 |
addr += 9;
|
| 397 |
} |
| 398 |
if (pci_parse_devaddr(addr, domp, busp, slotp)) {
|
| 399 |
monitor_printf(mon, "Invalid pci address\n");
|
| 400 |
return -1; |
| 401 |
} |
| 402 |
return 0; |
| 403 |
} |
| 404 |
|
| 405 |
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
| 406 |
{
|
| 407 |
int dom, bus;
|
| 408 |
unsigned slot;
|
| 409 |
|
| 410 |
if (!devaddr) {
|
| 411 |
*devfnp = -1;
|
| 412 |
return pci_find_bus(pci_find_host_bus(0), 0); |
| 413 |
} |
| 414 |
|
| 415 |
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) { |
| 416 |
return NULL; |
| 417 |
} |
| 418 |
|
| 419 |
*devfnp = slot << 3;
|
| 420 |
return pci_find_bus(pci_find_host_bus(0), bus); |
| 421 |
} |
| 422 |
|
| 423 |
static void pci_init_cmask(PCIDevice *dev) |
| 424 |
{
|
| 425 |
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
|
| 426 |
pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
|
| 427 |
dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
| 428 |
dev->cmask[PCI_REVISION_ID] = 0xff;
|
| 429 |
dev->cmask[PCI_CLASS_PROG] = 0xff;
|
| 430 |
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
|
| 431 |
dev->cmask[PCI_HEADER_TYPE] = 0xff;
|
| 432 |
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
|
| 433 |
} |
| 434 |
|
| 435 |
static void pci_init_wmask(PCIDevice *dev) |
| 436 |
{
|
| 437 |
int i;
|
| 438 |
int config_size = pci_config_size(dev);
|
| 439 |
|
| 440 |
dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
|
| 441 |
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
|
| 442 |
pci_set_word(dev->wmask + PCI_COMMAND, |
| 443 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 444 |
for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
|
| 445 |
dev->wmask[i] = 0xff;
|
| 446 |
} |
| 447 |
|
| 448 |
static void pci_init_wmask_bridge(PCIDevice *d) |
| 449 |
{
|
| 450 |
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
|
| 451 |
PCI_SEC_LETENCY_TIMER */
|
| 452 |
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); |
| 453 |
|
| 454 |
/* base and limit */
|
| 455 |
d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
|
| 456 |
d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
|
| 457 |
pci_set_word(d->wmask + PCI_MEMORY_BASE, |
| 458 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
| 459 |
pci_set_word(d->wmask + PCI_MEMORY_LIMIT, |
| 460 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
| 461 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, |
| 462 |
PCI_PREF_RANGE_MASK & 0xffff);
|
| 463 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, |
| 464 |
PCI_PREF_RANGE_MASK & 0xffff);
|
| 465 |
|
| 466 |
/* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
|
| 467 |
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); |
| 468 |
|
| 469 |
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
|
| 470 |
} |
| 471 |
|
| 472 |
static void pci_config_alloc(PCIDevice *pci_dev) |
| 473 |
{
|
| 474 |
int config_size = pci_config_size(pci_dev);
|
| 475 |
|
| 476 |
pci_dev->config = qemu_mallocz(config_size); |
| 477 |
pci_dev->cmask = qemu_mallocz(config_size); |
| 478 |
pci_dev->wmask = qemu_mallocz(config_size); |
| 479 |
pci_dev->used = qemu_mallocz(config_size); |
| 480 |
} |
| 481 |
|
| 482 |
static void pci_config_free(PCIDevice *pci_dev) |
| 483 |
{
|
| 484 |
qemu_free(pci_dev->config); |
| 485 |
qemu_free(pci_dev->cmask); |
| 486 |
qemu_free(pci_dev->wmask); |
| 487 |
qemu_free(pci_dev->used); |
| 488 |
} |
| 489 |
|
| 490 |
/* -1 for devfn means auto assign */
|
| 491 |
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
|
| 492 |
const char *name, int devfn, |
| 493 |
PCIConfigReadFunc *config_read, |
| 494 |
PCIConfigWriteFunc *config_write, |
| 495 |
uint8_t header_type) |
| 496 |
{
|
| 497 |
if (devfn < 0) { |
| 498 |
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
| 499 |
if (!bus->devices[devfn])
|
| 500 |
goto found;
|
| 501 |
} |
| 502 |
hw_error("PCI: no devfn available for %s, all in use\n", name);
|
| 503 |
found: ;
|
| 504 |
} else if (bus->devices[devfn]) { |
| 505 |
hw_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
|
| 506 |
name, bus->devices[devfn]->name); |
| 507 |
} |
| 508 |
pci_dev->bus = bus; |
| 509 |
pci_dev->devfn = devfn; |
| 510 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
| 511 |
memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
| 512 |
pci_config_alloc(pci_dev); |
| 513 |
|
| 514 |
header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
| 515 |
if (header_type == PCI_HEADER_TYPE_NORMAL) {
|
| 516 |
pci_set_default_subsystem_id(pci_dev); |
| 517 |
} |
| 518 |
pci_init_cmask(pci_dev); |
| 519 |
pci_init_wmask(pci_dev); |
| 520 |
if (header_type == PCI_HEADER_TYPE_BRIDGE) {
|
| 521 |
pci_init_wmask_bridge(pci_dev); |
| 522 |
} |
| 523 |
|
| 524 |
if (!config_read)
|
| 525 |
config_read = pci_default_read_config; |
| 526 |
if (!config_write)
|
| 527 |
config_write = pci_default_write_config; |
| 528 |
pci_dev->config_read = config_read; |
| 529 |
pci_dev->config_write = config_write; |
| 530 |
bus->devices[devfn] = pci_dev; |
| 531 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
| 532 |
pci_dev->version_id = 2; /* Current pci device vmstate version */ |
| 533 |
return pci_dev;
|
| 534 |
} |
| 535 |
|
| 536 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
| 537 |
int instance_size, int devfn, |
| 538 |
PCIConfigReadFunc *config_read, |
| 539 |
PCIConfigWriteFunc *config_write) |
| 540 |
{
|
| 541 |
PCIDevice *pci_dev; |
| 542 |
|
| 543 |
pci_dev = qemu_mallocz(instance_size); |
| 544 |
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
| 545 |
config_read, config_write, |
| 546 |
PCI_HEADER_TYPE_NORMAL); |
| 547 |
return pci_dev;
|
| 548 |
} |
| 549 |
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
|
| 550 |
{
|
| 551 |
return addr + pci_mem_base;
|
| 552 |
} |
| 553 |
|
| 554 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
| 555 |
{
|
| 556 |
PCIIORegion *r; |
| 557 |
int i;
|
| 558 |
|
| 559 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
| 560 |
r = &pci_dev->io_regions[i]; |
| 561 |
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
|
| 562 |
continue;
|
| 563 |
if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
|
| 564 |
isa_unassign_ioport(r->addr, r->filtered_size); |
| 565 |
} else {
|
| 566 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
| 567 |
r->filtered_size, |
| 568 |
IO_MEM_UNASSIGNED); |
| 569 |
} |
| 570 |
} |
| 571 |
} |
| 572 |
|
| 573 |
static int pci_unregister_device(DeviceState *dev) |
| 574 |
{
|
| 575 |
PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev); |
| 576 |
PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info); |
| 577 |
int ret = 0; |
| 578 |
|
| 579 |
if (info->exit)
|
| 580 |
ret = info->exit(pci_dev); |
| 581 |
if (ret)
|
| 582 |
return ret;
|
| 583 |
|
| 584 |
pci_unregister_io_regions(pci_dev); |
| 585 |
|
| 586 |
qemu_free_irqs(pci_dev->irq); |
| 587 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
| 588 |
pci_config_free(pci_dev); |
| 589 |
return 0; |
| 590 |
} |
| 591 |
|
| 592 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
| 593 |
pcibus_t size, int type,
|
| 594 |
PCIMapIORegionFunc *map_func) |
| 595 |
{
|
| 596 |
PCIIORegion *r; |
| 597 |
uint32_t addr; |
| 598 |
pcibus_t wmask; |
| 599 |
|
| 600 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
| 601 |
return;
|
| 602 |
|
| 603 |
if (size & (size-1)) { |
| 604 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
| 605 |
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
| 606 |
exit(1);
|
| 607 |
} |
| 608 |
|
| 609 |
r = &pci_dev->io_regions[region_num]; |
| 610 |
r->addr = PCI_BAR_UNMAPPED; |
| 611 |
r->size = size; |
| 612 |
r->filtered_size = size; |
| 613 |
r->type = type; |
| 614 |
r->map_func = map_func; |
| 615 |
|
| 616 |
wmask = ~(size - 1);
|
| 617 |
addr = pci_bar(pci_dev, region_num); |
| 618 |
if (region_num == PCI_ROM_SLOT) {
|
| 619 |
/* ROM enable bit is writeable */
|
| 620 |
wmask |= PCI_ROM_ADDRESS_ENABLE; |
| 621 |
} |
| 622 |
pci_set_long(pci_dev->config + addr, type); |
| 623 |
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
|
| 624 |
r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
| 625 |
pci_set_quad(pci_dev->wmask + addr, wmask); |
| 626 |
pci_set_quad(pci_dev->cmask + addr, ~0ULL);
|
| 627 |
} else {
|
| 628 |
pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
|
| 629 |
pci_set_long(pci_dev->cmask + addr, 0xffffffff);
|
| 630 |
} |
| 631 |
} |
| 632 |
|
| 633 |
static uint32_t pci_config_get_io_base(PCIDevice *d,
|
| 634 |
uint32_t base, uint32_t base_upper16) |
| 635 |
{
|
| 636 |
uint32_t val; |
| 637 |
|
| 638 |
val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
|
| 639 |
if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
|
| 640 |
val |= (uint32_t)pci_get_word(d->config + PCI_IO_BASE_UPPER16) << 16;
|
| 641 |
} |
| 642 |
return val;
|
| 643 |
} |
| 644 |
|
| 645 |
static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
|
| 646 |
{
|
| 647 |
return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
|
| 648 |
<< 16;
|
| 649 |
} |
| 650 |
|
| 651 |
static uint64_t pci_config_get_pref_base(PCIDevice *d,
|
| 652 |
uint32_t base, uint32_t upper) |
| 653 |
{
|
| 654 |
uint64_t val; |
| 655 |
val = ((uint64_t)pci_get_word(d->config + base) & |
| 656 |
PCI_PREF_RANGE_MASK) << 16;
|
| 657 |
val |= (uint64_t)pci_get_long(d->config + upper) << 32;
|
| 658 |
return val;
|
| 659 |
} |
| 660 |
|
| 661 |
static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
|
| 662 |
{
|
| 663 |
pcibus_t base; |
| 664 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
| 665 |
base = pci_config_get_io_base(bridge, |
| 666 |
PCI_IO_BASE, PCI_IO_BASE_UPPER16); |
| 667 |
} else {
|
| 668 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
| 669 |
base = pci_config_get_pref_base( |
| 670 |
bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32); |
| 671 |
} else {
|
| 672 |
base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE); |
| 673 |
} |
| 674 |
} |
| 675 |
|
| 676 |
return base;
|
| 677 |
} |
| 678 |
|
| 679 |
static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
|
| 680 |
{
|
| 681 |
pcibus_t limit; |
| 682 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
| 683 |
limit = pci_config_get_io_base(bridge, |
| 684 |
PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16); |
| 685 |
limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */ |
| 686 |
} else {
|
| 687 |
if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
|
| 688 |
limit = pci_config_get_pref_base( |
| 689 |
bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32); |
| 690 |
} else {
|
| 691 |
limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT); |
| 692 |
} |
| 693 |
limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */ |
| 694 |
} |
| 695 |
return limit;
|
| 696 |
} |
| 697 |
|
| 698 |
static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size, |
| 699 |
uint8_t type) |
| 700 |
{
|
| 701 |
pcibus_t base = *addr; |
| 702 |
pcibus_t limit = *addr + *size - 1;
|
| 703 |
PCIDevice *br; |
| 704 |
|
| 705 |
for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
|
| 706 |
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
| 707 |
|
| 708 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
| 709 |
if (!(cmd & PCI_COMMAND_IO)) {
|
| 710 |
goto no_map;
|
| 711 |
} |
| 712 |
} else {
|
| 713 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
| 714 |
goto no_map;
|
| 715 |
} |
| 716 |
} |
| 717 |
|
| 718 |
base = MAX(base, pci_bridge_get_base(br, type)); |
| 719 |
limit = MIN(limit, pci_bridge_get_limit(br, type)); |
| 720 |
} |
| 721 |
|
| 722 |
if (base > limit) {
|
| 723 |
no_map:
|
| 724 |
*addr = PCI_BAR_UNMAPPED; |
| 725 |
*size = 0;
|
| 726 |
} else {
|
| 727 |
*addr = base; |
| 728 |
*size = limit - base + 1;
|
| 729 |
} |
| 730 |
} |
| 731 |
|
| 732 |
static void pci_update_mappings(PCIDevice *d) |
| 733 |
{
|
| 734 |
PCIIORegion *r; |
| 735 |
int cmd, i;
|
| 736 |
pcibus_t last_addr, new_addr; |
| 737 |
pcibus_t filtered_size; |
| 738 |
|
| 739 |
cmd = pci_get_word(d->config + PCI_COMMAND); |
| 740 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
| 741 |
r = &d->io_regions[i]; |
| 742 |
|
| 743 |
/* this region isn't registered */
|
| 744 |
if (r->size == 0) |
| 745 |
continue;
|
| 746 |
|
| 747 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
| 748 |
if (cmd & PCI_COMMAND_IO) {
|
| 749 |
new_addr = pci_get_long(d->config + pci_bar(d, i)); |
| 750 |
new_addr = new_addr & ~(r->size - 1);
|
| 751 |
last_addr = new_addr + r->size - 1;
|
| 752 |
/* NOTE: we have only 64K ioports on PC */
|
| 753 |
if (last_addr <= new_addr || new_addr == 0 || |
| 754 |
last_addr >= 0x10000) {
|
| 755 |
new_addr = PCI_BAR_UNMAPPED; |
| 756 |
} |
| 757 |
} else {
|
| 758 |
new_addr = PCI_BAR_UNMAPPED; |
| 759 |
} |
| 760 |
} else {
|
| 761 |
if (cmd & PCI_COMMAND_MEMORY) {
|
| 762 |
if (r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
| 763 |
new_addr = pci_get_quad(d->config + pci_bar(d, i)); |
| 764 |
} else {
|
| 765 |
new_addr = pci_get_long(d->config + pci_bar(d, i)); |
| 766 |
} |
| 767 |
/* the ROM slot has a specific enable bit */
|
| 768 |
if (i == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE))
|
| 769 |
goto no_mem_map;
|
| 770 |
new_addr = new_addr & ~(r->size - 1);
|
| 771 |
last_addr = new_addr + r->size - 1;
|
| 772 |
/* NOTE: we do not support wrapping */
|
| 773 |
/* XXX: as we cannot support really dynamic
|
| 774 |
mappings, we handle specific values as invalid
|
| 775 |
mappings. */
|
| 776 |
if (last_addr <= new_addr || new_addr == 0 || |
| 777 |
last_addr == PCI_BAR_UNMAPPED || |
| 778 |
|
| 779 |
/* Now pcibus_t is 64bit.
|
| 780 |
* Check if 32 bit BAR wrap around explicitly.
|
| 781 |
* Without this, PC ide doesn't work well.
|
| 782 |
* TODO: remove this work around.
|
| 783 |
*/
|
| 784 |
(!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) && |
| 785 |
last_addr >= UINT32_MAX) || |
| 786 |
|
| 787 |
/*
|
| 788 |
* OS is allowed to set BAR beyond its addressable
|
| 789 |
* bits. For example, 32 bit OS can set 64bit bar
|
| 790 |
* to >4G. Check it.
|
| 791 |
*/
|
| 792 |
last_addr >= TARGET_PHYS_ADDR_MAX) {
|
| 793 |
new_addr = PCI_BAR_UNMAPPED; |
| 794 |
} |
| 795 |
} else {
|
| 796 |
no_mem_map:
|
| 797 |
new_addr = PCI_BAR_UNMAPPED; |
| 798 |
} |
| 799 |
} |
| 800 |
|
| 801 |
/* bridge filtering */
|
| 802 |
filtered_size = r->size; |
| 803 |
if (new_addr != PCI_BAR_UNMAPPED) {
|
| 804 |
pci_bridge_filter(d, &new_addr, &filtered_size, r->type); |
| 805 |
} |
| 806 |
|
| 807 |
/* This bar isn't changed */
|
| 808 |
if (new_addr == r->addr && filtered_size == r->filtered_size)
|
| 809 |
continue;
|
| 810 |
|
| 811 |
/* now do the real mapping */
|
| 812 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
| 813 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
| 814 |
int class;
|
| 815 |
/* NOTE: specific hack for IDE in PC case:
|
| 816 |
only one byte must be mapped. */
|
| 817 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
| 818 |
if (class == 0x0101 && r->size == 4) { |
| 819 |
isa_unassign_ioport(r->addr + 2, 1); |
| 820 |
} else {
|
| 821 |
isa_unassign_ioport(r->addr, r->filtered_size); |
| 822 |
} |
| 823 |
} else {
|
| 824 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
| 825 |
r->filtered_size, |
| 826 |
IO_MEM_UNASSIGNED); |
| 827 |
qemu_unregister_coalesced_mmio(r->addr, r->filtered_size); |
| 828 |
} |
| 829 |
} |
| 830 |
r->addr = new_addr; |
| 831 |
r->filtered_size = filtered_size; |
| 832 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
| 833 |
/*
|
| 834 |
* TODO: currently almost all the map funcions assumes
|
| 835 |
* filtered_size == size and addr & ~(size - 1) == addr.
|
| 836 |
* However with bridge filtering, they aren't always true.
|
| 837 |
* Teach them such cases, such that filtered_size < size and
|
| 838 |
* addr & (size - 1) != 0.
|
| 839 |
*/
|
| 840 |
r->map_func(d, i, r->addr, r->filtered_size, r->type); |
| 841 |
} |
| 842 |
} |
| 843 |
} |
| 844 |
|
| 845 |
uint32_t pci_default_read_config(PCIDevice *d, |
| 846 |
uint32_t address, int len)
|
| 847 |
{
|
| 848 |
uint32_t val = 0;
|
| 849 |
assert(len == 1 || len == 2 || len == 4); |
| 850 |
len = MIN(len, pci_config_size(d) - address); |
| 851 |
memcpy(&val, d->config + address, len); |
| 852 |
return le32_to_cpu(val);
|
| 853 |
} |
| 854 |
|
| 855 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
| 856 |
{
|
| 857 |
int i;
|
| 858 |
uint32_t config_size = pci_config_size(d); |
| 859 |
|
| 860 |
for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) { |
| 861 |
uint8_t wmask = d->wmask[addr + i]; |
| 862 |
d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
| 863 |
} |
| 864 |
if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
| 865 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
|
| 866 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
|
| 867 |
range_covers_byte(addr, l, PCI_COMMAND)) |
| 868 |
pci_update_mappings(d); |
| 869 |
} |
| 870 |
|
| 871 |
/***********************************************************/
|
| 872 |
/* generic PCI irq support */
|
| 873 |
|
| 874 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
| 875 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
| 876 |
{
|
| 877 |
PCIDevice *pci_dev = opaque; |
| 878 |
PCIBus *bus; |
| 879 |
int change;
|
| 880 |
|
| 881 |
change = level - pci_dev->irq_state[irq_num]; |
| 882 |
if (!change)
|
| 883 |
return;
|
| 884 |
|
| 885 |
pci_dev->irq_state[irq_num] = level; |
| 886 |
for (;;) {
|
| 887 |
bus = pci_dev->bus; |
| 888 |
irq_num = bus->map_irq(pci_dev, irq_num); |
| 889 |
if (bus->set_irq)
|
| 890 |
break;
|
| 891 |
pci_dev = bus->parent_dev; |
| 892 |
} |
| 893 |
bus->irq_count[irq_num] += change; |
| 894 |
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
| 895 |
} |
| 896 |
|
| 897 |
/***********************************************************/
|
| 898 |
/* monitor info on PCI */
|
| 899 |
|
| 900 |
typedef struct { |
| 901 |
uint16_t class; |
| 902 |
const char *desc; |
| 903 |
} pci_class_desc; |
| 904 |
|
| 905 |
static const pci_class_desc pci_class_descriptions[] = |
| 906 |
{
|
| 907 |
{ 0x0100, "SCSI controller"},
|
| 908 |
{ 0x0101, "IDE controller"},
|
| 909 |
{ 0x0102, "Floppy controller"},
|
| 910 |
{ 0x0103, "IPI controller"},
|
| 911 |
{ 0x0104, "RAID controller"},
|
| 912 |
{ 0x0106, "SATA controller"},
|
| 913 |
{ 0x0107, "SAS controller"},
|
| 914 |
{ 0x0180, "Storage controller"},
|
| 915 |
{ 0x0200, "Ethernet controller"},
|
| 916 |
{ 0x0201, "Token Ring controller"},
|
| 917 |
{ 0x0202, "FDDI controller"},
|
| 918 |
{ 0x0203, "ATM controller"},
|
| 919 |
{ 0x0280, "Network controller"},
|
| 920 |
{ 0x0300, "VGA controller"},
|
| 921 |
{ 0x0301, "XGA controller"},
|
| 922 |
{ 0x0302, "3D controller"},
|
| 923 |
{ 0x0380, "Display controller"},
|
| 924 |
{ 0x0400, "Video controller"},
|
| 925 |
{ 0x0401, "Audio controller"},
|
| 926 |
{ 0x0402, "Phone"},
|
| 927 |
{ 0x0480, "Multimedia controller"},
|
| 928 |
{ 0x0500, "RAM controller"},
|
| 929 |
{ 0x0501, "Flash controller"},
|
| 930 |
{ 0x0580, "Memory controller"},
|
| 931 |
{ 0x0600, "Host bridge"},
|
| 932 |
{ 0x0601, "ISA bridge"},
|
| 933 |
{ 0x0602, "EISA bridge"},
|
| 934 |
{ 0x0603, "MC bridge"},
|
| 935 |
{ 0x0604, "PCI bridge"},
|
| 936 |
{ 0x0605, "PCMCIA bridge"},
|
| 937 |
{ 0x0606, "NUBUS bridge"},
|
| 938 |
{ 0x0607, "CARDBUS bridge"},
|
| 939 |
{ 0x0608, "RACEWAY bridge"},
|
| 940 |
{ 0x0680, "Bridge"},
|
| 941 |
{ 0x0c03, "USB controller"},
|
| 942 |
{ 0, NULL}
|
| 943 |
}; |
| 944 |
|
| 945 |
static void pci_info_device(PCIBus *bus, PCIDevice *d) |
| 946 |
{
|
| 947 |
Monitor *mon = cur_mon; |
| 948 |
int i, class;
|
| 949 |
PCIIORegion *r; |
| 950 |
const pci_class_desc *desc;
|
| 951 |
|
| 952 |
monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
| 953 |
pci_bus_num(d->bus), |
| 954 |
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn)); |
| 955 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
| 956 |
monitor_printf(mon, " ");
|
| 957 |
desc = pci_class_descriptions; |
| 958 |
while (desc->desc && class != desc->class)
|
| 959 |
desc++; |
| 960 |
if (desc->desc) {
|
| 961 |
monitor_printf(mon, "%s", desc->desc);
|
| 962 |
} else {
|
| 963 |
monitor_printf(mon, "Class %04x", class);
|
| 964 |
} |
| 965 |
monitor_printf(mon, ": PCI device %04x:%04x\n",
|
| 966 |
pci_get_word(d->config + PCI_VENDOR_ID), |
| 967 |
pci_get_word(d->config + PCI_DEVICE_ID)); |
| 968 |
|
| 969 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
| 970 |
monitor_printf(mon, " IRQ %d.\n",
|
| 971 |
d->config[PCI_INTERRUPT_LINE]); |
| 972 |
} |
| 973 |
if (class == 0x0604) { |
| 974 |
uint64_t base; |
| 975 |
uint64_t limit; |
| 976 |
|
| 977 |
monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
| 978 |
monitor_printf(mon, " secondary bus %d.\n",
|
| 979 |
d->config[PCI_SECONDARY_BUS]); |
| 980 |
monitor_printf(mon, " subordinate bus %d.\n",
|
| 981 |
d->config[PCI_SUBORDINATE_BUS]); |
| 982 |
|
| 983 |
base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO); |
| 984 |
limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO); |
| 985 |
monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n", |
| 986 |
base, limit); |
| 987 |
|
| 988 |
base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY); |
| 989 |
limit= pci_config_get_memory_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY); |
| 990 |
monitor_printf(mon, |
| 991 |
" memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n", |
| 992 |
base, limit); |
| 993 |
|
| 994 |
base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY | |
| 995 |
PCI_BASE_ADDRESS_MEM_PREFETCH); |
| 996 |
limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY | |
| 997 |
PCI_BASE_ADDRESS_MEM_PREFETCH); |
| 998 |
monitor_printf(mon, " prefetchable memory range "
|
| 999 |
"[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit); |
| 1000 |
} |
| 1001 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
| 1002 |
r = &d->io_regions[i]; |
| 1003 |
if (r->size != 0) { |
| 1004 |
monitor_printf(mon, " BAR%d: ", i);
|
| 1005 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
| 1006 |
monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
|
| 1007 |
" [0x%04"FMT_PCIBUS"].\n", |
| 1008 |
r->addr, r->addr + r->size - 1);
|
| 1009 |
} else {
|
| 1010 |
const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ? |
| 1011 |
"64 bit" : "32 bit"; |
| 1012 |
const char *prefetch = |
| 1013 |
r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ? |
| 1014 |
" prefetchable" : ""; |
| 1015 |
|
| 1016 |
monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
|
| 1017 |
" [0x%08"FMT_PCIBUS"].\n", |
| 1018 |
type, prefetch, |
| 1019 |
r->addr, r->addr + r->size - 1);
|
| 1020 |
} |
| 1021 |
} |
| 1022 |
} |
| 1023 |
monitor_printf(mon, " id \"%s\"\n", d->qdev.id ? d->qdev.id : ""); |
| 1024 |
if (class == 0x0604 && d->config[0x19] != 0) { |
| 1025 |
pci_for_each_device(bus, d->config[0x19], pci_info_device);
|
| 1026 |
} |
| 1027 |
} |
| 1028 |
|
| 1029 |
static void pci_for_each_device_under_bus(PCIBus *bus, |
| 1030 |
void (*fn)(PCIBus *b, PCIDevice *d))
|
| 1031 |
{
|
| 1032 |
PCIDevice *d; |
| 1033 |
int devfn;
|
| 1034 |
|
| 1035 |
for(devfn = 0; devfn < 256; devfn++) { |
| 1036 |
d = bus->devices[devfn]; |
| 1037 |
if (d)
|
| 1038 |
fn(bus, d); |
| 1039 |
} |
| 1040 |
} |
| 1041 |
|
| 1042 |
void pci_for_each_device(PCIBus *bus, int bus_num, |
| 1043 |
void (*fn)(PCIBus *b, PCIDevice *d))
|
| 1044 |
{
|
| 1045 |
bus = pci_find_bus(bus, bus_num); |
| 1046 |
|
| 1047 |
if (bus) {
|
| 1048 |
pci_for_each_device_under_bus(bus, fn); |
| 1049 |
} |
| 1050 |
} |
| 1051 |
|
| 1052 |
void pci_info(Monitor *mon)
|
| 1053 |
{
|
| 1054 |
struct PCIHostBus *host;
|
| 1055 |
QLIST_FOREACH(host, &host_buses, next) {
|
| 1056 |
pci_for_each_device(host->bus, 0, pci_info_device);
|
| 1057 |
} |
| 1058 |
} |
| 1059 |
|
| 1060 |
static const char * const pci_nic_models[] = { |
| 1061 |
"ne2k_pci",
|
| 1062 |
"i82551",
|
| 1063 |
"i82557b",
|
| 1064 |
"i82559er",
|
| 1065 |
"rtl8139",
|
| 1066 |
"e1000",
|
| 1067 |
"pcnet",
|
| 1068 |
"virtio",
|
| 1069 |
NULL
|
| 1070 |
}; |
| 1071 |
|
| 1072 |
static const char * const pci_nic_names[] = { |
| 1073 |
"ne2k_pci",
|
| 1074 |
"i82551",
|
| 1075 |
"i82557b",
|
| 1076 |
"i82559er",
|
| 1077 |
"rtl8139",
|
| 1078 |
"e1000",
|
| 1079 |
"pcnet",
|
| 1080 |
"virtio-net-pci",
|
| 1081 |
NULL
|
| 1082 |
}; |
| 1083 |
|
| 1084 |
/* Initialize a PCI NIC. */
|
| 1085 |
/* FIXME callers should check for failure, but don't */
|
| 1086 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
| 1087 |
const char *default_devaddr) |
| 1088 |
{
|
| 1089 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
| 1090 |
PCIBus *bus; |
| 1091 |
int devfn;
|
| 1092 |
PCIDevice *pci_dev; |
| 1093 |
DeviceState *dev; |
| 1094 |
int i;
|
| 1095 |
|
| 1096 |
i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
| 1097 |
if (i < 0) |
| 1098 |
return NULL; |
| 1099 |
|
| 1100 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
| 1101 |
if (!bus) {
|
| 1102 |
qemu_error("Invalid PCI device address %s for device %s\n",
|
| 1103 |
devaddr, pci_nic_names[i]); |
| 1104 |
return NULL; |
| 1105 |
} |
| 1106 |
|
| 1107 |
pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
| 1108 |
dev = &pci_dev->qdev; |
| 1109 |
if (nd->name)
|
| 1110 |
dev->id = qemu_strdup(nd->name); |
| 1111 |
qdev_set_nic_properties(dev, nd); |
| 1112 |
if (qdev_init(dev) < 0) |
| 1113 |
return NULL; |
| 1114 |
return pci_dev;
|
| 1115 |
} |
| 1116 |
|
| 1117 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
| 1118 |
const char *default_devaddr) |
| 1119 |
{
|
| 1120 |
PCIDevice *res; |
| 1121 |
|
| 1122 |
if (qemu_show_nic_models(nd->model, pci_nic_models))
|
| 1123 |
exit(0);
|
| 1124 |
|
| 1125 |
res = pci_nic_init(nd, default_model, default_devaddr); |
| 1126 |
if (!res)
|
| 1127 |
exit(1);
|
| 1128 |
return res;
|
| 1129 |
} |
| 1130 |
|
| 1131 |
typedef struct { |
| 1132 |
PCIDevice dev; |
| 1133 |
PCIBus bus; |
| 1134 |
uint32_t vid; |
| 1135 |
uint32_t did; |
| 1136 |
} PCIBridge; |
| 1137 |
|
| 1138 |
|
| 1139 |
static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d) |
| 1140 |
{
|
| 1141 |
pci_update_mappings(d); |
| 1142 |
} |
| 1143 |
|
| 1144 |
static void pci_bridge_update_mappings(PCIBus *b) |
| 1145 |
{
|
| 1146 |
PCIBus *child; |
| 1147 |
|
| 1148 |
pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn); |
| 1149 |
|
| 1150 |
QLIST_FOREACH(child, &b->child, sibling) {
|
| 1151 |
pci_bridge_update_mappings(child); |
| 1152 |
} |
| 1153 |
} |
| 1154 |
|
| 1155 |
static void pci_bridge_write_config(PCIDevice *d, |
| 1156 |
uint32_t address, uint32_t val, int len)
|
| 1157 |
{
|
| 1158 |
pci_default_write_config(d, address, val, len); |
| 1159 |
|
| 1160 |
if (/* io base/limit */ |
| 1161 |
ranges_overlap(address, len, PCI_IO_BASE, 2) ||
|
| 1162 |
|
| 1163 |
/* memory base/limit, prefetchable base/limit and
|
| 1164 |
io base/limit upper 16 */
|
| 1165 |
ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
|
| 1166 |
pci_bridge_update_mappings(d->bus); |
| 1167 |
} |
| 1168 |
} |
| 1169 |
|
| 1170 |
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
|
| 1171 |
{
|
| 1172 |
PCIBus *sec; |
| 1173 |
|
| 1174 |
if (!bus)
|
| 1175 |
return NULL; |
| 1176 |
|
| 1177 |
if (pci_bus_num(bus) == bus_num) {
|
| 1178 |
return bus;
|
| 1179 |
} |
| 1180 |
|
| 1181 |
/* try child bus */
|
| 1182 |
QLIST_FOREACH(sec, &bus->child, sibling) {
|
| 1183 |
if (pci_bus_num(sec) <= bus_num && bus_num <= pci_sub_bus(sec)) {
|
| 1184 |
return pci_find_bus(sec, bus_num);
|
| 1185 |
} |
| 1186 |
} |
| 1187 |
|
| 1188 |
return NULL; |
| 1189 |
} |
| 1190 |
|
| 1191 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function) |
| 1192 |
{
|
| 1193 |
bus = pci_find_bus(bus, bus_num); |
| 1194 |
|
| 1195 |
if (!bus)
|
| 1196 |
return NULL; |
| 1197 |
|
| 1198 |
return bus->devices[PCI_DEVFN(slot, function)];
|
| 1199 |
} |
| 1200 |
|
| 1201 |
static int pci_bridge_initfn(PCIDevice *dev) |
| 1202 |
{
|
| 1203 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev); |
| 1204 |
|
| 1205 |
pci_config_set_vendor_id(s->dev.config, s->vid); |
| 1206 |
pci_config_set_device_id(s->dev.config, s->did); |
| 1207 |
|
| 1208 |
/* TODO: intial value
|
| 1209 |
* command register:
|
| 1210 |
* According to PCI bridge spec, after reset
|
| 1211 |
* bus master bit is off
|
| 1212 |
* memory space enable bit is off
|
| 1213 |
* According to manual (805-1251.pdf).(See abp_pbi.c for its links.)
|
| 1214 |
* the reset value should be zero unless the boot pin is tied high
|
| 1215 |
* (which is tru) and thus it should be PCI_COMMAND_MEMORY.
|
| 1216 |
*
|
| 1217 |
* For now, don't touch the value.
|
| 1218 |
* Later command register will be set to zero and apb_pci.c will
|
| 1219 |
* override the value.
|
| 1220 |
* Same for latency timer, and multi function bit of header type.
|
| 1221 |
*/
|
| 1222 |
pci_set_word(dev->config + PCI_COMMAND, |
| 1223 |
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 1224 |
|
| 1225 |
pci_set_word(dev->config + PCI_STATUS, |
| 1226 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
| 1227 |
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI); |
| 1228 |
dev->config[PCI_LATENCY_TIMER] = 0x10;
|
| 1229 |
dev->config[PCI_HEADER_TYPE] = |
| 1230 |
PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; |
| 1231 |
pci_set_word(dev->config + PCI_SEC_STATUS, |
| 1232 |
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK); |
| 1233 |
return 0; |
| 1234 |
} |
| 1235 |
|
| 1236 |
static int pci_bridge_exitfn(PCIDevice *pci_dev) |
| 1237 |
{
|
| 1238 |
PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev); |
| 1239 |
PCIBus *bus = &s->bus; |
| 1240 |
pci_unregister_secondary_bus(bus); |
| 1241 |
return 0; |
| 1242 |
} |
| 1243 |
|
| 1244 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
| 1245 |
pci_map_irq_fn map_irq, const char *name) |
| 1246 |
{
|
| 1247 |
PCIDevice *dev; |
| 1248 |
PCIBridge *s; |
| 1249 |
|
| 1250 |
dev = pci_create(bus, devfn, "pci-bridge");
|
| 1251 |
qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
|
| 1252 |
qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
|
| 1253 |
qdev_init_nofail(&dev->qdev); |
| 1254 |
|
| 1255 |
s = DO_UPCAST(PCIBridge, dev, dev); |
| 1256 |
pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name); |
| 1257 |
return &s->bus;
|
| 1258 |
} |
| 1259 |
|
| 1260 |
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base) |
| 1261 |
{
|
| 1262 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
| 1263 |
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev); |
| 1264 |
PCIBus *bus; |
| 1265 |
int devfn, rc;
|
| 1266 |
|
| 1267 |
/* initialize cap_present for pci_is_express() and pci_config_size() */
|
| 1268 |
if (info->is_express) {
|
| 1269 |
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
| 1270 |
} |
| 1271 |
|
| 1272 |
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev)); |
| 1273 |
devfn = pci_dev->devfn; |
| 1274 |
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn, |
| 1275 |
info->config_read, info->config_write, |
| 1276 |
info->header_type); |
| 1277 |
rc = info->init(pci_dev); |
| 1278 |
if (rc != 0) |
| 1279 |
return rc;
|
| 1280 |
if (qdev->hotplugged)
|
| 1281 |
bus->hotplug(pci_dev, 1);
|
| 1282 |
return 0; |
| 1283 |
} |
| 1284 |
|
| 1285 |
static int pci_unplug_device(DeviceState *qdev) |
| 1286 |
{
|
| 1287 |
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev); |
| 1288 |
|
| 1289 |
dev->bus->hotplug(dev, 0);
|
| 1290 |
return 0; |
| 1291 |
} |
| 1292 |
|
| 1293 |
void pci_qdev_register(PCIDeviceInfo *info)
|
| 1294 |
{
|
| 1295 |
info->qdev.init = pci_qdev_init; |
| 1296 |
info->qdev.unplug = pci_unplug_device; |
| 1297 |
info->qdev.exit = pci_unregister_device; |
| 1298 |
info->qdev.bus_info = &pci_bus_info; |
| 1299 |
qdev_register(&info->qdev); |
| 1300 |
} |
| 1301 |
|
| 1302 |
void pci_qdev_register_many(PCIDeviceInfo *info)
|
| 1303 |
{
|
| 1304 |
while (info->qdev.name) {
|
| 1305 |
pci_qdev_register(info); |
| 1306 |
info++; |
| 1307 |
} |
| 1308 |
} |
| 1309 |
|
| 1310 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
| 1311 |
{
|
| 1312 |
DeviceState *dev; |
| 1313 |
|
| 1314 |
dev = qdev_create(&bus->qbus, name); |
| 1315 |
qdev_prop_set_uint32(dev, "addr", devfn);
|
| 1316 |
return DO_UPCAST(PCIDevice, qdev, dev);
|
| 1317 |
} |
| 1318 |
|
| 1319 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
| 1320 |
{
|
| 1321 |
PCIDevice *dev = pci_create(bus, devfn, name); |
| 1322 |
qdev_init_nofail(&dev->qdev); |
| 1323 |
return dev;
|
| 1324 |
} |
| 1325 |
|
| 1326 |
static int pci_find_space(PCIDevice *pdev, uint8_t size) |
| 1327 |
{
|
| 1328 |
int config_size = pci_config_size(pdev);
|
| 1329 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
| 1330 |
int i;
|
| 1331 |
for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
|
| 1332 |
if (pdev->used[i])
|
| 1333 |
offset = i + 1;
|
| 1334 |
else if (i - offset + 1 == size) |
| 1335 |
return offset;
|
| 1336 |
return 0; |
| 1337 |
} |
| 1338 |
|
| 1339 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
| 1340 |
uint8_t *prev_p) |
| 1341 |
{
|
| 1342 |
uint8_t next, prev; |
| 1343 |
|
| 1344 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
| 1345 |
return 0; |
| 1346 |
|
| 1347 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
| 1348 |
prev = next + PCI_CAP_LIST_NEXT) |
| 1349 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
| 1350 |
break;
|
| 1351 |
|
| 1352 |
if (prev_p)
|
| 1353 |
*prev_p = prev; |
| 1354 |
return next;
|
| 1355 |
} |
| 1356 |
|
| 1357 |
/* Reserve space and add capability to the linked list in pci config space */
|
| 1358 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
| 1359 |
{
|
| 1360 |
uint8_t offset = pci_find_space(pdev, size); |
| 1361 |
uint8_t *config = pdev->config + offset; |
| 1362 |
if (!offset)
|
| 1363 |
return -ENOSPC;
|
| 1364 |
config[PCI_CAP_LIST_ID] = cap_id; |
| 1365 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
| 1366 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
| 1367 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
| 1368 |
memset(pdev->used + offset, 0xFF, size);
|
| 1369 |
/* Make capability read-only by default */
|
| 1370 |
memset(pdev->wmask + offset, 0, size);
|
| 1371 |
/* Check capability by default */
|
| 1372 |
memset(pdev->cmask + offset, 0xFF, size);
|
| 1373 |
return offset;
|
| 1374 |
} |
| 1375 |
|
| 1376 |
/* Unlink capability from the pci config space. */
|
| 1377 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
| 1378 |
{
|
| 1379 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
| 1380 |
if (!offset)
|
| 1381 |
return;
|
| 1382 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
| 1383 |
/* Make capability writeable again */
|
| 1384 |
memset(pdev->wmask + offset, 0xff, size);
|
| 1385 |
/* Clear cmask as device-specific registers can't be checked */
|
| 1386 |
memset(pdev->cmask + offset, 0, size);
|
| 1387 |
memset(pdev->used + offset, 0, size);
|
| 1388 |
|
| 1389 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
| 1390 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
| 1391 |
} |
| 1392 |
|
| 1393 |
/* Reserve space for capability at a known offset (to call after load). */
|
| 1394 |
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
| 1395 |
{
|
| 1396 |
memset(pdev->used + offset, 0xff, size);
|
| 1397 |
} |
| 1398 |
|
| 1399 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
| 1400 |
{
|
| 1401 |
return pci_find_capability_list(pdev, cap_id, NULL); |
| 1402 |
} |
| 1403 |
|
| 1404 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
| 1405 |
{
|
| 1406 |
PCIDevice *d = (PCIDevice *)dev; |
| 1407 |
const pci_class_desc *desc;
|
| 1408 |
char ctxt[64]; |
| 1409 |
PCIIORegion *r; |
| 1410 |
int i, class;
|
| 1411 |
|
| 1412 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
| 1413 |
desc = pci_class_descriptions; |
| 1414 |
while (desc->desc && class != desc->class)
|
| 1415 |
desc++; |
| 1416 |
if (desc->desc) {
|
| 1417 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
| 1418 |
} else {
|
| 1419 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
| 1420 |
} |
| 1421 |
|
| 1422 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
| 1423 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
| 1424 |
indent, "", ctxt,
|
| 1425 |
d->config[PCI_SECONDARY_BUS], |
| 1426 |
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
| 1427 |
pci_get_word(d->config + PCI_VENDOR_ID), |
| 1428 |
pci_get_word(d->config + PCI_DEVICE_ID), |
| 1429 |
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), |
| 1430 |
pci_get_word(d->config + PCI_SUBSYSTEM_ID)); |
| 1431 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
| 1432 |
r = &d->io_regions[i]; |
| 1433 |
if (!r->size)
|
| 1434 |
continue;
|
| 1435 |
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
|
| 1436 |
" [0x%"FMT_PCIBUS"]\n", |
| 1437 |
indent, "",
|
| 1438 |
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
| 1439 |
r->addr, r->addr + r->size - 1);
|
| 1440 |
} |
| 1441 |
} |
| 1442 |
|
| 1443 |
static PCIDeviceInfo bridge_info = {
|
| 1444 |
.qdev.name = "pci-bridge",
|
| 1445 |
.qdev.size = sizeof(PCIBridge),
|
| 1446 |
.init = pci_bridge_initfn, |
| 1447 |
.exit = pci_bridge_exitfn, |
| 1448 |
.config_write = pci_bridge_write_config, |
| 1449 |
.qdev.props = (Property[]) {
|
| 1450 |
DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0), |
| 1451 |
DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0), |
| 1452 |
DEFINE_PROP_END_OF_LIST(), |
| 1453 |
} |
| 1454 |
}; |
| 1455 |
|
| 1456 |
static void pci_register_devices(void) |
| 1457 |
{
|
| 1458 |
pci_qdev_register(&bridge_info); |
| 1459 |
} |
| 1460 |
|
| 1461 |
device_init(pci_register_devices) |