Revision deb54399
| b/hw/ac97.c | ||
|---|---|---|
| 1336 | 1336 |
s = &d->ac97; |
| 1337 | 1337 |
s->pci_dev = &d->dev; |
| 1338 | 1338 |
c = d->dev.config; |
| 1339 |
c[0x00] = 0x86; /* vid vendor id intel ro */ |
|
| 1340 |
c[0x01] = 0x80; /* intel */ |
|
| 1341 |
|
|
| 1342 |
c[0x02] = 0x15; /* did device id 82801 ro */ |
|
| 1343 |
c[0x03] = 0x24; /* 82801aa */ |
|
| 1339 |
pci_config_set_vendor_id(c, PCI_VENDOR_ID_INTEL); /* ro */ |
|
| 1340 |
pci_config_set_device_id(c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */ |
|
| 1344 | 1341 |
|
| 1345 | 1342 |
c[0x04] = 0x00; /* pcicmd pci command rw, ro */ |
| 1346 | 1343 |
c[0x05] = 0x00; |
| b/hw/acpi.c | ||
|---|---|---|
| 503 | 503 |
devfn, NULL, pm_write_config); |
| 504 | 504 |
pm_state = s; |
| 505 | 505 |
pci_conf = s->dev.config; |
| 506 |
pci_conf[0x00] = 0x86; |
|
| 507 |
pci_conf[0x01] = 0x80; |
|
| 508 |
pci_conf[0x02] = 0x13; |
|
| 509 |
pci_conf[0x03] = 0x71; |
|
| 506 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
|
| 507 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
|
| 510 | 508 |
pci_conf[0x06] = 0x80; |
| 511 | 509 |
pci_conf[0x07] = 0x02; |
| 512 | 510 |
pci_conf[0x08] = 0x03; // revision number |
| b/hw/apb_pci.c | ||
|---|---|---|
| 252 | 252 |
|
| 253 | 253 |
d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice), |
| 254 | 254 |
0, NULL, NULL); |
| 255 |
d->config[0x00] = 0x8e; // vendor_id : Sun |
|
| 256 |
d->config[0x01] = 0x10; |
|
| 257 |
d->config[0x02] = 0x00; // device_id |
|
| 258 |
d->config[0x03] = 0xa0; |
|
| 255 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_SUN); |
|
| 256 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_SUN_SABRE); |
|
| 259 | 257 |
d->config[0x04] = 0x06; // command = bus master, pci mem |
| 260 | 258 |
d->config[0x05] = 0x00; |
| 261 | 259 |
d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
| b/hw/cirrus_vga.c | ||
|---|---|---|
| 173 | 173 |
#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte |
| 174 | 174 |
#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte |
| 175 | 175 |
|
| 176 |
// PCI 0x00: vendor, 0x02: device |
|
| 177 |
#define PCI_VENDOR_CIRRUS 0x1013 |
|
| 176 |
// PCI 0x02: device |
|
| 178 | 177 |
#define PCI_DEVICE_CLGD5462 0x00d0 |
| 179 | 178 |
#define PCI_DEVICE_CLGD5465 0x00d6 |
| 180 | 179 |
|
| ... | ... | |
| 3376 | 3375 |
sizeof(PCICirrusVGAState), |
| 3377 | 3376 |
-1, NULL, pci_cirrus_write_config); |
| 3378 | 3377 |
pci_conf = d->dev.config; |
| 3379 |
pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff); |
|
| 3380 |
pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8); |
|
| 3381 |
pci_conf[0x02] = (uint8_t) (device_id & 0xff); |
|
| 3382 |
pci_conf[0x03] = (uint8_t) (device_id >> 8); |
|
| 3378 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS); |
|
| 3379 |
pci_config_set_device_id(pci_conf, device_id); |
|
| 3383 | 3380 |
pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS; |
| 3384 | 3381 |
pci_conf[0x0a] = PCI_CLASS_SUB_VGA; |
| 3385 | 3382 |
pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY; |
| b/hw/e1000.c | ||
|---|---|---|
| 1049 | 1049 |
pci_conf = d->dev.config; |
| 1050 | 1050 |
memset(pci_conf, 0, 256); |
| 1051 | 1051 |
|
| 1052 |
*(uint16_t *)(pci_conf+0x00) = cpu_to_le16(0x8086);
|
|
| 1053 |
*(uint16_t *)(pci_conf+0x02) = cpu_to_le16(E1000_DEVID);
|
|
| 1052 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
|
|
| 1053 |
pci_config_set_device_id(pci_conf, E1000_DEVID);
|
|
| 1054 | 1054 |
*(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407); |
| 1055 | 1055 |
*(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010); |
| 1056 | 1056 |
pci_conf[0x08] = 0x03; |
| b/hw/eepro100.c | ||
|---|---|---|
| 422 | 422 |
logout("%p\n", s);
|
| 423 | 423 |
|
| 424 | 424 |
/* PCI Vendor ID */ |
| 425 |
PCI_CONFIG_16(PCI_VENDOR_ID, 0x8086);
|
|
| 425 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
|
|
| 426 | 426 |
/* PCI Device ID */ |
| 427 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
|
|
| 427 |
pci_config_set_device_id(pci_conf, 0x1209);
|
|
| 428 | 428 |
/* PCI Command */ |
| 429 | 429 |
PCI_CONFIG_16(PCI_COMMAND, 0x0000); |
| 430 | 430 |
/* PCI Status */ |
| b/hw/es1370.c | ||
|---|---|---|
| 1031 | 1031 |
} |
| 1032 | 1032 |
|
| 1033 | 1033 |
c = d->dev.config; |
| 1034 |
c[0x00] = 0x74; |
|
| 1035 |
c[0x01] = 0x12; |
|
| 1036 |
c[0x02] = 0x00; |
|
| 1037 |
c[0x03] = 0x50; |
|
| 1034 |
pci_config_set_vendor_id(c, PCI_VENDOR_ID_ENSONIQ); |
|
| 1035 |
pci_config_set_device_id(c, PCI_DEVICE_ID_ENSONIQ_ES1370); |
|
| 1038 | 1036 |
c[0x07] = 2 << 1; |
| 1039 | 1037 |
c[0x0a] = 0x01; |
| 1040 | 1038 |
c[0x0b] = 0x04; |
| b/hw/grackle_pci.c | ||
|---|---|---|
| 144 | 144 |
cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data); |
| 145 | 145 |
d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice), |
| 146 | 146 |
0, NULL, NULL); |
| 147 |
d->config[0x00] = 0x57; // vendor_id |
|
| 148 |
d->config[0x01] = 0x10; |
|
| 149 |
d->config[0x02] = 0x02; // device_id |
|
| 150 |
d->config[0x03] = 0x00; |
|
| 147 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); |
|
| 148 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106); |
|
| 151 | 149 |
d->config[0x08] = 0x00; // revision |
| 152 | 150 |
d->config[0x09] = 0x01; |
| 153 | 151 |
d->config[0x0a] = 0x00; // class_sub = host |
| b/hw/gt64xxx.c | ||
|---|---|---|
| 1136 | 1136 |
|
| 1137 | 1137 |
/* FIXME: Malta specific hw assumptions ahead */ |
| 1138 | 1138 |
|
| 1139 |
d->config[0x00] = 0xab; /* vendor_id */ |
|
| 1140 |
d->config[0x01] = 0x11; |
|
| 1141 |
d->config[0x02] = 0x20; /* device_id */ |
|
| 1142 |
d->config[0x03] = 0x46; |
|
| 1139 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MARVELL); |
|
| 1140 |
pci_config_set_device_id(d->config, 0x4620); /* device_id */ |
|
| 1143 | 1141 |
|
| 1144 | 1142 |
d->config[0x04] = 0x00; |
| 1145 | 1143 |
d->config[0x05] = 0x00; |
| b/hw/ide.c | ||
|---|---|---|
| 3342 | 3342 |
NULL, NULL); |
| 3343 | 3343 |
d->type = IDE_TYPE_CMD646; |
| 3344 | 3344 |
pci_conf = d->dev.config; |
| 3345 |
pci_conf[0x00] = 0x95; // CMD646 |
|
| 3346 |
pci_conf[0x01] = 0x10; |
|
| 3347 |
pci_conf[0x02] = 0x46; |
|
| 3348 |
pci_conf[0x03] = 0x06; |
|
| 3345 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD); |
|
| 3346 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646); |
|
| 3349 | 3347 |
|
| 3350 | 3348 |
pci_conf[0x08] = 0x07; // IDE controller revision |
| 3351 | 3349 |
pci_conf[0x09] = 0x8f; |
| ... | ... | |
| 3417 | 3415 |
d->type = IDE_TYPE_PIIX3; |
| 3418 | 3416 |
|
| 3419 | 3417 |
pci_conf = d->dev.config; |
| 3420 |
pci_conf[0x00] = 0x86; // Intel |
|
| 3421 |
pci_conf[0x01] = 0x80; |
|
| 3422 |
pci_conf[0x02] = 0x10; |
|
| 3423 |
pci_conf[0x03] = 0x70; |
|
| 3418 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
|
| 3419 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1); |
|
| 3424 | 3420 |
pci_conf[0x09] = 0x80; // legacy ATA mode |
| 3425 | 3421 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
| 3426 | 3422 |
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
| ... | ... | |
| 3456 | 3452 |
d->type = IDE_TYPE_PIIX4; |
| 3457 | 3453 |
|
| 3458 | 3454 |
pci_conf = d->dev.config; |
| 3459 |
pci_conf[0x00] = 0x86; // Intel |
|
| 3460 |
pci_conf[0x01] = 0x80; |
|
| 3461 |
pci_conf[0x02] = 0x11; |
|
| 3462 |
pci_conf[0x03] = 0x71; |
|
| 3455 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
|
| 3456 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB); |
|
| 3463 | 3457 |
pci_conf[0x09] = 0x80; // legacy ATA mode |
| 3464 | 3458 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE |
| 3465 | 3459 |
pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage |
| b/hw/lsi53c895a.c | ||
|---|---|---|
| 1963 | 1963 |
void *lsi_scsi_init(PCIBus *bus, int devfn) |
| 1964 | 1964 |
{
|
| 1965 | 1965 |
LSIState *s; |
| 1966 |
uint8_t *pci_conf; |
|
| 1966 | 1967 |
|
| 1967 | 1968 |
s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA", |
| 1968 | 1969 |
sizeof(*s), devfn, NULL, NULL); |
| ... | ... | |
| 1971 | 1972 |
return NULL; |
| 1972 | 1973 |
} |
| 1973 | 1974 |
|
| 1975 |
pci_conf = s->pci_dev.config; |
|
| 1976 |
|
|
| 1974 | 1977 |
/* PCI Vendor ID (word) */ |
| 1975 |
s->pci_dev.config[0x00] = 0x00; |
|
| 1976 |
s->pci_dev.config[0x01] = 0x10; |
|
| 1978 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_LSI_LOGIC); |
|
| 1977 | 1979 |
/* PCI device ID (word) */ |
| 1978 |
s->pci_dev.config[0x02] = 0x12; |
|
| 1979 |
s->pci_dev.config[0x03] = 0x00; |
|
| 1980 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A); |
|
| 1980 | 1981 |
/* PCI base class code */ |
| 1981 |
s->pci_dev.config[0x0b] = 0x01;
|
|
| 1982 |
pci_conf[0x0b] = 0x01;
|
|
| 1982 | 1983 |
/* PCI subsystem ID */ |
| 1983 |
s->pci_dev.config[0x2e] = 0x00;
|
|
| 1984 |
s->pci_dev.config[0x2f] = 0x10;
|
|
| 1984 |
pci_conf[0x2e] = 0x00;
|
|
| 1985 |
pci_conf[0x2f] = 0x10;
|
|
| 1985 | 1986 |
/* PCI latency timer = 255 */ |
| 1986 |
s->pci_dev.config[0x0d] = 0xff;
|
|
| 1987 |
pci_conf[0x0d] = 0xff;
|
|
| 1987 | 1988 |
/* Interrupt pin 1 */ |
| 1988 |
s->pci_dev.config[0x3d] = 0x01;
|
|
| 1989 |
pci_conf[0x3d] = 0x01;
|
|
| 1989 | 1990 |
|
| 1990 | 1991 |
s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn, |
| 1991 | 1992 |
lsi_mmio_writefn, s); |
| b/hw/macio.c | ||
|---|---|---|
| 106 | 106 |
macio_state->ide_mem_index[i] = -1; |
| 107 | 107 |
/* Note: this code is strongly inspirated from the corresponding code |
| 108 | 108 |
in PearPC */ |
| 109 |
d->config[0x00] = 0x6b; // vendor_id |
|
| 110 |
d->config[0x01] = 0x10; |
|
| 111 |
d->config[0x02] = device_id; |
|
| 112 |
d->config[0x03] = device_id >> 8; |
|
| 109 |
|
|
| 110 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
|
| 111 |
pci_config_set_device_id(d->config, device_id); |
|
| 113 | 112 |
|
| 114 | 113 |
d->config[0x0a] = 0x00; // class_sub = pci2pci |
| 115 | 114 |
d->config[0x0b] = 0xff; // class_base = bridge |
| b/hw/ne2000.c | ||
|---|---|---|
| 790 | 790 |
devfn, |
| 791 | 791 |
NULL, NULL); |
| 792 | 792 |
pci_conf = d->dev.config; |
| 793 |
pci_conf[0x00] = 0xec; // Realtek 8029 |
|
| 794 |
pci_conf[0x01] = 0x10; |
|
| 795 |
pci_conf[0x02] = 0x29; |
|
| 796 |
pci_conf[0x03] = 0x80; |
|
| 793 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
|
| 794 |
pci_config_set_device_id(pci_conf, 0x8029); // Realtek 8029 |
|
| 797 | 795 |
pci_conf[0x0a] = 0x00; // ethernet network controller |
| 798 | 796 |
pci_conf[0x0b] = 0x02; |
| 799 | 797 |
pci_conf[0x0e] = 0x00; // header_type |
| b/hw/openpic.c | ||
|---|---|---|
| 1017 | 1017 |
if (opp == NULL) |
| 1018 | 1018 |
return NULL; |
| 1019 | 1019 |
pci_conf = opp->pci_dev.config; |
| 1020 |
pci_conf[0x00] = 0x14; // IBM MPIC2 |
|
| 1021 |
pci_conf[0x01] = 0x10; |
|
| 1022 |
pci_conf[0x02] = 0xFF; |
|
| 1023 |
pci_conf[0x03] = 0xFF; |
|
| 1020 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); |
|
| 1021 |
pci_config_set_device_id(pci_conf, 0xffff); // MPIC2 |
|
| 1024 | 1022 |
pci_conf[0x0a] = 0x80; // PIC |
| 1025 | 1023 |
pci_conf[0x0b] = 0x08; |
| 1026 | 1024 |
pci_conf[0x0e] = 0x00; // header_type |
| b/hw/pci.h | ||
|---|---|---|
| 8 | 8 |
|
| 9 | 9 |
extern target_phys_addr_t pci_mem_base; |
| 10 | 10 |
|
| 11 |
/* see pci-ids.txt */ |
|
| 11 |
#define PCI_VENDOR_ID_LSI_LOGIC 0x1000 |
|
| 12 |
#define PCI_DEVICE_ID_LSI_53C895A 0x0012 |
|
| 13 |
|
|
| 14 |
#define PCI_VENDOR_ID_DEC 0x1011 |
|
| 15 |
|
|
| 16 |
#define PCI_VENDOR_ID_CIRRUS 0x1013 |
|
| 17 |
|
|
| 18 |
#define PCI_VENDOR_ID_IBM 0x1014 |
|
| 19 |
|
|
| 20 |
#define PCI_VENDOR_ID_AMD 0x1022 |
|
| 21 |
#define PCI_DEVICE_ID_AMD_LANCE 0x2000 |
|
| 22 |
|
|
| 23 |
#define PCI_VENDOR_ID_HITACHI 0x1054 |
|
| 24 |
|
|
| 25 |
#define PCI_VENDOR_ID_MOTOROLA 0x1057 |
|
| 26 |
#define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 |
|
| 27 |
#define PCI_DEVICE_ID_MOTOROLA_RAVEN 0x4801 |
|
| 28 |
|
|
| 29 |
#define PCI_VENDOR_ID_APPLE 0x106b |
|
| 30 |
#define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 |
|
| 31 |
|
|
| 32 |
#define PCI_VENDOR_ID_SUN 0x108e |
|
| 33 |
#define PCI_DEVICE_ID_SUN_EBUS 0x1000 |
|
| 34 |
#define PCI_DEVICE_ID_SUN_SABRE 0xa000 |
|
| 35 |
|
|
| 36 |
#define PCI_VENDOR_ID_CMD 0x1095 |
|
| 37 |
#define PCI_DEVICE_ID_CMD_646 0x0646 |
|
| 38 |
|
|
| 39 |
#define PCI_VENDOR_ID_REALTEK 0x10ec |
|
| 40 |
#define PCI_DEVICE_ID_REALTEK_8139 0x8139 |
|
| 41 |
|
|
| 42 |
#define PCI_VENDOR_ID_XILINX 0x10ee |
|
| 43 |
|
|
| 44 |
#define PCI_VENDOR_ID_MARVELL 0x11ab |
|
| 45 |
|
|
| 46 |
#define PCI_VENDOR_ID_ENSONIQ 0x1274 |
|
| 47 |
#define PCI_DEVICE_ID_ENSONIQ_ES1370 0x5000 |
|
| 48 |
|
|
| 49 |
#define PCI_VENDOR_ID_VMWARE 0x15ad |
|
| 50 |
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
|
| 51 |
#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
|
| 52 |
#define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
|
| 53 |
#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
|
| 54 |
#define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
|
| 55 |
|
|
| 56 |
#define PCI_VENDOR_ID_INTEL 0x8086 |
|
| 57 |
#define PCI_DEVICE_ID_INTEL_82441 0x1237 |
|
| 58 |
#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 |
|
| 59 |
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 |
|
| 60 |
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 |
|
| 61 |
#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 |
|
| 62 |
#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110 |
|
| 63 |
#define PCI_DEVICE_ID_INTEL_82371AB 0x7111 |
|
| 64 |
#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 |
|
| 65 |
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 |
|
| 66 |
|
|
| 67 |
/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ |
|
| 12 | 68 |
#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 |
| 13 | 69 |
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 |
| 14 | 70 |
#define PCI_SUBDEVICE_ID_QEMU 0x1100 |
| ... | ... | |
| 130 | 186 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id, |
| 131 | 187 |
pci_map_irq_fn map_irq, const char *name); |
| 132 | 188 |
|
| 189 |
static inline void |
|
| 190 |
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val) |
|
| 191 |
{
|
|
| 192 |
cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val); |
|
| 193 |
} |
|
| 194 |
|
|
| 195 |
static inline void |
|
| 196 |
pci_config_set_device_id(uint8_t *pci_config, uint16_t val) |
|
| 197 |
{
|
|
| 198 |
cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val); |
|
| 199 |
} |
|
| 200 |
|
|
| 133 | 201 |
/* lsi53c895a.c */ |
| 134 | 202 |
#define LSI_MAX_DEVS 7 |
| 135 | 203 |
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
| b/hw/pcnet.c | ||
|---|---|---|
| 2000 | 2000 |
|
| 2001 | 2001 |
pci_conf = d->dev.config; |
| 2002 | 2002 |
|
| 2003 |
*(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
|
|
| 2004 |
*(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
|
|
| 2003 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
|
|
| 2004 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
|
|
| 2005 | 2005 |
*(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007); |
| 2006 | 2006 |
*(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280); |
| 2007 | 2007 |
pci_conf[0x08] = 0x10; |
| b/hw/piix_pci.c | ||
|---|---|---|
| 192 | 192 |
d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0, |
| 193 | 193 |
NULL, i440fx_write_config); |
| 194 | 194 |
|
| 195 |
d->config[0x00] = 0x86; // vendor_id |
|
| 196 |
d->config[0x01] = 0x80; |
|
| 197 |
d->config[0x02] = 0x37; // device_id |
|
| 198 |
d->config[0x03] = 0x12; |
|
| 195 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL); |
|
| 196 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441); |
|
| 199 | 197 |
d->config[0x08] = 0x02; // revision |
| 200 | 198 |
d->config[0x0a] = 0x00; // class_sub = host2pci |
| 201 | 199 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
| ... | ... | |
| 337 | 335 |
piix3_dev = d; |
| 338 | 336 |
pci_conf = d->config; |
| 339 | 337 |
|
| 340 |
pci_conf[0x00] = 0x86; // Intel |
|
| 341 |
pci_conf[0x01] = 0x80; |
|
| 342 |
pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
|
| 343 |
pci_conf[0x03] = 0x70; |
|
| 338 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
|
| 339 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
|
| 344 | 340 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
| 345 | 341 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
| 346 | 342 |
pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
| ... | ... | |
| 361 | 357 |
piix4_dev = d; |
| 362 | 358 |
pci_conf = d->config; |
| 363 | 359 |
|
| 364 |
pci_conf[0x00] = 0x86; // Intel |
|
| 365 |
pci_conf[0x01] = 0x80; |
|
| 366 |
pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge |
|
| 367 |
pci_conf[0x03] = 0x71; |
|
| 360 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
|
| 361 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge |
|
| 368 | 362 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
| 369 | 363 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
| 370 | 364 |
pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
| b/hw/ppc4xx_pci.c | ||
|---|---|---|
| 366 | 366 |
PPC4xxPCIState *controller; |
| 367 | 367 |
int index; |
| 368 | 368 |
static int ppc4xx_pci_id; |
| 369 |
uint8_t *pci_conf; |
|
| 369 | 370 |
|
| 370 | 371 |
controller = qemu_mallocz(sizeof(PPC4xxPCIState)); |
| 371 | 372 |
if (!controller) |
| ... | ... | |
| 378 | 379 |
controller->pci_dev = pci_register_device(controller->pci_state.bus, |
| 379 | 380 |
"host bridge", sizeof(PCIDevice), |
| 380 | 381 |
0, NULL, NULL); |
| 381 |
controller->pci_dev->config[0x00] = 0x14; // vendor_id |
|
| 382 |
controller->pci_dev->config[0x01] = 0x10; |
|
| 383 |
controller->pci_dev->config[0x02] = 0x7f; // device_id |
|
| 384 |
controller->pci_dev->config[0x03] = 0x02; |
|
| 385 |
controller->pci_dev->config[0x0a] = 0x80; // class_sub = other bridge type |
|
| 386 |
controller->pci_dev->config[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 382 |
pci_conf = controller->pci_dev->config; |
|
| 383 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); |
|
| 384 |
pci_config_set_device_id(pci_conf, 0x027f); // device_id |
|
| 385 |
pci_conf[0x0a] = 0x80; // class_sub = other bridge type |
|
| 386 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
|
| 387 | 387 |
|
| 388 | 388 |
/* CFGADDR */ |
| 389 | 389 |
index = cpu_register_io_memory(0, pci4xx_cfgaddr_read, |
| b/hw/prep_pci.c | ||
|---|---|---|
| 155 | 155 |
/* PCI host bridge */ |
| 156 | 156 |
d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven", |
| 157 | 157 |
sizeof(PCIDevice), 0, NULL, NULL); |
| 158 |
d->config[0x00] = 0x57; // vendor_id : Motorola |
|
| 159 |
d->config[0x01] = 0x10; |
|
| 160 |
d->config[0x02] = 0x01; // device_id : Raven |
|
| 161 |
d->config[0x03] = 0x48; |
|
| 158 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); |
|
| 159 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN); |
|
| 162 | 160 |
d->config[0x08] = 0x00; // revision |
| 163 | 161 |
d->config[0x0A] = 0x00; // class_sub = pci host |
| 164 | 162 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
| b/hw/rtl8139.c | ||
|---|---|---|
| 1187 | 1187 |
s->eeprom.contents[0] = 0x8129; |
| 1188 | 1188 |
#if 1 |
| 1189 | 1189 |
// PCI vendor and device ID should be mirrored here |
| 1190 |
s->eeprom.contents[1] = 0x10ec;
|
|
| 1191 |
s->eeprom.contents[2] = 0x8139;
|
|
| 1190 |
s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
|
|
| 1191 |
s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
|
|
| 1192 | 1192 |
#endif |
| 1193 | 1193 |
|
| 1194 | 1194 |
s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8; |
| ... | ... | |
| 3425 | 3425 |
devfn, |
| 3426 | 3426 |
NULL, NULL); |
| 3427 | 3427 |
pci_conf = d->dev.config; |
| 3428 |
pci_conf[0x00] = 0xec; /* Realtek 8139 */ |
|
| 3429 |
pci_conf[0x01] = 0x10; |
|
| 3430 |
pci_conf[0x02] = 0x39; |
|
| 3431 |
pci_conf[0x03] = 0x81; |
|
| 3428 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
|
| 3429 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139); |
|
| 3432 | 3430 |
pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */ |
| 3433 | 3431 |
pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */ |
| 3434 | 3432 |
pci_conf[0x0a] = 0x00; /* ethernet network controller */ |
| b/hw/sh_pci.c | ||
|---|---|---|
| 188 | 188 |
cpu_register_physical_memory(0xfe240000, 0x40000, iop); |
| 189 | 189 |
cpu_register_physical_memory(0xfd000000, 0x1000000, mem); |
| 190 | 190 |
|
| 191 |
p->dev->config[0x00] = 0x54; // HITACHI |
|
| 192 |
p->dev->config[0x01] = 0x10; // |
|
| 193 |
p->dev->config[0x02] = 0x0e; // SH7751R |
|
| 194 |
p->dev->config[0x03] = 0x35; // |
|
| 191 |
pci_config_set_vendor_id(p->dev->config, PCI_VENDOR_ID_HITACHI); |
|
| 192 |
pci_config_set_device_id(p->dev->config, 0x350e); // SH7751R |
|
| 195 | 193 |
p->dev->config[0x04] = 0x80; |
| 196 | 194 |
p->dev->config[0x05] = 0x00; |
| 197 | 195 |
p->dev->config[0x06] = 0x90; |
| b/hw/sun4u.c | ||
|---|---|---|
| 365 | 365 |
PCIDevice *s; |
| 366 | 366 |
|
| 367 | 367 |
s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL); |
| 368 |
s->config[0x00] = 0x8e; // vendor_id : Sun |
|
| 369 |
s->config[0x01] = 0x10; |
|
| 370 |
s->config[0x02] = 0x00; // device_id |
|
| 371 |
s->config[0x03] = 0x10; |
|
| 368 |
pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
|
| 369 |
pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); |
|
| 372 | 370 |
s->config[0x04] = 0x06; // command = bus master, pci mem |
| 373 | 371 |
s->config[0x05] = 0x00; |
| 374 | 372 |
s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
| b/hw/unin_pci.c | ||
|---|---|---|
| 174 | 174 |
cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
| 175 | 175 |
d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice), |
| 176 | 176 |
11 << 3, NULL, NULL); |
| 177 |
d->config[0x00] = 0x6b; // vendor_id : Apple |
|
| 178 |
d->config[0x01] = 0x10; |
|
| 179 |
d->config[0x02] = 0x1F; // device_id |
|
| 180 |
d->config[0x03] = 0x00; |
|
| 177 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
|
| 178 |
pci_config_set_device_id(d->config, 0x001f); // device_id |
|
| 181 | 179 |
d->config[0x08] = 0x00; // revision |
| 182 | 180 |
d->config[0x0A] = 0x00; // class_sub = pci host |
| 183 | 181 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
| ... | ... | |
| 190 | 188 |
/* pci-to-pci bridge */ |
| 191 | 189 |
d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
|
| 192 | 190 |
NULL, NULL); |
| 193 |
d->config[0x00] = 0x11; // vendor_id : TI |
|
| 194 |
d->config[0x01] = 0x10; |
|
| 195 |
d->config[0x02] = 0x26; // device_id |
|
| 196 |
d->config[0x03] = 0x00; |
|
| 191 |
pci_config_set_vendor_id(d->config, 0x1011); // vendor_id : TI |
|
| 192 |
pci_config_set_device_id(d->config, 0x0026); // device_id |
|
| 197 | 193 |
d->config[0x08] = 0x05; // revision |
| 198 | 194 |
d->config[0x0A] = 0x04; // class_sub = pci2pci |
| 199 | 195 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
| ... | ... | |
| 229 | 225 |
|
| 230 | 226 |
d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
|
| 231 | 227 |
NULL, NULL); |
| 232 |
d->config[0x00] = 0x6b; // vendor_id : Apple |
|
| 233 |
d->config[0x01] = 0x10; |
|
| 234 |
d->config[0x02] = 0x20; // device_id |
|
| 235 |
d->config[0x03] = 0x00; |
|
| 228 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
|
| 229 |
pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP); |
|
| 236 | 230 |
d->config[0x08] = 0x00; // revision |
| 237 | 231 |
d->config[0x0A] = 0x00; // class_sub = pci host |
| 238 | 232 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
| ... | ... | |
| 254 | 248 |
|
| 255 | 249 |
d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
|
| 256 | 250 |
3, 11 << 3, NULL, NULL); |
| 257 |
d->config[0x00] = 0x6b; // vendor_id : Apple |
|
| 258 |
d->config[0x01] = 0x10; |
|
| 259 |
d->config[0x02] = 0x1E; // device_id |
|
| 260 |
d->config[0x03] = 0x00; |
|
| 251 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); |
|
| 252 |
pci_config_set_device_id(d->config, 0x001E); // device_id |
|
| 261 | 253 |
d->config[0x08] = 0x00; // revision |
| 262 | 254 |
d->config[0x0A] = 0x00; // class_sub = pci host |
| 263 | 255 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
| b/hw/usb-ohci.c | ||
|---|---|---|
| 1671 | 1671 |
void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn) |
| 1672 | 1672 |
{
|
| 1673 | 1673 |
OHCIPCIState *ohci; |
| 1674 |
int vid = 0x106b; |
|
| 1675 |
int did = 0x003f; |
|
| 1676 | 1674 |
|
| 1677 | 1675 |
ohci = (OHCIPCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci), |
| 1678 | 1676 |
devfn, NULL, NULL); |
| ... | ... | |
| 1681 | 1679 |
return; |
| 1682 | 1680 |
} |
| 1683 | 1681 |
|
| 1684 |
ohci->pci_dev.config[0x00] = vid & 0xff; |
|
| 1685 |
ohci->pci_dev.config[0x01] = (vid >> 8) & 0xff; |
|
| 1686 |
ohci->pci_dev.config[0x02] = did & 0xff; |
|
| 1687 |
ohci->pci_dev.config[0x03] = (did >> 8) & 0xff; |
|
| 1682 |
pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE); |
|
| 1683 |
pci_config_set_device_id(ohci->pci_dev.config, 0x003f); // device_id |
|
| 1688 | 1684 |
ohci->pci_dev.config[0x09] = 0x10; /* OHCI */ |
| 1689 | 1685 |
ohci->pci_dev.config[0x0a] = 0x3; |
| 1690 | 1686 |
ohci->pci_dev.config[0x0b] = 0xc; |
| b/hw/usb-uhci.c | ||
|---|---|---|
| 1080 | 1080 |
"USB-UHCI", sizeof(UHCIState), |
| 1081 | 1081 |
devfn, NULL, NULL); |
| 1082 | 1082 |
pci_conf = s->dev.config; |
| 1083 |
pci_conf[0x00] = 0x86; |
|
| 1084 |
pci_conf[0x01] = 0x80; |
|
| 1085 |
pci_conf[0x02] = 0x20; |
|
| 1086 |
pci_conf[0x03] = 0x70; |
|
| 1083 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
|
| 1084 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2); |
|
| 1087 | 1085 |
pci_conf[0x08] = 0x01; // revision number |
| 1088 | 1086 |
pci_conf[0x09] = 0x00; |
| 1089 | 1087 |
pci_conf[0x0a] = 0x03; |
| ... | ... | |
| 1117 | 1115 |
"USB-UHCI", sizeof(UHCIState), |
| 1118 | 1116 |
devfn, NULL, NULL); |
| 1119 | 1117 |
pci_conf = s->dev.config; |
| 1120 |
pci_conf[0x00] = 0x86; |
|
| 1121 |
pci_conf[0x01] = 0x80; |
|
| 1122 |
pci_conf[0x02] = 0x12; |
|
| 1123 |
pci_conf[0x03] = 0x71; |
|
| 1118 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
|
| 1119 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2); |
|
| 1124 | 1120 |
pci_conf[0x08] = 0x01; // revision number |
| 1125 | 1121 |
pci_conf[0x09] = 0x00; |
| 1126 | 1122 |
pci_conf[0x0a] = 0x03; |
| b/hw/versatile_pci.c | ||
|---|---|---|
| 124 | 124 |
isa_mmio_init(base + 0x03000000, 0x00100000); |
| 125 | 125 |
} |
| 126 | 126 |
|
| 127 |
d->config[0x00] = 0xee; // vendor_id |
|
| 128 |
d->config[0x01] = 0x10; |
|
| 127 |
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_XILINX); |
|
| 129 | 128 |
/* Both boards have the same device ID. Oh well. */ |
| 130 |
d->config[0x02] = 0x00; // device_id |
|
| 131 |
d->config[0x03] = 0x03; |
|
| 129 |
pci_config_set_device_id(d->config, 0x0300); // device_id |
|
| 132 | 130 |
d->config[0x04] = 0x00; |
| 133 | 131 |
d->config[0x05] = 0x00; |
| 134 | 132 |
d->config[0x06] = 0x20; |
| b/hw/vga.c | ||
|---|---|---|
| 2512 | 2512 |
s->pci_dev = &d->dev; |
| 2513 | 2513 |
|
| 2514 | 2514 |
pci_conf = d->dev.config; |
| 2515 |
pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID) |
|
| 2516 |
pci_conf[0x01] = 0x12; |
|
| 2517 |
pci_conf[0x02] = 0x11; |
|
| 2518 |
pci_conf[0x03] = 0x11; |
|
| 2515 |
pci_config_set_vendor_id(pci_conf, 0x1234); // dummy VGA (same as Bochs ID) |
|
| 2516 |
pci_config_set_device_id(pci_conf, 0x1111); |
|
| 2519 | 2517 |
pci_conf[0x0a] = 0x00; // VGA controller |
| 2520 | 2518 |
pci_conf[0x0b] = 0x03; |
| 2521 | 2519 |
pci_conf[0x0e] = 0x00; // header_type |
| b/hw/virtio.c | ||
|---|---|---|
| 830 | 830 |
vdev->vq = qemu_mallocz(sizeof(VirtQueue) * VIRTIO_PCI_QUEUE_MAX); |
| 831 | 831 |
|
| 832 | 832 |
config = pci_dev->config; |
| 833 |
config[0x00] = vendor & 0xFF; |
|
| 834 |
config[0x01] = (vendor >> 8) & 0xFF; |
|
| 835 |
config[0x02] = device & 0xFF; |
|
| 836 |
config[0x03] = (device >> 8) & 0xFF; |
|
| 833 |
pci_config_set_vendor_id(config, vendor); |
|
| 834 |
pci_config_set_device_id(config, device); |
|
| 837 | 835 |
|
| 838 | 836 |
config[0x08] = VIRTIO_PCI_ABI_VERSION; |
| 839 | 837 |
|
| b/hw/vmware_vga.c | ||
|---|---|---|
| 1204 | 1204 |
iomemtype); |
| 1205 | 1205 |
} |
| 1206 | 1206 |
|
| 1207 |
#define PCI_VENDOR_ID_VMWARE 0x15ad |
|
| 1208 |
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 |
|
| 1209 |
#define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 |
|
| 1210 |
#define PCI_DEVICE_ID_VMWARE_NET 0x0720 |
|
| 1211 |
#define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 |
|
| 1212 |
#define PCI_DEVICE_ID_VMWARE_IDE 0x1729 |
|
| 1213 | 1207 |
#define PCI_CLASS_BASE_DISPLAY 0x03 |
| 1214 | 1208 |
#define PCI_CLASS_SUB_VGA 0x00 |
| 1215 | 1209 |
#define PCI_CLASS_HEADERTYPE_00h 0x00 |
| ... | ... | |
| 1223 | 1217 |
s = (struct pci_vmsvga_state_s *) |
| 1224 | 1218 |
pci_register_device(bus, "QEMUware SVGA", |
| 1225 | 1219 |
sizeof(struct pci_vmsvga_state_s), -1, 0, 0); |
| 1226 |
s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff; |
|
| 1227 |
s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8; |
|
| 1228 |
s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff; |
|
| 1229 |
s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8; |
|
| 1220 |
pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE); |
|
| 1221 |
pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID); |
|
| 1230 | 1222 |
s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */ |
| 1231 | 1223 |
s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA; |
| 1232 | 1224 |
s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY; |
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