tcg-sparc: Fix brcond2
Much the same problem as recently fixed for hppa.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-sparc: Implement movcond.
tcg: Remove redundant pointer from TCGContext
The pointer entry 'temps' always refers to the array entry 'static_temps'.Removing the pointer and renaming 'static_temps' to 'temps' reduces thesize of TCGContext (4 or 8 byte) and allows better code generation....
Merge branch 'trivial-patches' of git://github.com/stefanha/qemu
tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS
There are several cases that can be handled easier inside bothtranslators and code generators if we have out-of-band valuesfor conditions. It's easy enough to handle ALWAYS and NEVER inthe natural way inside the tcg middle-end....
tcg: Add tcg_high_cond
The table that was recently added for hppa is generally usable.And with the renumbering of the TCG_COND constants it's not toodifficult to compute rather than have a table.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Add is_unsigned_cond
Before we rearrange the TCG_COND enumeration, add a predicate forthe (single) use of comparisons vs TCGCond.
tcg: remove obsolete jmp op
The TCG jmp operation doesn't really make sense in the QEMU context, itis unused, it is not implemented by some targets, and it is wronglyimplemented by some others.
This patch simply removes it.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg/arm: Use tcg_out_mov_reg rather than inline equivalent code
Use the recently introduced tcg_out_mov_reg() function rather thanthe equivalent inline code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>...
tci: Fix for AREG0 free mode
Support for helper functions with 5 arguments was missingin the code generator and in the interpreter.
There is no need to pass the constant TCG_AREG0 from thecode generator to the interpreter. Remove that code forthe INDEX_op_qemu_st* opcodes....
tcg/i386: fix build with -march < i686
The movcond_i32 op has to be protected with TCG_TARGET_HAS_movcond_i32to fix the build with -march < i686.
Thanks to Richard Henderson for the hint.
Reported-by: Alex Barcelo <abarcelo@ac.upc.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Sanity check goto_tb input
Checking that we don't try for idx != [01] is trivial. Checkingthat we don't issue more than one of any index requires a tadmore data and some ifdefs protecting that new variable.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg: Streamline movcond_i64 using 32-bit arithmetic
Avoiding 64-bit arithmetic (outside of the compare) reduces thegenerated op count from 15 to 12, and the generated code size oni686 from 105 to 88 bytes.
tcg: Streamline movcond_i64 using movcond_i32
When movcond_i32 is available we can further reduce the generatedop count from 12 to 6, and the generated code size on i686 from88 to 74 bytes.
tcg/mips: fix MIPS32 detection
Fix the MIPS32 cpu detection so that it also works with-march=octeon. Thanks to Andrew Pinski for the hint.
Cc: Andrew Pinski <apinski@cavium.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Adjust descriptions of *cond opcodes
The README file documented the operand ordering of the tcg_gen_*functions. Since we're documenting opcodes here, use the trueoperand ordering.
Signed-off-by: Richard Henderson <rth@twiddle.net>Cc: malc <av1474@comtv.ru>...
tcg: Emit ANDI as EXTU for appropriate constants
Note that andi_i64 failed to perform even the minimaloptimizations promised by the README.
tcg: Optimize initial inputs for ori_i64
Copy the same optimizations from ori_i32.
tcg: Emit XORI as NOT for appropriate constants
Note that xori_i64 failed to perform even the minimaloptimizations promised by the README.
tcg: Implement concat*_i64 with deposit_i64
For tcg_gen_concat_i32_i64 we only use deposit if the host supports it.For tcg_gen_concat32_i64 even if the host does not, as we get identicalcode before and after.
Note that this relies on the ANDI -> EXTU patch for the identity claim....
tcg: Add tcg_debug_assert
Like the C assert macro, except only enabled for CONFIG_DEBUG_TCG,and without having to set _NDEBUG and disable all other asserts atthe same time.
The use of __builtin_unreachable (when available) gives the compilerthe same information, which may (or may not) help it optimize better....
tcg: Sanity check deposit inputs
Given these are constants, checking once here means everythingafter can assume they're correct.
Merge branch 'tcg-sparc' of git://repo.or.cz/qemu/rth
Revert "tcg/mips"
This reverts commit ad49d1f75115663731bfe06dec61eed6775526ad.
This commit was not supposed to be pushed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/ppc32: Implement movcond32
Thanks to Richard Henderson
Signed-off-by: malc <av1474@comtv.ru>
tcg/mips
tcg/i386: Add shortcuts for registers used in L constraint
While 64 bit hosts use the first three registers which are also usedas function input parameters, 32 bit hosts use TCG_REG_EAX andTCG_REG_EDX which are not used in parameter passing.
After defining new register macros for the registers used in L...
tcg/i386: Remove unused registers from tcg_target_call_iarg_regs
32 bit x86 hosts don't need registers for helper function argumentsbecause they use the default stack based calling convention.
Removing the registers allows simpler code for functiontcg_target_get_call_iarg_regs_count....
tcg: Remove tcg_target_get_call_iarg_regs_count
The TCG targets no longer need individual implementations.
Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,'flags' is no longer used in tcg_target_get_call_iarg_regs_count.
The remaining tcg_target_get_call_iarg_regs_count is trivial and only...
tcg-hppa: Implement movcond
tcg/README: document tcg_gen_goto_tb restrictions
Seehttp://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.htmlfor the whole story.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
w64: Fix TCG helper functions with 5 arguments
TCG uses 6 registers for function arguments on 64 bit Linux hosts,but only 4 registers on W64 hosts.
Commit 2999a0b20074a7e4a58f56572bb1436749368f59 increased the numberof arguments for some important helper functions from 4 to 5...
tcg/optimize: rework copy progagation
The copy propagation pass tries to keep track what is a copy of whatand what has copy of what, and in addition it keep a circular list ofof all the copies. Unfortunately this doesn't fully work: a mov froma temp which has a state "COPY" changed it into a state "HAS_COPY"....
tcg/optimize: do copy propagation for all operations
It is possible to due copy propagation for all operations, even the onethat have side effects or clobber arguments (it only concerns inputarguments). That said, the call operation should be handled differently...
tcg/optimize: optimize "op r, a, a => mov r, a"
Now that we can easily detect all copies, we can optimize the"op r, a, a => mov r, a" case a bit more.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/optimize: optimize "op r, a, a => movi r, 0"
Now that it's possible to detect copies, we can optimize the casethe "op r, a, a => movi r, 0". This helps in the computation ofoverflow flags when one of the two args is 0.
tcg/optimize: further optimize brcond/movcond/setcond
When both argument of brcond/movcond/setcond are the same or when oneof the two values is a constant equal to zero, it's possible to dofurther optimizations.
tcg/optimize: prefer the "op a, a, b" form for commutative ops
The "op a, a, b" form is better handled on non-RISC host than the "opa, b, a" form, so swap the arguments to this form when possible, andwhen b is not a constant.
This reduces the number of generated instructions by a tiny bit....
tcg: remove #ifdef #endif around TCGOpcode tests
Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don'tneed to #ifdef #endif the one that are available only on some targets.This makes the code easier to read.
tcg/optimize: add constant folding for deposit
tcg/mips: optimize brcond arg, 0
MIPS has some conditional branch instructions when comparing with zero.Use them.
tcg/mips: optimize bswap{16,16s,32} on MIPS32R2
bswap operations can be optimized on MIPS32 Release 2 using the ROTR,WSBH and SEH instructions. We can't use the non-R2 code to implement theops due to registers constraints, so don't define the corresponding...
tcg/mips: implement rotl/rotr ops on MIPS32R2
rotr operations can be optimized on MIPS32 Release 2 using the ROTR andROTRV instructions. Also implemented rotl operations by subtracting theshift from 32.
tcg/mips: implement deposit op on MIPS32R2
deposit operations can be optimized on MIPS32 Release 2 using the INSinstruction.
tcg/mips: implement movcond op on MIPS32R2
movcond operation can be implemented on MIPS32 Release 2 using the MOVN,MOVZ, SLT and SLTU instructions.
tcg/optimize: remove TCG_TEMP_ANY
TCG_TEMP_ANY has no different meaning than TCG_TEMP_UNDEF, so usethe later instead.
tcg/optimize: check types in copy propagation
The copy propagation doesn't check the types of the temps during copypropagation. However TCG is using the mov_i32 for the i64 to i32conversion and thus the two are not equivalent.
With this patch tcg_opt_gen_mov() doesn't consider two temps of...
tcg-mips: fix wrong usage of 'Z' constraint
The 'Z' constraint has been introduced to map the zero register. Howeverwhen the op also accept a constant, there is no point to accept the zeroregister in addition.
tcg/mips: kill warnings in user mode
Recent versions of GCC emit warnings when compiling user mode targets.Kill them by reordering a bit the #ifdef.
tcg/mips: use TCGArg or TCGReg instead of int
Instead of int, use the correct TCGArg and TCGReg type: TCGReg whenrepresenting a TCG target register, TCGArg when representing the latteror a constant.
tcg/mips: don't use global pointer
Don't use the global pointer in TCG, in case helpers try access globalvariables.
tcg/mips: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCGtemps.
tcg-sparc: Preserve branch destinations during retranslation
Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg-sparc: Add %g/%o registers to alloc_order
tcg-sparc: Fix and enable direct TB chaining.
tcg-sparc: Clean up cruft stemming from attempts to use global registers.
Don't use -ffixed-gN. Don't link statically. Don't save/restoreAREG0 around calls. Don't allocate space on the stack for AREG0 save.
tcg-sparc: Mask shift immediates to avoid illegal insns.
The xtensa-test image generates a sra_i32 with count 0x40.Whether this is accident of tcg constant propagation ororiginating directly from the instruction stream is immaterial.
tcg-sparc: Use defines for temporaries.
And change from %i4/%i5 to %g1/%o7 to remove a v8plus fixme.
tcg-sparc: Support GUEST_BASE.
tcg-sparc: Change AREG0 in generated code to %i0.
We can now move the TCG variable from %g56 to a call-preservedwindowed register.
tcg-sparc: Fix qemu_ld/st to handle 32-bit host.
At the same time, split out the tlb load logic to a new function.Fixes the cases of two data registers and two address registers.Fixes the signature of, and adds missing, qemu_ld/st opcodes.
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Current code doesn't actually work in 32-bit mode at all. Sinceno one really noticed, drop the complication of v7 and v8 cpus.Eliminate the --sparc_cpu configure option and standardize macro...
tcg-sparc: Hack in qemu_ld/st64 for 32-bit.
Not actually implemented, but at least we avoid the tcg assert at startup.
tcg-sparc: Fix ADDX opcode.
tcg-hppa: Fix broken load/store helpers
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helperswas not respecting the ABI requirement for 64-bit valuesbeing aligned in registers.
Mirror the ARM port in use of helper functions to marshalarguments into the correct registers....
tcg-i386: Implement movcond
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Optimize movcond for constant comparisons
tcg: Optimize two-address commutative operations
While swapping constants to the second operand, swapsources matching destinations to the first operand.
tcg: Fix !USE_DIRECT_JUMP
Commit 6375e09e changed the type of TranslationBlock.tb_next,but failed to change the type of TCGContext.tb_next.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-hppa: Fix brcond2 and setcond2
Neither of these functions were performing double-wordcompares properly.
tcg: Introduce movcond
Implemented with setcond if the target does not providethe optional opcode.
tcg/optimize: fix end of basic block detection
Commit e31b0a7c050711884ad570fe73df806520953618 fixed copy propagation on32-bit host by restricting the copy between different types. This was thewrong fix.
The real problem is that the all temps states should be reset at the end...
revert "TCG: fix copy propagation"
Given the copy propagation breakage on 32-bit hosts has been fixedcommit e31b0a7c050711884ad570fe73df806520953618 can be reverted.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/i386: allow constants in load/store ops
On x86, it is possible to move a constant value to memory. Add code tohandle a constant argument to load/store ops.
tcg: mark set_label with TCG_OPF_BB_END flag
set_label is effectively the end of a basic block, as no optimizationcan be made accross it. It was treated as such in the liveness analysiscode, but as a special case.
Mark it with TCG_OPF_BB_END flag so that this information can be used...
Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
Remove dyngen-exec.h and all references to it. Although included byhw/spapr_hcall.c, it does not seem to use it....
tcg/optimize: fix if/else/break coding style
optimizer.c contains some cases were the break is appearing in both theif and the else parts. Fix that by moving it to the outer part. Alsomove some common code there.
tcg/optimize: add constant folding for brcond
tcg/optimize: add constant folding for setcond
tcg/optimize: swap brcond/setcond arguments when possible
brcond and setcond ops are not commutative, but it's easy to compute thenew condition after swapping the arguments. Try to always put the constantargument in second position like for commutative ops, to help backends to...
tcg/optimize: simplify shift/rot r, 0, a => movi r, 0 cases
shift/rot r, 0, a is equivalent to movi r, 0.
tcg/optimize: simplify and r, a, 0 cases
and r, a, 0 is equivalent to a movi r, 0.
tcg/optimize: simplify or/xor r, a, 0 cases
or/xor r, a, 0 is equivalent to a mov r, a.
tcg/optimize: split expression simplification
Split expression simplification in multiple parts so that a given opcan appear multiple times. This patch should not change anything.
tcg: improve profiler
Now that there are two passes of optimization (optimize.c, liveness)there is no point of outputing the statistics of the liveness partonly. Update the code to take into account both optimizations.
tcg/s390: fix ld/st with CONFIG_TCG_PASS_AREG0
The load/store slow path has been broken in e141ab52d:- We need to move 4 registers for store functions and 3 registers for load functions and not the reverse.- According to the s390x calling convention the arguments of a function...
tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 code
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers wasbroken in that it did not respect the ABI requirement that 64bit values were passed in even-odd register pairs. The simplestway to fix this is to implement some new utility functions...
tcg/ia64: fix and optimize ld/st slow path
Store slow path has been broken in e141ab52d:- the arguments are shifted before the last one (mem_index) is written.- the shift is done for both slow and fast paths.
Fix that. Also optimize a bit by bundling the move together. This still...
tcg/ia64: fix prologue/epilogue
Prologue and epilogue code has been broken in cea5f9a28.
tcg/arm: Fix broken CONFIG_TCG_PASS_AREG0 code
tci: don't write zero for reloc in tci_out_label
If tci_out_label is called in the context of tcg_gen_code_search_pc, wecould be overwriting an already patched relocation with zero -- and notrepatch it because the set_label is past search_pc, causing a QEMU crash...
TCG: Fix compile breakage in tcg_dump_ops
Commit eeacee4d865 changed the syntax of tcg_dump_ops, but didn't convertall users (notably missing the ppc ones) to it. Fix them to the new syntax.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: malc <av1474@comtv.ru>
qemu-log: cleanup
Don't use global variables directly but via accessor functions. Rename globals.
Convert macros to functions, add GCC format attributes.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/ppc: Handle _CALL_DARWIN being undefined on Darwin
powerpc-apple-darwin9-gcc-4.2.1 (GCC) 4.2.1 (Apple Inc. build 5577)does not define _CALL_DARWIN, leading to unexpected behavior w.r.t.register clobbering and stack frame layout.
Since _CALL_DARWIN is a reserved identifier, define a custom...
tcg/ppc64: Don't hardcode register numbers for qemu_ld/st
Facilitates using r3 for prepended AREG0.
Signed-off-by: Andreas F?rber <afaerber@suse.de>Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc64: Fix CONFIG_TCG_PASS_AREG0
In qemu_ld/st load the registers for the helper calls directly ratherthan rotating them around afterwards for AREG0.
Also clobber the additional register.
tcg/ppc: Don't hardcode register numbers
Also assure i64 alignment where necessary.
Alignment code optimization suggested by malc.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
tcg/ppc: Clobber r5 for 64-bit qemu_ld
This accounts for the additional addr_reg2 register.
tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode
Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,based on patches by malc.
Also adjust the registers clobbered, based on patch by Alex.
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Alexander Graf <agraf@suse.de>...
tcg/ppc: Do not overwrite lower address word on Darwin and AIX
For targets where TARGET_LONG_BITS != 32, i.e. 64-bit guests,addr_reg is moved to r4. For hosts without TCG_TARGET_CALL_ALIGN_ARGSeither data_reg2 or data_reg or a masked version thereof would overwrite...