189 |
189 |
|
190 |
190 |
static void spr_write_ibatu (void *opaque, int sprn)
|
191 |
191 |
{
|
192 |
|
DisasContext *ctx = opaque;
|
193 |
|
|
194 |
192 |
gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
|
195 |
|
GEN_STOP(ctx);
|
196 |
193 |
}
|
197 |
194 |
|
198 |
195 |
static void spr_write_ibatu_h (void *opaque, int sprn)
|
199 |
196 |
{
|
200 |
|
DisasContext *ctx = opaque;
|
201 |
|
|
202 |
197 |
gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
|
203 |
|
GEN_STOP(ctx);
|
204 |
198 |
}
|
205 |
199 |
|
206 |
200 |
static void spr_write_ibatl (void *opaque, int sprn)
|
207 |
201 |
{
|
208 |
|
DisasContext *ctx = opaque;
|
209 |
|
|
210 |
202 |
gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
|
211 |
|
GEN_STOP(ctx);
|
212 |
203 |
}
|
213 |
204 |
|
214 |
205 |
static void spr_write_ibatl_h (void *opaque, int sprn)
|
215 |
206 |
{
|
216 |
|
DisasContext *ctx = opaque;
|
217 |
|
|
218 |
207 |
gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
|
219 |
|
GEN_STOP(ctx);
|
220 |
208 |
}
|
221 |
209 |
|
222 |
210 |
/* DBAT0U...DBAT7U */
|
... | ... | |
233 |
221 |
|
234 |
222 |
static void spr_write_dbatu (void *opaque, int sprn)
|
235 |
223 |
{
|
236 |
|
DisasContext *ctx = opaque;
|
237 |
|
|
238 |
224 |
gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
|
239 |
|
GEN_STOP(ctx);
|
240 |
225 |
}
|
241 |
226 |
|
242 |
227 |
static void spr_write_dbatu_h (void *opaque, int sprn)
|
243 |
228 |
{
|
244 |
|
DisasContext *ctx = opaque;
|
245 |
|
|
246 |
229 |
gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
|
247 |
|
GEN_STOP(ctx);
|
248 |
230 |
}
|
249 |
231 |
|
250 |
232 |
static void spr_write_dbatl (void *opaque, int sprn)
|
251 |
233 |
{
|
252 |
|
DisasContext *ctx = opaque;
|
253 |
|
|
254 |
234 |
gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
|
255 |
|
GEN_STOP(ctx);
|
256 |
235 |
}
|
257 |
236 |
|
258 |
237 |
static void spr_write_dbatl_h (void *opaque, int sprn)
|
259 |
238 |
{
|
260 |
|
DisasContext *ctx = opaque;
|
261 |
|
|
262 |
239 |
gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
|
263 |
|
GEN_STOP(ctx);
|
264 |
240 |
}
|
265 |
241 |
|
266 |
242 |
/* SDR1 */
|
... | ... | |
271 |
247 |
|
272 |
248 |
static void spr_write_sdr1 (void *opaque, int sprn)
|
273 |
249 |
{
|
274 |
|
DisasContext *ctx = opaque;
|
275 |
|
|
276 |
250 |
gen_op_store_sdr1();
|
277 |
|
GEN_STOP(ctx);
|
278 |
251 |
}
|
279 |
252 |
|
280 |
253 |
/* 64 bits PowerPC specific SPRs */
|
... | ... | |
291 |
264 |
DisasContext *ctx = opaque;
|
292 |
265 |
|
293 |
266 |
gen_op_store_asr();
|
294 |
|
GEN_STOP(ctx);
|
295 |
267 |
}
|
296 |
268 |
#endif
|
297 |
269 |
#endif
|
... | ... | |
329 |
301 |
|
330 |
302 |
static void spr_write_601_ubatu (void *opaque, int sprn)
|
331 |
303 |
{
|
332 |
|
DisasContext *ctx = opaque;
|
333 |
|
|
334 |
304 |
gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
|
335 |
|
GEN_STOP(ctx);
|
336 |
305 |
}
|
337 |
306 |
|
338 |
307 |
static void spr_write_601_ubatl (void *opaque, int sprn)
|
339 |
308 |
{
|
340 |
|
DisasContext *ctx = opaque;
|
341 |
|
|
342 |
309 |
gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
|
343 |
|
GEN_STOP(ctx);
|
344 |
310 |
}
|
345 |
311 |
#endif
|
346 |
312 |
|
... | ... | |
367 |
333 |
|
368 |
334 |
static void spr_write_40x_sler (void *opaque, int sprn)
|
369 |
335 |
{
|
370 |
|
DisasContext *ctx = opaque;
|
371 |
|
|
372 |
336 |
gen_op_store_40x_sler();
|
373 |
|
/* We must stop the translation as we may have changed
|
374 |
|
* some regions endianness
|
375 |
|
*/
|
376 |
|
GEN_STOP(ctx);
|
377 |
337 |
}
|
378 |
338 |
|
379 |
339 |
static void spr_write_booke_tcr (void *opaque, int sprn)
|
... | ... | |
397 |
357 |
|
398 |
358 |
static void spr_write_403_pbr (void *opaque, int sprn)
|
399 |
359 |
{
|
400 |
|
DisasContext *ctx = opaque;
|
401 |
|
|
402 |
360 |
gen_op_store_403_pb(sprn - SPR_403_PBL1);
|
403 |
|
GEN_STOP(ctx);
|
404 |
361 |
}
|
405 |
362 |
|
406 |
363 |
static void spr_write_pir (void *opaque, int sprn)
|