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/*
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 *  MIPS emulation micro-operations for qemu.
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 * 
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 *  Copyright (c) 2004-2005 Jocelyn Mayer
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 *  Copyright (c) 2006 Marius Groeger (FPU operations)
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 *  Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include "config.h"
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#include "exec.h"
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#ifndef CALL_FROM_TB0
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#define CALL_FROM_TB0(func) func()
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#endif
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#ifndef CALL_FROM_TB1
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#define CALL_FROM_TB1(func, arg0) func(arg0)
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#endif
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#ifndef CALL_FROM_TB1_CONST16
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#define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
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#endif
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#ifndef CALL_FROM_TB2
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#define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
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#endif
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#ifndef CALL_FROM_TB2_CONST16
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#define CALL_FROM_TB2_CONST16(func, arg0, arg1)     \
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        CALL_FROM_TB2(func, arg0, arg1)
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#endif
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#ifndef CALL_FROM_TB3
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#define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
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#endif
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#ifndef CALL_FROM_TB4
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#define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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        func(arg0, arg1, arg2, arg3)
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#endif
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#define REG 1
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#include "op_template.c"
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#undef REG
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#define REG 2
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#include "op_template.c"
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#undef REG
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#define REG 3
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#include "op_template.c"
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#undef REG
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#define REG 4
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#include "op_template.c"
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#undef REG
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#define REG 5
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#include "op_template.c"
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#undef REG
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#define REG 6
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#include "op_template.c"
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#undef REG
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#define REG 7
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#include "op_template.c"
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#undef REG
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#define REG 8
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#include "op_template.c"
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#undef REG
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#define REG 9
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#include "op_template.c"
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#undef REG
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#define REG 10
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#include "op_template.c"
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#undef REG
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#define REG 11
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#include "op_template.c"
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#undef REG
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#define REG 12
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#include "op_template.c"
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#undef REG
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#define REG 13
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#include "op_template.c"
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#undef REG
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#define REG 14
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#include "op_template.c"
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#undef REG
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#define REG 15
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#include "op_template.c"
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#undef REG
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#define REG 16
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#include "op_template.c"
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#undef REG
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#define REG 17
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#include "op_template.c"
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#undef REG
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#define REG 18
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#include "op_template.c"
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#undef REG
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#define REG 19
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#include "op_template.c"
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#undef REG
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#define REG 20
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#include "op_template.c"
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#undef REG
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#define REG 21
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#include "op_template.c"
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#undef REG
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#define REG 22
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#include "op_template.c"
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#undef REG
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#define REG 23
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#include "op_template.c"
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#undef REG
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#define REG 24
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#include "op_template.c"
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#undef REG
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#define REG 25
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#include "op_template.c"
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#undef REG
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#define REG 26
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#include "op_template.c"
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#undef REG
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#define REG 27
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#include "op_template.c"
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#undef REG
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#define REG 28
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#include "op_template.c"
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#undef REG
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#define REG 29
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#include "op_template.c"
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#undef REG
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#define REG 30
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#include "op_template.c"
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#undef REG
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#define REG 31
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#include "op_template.c"
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#undef REG
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#define TN
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#include "op_template.c"
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#undef TN
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#define FREG 0
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#include "fop_template.c"
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#undef FREG
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#define FREG 1
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#include "fop_template.c"
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#undef FREG
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#define FREG 2
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#include "fop_template.c"
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#undef FREG
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#define FREG 3
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#include "fop_template.c"
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#undef FREG
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#define FREG 4
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#include "fop_template.c"
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#undef FREG
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#define FREG 5
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#include "fop_template.c"
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#undef FREG
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#define FREG 6
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#include "fop_template.c"
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#undef FREG
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#define FREG 7
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#include "fop_template.c"
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#undef FREG
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#define FREG 8
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#include "fop_template.c"
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#undef FREG
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#define FREG 9
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#include "fop_template.c"
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#undef FREG
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#define FREG 10
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#include "fop_template.c"
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#undef FREG
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#define FREG 11
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#include "fop_template.c"
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#undef FREG
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#define FREG 12
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#include "fop_template.c"
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#undef FREG
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#define FREG 13
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#include "fop_template.c"
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#undef FREG
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#define FREG 14
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#include "fop_template.c"
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#undef FREG
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#define FREG 15
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#include "fop_template.c"
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#undef FREG
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#define FREG 16
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#include "fop_template.c"
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#undef FREG
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#define FREG 17
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#include "fop_template.c"
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#undef FREG
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#define FREG 18
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#include "fop_template.c"
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#undef FREG
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#define FREG 19
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#include "fop_template.c"
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#undef FREG
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#define FREG 20
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#include "fop_template.c"
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#undef FREG
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#define FREG 21
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#include "fop_template.c"
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#undef FREG
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#define FREG 22
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#include "fop_template.c"
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#undef FREG
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#define FREG 23
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#include "fop_template.c"
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#undef FREG
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#define FREG 24
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#include "fop_template.c"
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#undef FREG
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#define FREG 25
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#include "fop_template.c"
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#undef FREG
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#define FREG 26
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#include "fop_template.c"
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#undef FREG
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#define FREG 27
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#include "fop_template.c"
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#undef FREG
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#define FREG 28
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#include "fop_template.c"
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#undef FREG
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#define FREG 29
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#include "fop_template.c"
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#undef FREG
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#define FREG 30
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#include "fop_template.c"
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#undef FREG
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#define FREG 31
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#include "fop_template.c"
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#undef FREG
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#define FTN
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#include "fop_template.c"
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#undef FTN
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void op_dup_T0 (void)
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{
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    T2 = T0;
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    RETURN();
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}
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void op_load_HI (void)
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{
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    T0 = env->HI;
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    RETURN();
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}
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void op_store_HI (void)
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{
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    env->HI = T0;
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    RETURN();
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}
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void op_load_LO (void)
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{
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    T0 = env->LO;
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    RETURN();
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}
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void op_store_LO (void)
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{
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    env->LO = T0;
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    RETURN();
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}
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/* Load and store */
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#define MEMSUFFIX _raw
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#include "op_mem.c"
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#undef MEMSUFFIX
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.c"
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#undef MEMSUFFIX
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#define MEMSUFFIX _kernel
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#include "op_mem.c"
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#undef MEMSUFFIX
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#endif
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/* Addresses computation */
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void op_addr_add (void)
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{
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/* For compatibility with 32-bit code, data reference in user mode
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   with Status_UX = 0 should be casted to 32-bit and sign extended.
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   See the MIPS64 PRA manual, section 4.10. */
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#ifdef TARGET_MIPS64
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    if ((env->CP0_Status & (1 << CP0St_UM)) &&
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        !(env->CP0_Status & (1 << CP0St_UX)))
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        T0 = (int64_t)(int32_t)(T0 + T1);
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    else
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#endif
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        T0 += T1;
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    RETURN();
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}
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/* Arithmetic */
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void op_add (void)
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{
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    T0 = (int32_t)((int32_t)T0 + (int32_t)T1);
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    RETURN();
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}
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void op_addo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 + (int32_t)T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_sub (void)
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{
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    T0 = (int32_t)((int32_t)T0 - (int32_t)T1);
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    RETURN();
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}
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void op_subo (void)
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{
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    target_ulong tmp;
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    tmp = (int32_t)T0;
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    T0 = (int32_t)T0 - (int32_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    T0 = (int32_t)T0;
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    RETURN();
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}
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void op_mul (void)
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{
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    T0 = (int32_t)((int32_t)T0 * (int32_t)T1);
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    RETURN();
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}
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#if HOST_LONG_BITS < 64
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void op_div (void)
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{
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    CALL_FROM_TB0(do_div);
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    RETURN();
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}
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#else
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void op_div (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
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        env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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    }
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    RETURN();
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}
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#endif
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void op_divu (void)
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{
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    if (T1 != 0) {
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        env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1);
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        env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1);
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    }
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    RETURN();
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}
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#ifdef TARGET_MIPS64
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/* Arithmetic */
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void op_dadd (void)
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{
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    T0 += T1;
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    RETURN();
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}
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void op_daddo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 += T1;
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    if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) {
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        /* operands of same sign, result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dsub (void)
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{
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    T0 -= T1;
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    RETURN();
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}
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void op_dsubo (void)
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{
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    target_long tmp;
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    tmp = T0;
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    T0 = (int64_t)T0 - (int64_t)T1;
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    if (((tmp ^ T1) & (tmp ^ T0)) >> 63) {
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        /* operands of different sign, first operand and result different sign */
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        CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW);
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    }
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    RETURN();
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}
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void op_dmul (void)
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{
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    T0 = (int64_t)T0 * (int64_t)T1;
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    RETURN();
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}
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/* Those might call libgcc functions.  */
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void op_ddiv (void)
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{
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    do_ddiv();
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    RETURN();
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}
434 c570fd16 ths
435 80c27194 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
436 c570fd16 ths
void op_ddivu (void)
437 c570fd16 ths
{
438 c570fd16 ths
    do_ddivu();
439 c570fd16 ths
    RETURN();
440 c570fd16 ths
}
441 c570fd16 ths
#else
442 c570fd16 ths
void op_ddivu (void)
443 c570fd16 ths
{
444 c570fd16 ths
    if (T1 != 0) {
445 6af0bf9c bellard
        env->LO = T0 / T1;
446 6af0bf9c bellard
        env->HI = T0 % T1;
447 6af0bf9c bellard
    }
448 6af0bf9c bellard
    RETURN();
449 6af0bf9c bellard
}
450 c570fd16 ths
#endif
451 60aa19ab ths
#endif /* TARGET_MIPS64 */
452 6af0bf9c bellard
453 6af0bf9c bellard
/* Logical */
454 6af0bf9c bellard
void op_and (void)
455 6af0bf9c bellard
{
456 6af0bf9c bellard
    T0 &= T1;
457 6af0bf9c bellard
    RETURN();
458 6af0bf9c bellard
}
459 6af0bf9c bellard
460 6af0bf9c bellard
void op_nor (void)
461 6af0bf9c bellard
{
462 6af0bf9c bellard
    T0 = ~(T0 | T1);
463 6af0bf9c bellard
    RETURN();
464 6af0bf9c bellard
}
465 6af0bf9c bellard
466 6af0bf9c bellard
void op_or (void)
467 6af0bf9c bellard
{
468 6af0bf9c bellard
    T0 |= T1;
469 6af0bf9c bellard
    RETURN();
470 6af0bf9c bellard
}
471 6af0bf9c bellard
472 6af0bf9c bellard
void op_xor (void)
473 6af0bf9c bellard
{
474 6af0bf9c bellard
    T0 ^= T1;
475 6af0bf9c bellard
    RETURN();
476 6af0bf9c bellard
}
477 6af0bf9c bellard
478 6af0bf9c bellard
void op_sll (void)
479 6af0bf9c bellard
{
480 5a63bcb2 ths
    T0 = (int32_t)((uint32_t)T0 << T1);
481 6af0bf9c bellard
    RETURN();
482 6af0bf9c bellard
}
483 6af0bf9c bellard
484 6af0bf9c bellard
void op_sra (void)
485 6af0bf9c bellard
{
486 5a63bcb2 ths
    T0 = (int32_t)((int32_t)T0 >> T1);
487 6af0bf9c bellard
    RETURN();
488 6af0bf9c bellard
}
489 6af0bf9c bellard
490 6af0bf9c bellard
void op_srl (void)
491 6af0bf9c bellard
{
492 5a63bcb2 ths
    T0 = (int32_t)((uint32_t)T0 >> T1);
493 6af0bf9c bellard
    RETURN();
494 6af0bf9c bellard
}
495 6af0bf9c bellard
496 7a387fff ths
void op_rotr (void)
497 7a387fff ths
{
498 7a387fff ths
    target_ulong tmp;
499 7a387fff ths
500 7a387fff ths
    if (T1) {
501 5a63bcb2 ths
       tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
502 5a63bcb2 ths
       T0 = (int32_t)((uint32_t)T0 >> T1) | tmp;
503 5a63bcb2 ths
    }
504 7a387fff ths
    RETURN();
505 7a387fff ths
}
506 7a387fff ths
507 6af0bf9c bellard
void op_sllv (void)
508 6af0bf9c bellard
{
509 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
510 6af0bf9c bellard
    RETURN();
511 6af0bf9c bellard
}
512 6af0bf9c bellard
513 6af0bf9c bellard
void op_srav (void)
514 6af0bf9c bellard
{
515 5dc4b744 ths
    T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
516 6af0bf9c bellard
    RETURN();
517 6af0bf9c bellard
}
518 6af0bf9c bellard
519 6af0bf9c bellard
void op_srlv (void)
520 6af0bf9c bellard
{
521 5dc4b744 ths
    T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
522 6af0bf9c bellard
    RETURN();
523 6af0bf9c bellard
}
524 6af0bf9c bellard
525 7a387fff ths
void op_rotrv (void)
526 7a387fff ths
{
527 7a387fff ths
    target_ulong tmp;
528 7a387fff ths
529 7a387fff ths
    T0 &= 0x1F;
530 7a387fff ths
    if (T0) {
531 5dc4b744 ths
       tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
532 5dc4b744 ths
       T0 = (int32_t)((uint32_t)T1 >> T0) | tmp;
533 7a387fff ths
    } else
534 7a387fff ths
       T0 = T1;
535 7a387fff ths
    RETURN();
536 7a387fff ths
}
537 7a387fff ths
538 6af0bf9c bellard
void op_clo (void)
539 6af0bf9c bellard
{
540 6af0bf9c bellard
    int n;
541 6af0bf9c bellard
542 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
543 6af0bf9c bellard
        T0 = 32;
544 6af0bf9c bellard
    } else {
545 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
546 6af0bf9c bellard
            if (!(T0 & (1 << 31)))
547 6af0bf9c bellard
                break;
548 6af0bf9c bellard
            T0 = T0 << 1;
549 6af0bf9c bellard
        }
550 6af0bf9c bellard
        T0 = n;
551 6af0bf9c bellard
    }
552 6af0bf9c bellard
    RETURN();
553 6af0bf9c bellard
}
554 6af0bf9c bellard
555 6af0bf9c bellard
void op_clz (void)
556 6af0bf9c bellard
{
557 6af0bf9c bellard
    int n;
558 6af0bf9c bellard
559 6af0bf9c bellard
    if (T0 == 0) {
560 6af0bf9c bellard
        T0 = 32;
561 6af0bf9c bellard
    } else {
562 6af0bf9c bellard
        for (n = 0; n < 32; n++) {
563 6af0bf9c bellard
            if (T0 & (1 << 31))
564 6af0bf9c bellard
                break;
565 6af0bf9c bellard
            T0 = T0 << 1;
566 6af0bf9c bellard
        }
567 6af0bf9c bellard
        T0 = n;
568 6af0bf9c bellard
    }
569 6af0bf9c bellard
    RETURN();
570 6af0bf9c bellard
}
571 6af0bf9c bellard
572 60aa19ab ths
#ifdef TARGET_MIPS64
573 c570fd16 ths
574 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
575 c570fd16 ths
/* Those might call libgcc functions.  */
576 c570fd16 ths
void op_dsll (void)
577 6af0bf9c bellard
{
578 c570fd16 ths
    CALL_FROM_TB0(do_dsll);
579 c570fd16 ths
    RETURN();
580 6af0bf9c bellard
}
581 6af0bf9c bellard
582 c570fd16 ths
void op_dsll32 (void)
583 6af0bf9c bellard
{
584 c570fd16 ths
    CALL_FROM_TB0(do_dsll32);
585 c570fd16 ths
    RETURN();
586 6af0bf9c bellard
}
587 6af0bf9c bellard
588 c570fd16 ths
void op_dsra (void)
589 6af0bf9c bellard
{
590 c570fd16 ths
    CALL_FROM_TB0(do_dsra);
591 6af0bf9c bellard
    RETURN();
592 6af0bf9c bellard
}
593 6af0bf9c bellard
594 c570fd16 ths
void op_dsra32 (void)
595 6af0bf9c bellard
{
596 c570fd16 ths
    CALL_FROM_TB0(do_dsra32);
597 6af0bf9c bellard
    RETURN();
598 6af0bf9c bellard
}
599 6af0bf9c bellard
600 c570fd16 ths
void op_dsrl (void)
601 6af0bf9c bellard
{
602 c570fd16 ths
    CALL_FROM_TB0(do_dsrl);
603 c570fd16 ths
    RETURN();
604 c570fd16 ths
}
605 6af0bf9c bellard
606 c570fd16 ths
void op_dsrl32 (void)
607 c570fd16 ths
{
608 c570fd16 ths
    CALL_FROM_TB0(do_dsrl32);
609 6af0bf9c bellard
    RETURN();
610 6af0bf9c bellard
}
611 6af0bf9c bellard
612 c570fd16 ths
void op_drotr (void)
613 6af0bf9c bellard
{
614 c570fd16 ths
    CALL_FROM_TB0(do_drotr);
615 c570fd16 ths
    RETURN();
616 c570fd16 ths
}
617 6af0bf9c bellard
618 c570fd16 ths
void op_drotr32 (void)
619 c570fd16 ths
{
620 c570fd16 ths
    CALL_FROM_TB0(do_drotr32);
621 6af0bf9c bellard
    RETURN();
622 6af0bf9c bellard
}
623 6af0bf9c bellard
624 c570fd16 ths
void op_dsllv (void)
625 6af0bf9c bellard
{
626 c570fd16 ths
    CALL_FROM_TB0(do_dsllv);
627 c570fd16 ths
    RETURN();
628 c570fd16 ths
}
629 6af0bf9c bellard
630 c570fd16 ths
void op_dsrav (void)
631 c570fd16 ths
{
632 c570fd16 ths
    CALL_FROM_TB0(do_dsrav);
633 6af0bf9c bellard
    RETURN();
634 6af0bf9c bellard
}
635 6af0bf9c bellard
636 c570fd16 ths
void op_dsrlv (void)
637 6af0bf9c bellard
{
638 c570fd16 ths
    CALL_FROM_TB0(do_dsrlv);
639 c570fd16 ths
    RETURN();
640 c570fd16 ths
}
641 6af0bf9c bellard
642 c570fd16 ths
void op_drotrv (void)
643 c570fd16 ths
{
644 c570fd16 ths
    CALL_FROM_TB0(do_drotrv);
645 6af0bf9c bellard
    RETURN();
646 6af0bf9c bellard
}
647 c570fd16 ths
648 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
649 c570fd16 ths
650 c570fd16 ths
void op_dsll (void)
651 c570fd16 ths
{
652 c570fd16 ths
    T0 = T0 << T1;
653 c570fd16 ths
    RETURN();
654 c570fd16 ths
}
655 c570fd16 ths
656 c570fd16 ths
void op_dsll32 (void)
657 c570fd16 ths
{
658 c570fd16 ths
    T0 = T0 << (T1 + 32);
659 c570fd16 ths
    RETURN();
660 c570fd16 ths
}
661 c570fd16 ths
662 c570fd16 ths
void op_dsra (void)
663 c570fd16 ths
{
664 c570fd16 ths
    T0 = (int64_t)T0 >> T1;
665 c570fd16 ths
    RETURN();
666 c570fd16 ths
}
667 c570fd16 ths
668 c570fd16 ths
void op_dsra32 (void)
669 c570fd16 ths
{
670 c570fd16 ths
    T0 = (int64_t)T0 >> (T1 + 32);
671 c570fd16 ths
    RETURN();
672 c570fd16 ths
}
673 c570fd16 ths
674 c570fd16 ths
void op_dsrl (void)
675 c570fd16 ths
{
676 c570fd16 ths
    T0 = T0 >> T1;
677 c570fd16 ths
    RETURN();
678 c570fd16 ths
}
679 c570fd16 ths
680 c570fd16 ths
void op_dsrl32 (void)
681 c570fd16 ths
{
682 c570fd16 ths
    T0 = T0 >> (T1 + 32);
683 c570fd16 ths
    RETURN();
684 c570fd16 ths
}
685 c570fd16 ths
686 c570fd16 ths
void op_drotr (void)
687 c570fd16 ths
{
688 c570fd16 ths
    target_ulong tmp;
689 c570fd16 ths
690 c570fd16 ths
    if (T1) {
691 c570fd16 ths
       tmp = T0 << (0x40 - T1);
692 c570fd16 ths
       T0 = (T0 >> T1) | tmp;
693 5a63bcb2 ths
    }
694 c570fd16 ths
    RETURN();
695 c570fd16 ths
}
696 c570fd16 ths
697 c570fd16 ths
void op_drotr32 (void)
698 c570fd16 ths
{
699 c570fd16 ths
    target_ulong tmp;
700 c570fd16 ths
701 c570fd16 ths
    if (T1) {
702 c570fd16 ths
       tmp = T0 << (0x40 - (32 + T1));
703 c570fd16 ths
       T0 = (T0 >> (32 + T1)) | tmp;
704 5a63bcb2 ths
    }
705 c570fd16 ths
    RETURN();
706 c570fd16 ths
}
707 c570fd16 ths
708 c570fd16 ths
void op_dsllv (void)
709 c570fd16 ths
{
710 c570fd16 ths
    T0 = T1 << (T0 & 0x3F);
711 c570fd16 ths
    RETURN();
712 c570fd16 ths
}
713 c570fd16 ths
714 c570fd16 ths
void op_dsrav (void)
715 c570fd16 ths
{
716 c570fd16 ths
    T0 = (int64_t)T1 >> (T0 & 0x3F);
717 c570fd16 ths
    RETURN();
718 c570fd16 ths
}
719 c570fd16 ths
720 c570fd16 ths
void op_dsrlv (void)
721 c570fd16 ths
{
722 c570fd16 ths
    T0 = T1 >> (T0 & 0x3F);
723 c570fd16 ths
    RETURN();
724 c570fd16 ths
}
725 c570fd16 ths
726 c570fd16 ths
void op_drotrv (void)
727 c570fd16 ths
{
728 c570fd16 ths
    target_ulong tmp;
729 c570fd16 ths
730 c570fd16 ths
    T0 &= 0x3F;
731 c570fd16 ths
    if (T0) {
732 c570fd16 ths
       tmp = T1 << (0x40 - T0);
733 c570fd16 ths
       T0 = (T1 >> T0) | tmp;
734 c570fd16 ths
    } else
735 c570fd16 ths
       T0 = T1;
736 c570fd16 ths
    RETURN();
737 c570fd16 ths
}
738 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
739 c570fd16 ths
740 c570fd16 ths
void op_dclo (void)
741 c570fd16 ths
{
742 c570fd16 ths
    int n;
743 c570fd16 ths
744 c570fd16 ths
    if (T0 == ~((target_ulong)0)) {
745 c570fd16 ths
        T0 = 64;
746 c570fd16 ths
    } else {
747 c570fd16 ths
        for (n = 0; n < 64; n++) {
748 c570fd16 ths
            if (!(T0 & (1ULL << 63)))
749 c570fd16 ths
                break;
750 c570fd16 ths
            T0 = T0 << 1;
751 c570fd16 ths
        }
752 c570fd16 ths
        T0 = n;
753 c570fd16 ths
    }
754 c570fd16 ths
    RETURN();
755 c570fd16 ths
}
756 c570fd16 ths
757 c570fd16 ths
void op_dclz (void)
758 c570fd16 ths
{
759 c570fd16 ths
    int n;
760 c570fd16 ths
761 c570fd16 ths
    if (T0 == 0) {
762 c570fd16 ths
        T0 = 64;
763 c570fd16 ths
    } else {
764 c570fd16 ths
        for (n = 0; n < 64; n++) {
765 c570fd16 ths
            if (T0 & (1ULL << 63))
766 c570fd16 ths
                break;
767 c570fd16 ths
            T0 = T0 << 1;
768 c570fd16 ths
        }
769 c570fd16 ths
        T0 = n;
770 c570fd16 ths
    }
771 c570fd16 ths
    RETURN();
772 c570fd16 ths
}
773 c570fd16 ths
#endif
774 c570fd16 ths
775 c570fd16 ths
/* 64 bits arithmetic */
776 c570fd16 ths
#if TARGET_LONG_BITS > HOST_LONG_BITS
777 6af0bf9c bellard
void op_mult (void)
778 6af0bf9c bellard
{
779 6af0bf9c bellard
    CALL_FROM_TB0(do_mult);
780 6af0bf9c bellard
    RETURN();
781 6af0bf9c bellard
}
782 6af0bf9c bellard
783 6af0bf9c bellard
void op_multu (void)
784 6af0bf9c bellard
{
785 6af0bf9c bellard
    CALL_FROM_TB0(do_multu);
786 6af0bf9c bellard
    RETURN();
787 6af0bf9c bellard
}
788 6af0bf9c bellard
789 6af0bf9c bellard
void op_madd (void)
790 6af0bf9c bellard
{
791 6af0bf9c bellard
    CALL_FROM_TB0(do_madd);
792 6af0bf9c bellard
    RETURN();
793 6af0bf9c bellard
}
794 6af0bf9c bellard
795 6af0bf9c bellard
void op_maddu (void)
796 6af0bf9c bellard
{
797 6af0bf9c bellard
    CALL_FROM_TB0(do_maddu);
798 6af0bf9c bellard
    RETURN();
799 6af0bf9c bellard
}
800 6af0bf9c bellard
801 6af0bf9c bellard
void op_msub (void)
802 6af0bf9c bellard
{
803 6af0bf9c bellard
    CALL_FROM_TB0(do_msub);
804 6af0bf9c bellard
    RETURN();
805 6af0bf9c bellard
}
806 6af0bf9c bellard
807 6af0bf9c bellard
void op_msubu (void)
808 6af0bf9c bellard
{
809 6af0bf9c bellard
    CALL_FROM_TB0(do_msubu);
810 6af0bf9c bellard
    RETURN();
811 6af0bf9c bellard
}
812 c570fd16 ths
813 c570fd16 ths
#else /* TARGET_LONG_BITS > HOST_LONG_BITS */
814 c570fd16 ths
815 c570fd16 ths
static inline uint64_t get_HILO (void)
816 c570fd16 ths
{
817 c570fd16 ths
    return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO);
818 c570fd16 ths
}
819 c570fd16 ths
820 c570fd16 ths
static inline void set_HILO (uint64_t HILO)
821 c570fd16 ths
{
822 5dc4b744 ths
    env->LO = (int32_t)(HILO & 0xFFFFFFFF);
823 5dc4b744 ths
    env->HI = (int32_t)(HILO >> 32);
824 c570fd16 ths
}
825 c570fd16 ths
826 c570fd16 ths
void op_mult (void)
827 c570fd16 ths
{
828 c570fd16 ths
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
829 c570fd16 ths
    RETURN();
830 c570fd16 ths
}
831 c570fd16 ths
832 c570fd16 ths
void op_multu (void)
833 c570fd16 ths
{
834 c570fd16 ths
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
835 c570fd16 ths
    RETURN();
836 c570fd16 ths
}
837 c570fd16 ths
838 c570fd16 ths
void op_madd (void)
839 c570fd16 ths
{
840 c570fd16 ths
    int64_t tmp;
841 c570fd16 ths
842 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
843 c570fd16 ths
    set_HILO((int64_t)get_HILO() + tmp);
844 c570fd16 ths
    RETURN();
845 c570fd16 ths
}
846 c570fd16 ths
847 c570fd16 ths
void op_maddu (void)
848 c570fd16 ths
{
849 c570fd16 ths
    uint64_t tmp;
850 c570fd16 ths
851 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
852 c570fd16 ths
    set_HILO(get_HILO() + tmp);
853 c570fd16 ths
    RETURN();
854 c570fd16 ths
}
855 c570fd16 ths
856 c570fd16 ths
void op_msub (void)
857 c570fd16 ths
{
858 c570fd16 ths
    int64_t tmp;
859 c570fd16 ths
860 c570fd16 ths
    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
861 c570fd16 ths
    set_HILO((int64_t)get_HILO() - tmp);
862 c570fd16 ths
    RETURN();
863 c570fd16 ths
}
864 c570fd16 ths
865 c570fd16 ths
void op_msubu (void)
866 c570fd16 ths
{
867 c570fd16 ths
    uint64_t tmp;
868 c570fd16 ths
869 c570fd16 ths
    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
870 c570fd16 ths
    set_HILO(get_HILO() - tmp);
871 c570fd16 ths
    RETURN();
872 c570fd16 ths
}
873 c570fd16 ths
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
874 c570fd16 ths
875 60aa19ab ths
#ifdef TARGET_MIPS64
876 c570fd16 ths
void op_dmult (void)
877 c570fd16 ths
{
878 69d35728 ths
    CALL_FROM_TB4(muls64, &(env->HI), &(env->LO), T0, T1);
879 c570fd16 ths
    RETURN();
880 c570fd16 ths
}
881 c570fd16 ths
882 c570fd16 ths
void op_dmultu (void)
883 c570fd16 ths
{
884 69d35728 ths
    CALL_FROM_TB4(mulu64, &(env->HI), &(env->LO), T0, T1);
885 c570fd16 ths
    RETURN();
886 c570fd16 ths
}
887 6af0bf9c bellard
#endif
888 6af0bf9c bellard
889 6af0bf9c bellard
/* Conditional moves */
890 6af0bf9c bellard
void op_movn (void)
891 6af0bf9c bellard
{
892 6af0bf9c bellard
    if (T1 != 0)
893 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
894 6af0bf9c bellard
    RETURN();
895 6af0bf9c bellard
}
896 6af0bf9c bellard
897 6af0bf9c bellard
void op_movz (void)
898 6af0bf9c bellard
{
899 6af0bf9c bellard
    if (T1 == 0)
900 6af0bf9c bellard
        env->gpr[PARAM1] = T0;
901 6af0bf9c bellard
    RETURN();
902 6af0bf9c bellard
}
903 6af0bf9c bellard
904 7a387fff ths
void op_movf (void)
905 7a387fff ths
{
906 7a387fff ths
    if (!(env->fcr31 & PARAM1))
907 5a5012ec ths
        T0 = T1;
908 7a387fff ths
    RETURN();
909 7a387fff ths
}
910 7a387fff ths
911 7a387fff ths
void op_movt (void)
912 7a387fff ths
{
913 7a387fff ths
    if (env->fcr31 & PARAM1)
914 5a5012ec ths
        T0 = T1;
915 7a387fff ths
    RETURN();
916 7a387fff ths
}
917 7a387fff ths
918 6af0bf9c bellard
/* Tests */
919 6af0bf9c bellard
#define OP_COND(name, cond) \
920 6af0bf9c bellard
void glue(op_, name) (void) \
921 6af0bf9c bellard
{                           \
922 6af0bf9c bellard
    if (cond) {             \
923 6af0bf9c bellard
        T0 = 1;             \
924 6af0bf9c bellard
    } else {                \
925 6af0bf9c bellard
        T0 = 0;             \
926 6af0bf9c bellard
    }                       \
927 6af0bf9c bellard
    RETURN();               \
928 6af0bf9c bellard
}
929 6af0bf9c bellard
930 6af0bf9c bellard
OP_COND(eq, T0 == T1);
931 6af0bf9c bellard
OP_COND(ne, T0 != T1);
932 f469b9db ths
OP_COND(ge, (target_long)T0 >= (target_long)T1);
933 6af0bf9c bellard
OP_COND(geu, T0 >= T1);
934 f469b9db ths
OP_COND(lt, (target_long)T0 < (target_long)T1);
935 6af0bf9c bellard
OP_COND(ltu, T0 < T1);
936 f469b9db ths
OP_COND(gez, (target_long)T0 >= 0);
937 f469b9db ths
OP_COND(gtz, (target_long)T0 > 0);
938 f469b9db ths
OP_COND(lez, (target_long)T0 <= 0);
939 f469b9db ths
OP_COND(ltz, (target_long)T0 < 0);
940 6af0bf9c bellard
941 7a387fff ths
/* Branches */
942 c53be334 bellard
void OPPROTO op_goto_tb0(void)
943 c53be334 bellard
{
944 c53be334 bellard
    GOTO_TB(op_goto_tb0, PARAM1, 0);
945 7a387fff ths
    RETURN();
946 c53be334 bellard
}
947 c53be334 bellard
948 c53be334 bellard
void OPPROTO op_goto_tb1(void)
949 c53be334 bellard
{
950 c53be334 bellard
    GOTO_TB(op_goto_tb1, PARAM1, 1);
951 7a387fff ths
    RETURN();
952 c53be334 bellard
}
953 6af0bf9c bellard
954 6af0bf9c bellard
/* Branch to register */
955 6af0bf9c bellard
void op_save_breg_target (void)
956 6af0bf9c bellard
{
957 6af0bf9c bellard
    env->btarget = T2;
958 7a387fff ths
    RETURN();
959 6af0bf9c bellard
}
960 6af0bf9c bellard
961 6af0bf9c bellard
void op_restore_breg_target (void)
962 6af0bf9c bellard
{
963 6af0bf9c bellard
    T2 = env->btarget;
964 7a387fff ths
    RETURN();
965 6af0bf9c bellard
}
966 6af0bf9c bellard
967 6af0bf9c bellard
void op_breg (void)
968 6af0bf9c bellard
{
969 6af0bf9c bellard
    env->PC = T2;
970 6af0bf9c bellard
    RETURN();
971 6af0bf9c bellard
}
972 6af0bf9c bellard
973 6af0bf9c bellard
void op_save_btarget (void)
974 6af0bf9c bellard
{
975 6af0bf9c bellard
    env->btarget = PARAM1;
976 6af0bf9c bellard
    RETURN();
977 6af0bf9c bellard
}
978 6af0bf9c bellard
979 6af0bf9c bellard
/* Conditional branch */
980 6af0bf9c bellard
void op_set_bcond (void)
981 6af0bf9c bellard
{
982 6af0bf9c bellard
    T2 = T0;
983 6af0bf9c bellard
    RETURN();
984 6af0bf9c bellard
}
985 6af0bf9c bellard
986 6af0bf9c bellard
void op_save_bcond (void)
987 6af0bf9c bellard
{
988 6af0bf9c bellard
    env->bcond = T2;
989 6af0bf9c bellard
    RETURN();
990 6af0bf9c bellard
}
991 6af0bf9c bellard
992 6af0bf9c bellard
void op_restore_bcond (void)
993 6af0bf9c bellard
{
994 6af0bf9c bellard
    T2 = env->bcond;
995 6af0bf9c bellard
    RETURN();
996 6af0bf9c bellard
}
997 6af0bf9c bellard
998 c53be334 bellard
void op_jnz_T2 (void)
999 6af0bf9c bellard
{
1000 c53be334 bellard
    if (T2)
1001 c53be334 bellard
        GOTO_LABEL_PARAM(1);
1002 6af0bf9c bellard
    RETURN();
1003 6af0bf9c bellard
}
1004 6af0bf9c bellard
1005 6af0bf9c bellard
/* CP0 functions */
1006 873eb012 ths
void op_mfc0_index (void)
1007 6af0bf9c bellard
{
1008 9c2149c8 ths
    T0 = env->CP0_Index;
1009 873eb012 ths
    RETURN();
1010 873eb012 ths
}
1011 873eb012 ths
1012 873eb012 ths
void op_mfc0_random (void)
1013 873eb012 ths
{
1014 873eb012 ths
    CALL_FROM_TB0(do_mfc0_random);
1015 873eb012 ths
    RETURN();
1016 873eb012 ths
}
1017 873eb012 ths
1018 873eb012 ths
void op_mfc0_entrylo0 (void)
1019 873eb012 ths
{
1020 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo0;
1021 873eb012 ths
    RETURN();
1022 873eb012 ths
}
1023 873eb012 ths
1024 873eb012 ths
void op_mfc0_entrylo1 (void)
1025 873eb012 ths
{
1026 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryLo1;
1027 873eb012 ths
    RETURN();
1028 873eb012 ths
}
1029 873eb012 ths
1030 873eb012 ths
void op_mfc0_context (void)
1031 873eb012 ths
{
1032 9c2149c8 ths
    T0 = (int32_t)env->CP0_Context;
1033 873eb012 ths
    RETURN();
1034 873eb012 ths
}
1035 873eb012 ths
1036 873eb012 ths
void op_mfc0_pagemask (void)
1037 873eb012 ths
{
1038 9c2149c8 ths
    T0 = env->CP0_PageMask;
1039 873eb012 ths
    RETURN();
1040 873eb012 ths
}
1041 873eb012 ths
1042 7a387fff ths
void op_mfc0_pagegrain (void)
1043 7a387fff ths
{
1044 9c2149c8 ths
    T0 = env->CP0_PageGrain;
1045 7a387fff ths
    RETURN();
1046 7a387fff ths
}
1047 7a387fff ths
1048 873eb012 ths
void op_mfc0_wired (void)
1049 873eb012 ths
{
1050 9c2149c8 ths
    T0 = env->CP0_Wired;
1051 873eb012 ths
    RETURN();
1052 873eb012 ths
}
1053 873eb012 ths
1054 7a387fff ths
void op_mfc0_hwrena (void)
1055 7a387fff ths
{
1056 9c2149c8 ths
    T0 = env->CP0_HWREna;
1057 7a387fff ths
    RETURN();
1058 7a387fff ths
}
1059 7a387fff ths
1060 873eb012 ths
void op_mfc0_badvaddr (void)
1061 873eb012 ths
{
1062 9c2149c8 ths
    T0 = (int32_t)env->CP0_BadVAddr;
1063 873eb012 ths
    RETURN();
1064 873eb012 ths
}
1065 873eb012 ths
1066 873eb012 ths
void op_mfc0_count (void)
1067 873eb012 ths
{
1068 873eb012 ths
    CALL_FROM_TB0(do_mfc0_count);
1069 873eb012 ths
    RETURN();
1070 873eb012 ths
}
1071 873eb012 ths
1072 873eb012 ths
void op_mfc0_entryhi (void)
1073 873eb012 ths
{
1074 9c2149c8 ths
    T0 = (int32_t)env->CP0_EntryHi;
1075 873eb012 ths
    RETURN();
1076 873eb012 ths
}
1077 873eb012 ths
1078 873eb012 ths
void op_mfc0_compare (void)
1079 873eb012 ths
{
1080 9c2149c8 ths
    T0 = env->CP0_Compare;
1081 873eb012 ths
    RETURN();
1082 873eb012 ths
}
1083 873eb012 ths
1084 873eb012 ths
void op_mfc0_status (void)
1085 873eb012 ths
{
1086 9c2149c8 ths
    T0 = env->CP0_Status;
1087 873eb012 ths
    RETURN();
1088 873eb012 ths
}
1089 873eb012 ths
1090 7a387fff ths
void op_mfc0_intctl (void)
1091 7a387fff ths
{
1092 9c2149c8 ths
    T0 = env->CP0_IntCtl;
1093 7a387fff ths
    RETURN();
1094 7a387fff ths
}
1095 7a387fff ths
1096 7a387fff ths
void op_mfc0_srsctl (void)
1097 7a387fff ths
{
1098 9c2149c8 ths
    T0 = env->CP0_SRSCtl;
1099 9c2149c8 ths
    RETURN();
1100 9c2149c8 ths
}
1101 9c2149c8 ths
1102 9c2149c8 ths
void op_mfc0_srsmap (void)
1103 9c2149c8 ths
{
1104 9c2149c8 ths
    T0 = env->CP0_SRSMap;
1105 7a387fff ths
    RETURN();
1106 7a387fff ths
}
1107 7a387fff ths
1108 873eb012 ths
void op_mfc0_cause (void)
1109 873eb012 ths
{
1110 9c2149c8 ths
    T0 = env->CP0_Cause;
1111 873eb012 ths
    RETURN();
1112 873eb012 ths
}
1113 873eb012 ths
1114 873eb012 ths
void op_mfc0_epc (void)
1115 873eb012 ths
{
1116 9c2149c8 ths
    T0 = (int32_t)env->CP0_EPC;
1117 873eb012 ths
    RETURN();
1118 873eb012 ths
}
1119 873eb012 ths
1120 873eb012 ths
void op_mfc0_prid (void)
1121 873eb012 ths
{
1122 9c2149c8 ths
    T0 = env->CP0_PRid;
1123 873eb012 ths
    RETURN();
1124 873eb012 ths
}
1125 873eb012 ths
1126 7a387fff ths
void op_mfc0_ebase (void)
1127 7a387fff ths
{
1128 b29a0341 ths
    T0 = env->CP0_EBase;
1129 7a387fff ths
    RETURN();
1130 7a387fff ths
}
1131 7a387fff ths
1132 873eb012 ths
void op_mfc0_config0 (void)
1133 873eb012 ths
{
1134 9c2149c8 ths
    T0 = env->CP0_Config0;
1135 873eb012 ths
    RETURN();
1136 873eb012 ths
}
1137 873eb012 ths
1138 873eb012 ths
void op_mfc0_config1 (void)
1139 873eb012 ths
{
1140 9c2149c8 ths
    T0 = env->CP0_Config1;
1141 873eb012 ths
    RETURN();
1142 873eb012 ths
}
1143 873eb012 ths
1144 7a387fff ths
void op_mfc0_config2 (void)
1145 7a387fff ths
{
1146 9c2149c8 ths
    T0 = env->CP0_Config2;
1147 7a387fff ths
    RETURN();
1148 7a387fff ths
}
1149 7a387fff ths
1150 7a387fff ths
void op_mfc0_config3 (void)
1151 7a387fff ths
{
1152 9c2149c8 ths
    T0 = env->CP0_Config3;
1153 7a387fff ths
    RETURN();
1154 7a387fff ths
}
1155 7a387fff ths
1156 e397ee33 ths
void op_mfc0_config6 (void)
1157 e397ee33 ths
{
1158 e397ee33 ths
    T0 = env->CP0_Config6;
1159 e397ee33 ths
    RETURN();
1160 e397ee33 ths
}
1161 e397ee33 ths
1162 e397ee33 ths
void op_mfc0_config7 (void)
1163 e397ee33 ths
{
1164 e397ee33 ths
    T0 = env->CP0_Config7;
1165 e397ee33 ths
    RETURN();
1166 e397ee33 ths
}
1167 e397ee33 ths
1168 873eb012 ths
void op_mfc0_lladdr (void)
1169 873eb012 ths
{
1170 9c2149c8 ths
    T0 = (int32_t)env->CP0_LLAddr >> 4;
1171 873eb012 ths
    RETURN();
1172 873eb012 ths
}
1173 873eb012 ths
1174 7a387fff ths
void op_mfc0_watchlo0 (void)
1175 873eb012 ths
{
1176 5dc4b744 ths
    T0 = (int32_t)env->CP0_WatchLo;
1177 873eb012 ths
    RETURN();
1178 873eb012 ths
}
1179 873eb012 ths
1180 7a387fff ths
void op_mfc0_watchhi0 (void)
1181 873eb012 ths
{
1182 9c2149c8 ths
    T0 = env->CP0_WatchHi;
1183 873eb012 ths
    RETURN();
1184 873eb012 ths
}
1185 873eb012 ths
1186 7a387fff ths
void op_mfc0_xcontext (void)
1187 7a387fff ths
{
1188 9c2149c8 ths
    T0 = (int32_t)env->CP0_XContext;
1189 7a387fff ths
    RETURN();
1190 7a387fff ths
}
1191 7a387fff ths
1192 7a387fff ths
void op_mfc0_framemask (void)
1193 7a387fff ths
{
1194 7a387fff ths
    T0 = env->CP0_Framemask;
1195 7a387fff ths
    RETURN();
1196 7a387fff ths
}
1197 7a387fff ths
1198 873eb012 ths
void op_mfc0_debug (void)
1199 873eb012 ths
{
1200 9c2149c8 ths
    T0 = env->CP0_Debug;
1201 873eb012 ths
    if (env->hflags & MIPS_HFLAG_DM)
1202 873eb012 ths
        T0 |= 1 << CP0DB_DM;
1203 873eb012 ths
    RETURN();
1204 873eb012 ths
}
1205 873eb012 ths
1206 873eb012 ths
void op_mfc0_depc (void)
1207 873eb012 ths
{
1208 9c2149c8 ths
    T0 = (int32_t)env->CP0_DEPC;
1209 873eb012 ths
    RETURN();
1210 873eb012 ths
}
1211 873eb012 ths
1212 7a387fff ths
void op_mfc0_performance0 (void)
1213 7a387fff ths
{
1214 9c2149c8 ths
    T0 = env->CP0_Performance0;
1215 7a387fff ths
    RETURN();
1216 7a387fff ths
}
1217 7a387fff ths
1218 873eb012 ths
void op_mfc0_taglo (void)
1219 873eb012 ths
{
1220 9c2149c8 ths
    T0 = env->CP0_TagLo;
1221 873eb012 ths
    RETURN();
1222 873eb012 ths
}
1223 873eb012 ths
1224 873eb012 ths
void op_mfc0_datalo (void)
1225 873eb012 ths
{
1226 9c2149c8 ths
    T0 = env->CP0_DataLo;
1227 873eb012 ths
    RETURN();
1228 873eb012 ths
}
1229 873eb012 ths
1230 7a387fff ths
void op_mfc0_taghi (void)
1231 7a387fff ths
{
1232 9c2149c8 ths
    T0 = env->CP0_TagHi;
1233 7a387fff ths
    RETURN();
1234 7a387fff ths
}
1235 7a387fff ths
1236 7a387fff ths
void op_mfc0_datahi (void)
1237 7a387fff ths
{
1238 9c2149c8 ths
    T0 = env->CP0_DataHi;
1239 7a387fff ths
    RETURN();
1240 7a387fff ths
}
1241 7a387fff ths
1242 873eb012 ths
void op_mfc0_errorepc (void)
1243 873eb012 ths
{
1244 9c2149c8 ths
    T0 = (int32_t)env->CP0_ErrorEPC;
1245 873eb012 ths
    RETURN();
1246 873eb012 ths
}
1247 873eb012 ths
1248 873eb012 ths
void op_mfc0_desave (void)
1249 873eb012 ths
{
1250 9c2149c8 ths
    T0 = env->CP0_DESAVE;
1251 6af0bf9c bellard
    RETURN();
1252 6af0bf9c bellard
}
1253 6af0bf9c bellard
1254 8c0fdd85 ths
void op_mtc0_index (void)
1255 6af0bf9c bellard
{
1256 fcb4a419 ths
    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 % env->nb_tlb);
1257 8c0fdd85 ths
    RETURN();
1258 8c0fdd85 ths
}
1259 8c0fdd85 ths
1260 8c0fdd85 ths
void op_mtc0_entrylo0 (void)
1261 8c0fdd85 ths
{
1262 7a387fff ths
    /* Large physaddr not implemented */
1263 7a387fff ths
    /* 1k pages not implemented */
1264 f1b0aa5d ths
    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
1265 8c0fdd85 ths
    RETURN();
1266 8c0fdd85 ths
}
1267 8c0fdd85 ths
1268 8c0fdd85 ths
void op_mtc0_entrylo1 (void)
1269 8c0fdd85 ths
{
1270 7a387fff ths
    /* Large physaddr not implemented */
1271 7a387fff ths
    /* 1k pages not implemented */
1272 f1b0aa5d ths
    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
1273 8c0fdd85 ths
    RETURN();
1274 8c0fdd85 ths
}
1275 8c0fdd85 ths
1276 8c0fdd85 ths
void op_mtc0_context (void)
1277 8c0fdd85 ths
{
1278 534ce69f ths
    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
1279 8c0fdd85 ths
    RETURN();
1280 8c0fdd85 ths
}
1281 8c0fdd85 ths
1282 8c0fdd85 ths
void op_mtc0_pagemask (void)
1283 8c0fdd85 ths
{
1284 7a387fff ths
    /* 1k pages not implemented */
1285 f2e9ebef ths
    env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1286 7a387fff ths
    RETURN();
1287 7a387fff ths
}
1288 7a387fff ths
1289 7a387fff ths
void op_mtc0_pagegrain (void)
1290 7a387fff ths
{
1291 7a387fff ths
    /* SmartMIPS not implemented */
1292 7a387fff ths
    /* Large physaddr not implemented */
1293 7a387fff ths
    /* 1k pages not implemented */
1294 7a387fff ths
    env->CP0_PageGrain = 0;
1295 8c0fdd85 ths
    RETURN();
1296 8c0fdd85 ths
}
1297 8c0fdd85 ths
1298 8c0fdd85 ths
void op_mtc0_wired (void)
1299 8c0fdd85 ths
{
1300 fcb4a419 ths
    env->CP0_Wired = T0 % env->nb_tlb;
1301 7a387fff ths
    RETURN();
1302 7a387fff ths
}
1303 7a387fff ths
1304 7a387fff ths
void op_mtc0_hwrena (void)
1305 7a387fff ths
{
1306 7a387fff ths
    env->CP0_HWREna = T0 & 0x0000000F;
1307 8c0fdd85 ths
    RETURN();
1308 8c0fdd85 ths
}
1309 8c0fdd85 ths
1310 8c0fdd85 ths
void op_mtc0_count (void)
1311 8c0fdd85 ths
{
1312 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1313 8c0fdd85 ths
    RETURN();
1314 8c0fdd85 ths
}
1315 8c0fdd85 ths
1316 8c0fdd85 ths
void op_mtc0_entryhi (void)
1317 8c0fdd85 ths
{
1318 0feef828 ths
    target_ulong old, val;
1319 8c0fdd85 ths
1320 7a387fff ths
    /* 1k pages not implemented */
1321 100ce988 ths
    val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1322 100ce988 ths
#ifdef TARGET_MIPS64
1323 100ce988 ths
    val = T0 & 0xC00000FFFFFFFFFFULL;
1324 100ce988 ths
#endif
1325 8c0fdd85 ths
    old = env->CP0_EntryHi;
1326 8c0fdd85 ths
    env->CP0_EntryHi = val;
1327 8c0fdd85 ths
    /* If the ASID changes, flush qemu's TLB.  */
1328 8c0fdd85 ths
    if ((old & 0xFF) != (val & 0xFF))
1329 8c0fdd85 ths
        CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1330 8c0fdd85 ths
    RETURN();
1331 8c0fdd85 ths
}
1332 8c0fdd85 ths
1333 8c0fdd85 ths
void op_mtc0_compare (void)
1334 8c0fdd85 ths
{
1335 8c0fdd85 ths
    CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1336 8c0fdd85 ths
    RETURN();
1337 8c0fdd85 ths
}
1338 8c0fdd85 ths
1339 8c0fdd85 ths
void op_mtc0_status (void)
1340 8c0fdd85 ths
{
1341 4de9b249 ths
    uint32_t val, old;
1342 5a5012ec ths
    uint32_t mask = env->Status_rw_bitmask;
1343 8c0fdd85 ths
1344 f1b0aa5d ths
    /* No reverse endianness, no MDMX/DSP, no 64bit ops
1345 f1b0aa5d ths
       implemented. */
1346 f1b0aa5d ths
    val = T0 & mask;
1347 8c0fdd85 ths
    old = env->CP0_Status;
1348 f41c52f1 ths
    if (!(val & (1 << CP0St_EXL)) &&
1349 f41c52f1 ths
        !(val & (1 << CP0St_ERL)) &&
1350 f41c52f1 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
1351 f41c52f1 ths
        (val & (1 << CP0St_UM)))
1352 f41c52f1 ths
        env->hflags |= MIPS_HFLAG_UM;
1353 5a5012ec ths
    env->CP0_Status = (env->CP0_Status & ~mask) | val;
1354 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
1355 f41c52f1 ths
        CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1356 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
1357 8c0fdd85 ths
    RETURN();
1358 8c0fdd85 ths
}
1359 8c0fdd85 ths
1360 7a387fff ths
void op_mtc0_intctl (void)
1361 7a387fff ths
{
1362 c090a8f4 ths
    /* vectored interrupts not implemented, timer on int 7,
1363 c090a8f4 ths
       no performance counters. */
1364 c090a8f4 ths
    env->CP0_IntCtl |= T0 & 0x000002e0;
1365 7a387fff ths
    RETURN();
1366 7a387fff ths
}
1367 7a387fff ths
1368 7a387fff ths
void op_mtc0_srsctl (void)
1369 7a387fff ths
{
1370 7a387fff ths
    /* shadow registers not implemented */
1371 7a387fff ths
    env->CP0_SRSCtl = 0;
1372 7a387fff ths
    RETURN();
1373 7a387fff ths
}
1374 7a387fff ths
1375 9c2149c8 ths
void op_mtc0_srsmap (void)
1376 9c2149c8 ths
{
1377 9c2149c8 ths
    /* shadow registers not implemented */
1378 9c2149c8 ths
    env->CP0_SRSMap = 0;
1379 9c2149c8 ths
    RETURN();
1380 9c2149c8 ths
}
1381 9c2149c8 ths
1382 8c0fdd85 ths
void op_mtc0_cause (void)
1383 8c0fdd85 ths
{
1384 39d51eb8 ths
    uint32_t mask = 0x00C00300;
1385 39d51eb8 ths
1386 39d51eb8 ths
    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
1387 39d51eb8 ths
        mask |= 1 << CP0Ca_DC;
1388 39d51eb8 ths
1389 e58c8ba5 ths
    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1390 8c0fdd85 ths
1391 4de9b249 ths
    /* Handle the software interrupt as an hardware one, as they
1392 4de9b249 ths
       are very similar */
1393 4de9b249 ths
    if (T0 & CP0Ca_IP_mask) {
1394 4de9b249 ths
        CALL_FROM_TB1(cpu_mips_update_irq, env);
1395 8c0fdd85 ths
    }
1396 8c0fdd85 ths
    RETURN();
1397 8c0fdd85 ths
}
1398 8c0fdd85 ths
1399 8c0fdd85 ths
void op_mtc0_epc (void)
1400 8c0fdd85 ths
{
1401 f1b0aa5d ths
    env->CP0_EPC = T0;
1402 8c0fdd85 ths
    RETURN();
1403 8c0fdd85 ths
}
1404 8c0fdd85 ths
1405 7a387fff ths
void op_mtc0_ebase (void)
1406 7a387fff ths
{
1407 7a387fff ths
    /* vectored interrupts not implemented */
1408 7a387fff ths
    /* Multi-CPU not implemented */
1409 b29a0341 ths
    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1410 7a387fff ths
    RETURN();
1411 7a387fff ths
}
1412 7a387fff ths
1413 8c0fdd85 ths
void op_mtc0_config0 (void)
1414 8c0fdd85 ths
{
1415 29929e34 ths
    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000001);
1416 8c0fdd85 ths
    RETURN();
1417 8c0fdd85 ths
}
1418 8c0fdd85 ths
1419 7a387fff ths
void op_mtc0_config2 (void)
1420 7a387fff ths
{
1421 7a387fff ths
    /* tertiary/secondary caches not implemented */
1422 7a387fff ths
    env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1423 7a387fff ths
    RETURN();
1424 7a387fff ths
}
1425 7a387fff ths
1426 7a387fff ths
void op_mtc0_watchlo0 (void)
1427 8c0fdd85 ths
{
1428 4e7a4a4e ths
    /* Watch exceptions for instructions, data loads, data stores
1429 4e7a4a4e ths
       not implemented. */
1430 f1b0aa5d ths
    env->CP0_WatchLo = (T0 & ~0x7);
1431 8c0fdd85 ths
    RETURN();
1432 8c0fdd85 ths
}
1433 8c0fdd85 ths
1434 7a387fff ths
void op_mtc0_watchhi0 (void)
1435 8c0fdd85 ths
{
1436 4e7a4a4e ths
    env->CP0_WatchHi = (T0 & 0x40FF0FF8);
1437 4e7a4a4e ths
    env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7);
1438 8c0fdd85 ths
    RETURN();
1439 8c0fdd85 ths
}
1440 8c0fdd85 ths
1441 7a387fff ths
void op_mtc0_framemask (void)
1442 7a387fff ths
{
1443 7a387fff ths
    env->CP0_Framemask = T0; /* XXX */
1444 7a387fff ths
    RETURN();
1445 7a387fff ths
}
1446 7a387fff ths
1447 8c0fdd85 ths
void op_mtc0_debug (void)
1448 8c0fdd85 ths
{
1449 8c0fdd85 ths
    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1450 8c0fdd85 ths
    if (T0 & (1 << CP0DB_DM))
1451 8c0fdd85 ths
        env->hflags |= MIPS_HFLAG_DM;
1452 8c0fdd85 ths
    else
1453 8c0fdd85 ths
        env->hflags &= ~MIPS_HFLAG_DM;
1454 8c0fdd85 ths
    RETURN();
1455 8c0fdd85 ths
}
1456 8c0fdd85 ths
1457 8c0fdd85 ths
void op_mtc0_depc (void)
1458 8c0fdd85 ths
{
1459 f1b0aa5d ths
    env->CP0_DEPC = T0;
1460 8c0fdd85 ths
    RETURN();
1461 8c0fdd85 ths
}
1462 8c0fdd85 ths
1463 7a387fff ths
void op_mtc0_performance0 (void)
1464 7a387fff ths
{
1465 7a387fff ths
    env->CP0_Performance0 = T0; /* XXX */
1466 7a387fff ths
    RETURN();
1467 7a387fff ths
}
1468 7a387fff ths
1469 8c0fdd85 ths
void op_mtc0_taglo (void)
1470 8c0fdd85 ths
{
1471 9c2149c8 ths
    env->CP0_TagLo = T0 & 0xFFFFFCF6;
1472 8c0fdd85 ths
    RETURN();
1473 8c0fdd85 ths
}
1474 8c0fdd85 ths
1475 7a387fff ths
void op_mtc0_datalo (void)
1476 7a387fff ths
{
1477 7a387fff ths
    env->CP0_DataLo = T0; /* XXX */
1478 7a387fff ths
    RETURN();
1479 7a387fff ths
}
1480 7a387fff ths
1481 7a387fff ths
void op_mtc0_taghi (void)
1482 7a387fff ths
{
1483 7a387fff ths
    env->CP0_TagHi = T0; /* XXX */
1484 7a387fff ths
    RETURN();
1485 7a387fff ths
}
1486 7a387fff ths
1487 7a387fff ths
void op_mtc0_datahi (void)
1488 7a387fff ths
{
1489 7a387fff ths
    env->CP0_DataHi = T0; /* XXX */
1490 7a387fff ths
    RETURN();
1491 7a387fff ths
}
1492 7a387fff ths
1493 8c0fdd85 ths
void op_mtc0_errorepc (void)
1494 8c0fdd85 ths
{
1495 f1b0aa5d ths
    env->CP0_ErrorEPC = T0;
1496 8c0fdd85 ths
    RETURN();
1497 8c0fdd85 ths
}
1498 8c0fdd85 ths
1499 8c0fdd85 ths
void op_mtc0_desave (void)
1500 8c0fdd85 ths
{
1501 8c0fdd85 ths
    env->CP0_DESAVE = T0;
1502 6af0bf9c bellard
    RETURN();
1503 6af0bf9c bellard
}
1504 6af0bf9c bellard
1505 534ce69f ths
#ifdef TARGET_MIPS64
1506 f1b0aa5d ths
void op_mtc0_xcontext (void)
1507 f1b0aa5d ths
{
1508 f1b0aa5d ths
    env->CP0_XContext = (env->CP0_XContext & 0x1ffffffffULL) | (T0 & ~0x1ffffffffULL);
1509 f1b0aa5d ths
    RETURN();
1510 f1b0aa5d ths
}
1511 f1b0aa5d ths
1512 9c2149c8 ths
void op_dmfc0_entrylo0 (void)
1513 9c2149c8 ths
{
1514 9c2149c8 ths
    T0 = env->CP0_EntryLo0;
1515 9c2149c8 ths
    RETURN();
1516 9c2149c8 ths
}
1517 9c2149c8 ths
1518 9c2149c8 ths
void op_dmfc0_entrylo1 (void)
1519 9c2149c8 ths
{
1520 9c2149c8 ths
    T0 = env->CP0_EntryLo1;
1521 9c2149c8 ths
    RETURN();
1522 9c2149c8 ths
}
1523 9c2149c8 ths
1524 9c2149c8 ths
void op_dmfc0_context (void)
1525 9c2149c8 ths
{
1526 9c2149c8 ths
    T0 = env->CP0_Context;
1527 9c2149c8 ths
    RETURN();
1528 9c2149c8 ths
}
1529 9c2149c8 ths
1530 9c2149c8 ths
void op_dmfc0_badvaddr (void)
1531 9c2149c8 ths
{
1532 9c2149c8 ths
    T0 = env->CP0_BadVAddr;
1533 9c2149c8 ths
    RETURN();
1534 9c2149c8 ths
}
1535 9c2149c8 ths
1536 9c2149c8 ths
void op_dmfc0_entryhi (void)
1537 9c2149c8 ths
{
1538 9c2149c8 ths
    T0 = env->CP0_EntryHi;
1539 9c2149c8 ths
    RETURN();
1540 9c2149c8 ths
}
1541 9c2149c8 ths
1542 9c2149c8 ths
void op_dmfc0_epc (void)
1543 9c2149c8 ths
{
1544 9c2149c8 ths
    T0 = env->CP0_EPC;
1545 9c2149c8 ths
    RETURN();
1546 9c2149c8 ths
}
1547 9c2149c8 ths
1548 9c2149c8 ths
void op_dmfc0_lladdr (void)
1549 9c2149c8 ths
{
1550 9c2149c8 ths
    T0 = env->CP0_LLAddr >> 4;
1551 9c2149c8 ths
    RETURN();
1552 9c2149c8 ths
}
1553 9c2149c8 ths
1554 9c2149c8 ths
void op_dmfc0_watchlo0 (void)
1555 9c2149c8 ths
{
1556 9c2149c8 ths
    T0 = env->CP0_WatchLo;
1557 9c2149c8 ths
    RETURN();
1558 9c2149c8 ths
}
1559 9c2149c8 ths
1560 9c2149c8 ths
void op_dmfc0_xcontext (void)
1561 9c2149c8 ths
{
1562 9c2149c8 ths
    T0 = env->CP0_XContext;
1563 9c2149c8 ths
    RETURN();
1564 9c2149c8 ths
}
1565 9c2149c8 ths
1566 9c2149c8 ths
void op_dmfc0_depc (void)
1567 9c2149c8 ths
{
1568 9c2149c8 ths
    T0 = env->CP0_DEPC;
1569 9c2149c8 ths
    RETURN();
1570 9c2149c8 ths
}
1571 9c2149c8 ths
1572 9c2149c8 ths
void op_dmfc0_errorepc (void)
1573 9c2149c8 ths
{
1574 9c2149c8 ths
    T0 = env->CP0_ErrorEPC;
1575 9c2149c8 ths
    RETURN();
1576 9c2149c8 ths
}
1577 534ce69f ths
#endif /* TARGET_MIPS64 */
1578 9c2149c8 ths
1579 5a5012ec ths
/* CP1 functions */
1580 6ea83fed bellard
#if 0
1581 6ea83fed bellard
# define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1582 6ea83fed bellard
#else
1583 6ea83fed bellard
# define DEBUG_FPU_STATE() do { } while(0)
1584 6ea83fed bellard
#endif
1585 6ea83fed bellard
1586 24c7b0e3 ths
void op_cp0_enabled(void)
1587 24c7b0e3 ths
{
1588 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_CU0)) &&
1589 24c7b0e3 ths
        (env->hflags & MIPS_HFLAG_UM)) {
1590 1579a72e ths
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0);
1591 24c7b0e3 ths
    }
1592 24c7b0e3 ths
    RETURN();
1593 24c7b0e3 ths
}
1594 24c7b0e3 ths
1595 6ea83fed bellard
void op_cp1_enabled(void)
1596 6ea83fed bellard
{
1597 6ea83fed bellard
    if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1598 1579a72e ths
        CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1599 6ea83fed bellard
    }
1600 6ea83fed bellard
    RETURN();
1601 6ea83fed bellard
}
1602 6ea83fed bellard
1603 57fa1fb3 ths
void op_cp1_64bitmode(void)
1604 57fa1fb3 ths
{
1605 57fa1fb3 ths
    if (!(env->CP0_Status & (1 << CP0St_FR))) {
1606 57fa1fb3 ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
1607 57fa1fb3 ths
    }
1608 57fa1fb3 ths
    RETURN();
1609 57fa1fb3 ths
}
1610 57fa1fb3 ths
1611 fd4a04eb ths
/*
1612 fd4a04eb ths
 * Verify if floating point register is valid; an operation is not defined
1613 fd4a04eb ths
 * if bit 0 of any register specification is set and the FR bit in the
1614 fd4a04eb ths
 * Status register equals zero, since the register numbers specify an
1615 fd4a04eb ths
 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1616 fd4a04eb ths
 * in the Status register equals one, both even and odd register numbers
1617 fd4a04eb ths
 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
1618 fd4a04eb ths
 *
1619 fd4a04eb ths
 * Multiple 64 bit wide registers can be checked by calling
1620 fd4a04eb ths
 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
1621 fd4a04eb ths
 */
1622 fd4a04eb ths
void op_cp1_registers(void)
1623 5a5012ec ths
{
1624 fd4a04eb ths
    if (!(env->CP0_Status & (1 << CP0St_FR)) && (PARAM1 & 1)) {
1625 fd4a04eb ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
1626 fd4a04eb ths
    }
1627 fd4a04eb ths
    RETURN();
1628 5a5012ec ths
}
1629 5a5012ec ths
1630 5a5012ec ths
void op_cfc1 (void)
1631 5a5012ec ths
{
1632 5a5012ec ths
    switch (T1) {
1633 5a5012ec ths
    case 0:
1634 5a5012ec ths
        T0 = (int32_t)env->fcr0;
1635 5a5012ec ths
        break;
1636 5a5012ec ths
    case 25:
1637 5a5012ec ths
        T0 = ((env->fcr31 >> 24) & 0xfe) | ((env->fcr31 >> 23) & 0x1);
1638 5a5012ec ths
        break;
1639 5a5012ec ths
    case 26:
1640 5a5012ec ths
        T0 = env->fcr31 & 0x0003f07c;
1641 5a5012ec ths
        break;
1642 5a5012ec ths
    case 28:
1643 5a5012ec ths
        T0 = (env->fcr31 & 0x00000f83) | ((env->fcr31 >> 22) & 0x4);
1644 5a5012ec ths
        break;
1645 5a5012ec ths
    default:
1646 5a5012ec ths
        T0 = (int32_t)env->fcr31;
1647 5a5012ec ths
        break;
1648 5a5012ec ths
    }
1649 5a5012ec ths
    DEBUG_FPU_STATE();
1650 5a5012ec ths
    RETURN();
1651 5a5012ec ths
}
1652 5a5012ec ths
1653 5a5012ec ths
void op_ctc1 (void)
1654 5a5012ec ths
{
1655 fd4a04eb ths
    CALL_FROM_TB0(do_ctc1);
1656 6ea83fed bellard
    DEBUG_FPU_STATE();
1657 6ea83fed bellard
    RETURN();
1658 6ea83fed bellard
}
1659 6ea83fed bellard
1660 6ea83fed bellard
void op_mfc1 (void)
1661 6ea83fed bellard
{
1662 6ea83fed bellard
    T0 = WT0;
1663 6ea83fed bellard
    DEBUG_FPU_STATE();
1664 6ea83fed bellard
    RETURN();
1665 6ea83fed bellard
}
1666 6ea83fed bellard
1667 6ea83fed bellard
void op_mtc1 (void)
1668 6ea83fed bellard
{
1669 6ea83fed bellard
    WT0 = T0;
1670 6ea83fed bellard
    DEBUG_FPU_STATE();
1671 6ea83fed bellard
    RETURN();
1672 6ea83fed bellard
}
1673 6ea83fed bellard
1674 5a5012ec ths
void op_dmfc1 (void)
1675 5a5012ec ths
{
1676 5a5012ec ths
    T0 = DT0;
1677 5a5012ec ths
    DEBUG_FPU_STATE();
1678 5a5012ec ths
    RETURN();
1679 5a5012ec ths
}
1680 5a5012ec ths
1681 5a5012ec ths
void op_dmtc1 (void)
1682 5a5012ec ths
{
1683 5a5012ec ths
    DT0 = T0;
1684 5a5012ec ths
    DEBUG_FPU_STATE();
1685 5a5012ec ths
    RETURN();
1686 5a5012ec ths
}
1687 5a5012ec ths
1688 5a5012ec ths
void op_mfhc1 (void)
1689 5a5012ec ths
{
1690 5a5012ec ths
    T0 = WTH0;
1691 5a5012ec ths
    DEBUG_FPU_STATE();
1692 5a5012ec ths
    RETURN();
1693 5a5012ec ths
}
1694 5a5012ec ths
1695 5a5012ec ths
void op_mthc1 (void)
1696 5a5012ec ths
{
1697 5a5012ec ths
    WTH0 = T0;
1698 5a5012ec ths
    DEBUG_FPU_STATE();
1699 5a5012ec ths
    RETURN();
1700 5a5012ec ths
}
1701 5a5012ec ths
1702 6ea83fed bellard
/* Float support.
1703 6ea83fed bellard
   Single precition routines have a "s" suffix, double precision a
1704 5a5012ec ths
   "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
1705 5a5012ec ths
   paired single lowwer "pl", paired single upper "pu".  */
1706 6ea83fed bellard
1707 6ea83fed bellard
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1708 6ea83fed bellard
1709 dd016883 bellard
FLOAT_OP(cvtd, s)
1710 dd016883 bellard
{
1711 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtd_s);
1712 dd016883 bellard
    DEBUG_FPU_STATE();
1713 dd016883 bellard
    RETURN();
1714 dd016883 bellard
}
1715 6ea83fed bellard
FLOAT_OP(cvtd, w)
1716 6ea83fed bellard
{
1717 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtd_w);
1718 5a5012ec ths
    DEBUG_FPU_STATE();
1719 5a5012ec ths
    RETURN();
1720 5a5012ec ths
}
1721 5a5012ec ths
FLOAT_OP(cvtd, l)
1722 5a5012ec ths
{
1723 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtd_l);
1724 5a5012ec ths
    DEBUG_FPU_STATE();
1725 5a5012ec ths
    RETURN();
1726 5a5012ec ths
}
1727 5a5012ec ths
FLOAT_OP(cvtl, d)
1728 5a5012ec ths
{
1729 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtl_d);
1730 5a5012ec ths
    DEBUG_FPU_STATE();
1731 5a5012ec ths
    RETURN();
1732 5a5012ec ths
}
1733 5a5012ec ths
FLOAT_OP(cvtl, s)
1734 5a5012ec ths
{
1735 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtl_s);
1736 5a5012ec ths
    DEBUG_FPU_STATE();
1737 5a5012ec ths
    RETURN();
1738 5a5012ec ths
}
1739 5a5012ec ths
FLOAT_OP(cvtps, s)
1740 5a5012ec ths
{
1741 5a5012ec ths
    WT2 = WT0;
1742 5a5012ec ths
    WTH2 = WT1;
1743 5a5012ec ths
    DEBUG_FPU_STATE();
1744 5a5012ec ths
    RETURN();
1745 5a5012ec ths
}
1746 5a5012ec ths
FLOAT_OP(cvtps, pw)
1747 5a5012ec ths
{
1748 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtps_pw);
1749 5a5012ec ths
    DEBUG_FPU_STATE();
1750 5a5012ec ths
    RETURN();
1751 5a5012ec ths
}
1752 5a5012ec ths
FLOAT_OP(cvtpw, ps)
1753 5a5012ec ths
{
1754 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtpw_ps);
1755 6ea83fed bellard
    DEBUG_FPU_STATE();
1756 6ea83fed bellard
    RETURN();
1757 6ea83fed bellard
}
1758 dd016883 bellard
FLOAT_OP(cvts, d)
1759 dd016883 bellard
{
1760 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvts_d);
1761 dd016883 bellard
    DEBUG_FPU_STATE();
1762 dd016883 bellard
    RETURN();
1763 dd016883 bellard
}
1764 6ea83fed bellard
FLOAT_OP(cvts, w)
1765 6ea83fed bellard
{
1766 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvts_w);
1767 5a5012ec ths
    DEBUG_FPU_STATE();
1768 5a5012ec ths
    RETURN();
1769 5a5012ec ths
}
1770 5a5012ec ths
FLOAT_OP(cvts, l)
1771 5a5012ec ths
{
1772 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvts_l);
1773 5a5012ec ths
    DEBUG_FPU_STATE();
1774 5a5012ec ths
    RETURN();
1775 5a5012ec ths
}
1776 5a5012ec ths
FLOAT_OP(cvts, pl)
1777 5a5012ec ths
{
1778 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvts_pl);
1779 5a5012ec ths
    DEBUG_FPU_STATE();
1780 5a5012ec ths
    RETURN();
1781 5a5012ec ths
}
1782 5a5012ec ths
FLOAT_OP(cvts, pu)
1783 5a5012ec ths
{
1784 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvts_pu);
1785 6ea83fed bellard
    DEBUG_FPU_STATE();
1786 6ea83fed bellard
    RETURN();
1787 6ea83fed bellard
}
1788 6ea83fed bellard
FLOAT_OP(cvtw, s)
1789 6ea83fed bellard
{
1790 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtw_s);
1791 6ea83fed bellard
    DEBUG_FPU_STATE();
1792 6ea83fed bellard
    RETURN();
1793 6ea83fed bellard
}
1794 6ea83fed bellard
FLOAT_OP(cvtw, d)
1795 6ea83fed bellard
{
1796 fd4a04eb ths
    CALL_FROM_TB0(do_float_cvtw_d);
1797 5a5012ec ths
    DEBUG_FPU_STATE();
1798 5a5012ec ths
    RETURN();
1799 5a5012ec ths
}
1800 5a5012ec ths
1801 5a5012ec ths
FLOAT_OP(pll, ps)
1802 5a5012ec ths
{
1803 5a5012ec ths
    DT2 = ((uint64_t)WT0 << 32) | WT1;
1804 5a5012ec ths
    DEBUG_FPU_STATE();
1805 5a5012ec ths
    RETURN();
1806 5a5012ec ths
}
1807 5a5012ec ths
FLOAT_OP(plu, ps)
1808 5a5012ec ths
{
1809 5a5012ec ths
    DT2 = ((uint64_t)WT0 << 32) | WTH1;
1810 5a5012ec ths
    DEBUG_FPU_STATE();
1811 5a5012ec ths
    RETURN();
1812 5a5012ec ths
}
1813 5a5012ec ths
FLOAT_OP(pul, ps)
1814 5a5012ec ths
{
1815 5a5012ec ths
    DT2 = ((uint64_t)WTH0 << 32) | WT1;
1816 5a5012ec ths
    DEBUG_FPU_STATE();
1817 5a5012ec ths
    RETURN();
1818 5a5012ec ths
}
1819 5a5012ec ths
FLOAT_OP(puu, ps)
1820 5a5012ec ths
{
1821 5a5012ec ths
    DT2 = ((uint64_t)WTH0 << 32) | WTH1;
1822 6ea83fed bellard
    DEBUG_FPU_STATE();
1823 6ea83fed bellard
    RETURN();
1824 6ea83fed bellard
}
1825 6ea83fed bellard
1826 fd4a04eb ths
#define FLOAT_ROUNDOP(op, ttype, stype)                    \
1827 fd4a04eb ths
FLOAT_OP(op ## ttype, stype)                               \
1828 fd4a04eb ths
{                                                          \
1829 fd4a04eb ths
    CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \
1830 fd4a04eb ths
    DEBUG_FPU_STATE();                                     \
1831 fd4a04eb ths
    RETURN();                                              \
1832 6ea83fed bellard
}
1833 6ea83fed bellard
1834 fd4a04eb ths
FLOAT_ROUNDOP(round, l, d)
1835 fd4a04eb ths
FLOAT_ROUNDOP(round, l, s)
1836 fd4a04eb ths
FLOAT_ROUNDOP(round, w, d)
1837 fd4a04eb ths
FLOAT_ROUNDOP(round, w, s)
1838 6ea83fed bellard
1839 fd4a04eb ths
FLOAT_ROUNDOP(trunc, l, d)
1840 fd4a04eb ths
FLOAT_ROUNDOP(trunc, l, s)
1841 fd4a04eb ths
FLOAT_ROUNDOP(trunc, w, d)
1842 fd4a04eb ths
FLOAT_ROUNDOP(trunc, w, s)
1843 6ea83fed bellard
1844 fd4a04eb ths
FLOAT_ROUNDOP(ceil, l, d)
1845 fd4a04eb ths
FLOAT_ROUNDOP(ceil, l, s)
1846 fd4a04eb ths
FLOAT_ROUNDOP(ceil, w, d)
1847 fd4a04eb ths
FLOAT_ROUNDOP(ceil, w, s)
1848 fd4a04eb ths
1849 fd4a04eb ths
FLOAT_ROUNDOP(floor, l, d)
1850 fd4a04eb ths
FLOAT_ROUNDOP(floor, l, s)
1851 fd4a04eb ths
FLOAT_ROUNDOP(floor, w, d)
1852 fd4a04eb ths
FLOAT_ROUNDOP(floor, w, s)
1853 fd4a04eb ths
#undef FLOAR_ROUNDOP
1854 6ea83fed bellard
1855 5a5012ec ths
FLOAT_OP(movf, d)
1856 5a5012ec ths
{
1857 5a5012ec ths
    if (!(env->fcr31 & PARAM1))
1858 5a5012ec ths
        DT2 = DT0;
1859 5a5012ec ths
    DEBUG_FPU_STATE();
1860 5a5012ec ths
    RETURN();
1861 5a5012ec ths
}
1862 5a5012ec ths
FLOAT_OP(movf, s)
1863 5a5012ec ths
{
1864 5a5012ec ths
    if (!(env->fcr31 & PARAM1))
1865 5a5012ec ths
        WT2 = WT0;
1866 5a5012ec ths
    DEBUG_FPU_STATE();
1867 5a5012ec ths
    RETURN();
1868 5a5012ec ths
}
1869 5a5012ec ths
FLOAT_OP(movf, ps)
1870 5a5012ec ths
{
1871 5a5012ec ths
    if (!(env->fcr31 & PARAM1)) {
1872 5a5012ec ths
        WT2 = WT0;
1873 5a5012ec ths
        WTH2 = WTH0;
1874 5a5012ec ths
    }
1875 5a5012ec ths
    DEBUG_FPU_STATE();
1876 5a5012ec ths
    RETURN();
1877 5a5012ec ths
}
1878 5a5012ec ths
FLOAT_OP(movt, d)
1879 5a5012ec ths
{
1880 5a5012ec ths
    if (env->fcr31 & PARAM1)
1881 5a5012ec ths
        DT2 = DT0;
1882 5a5012ec ths
    DEBUG_FPU_STATE();
1883 5a5012ec ths
    RETURN();
1884 5a5012ec ths
}
1885 5a5012ec ths
FLOAT_OP(movt, s)
1886 5a5012ec ths
{
1887 5a5012ec ths
    if (env->fcr31 & PARAM1)
1888 5a5012ec ths
        WT2 = WT0;
1889 5a5012ec ths
    DEBUG_FPU_STATE();
1890 5a5012ec ths
    RETURN();
1891 5a5012ec ths
}
1892 5a5012ec ths
FLOAT_OP(movt, ps)
1893 5a5012ec ths
{
1894 5a5012ec ths
    if (env->fcr31 & PARAM1) {
1895 5a5012ec ths
        WT2 = WT0;
1896 5a5012ec ths
        WTH2 = WTH0;
1897 5a5012ec ths
    }
1898 5a5012ec ths
    DEBUG_FPU_STATE();
1899 5a5012ec ths
    RETURN();
1900 5a5012ec ths
}
1901 5a5012ec ths
FLOAT_OP(movz, d)
1902 5a5012ec ths
{
1903 5a5012ec ths
    if (!T0)
1904 5a5012ec ths
        DT2 = DT0;
1905 5a5012ec ths
    DEBUG_FPU_STATE();
1906 5a5012ec ths
    RETURN();
1907 5a5012ec ths
}
1908 5a5012ec ths
FLOAT_OP(movz, s)
1909 5a5012ec ths
{
1910 5a5012ec ths
    if (!T0)
1911 5a5012ec ths
        WT2 = WT0;
1912 5a5012ec ths
    DEBUG_FPU_STATE();
1913 5a5012ec ths
    RETURN();
1914 5a5012ec ths
}
1915 5a5012ec ths
FLOAT_OP(movz, ps)
1916 5a5012ec ths
{
1917 5a5012ec ths
    if (!T0) {
1918 5a5012ec ths
        WT2 = WT0;
1919 5a5012ec ths
        WTH2 = WTH0;
1920 5a5012ec ths
    }
1921 5a5012ec ths
    DEBUG_FPU_STATE();
1922 5a5012ec ths
    RETURN();
1923 5a5012ec ths
}
1924 5a5012ec ths
FLOAT_OP(movn, d)
1925 5a5012ec ths
{
1926 5a5012ec ths
    if (T0)
1927 5a5012ec ths
        DT2 = DT0;
1928 5a5012ec ths
    DEBUG_FPU_STATE();
1929 5a5012ec ths
    RETURN();
1930 5a5012ec ths
}
1931 5a5012ec ths
FLOAT_OP(movn, s)
1932 5a5012ec ths
{
1933 5a5012ec ths
    if (T0)
1934 5a5012ec ths
        WT2 = WT0;
1935 5a5012ec ths
    DEBUG_FPU_STATE();
1936 5a5012ec ths
    RETURN();
1937 5a5012ec ths
}
1938 5a5012ec ths
FLOAT_OP(movn, ps)
1939 5a5012ec ths
{
1940 5a5012ec ths
    if (T0) {
1941 5a5012ec ths
        WT2 = WT0;
1942 5a5012ec ths
        WTH2 = WTH0;
1943 5a5012ec ths
    }
1944 5a5012ec ths
    DEBUG_FPU_STATE();
1945 5a5012ec ths
    RETURN();
1946 5a5012ec ths
}
1947 5a5012ec ths
1948 57fa1fb3 ths
/* operations calling helpers, for s, d and ps */
1949 57fa1fb3 ths
#define FLOAT_HOP(name) \
1950 6ea83fed bellard
FLOAT_OP(name, d)         \
1951 6ea83fed bellard
{                         \
1952 fd4a04eb ths
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
1953 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1954 fbcc6828 ths
    RETURN();             \
1955 6ea83fed bellard
}                         \
1956 6ea83fed bellard
FLOAT_OP(name, s)         \
1957 6ea83fed bellard
{                         \
1958 fd4a04eb ths
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
1959 5a5012ec ths
    DEBUG_FPU_STATE();    \
1960 fbcc6828 ths
    RETURN();             \
1961 5a5012ec ths
}                         \
1962 5a5012ec ths
FLOAT_OP(name, ps)        \
1963 5a5012ec ths
{                         \
1964 fd4a04eb ths
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
1965 6ea83fed bellard
    DEBUG_FPU_STATE();    \
1966 fbcc6828 ths
    RETURN();             \
1967 6ea83fed bellard
}
1968 57fa1fb3 ths
FLOAT_HOP(add)
1969 57fa1fb3 ths
FLOAT_HOP(sub)
1970 57fa1fb3 ths
FLOAT_HOP(mul)
1971 57fa1fb3 ths
FLOAT_HOP(div)
1972 57fa1fb3 ths
FLOAT_HOP(recip2)
1973 57fa1fb3 ths
FLOAT_HOP(rsqrt2)
1974 57fa1fb3 ths
FLOAT_HOP(rsqrt1)
1975 57fa1fb3 ths
FLOAT_HOP(recip1)
1976 57fa1fb3 ths
#undef FLOAT_HOP
1977 57fa1fb3 ths
1978 57fa1fb3 ths
/* operations calling helpers, for s and d */
1979 57fa1fb3 ths
#define FLOAT_HOP(name)   \
1980 57fa1fb3 ths
FLOAT_OP(name, d)         \
1981 57fa1fb3 ths
{                         \
1982 57fa1fb3 ths
    CALL_FROM_TB0(do_float_ ## name ## _d);  \
1983 57fa1fb3 ths
    DEBUG_FPU_STATE();    \
1984 57fa1fb3 ths
    RETURN();             \
1985 57fa1fb3 ths
}                         \
1986 57fa1fb3 ths
FLOAT_OP(name, s)         \
1987 57fa1fb3 ths
{                         \
1988 57fa1fb3 ths
    CALL_FROM_TB0(do_float_ ## name ## _s);  \
1989 57fa1fb3 ths
    DEBUG_FPU_STATE();    \
1990 57fa1fb3 ths
    RETURN();             \
1991 57fa1fb3 ths
}
1992 57fa1fb3 ths
FLOAT_HOP(rsqrt)
1993 57fa1fb3 ths
FLOAT_HOP(recip)
1994 57fa1fb3 ths
#undef FLOAT_HOP
1995 6ea83fed bellard
1996 57fa1fb3 ths
/* operations calling helpers, for ps */
1997 57fa1fb3 ths
#define FLOAT_HOP(name)   \
1998 57fa1fb3 ths
FLOAT_OP(name, ps)        \
1999 57fa1fb3 ths
{                         \
2000 57fa1fb3 ths
    CALL_FROM_TB0(do_float_ ## name ## _ps); \
2001 57fa1fb3 ths
    DEBUG_FPU_STATE();    \
2002 57fa1fb3 ths
    RETURN();             \
2003 fbcc6828 ths
}
2004 57fa1fb3 ths
FLOAT_HOP(addr)
2005 57fa1fb3 ths
FLOAT_HOP(mulr)
2006 57fa1fb3 ths
#undef FLOAT_HOP
2007 fbcc6828 ths
2008 5a5012ec ths
/* ternary operations */
2009 5a5012ec ths
#define FLOAT_TERNOP(name1, name2) \
2010 5a5012ec ths
FLOAT_OP(name1 ## name2, d)        \
2011 5a5012ec ths
{                                  \
2012 5a5012ec ths
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status);    \
2013 5a5012ec ths
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status);    \
2014 5a5012ec ths
    DEBUG_FPU_STATE();             \
2015 fbcc6828 ths
    RETURN();                      \
2016 5a5012ec ths
}                                  \
2017 5a5012ec ths
FLOAT_OP(name1 ## name2, s)        \
2018 5a5012ec ths
{                                  \
2019 5a5012ec ths
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2020 5a5012ec ths
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2021 5a5012ec ths
    DEBUG_FPU_STATE();             \
2022 fbcc6828 ths
    RETURN();                      \
2023 5a5012ec ths
}                                  \
2024 5a5012ec ths
FLOAT_OP(name1 ## name2, ps)       \
2025 5a5012ec ths
{                                  \
2026 5a5012ec ths
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2027 5a5012ec ths
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2028 5a5012ec ths
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2029 5a5012ec ths
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2030 5a5012ec ths
    DEBUG_FPU_STATE();             \
2031 fbcc6828 ths
    RETURN();                      \
2032 5a5012ec ths
}
2033 5a5012ec ths
FLOAT_TERNOP(mul, add)
2034 5a5012ec ths
FLOAT_TERNOP(mul, sub)
2035 5a5012ec ths
#undef FLOAT_TERNOP
2036 5a5012ec ths
2037 fbcc6828 ths
/* negated ternary operations */
2038 fbcc6828 ths
#define FLOAT_NTERNOP(name1, name2) \
2039 fbcc6828 ths
FLOAT_OP(n ## name1 ## name2, d)    \
2040 fbcc6828 ths
{                                   \
2041 fbcc6828 ths
    FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fp_status);    \
2042 fbcc6828 ths
    FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fp_status);    \
2043 fbcc6828 ths
    FDT2 ^= 1ULL << 63;             \
2044 fbcc6828 ths
    DEBUG_FPU_STATE();              \
2045 fbcc6828 ths
    RETURN();                       \
2046 fbcc6828 ths
}                                   \
2047 fbcc6828 ths
FLOAT_OP(n ## name1 ## name2, s)    \
2048 fbcc6828 ths
{                                   \
2049 fbcc6828 ths
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2050 fbcc6828 ths
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2051 fbcc6828 ths
    FST2 ^= 1 << 31;                \
2052 fbcc6828 ths
    DEBUG_FPU_STATE();              \
2053 fbcc6828 ths
    RETURN();                       \
2054 fbcc6828 ths
}                                   \
2055 fbcc6828 ths
FLOAT_OP(n ## name1 ## name2, ps)   \
2056 fbcc6828 ths
{                                   \
2057 fbcc6828 ths
    FST0 = float32_ ## name1 (FST0, FST1, &env->fp_status);    \
2058 fbcc6828 ths
    FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fp_status); \
2059 fbcc6828 ths
    FST2 = float32_ ## name2 (FST0, FST2, &env->fp_status);    \
2060 fbcc6828 ths
    FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fp_status); \
2061 fbcc6828 ths
    FST2 ^= 1 << 31;                \
2062 fbcc6828 ths
    FSTH2 ^= 1 << 31;               \
2063 fbcc6828 ths
    DEBUG_FPU_STATE();              \
2064 fbcc6828 ths
    RETURN();                       \
2065 fbcc6828 ths
}
2066 fbcc6828 ths
FLOAT_NTERNOP(mul, add)
2067 fbcc6828 ths
FLOAT_NTERNOP(mul, sub)
2068 fbcc6828 ths
#undef FLOAT_NTERNOP
2069 fbcc6828 ths
2070 6ea83fed bellard
/* unary operations, modifying fp status  */
2071 6ea83fed bellard
#define FLOAT_UNOP(name)  \
2072 6ea83fed bellard
FLOAT_OP(name, d)         \
2073 6ea83fed bellard
{                         \
2074 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0, &env->fp_status);   \
2075 6ea83fed bellard
    DEBUG_FPU_STATE();    \
2076 fbcc6828 ths
    RETURN();                      \
2077 6ea83fed bellard
}                         \
2078 6ea83fed bellard
FLOAT_OP(name, s)         \
2079 6ea83fed bellard
{                         \
2080 6ea83fed bellard
    FST2 = float32_ ## name(FST0, &env->fp_status);   \
2081 6ea83fed bellard
    DEBUG_FPU_STATE();    \
2082 57fa1fb3 ths
    RETURN();             \
2083 6ea83fed bellard
}
2084 6ea83fed bellard
FLOAT_UNOP(sqrt)
2085 6ea83fed bellard
#undef FLOAT_UNOP
2086 6ea83fed bellard
2087 6ea83fed bellard
/* unary operations, not modifying fp status  */
2088 6ea83fed bellard
#define FLOAT_UNOP(name)  \
2089 6ea83fed bellard
FLOAT_OP(name, d)         \
2090 6ea83fed bellard
{                         \
2091 6ea83fed bellard
    FDT2 = float64_ ## name(FDT0);   \
2092 6ea83fed bellard
    DEBUG_FPU_STATE();    \
2093 fbcc6828 ths
    RETURN();             \
2094 6ea83fed bellard
}                         \
2095 6ea83fed bellard
FLOAT_OP(name, s)         \
2096 6ea83fed bellard
{                         \
2097 6ea83fed bellard
    FST2 = float32_ ## name(FST0);   \
2098 6ea83fed bellard
    DEBUG_FPU_STATE();    \
2099 fbcc6828 ths
    RETURN();             \
2100 5a5012ec ths
}                         \
2101 5a5012ec ths
FLOAT_OP(name, ps)        \
2102 5a5012ec ths
{                         \
2103 5a5012ec ths
    FST2 = float32_ ## name(FST0);   \
2104 5a5012ec ths
    FSTH2 = float32_ ## name(FSTH0); \
2105 5a5012ec ths
    DEBUG_FPU_STATE();    \
2106 fbcc6828 ths
    RETURN();             \
2107 6ea83fed bellard
}
2108 6ea83fed bellard
FLOAT_UNOP(abs)
2109 6ea83fed bellard
FLOAT_UNOP(chs)
2110 6ea83fed bellard
#undef FLOAT_UNOP
2111 6ea83fed bellard
2112 6ea83fed bellard
FLOAT_OP(mov, d)
2113 6ea83fed bellard
{
2114 6ea83fed bellard
    FDT2 = FDT0;
2115 6ea83fed bellard
    DEBUG_FPU_STATE();
2116 6ea83fed bellard
    RETURN();
2117 6ea83fed bellard
}
2118 6ea83fed bellard
FLOAT_OP(mov, s)
2119 6ea83fed bellard
{
2120 6ea83fed bellard
    FST2 = FST0;
2121 6ea83fed bellard
    DEBUG_FPU_STATE();
2122 6ea83fed bellard
    RETURN();
2123 6ea83fed bellard
}
2124 5a5012ec ths
FLOAT_OP(mov, ps)
2125 5a5012ec ths
{
2126 5a5012ec ths
    FST2 = FST0;
2127 5a5012ec ths
    FSTH2 = FSTH0;
2128 5a5012ec ths
    DEBUG_FPU_STATE();
2129 5a5012ec ths
    RETURN();
2130 5a5012ec ths
}
2131 5a5012ec ths
FLOAT_OP(alnv, ps)
2132 5a5012ec ths
{
2133 5a5012ec ths
    switch (T0 & 0x7) {
2134 5a5012ec ths
    case 0:
2135 5a5012ec ths
        FST2 = FST0;
2136 5a5012ec ths
        FSTH2 = FSTH0;
2137 5a5012ec ths
        break;
2138 5a5012ec ths
    case 4:
2139 5a5012ec ths
#ifdef TARGET_WORDS_BIGENDIAN
2140 5a5012ec ths
        FSTH2 = FST0;
2141 5a5012ec ths
        FST2 = FSTH1;
2142 5a5012ec ths
#else
2143 5a5012ec ths
        FSTH2 = FST1;
2144 5a5012ec ths
        FST2 = FSTH0;
2145 5a5012ec ths
#endif
2146 5a5012ec ths
        break;
2147 5a5012ec ths
    default: /* unpredictable */
2148 5a5012ec ths
        break;
2149 5a5012ec ths
    }
2150 5a5012ec ths
    DEBUG_FPU_STATE();
2151 5a5012ec ths
    RETURN();
2152 5a5012ec ths
}
2153 6ea83fed bellard
2154 6ea83fed bellard
#ifdef CONFIG_SOFTFLOAT
2155 6ea83fed bellard
#define clear_invalid() do {                                \
2156 6ea83fed bellard
    int flags = get_float_exception_flags(&env->fp_status); \
2157 6ea83fed bellard
    flags &= ~float_flag_invalid;                           \
2158 6ea83fed bellard
    set_float_exception_flags(flags, &env->fp_status);      \
2159 6ea83fed bellard
} while(0)
2160 6ea83fed bellard
#else
2161 6ea83fed bellard
#define clear_invalid() do { } while(0)
2162 6ea83fed bellard
#endif
2163 6ea83fed bellard
2164 6ea83fed bellard
extern void dump_fpu_s(CPUState *env);
2165 6ea83fed bellard
2166 fd4a04eb ths
#define CMP_OP(fmt, op)                                \
2167 fd4a04eb ths
void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void)       \
2168 fd4a04eb ths
{                                                      \
2169 fd4a04eb ths
    CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \
2170 fd4a04eb ths
    DEBUG_FPU_STATE();                                 \
2171 fd4a04eb ths
    RETURN();                                          \
2172 fd4a04eb ths
}                                                      \
2173 fd4a04eb ths
void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void)    \
2174 fd4a04eb ths
{                                                      \
2175 fd4a04eb ths
    CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \
2176 fd4a04eb ths
    DEBUG_FPU_STATE();                                 \
2177 fd4a04eb ths
    RETURN();                                          \
2178 fd4a04eb ths
}
2179 fd4a04eb ths
#define CMP_OPS(op)   \
2180 fd4a04eb ths
CMP_OP(d, op)         \
2181 fd4a04eb ths
CMP_OP(s, op)         \
2182 fd4a04eb ths
CMP_OP(ps, op)
2183 fd4a04eb ths
2184 fd4a04eb ths
CMP_OPS(f)
2185 fd4a04eb ths
CMP_OPS(un)
2186 fd4a04eb ths
CMP_OPS(eq)
2187 fd4a04eb ths
CMP_OPS(ueq)
2188 fd4a04eb ths
CMP_OPS(olt)
2189 fd4a04eb ths
CMP_OPS(ult)
2190 fd4a04eb ths
CMP_OPS(ole)
2191 fd4a04eb ths
CMP_OPS(ule)
2192 fd4a04eb ths
CMP_OPS(sf)
2193 fd4a04eb ths
CMP_OPS(ngle)
2194 fd4a04eb ths
CMP_OPS(seq)
2195 fd4a04eb ths
CMP_OPS(ngl)
2196 fd4a04eb ths
CMP_OPS(lt)
2197 fd4a04eb ths
CMP_OPS(nge)
2198 fd4a04eb ths
CMP_OPS(le)
2199 fd4a04eb ths
CMP_OPS(ngt)
2200 fd4a04eb ths
#undef CMP_OPS
2201 fd4a04eb ths
#undef CMP_OP
2202 6ea83fed bellard
2203 6ea83fed bellard
void op_bc1f (void)
2204 6ea83fed bellard
{
2205 fd4a04eb ths
    T0 = !!(~GET_FP_COND(env) & (0x1 << PARAM1));
2206 5a5012ec ths
    DEBUG_FPU_STATE();
2207 5a5012ec ths
    RETURN();
2208 5a5012ec ths
}
2209 fd4a04eb ths
void op_bc1any2f (void)
2210 5a5012ec ths
{
2211 fd4a04eb ths
    T0 = !!(~GET_FP_COND(env) & (0x3 << PARAM1));
2212 5a5012ec ths
    DEBUG_FPU_STATE();
2213 5a5012ec ths
    RETURN();
2214 5a5012ec ths
}
2215 fd4a04eb ths
void op_bc1any4f (void)
2216 5a5012ec ths
{
2217 fd4a04eb ths
    T0 = !!(~GET_FP_COND(env) & (0xf << PARAM1));
2218 6ea83fed bellard
    DEBUG_FPU_STATE();
2219 6ea83fed bellard
    RETURN();
2220 6ea83fed bellard
}
2221 6ea83fed bellard
2222 6ea83fed bellard
void op_bc1t (void)
2223 6ea83fed bellard
{
2224 fd4a04eb ths
    T0 = !!(GET_FP_COND(env) & (0x1 << PARAM1));
2225 5a5012ec ths
    DEBUG_FPU_STATE();
2226 5a5012ec ths
    RETURN();
2227 5a5012ec ths
}
2228 fd4a04eb ths
void op_bc1any2t (void)
2229 5a5012ec ths
{
2230 fd4a04eb ths
    T0 = !!(GET_FP_COND(env) & (0x3 << PARAM1));
2231 5a5012ec ths
    DEBUG_FPU_STATE();
2232 5a5012ec ths
    RETURN();
2233 5a5012ec ths
}
2234 fd4a04eb ths
void op_bc1any4t (void)
2235 5a5012ec ths
{
2236 fd4a04eb ths
    T0 = !!(GET_FP_COND(env) & (0xf << PARAM1));
2237 6ea83fed bellard
    DEBUG_FPU_STATE();
2238 6ea83fed bellard
    RETURN();
2239 6ea83fed bellard
}
2240 6ea83fed bellard
2241 6af0bf9c bellard
void op_tlbwi (void)
2242 6af0bf9c bellard
{
2243 29929e34 ths
    CALL_FROM_TB0(env->do_tlbwi);
2244 6af0bf9c bellard
    RETURN();
2245 6af0bf9c bellard
}
2246 6af0bf9c bellard
2247 6af0bf9c bellard
void op_tlbwr (void)
2248 6af0bf9c bellard
{
2249 29929e34 ths
    CALL_FROM_TB0(env->do_tlbwr);
2250 6af0bf9c bellard
    RETURN();
2251 6af0bf9c bellard
}
2252 6af0bf9c bellard
2253 6af0bf9c bellard
void op_tlbp (void)
2254 6af0bf9c bellard
{
2255 29929e34 ths
    CALL_FROM_TB0(env->do_tlbp);
2256 6af0bf9c bellard
    RETURN();
2257 6af0bf9c bellard
}
2258 6af0bf9c bellard
2259 6af0bf9c bellard
void op_tlbr (void)
2260 6af0bf9c bellard
{
2261 29929e34 ths
    CALL_FROM_TB0(env->do_tlbr);
2262 6af0bf9c bellard
    RETURN();
2263 6af0bf9c bellard
}
2264 6af0bf9c bellard
2265 6af0bf9c bellard
/* Specials */
2266 6f5b89a0 ths
#if defined (CONFIG_USER_ONLY)
2267 6f5b89a0 ths
void op_tls_value (void)
2268 6f5b89a0 ths
{
2269 5a5012ec ths
    T0 = env->tls_value;
2270 6f5b89a0 ths
}
2271 6f5b89a0 ths
#endif
2272 6f5b89a0 ths
2273 6af0bf9c bellard
void op_pmon (void)
2274 6af0bf9c bellard
{
2275 6af0bf9c bellard
    CALL_FROM_TB1(do_pmon, PARAM1);
2276 7a387fff ths
    RETURN();
2277 7a387fff ths
}
2278 7a387fff ths
2279 7a387fff ths
void op_di (void)
2280 7a387fff ths
{
2281 7a387fff ths
    T0 = env->CP0_Status;
2282 4de9b249 ths
    env->CP0_Status = T0 & ~(1 << CP0St_IE);
2283 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2284 7a387fff ths
    RETURN();
2285 7a387fff ths
}
2286 7a387fff ths
2287 7a387fff ths
void op_ei (void)
2288 7a387fff ths
{
2289 7a387fff ths
    T0 = env->CP0_Status;
2290 4de9b249 ths
    env->CP0_Status = T0 | (1 << CP0St_IE);
2291 4de9b249 ths
    CALL_FROM_TB1(cpu_mips_update_irq, env);
2292 7a387fff ths
    RETURN();
2293 6af0bf9c bellard
}
2294 6af0bf9c bellard
2295 6af0bf9c bellard
void op_trap (void)
2296 6af0bf9c bellard
{
2297 6af0bf9c bellard
    if (T0) {
2298 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_TRAP);
2299 6af0bf9c bellard
    }
2300 6af0bf9c bellard
    RETURN();
2301 6af0bf9c bellard
}
2302 6af0bf9c bellard
2303 4ad40f36 bellard
void op_debug (void)
2304 4ad40f36 bellard
{
2305 7a387fff ths
    CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
2306 7a387fff ths
    RETURN();
2307 4ad40f36 bellard
}
2308 4ad40f36 bellard
2309 6af0bf9c bellard
void op_set_lladdr (void)
2310 6af0bf9c bellard
{
2311 6af0bf9c bellard
    env->CP0_LLAddr = T2;
2312 7a387fff ths
    RETURN();
2313 6af0bf9c bellard
}
2314 6af0bf9c bellard
2315 f41c52f1 ths
void debug_pre_eret (void);
2316 f41c52f1 ths
void debug_post_eret (void);
2317 6af0bf9c bellard
void op_eret (void)
2318 6af0bf9c bellard
{
2319 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2320 f41c52f1 ths
        CALL_FROM_TB0(debug_pre_eret);
2321 24c7b0e3 ths
    if (env->CP0_Status & (1 << CP0St_ERL)) {
2322 6af0bf9c bellard
        env->PC = env->CP0_ErrorEPC;
2323 24c7b0e3 ths
        env->CP0_Status &= ~(1 << CP0St_ERL);
2324 51e11d9e bellard
    } else {
2325 6af0bf9c bellard
        env->PC = env->CP0_EPC;
2326 24c7b0e3 ths
        env->CP0_Status &= ~(1 << CP0St_EXL);
2327 51e11d9e bellard
    }
2328 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2329 24c7b0e3 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2330 24c7b0e3 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2331 24c7b0e3 ths
        (env->CP0_Status & (1 << CP0St_UM)))
2332 24c7b0e3 ths
        env->hflags |= MIPS_HFLAG_UM;
2333 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2334 f41c52f1 ths
        CALL_FROM_TB0(debug_post_eret);
2335 6af0bf9c bellard
    env->CP0_LLAddr = 1;
2336 7a387fff ths
    RETURN();
2337 6af0bf9c bellard
}
2338 6af0bf9c bellard
2339 6af0bf9c bellard
void op_deret (void)
2340 6af0bf9c bellard
{
2341 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2342 f41c52f1 ths
        CALL_FROM_TB0(debug_pre_eret);
2343 6af0bf9c bellard
    env->PC = env->CP0_DEPC;
2344 24c7b0e3 ths
    env->hflags |= MIPS_HFLAG_DM;
2345 24c7b0e3 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2346 24c7b0e3 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2347 24c7b0e3 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2348 24c7b0e3 ths
        (env->CP0_Status & (1 << CP0St_UM)))
2349 24c7b0e3 ths
        env->hflags |= MIPS_HFLAG_UM;
2350 f41c52f1 ths
    if (loglevel & CPU_LOG_EXEC)
2351 f41c52f1 ths
        CALL_FROM_TB0(debug_post_eret);
2352 24c7b0e3 ths
    env->CP0_LLAddr = 1;
2353 7a387fff ths
    RETURN();
2354 7a387fff ths
}
2355 7a387fff ths
2356 7a387fff ths
void op_rdhwr_cpunum(void)
2357 7a387fff ths
{
2358 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2359 97428a4d ths
        (env->CP0_HWREna & (1 << 0)) ||
2360 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2361 1579a72e ths
        T0 = env->CP0_EBase & 0x3ff;
2362 7a387fff ths
    else
2363 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2364 7a387fff ths
    RETURN();
2365 7a387fff ths
}
2366 7a387fff ths
2367 7a387fff ths
void op_rdhwr_synci_step(void)
2368 7a387fff ths
{
2369 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2370 97428a4d ths
        (env->CP0_HWREna & (1 << 1)) ||
2371 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2372 1579a72e ths
        T0 = env->SYNCI_Step;
2373 7a387fff ths
    else
2374 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2375 7a387fff ths
    RETURN();
2376 7a387fff ths
}
2377 7a387fff ths
2378 7a387fff ths
void op_rdhwr_cc(void)
2379 7a387fff ths
{
2380 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2381 97428a4d ths
        (env->CP0_HWREna & (1 << 2)) ||
2382 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2383 1579a72e ths
        T0 = env->CP0_Count;
2384 7a387fff ths
    else
2385 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2386 7a387fff ths
    RETURN();
2387 7a387fff ths
}
2388 7a387fff ths
2389 7a387fff ths
void op_rdhwr_ccres(void)
2390 7a387fff ths
{
2391 1579a72e ths
    if (!(env->hflags & MIPS_HFLAG_UM) ||
2392 97428a4d ths
        (env->CP0_HWREna & (1 << 3)) ||
2393 1579a72e ths
        (env->CP0_Status & (1 << CP0St_CU0)))
2394 1579a72e ths
        T0 = env->CCRes;
2395 7a387fff ths
    else
2396 1579a72e ths
        CALL_FROM_TB1(do_raise_exception, EXCP_RI);
2397 1579a72e ths
    RETURN();
2398 1579a72e ths
}
2399 1579a72e ths
2400 6af0bf9c bellard
void op_save_state (void)
2401 6af0bf9c bellard
{
2402 6af0bf9c bellard
    env->hflags = PARAM1;
2403 6af0bf9c bellard
    RETURN();
2404 6af0bf9c bellard
}
2405 6af0bf9c bellard
2406 6af0bf9c bellard
void op_save_pc (void)
2407 6af0bf9c bellard
{
2408 6af0bf9c bellard
    env->PC = PARAM1;
2409 6af0bf9c bellard
    RETURN();
2410 6af0bf9c bellard
}
2411 6af0bf9c bellard
2412 16c00cb2 ths
void op_interrupt_restart (void)
2413 16c00cb2 ths
{
2414 16c00cb2 ths
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
2415 16c00cb2 ths
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
2416 16c00cb2 ths
        !(env->hflags & MIPS_HFLAG_DM) &&
2417 16c00cb2 ths
        (env->CP0_Status & (1 << CP0St_IE)) &&
2418 16c00cb2 ths
        (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
2419 16c00cb2 ths
        env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
2420 16c00cb2 ths
        CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT);
2421 16c00cb2 ths
    }
2422 16c00cb2 ths
    RETURN();
2423 16c00cb2 ths
}
2424 16c00cb2 ths
2425 6af0bf9c bellard
void op_raise_exception (void)
2426 6af0bf9c bellard
{
2427 6af0bf9c bellard
    CALL_FROM_TB1(do_raise_exception, PARAM1);
2428 6af0bf9c bellard
    RETURN();
2429 6af0bf9c bellard
}
2430 6af0bf9c bellard
2431 6af0bf9c bellard
void op_raise_exception_err (void)
2432 6af0bf9c bellard
{
2433 6af0bf9c bellard
    CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
2434 6af0bf9c bellard
    RETURN();
2435 6af0bf9c bellard
}
2436 6af0bf9c bellard
2437 6af0bf9c bellard
void op_exit_tb (void)
2438 6af0bf9c bellard
{
2439 6af0bf9c bellard
    EXIT_TB();
2440 7a387fff ths
    RETURN();
2441 6af0bf9c bellard
}
2442 6af0bf9c bellard
2443 4ad40f36 bellard
void op_wait (void)
2444 4ad40f36 bellard
{
2445 4ad40f36 bellard
    env->halted = 1;
2446 4ad40f36 bellard
    CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
2447 7a387fff ths
    RETURN();
2448 7a387fff ths
}
2449 7a387fff ths
2450 7a387fff ths
/* Bitfield operations. */
2451 7a387fff ths
void op_ext(void)
2452 7a387fff ths
{
2453 7a387fff ths
    unsigned int pos = PARAM1;
2454 7a387fff ths
    unsigned int size = PARAM2;
2455 7a387fff ths
2456 f757d6ff ths
    T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2457 7a387fff ths
    RETURN();
2458 7a387fff ths
}
2459 7a387fff ths
2460 7a387fff ths
void op_ins(void)
2461 7a387fff ths
{
2462 7a387fff ths
    unsigned int pos = PARAM1;
2463 7a387fff ths
    unsigned int size = PARAM2;
2464 f757d6ff ths
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2465 7a387fff ths
2466 171b31e7 ths
    T0 = (T0 & ~mask) | (((uint32_t)T1 << pos) & mask);
2467 7a387fff ths
    RETURN();
2468 7a387fff ths
}
2469 7a387fff ths
2470 7a387fff ths
void op_wsbh(void)
2471 7a387fff ths
{
2472 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
2473 7a387fff ths
    RETURN();
2474 7a387fff ths
}
2475 7a387fff ths
2476 60aa19ab ths
#ifdef TARGET_MIPS64
2477 c570fd16 ths
void op_dext(void)
2478 c570fd16 ths
{
2479 c570fd16 ths
    unsigned int pos = PARAM1;
2480 c570fd16 ths
    unsigned int size = PARAM2;
2481 c570fd16 ths
2482 f757d6ff ths
    T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0);
2483 c570fd16 ths
    RETURN();
2484 c570fd16 ths
}
2485 c570fd16 ths
2486 c570fd16 ths
void op_dins(void)
2487 c570fd16 ths
{
2488 c570fd16 ths
    unsigned int pos = PARAM1;
2489 c570fd16 ths
    unsigned int size = PARAM2;
2490 f757d6ff ths
    target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
2491 c570fd16 ths
2492 171b31e7 ths
    T0 = (T0 & ~mask) | ((T1 << pos) & mask);
2493 c570fd16 ths
    RETURN();
2494 c570fd16 ths
}
2495 c570fd16 ths
2496 7a387fff ths
void op_dsbh(void)
2497 7a387fff ths
{
2498 7a387fff ths
    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
2499 7a387fff ths
    RETURN();
2500 7a387fff ths
}
2501 7a387fff ths
2502 7a387fff ths
void op_dshd(void)
2503 7a387fff ths
{
2504 7a387fff ths
    T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
2505 7a387fff ths
    RETURN();
2506 7a387fff ths
}
2507 c570fd16 ths
#endif
2508 7a387fff ths
2509 7a387fff ths
void op_seb(void)
2510 7a387fff ths
{
2511 7a387fff ths
    T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
2512 7a387fff ths
    RETURN();
2513 7a387fff ths
}
2514 7a387fff ths
2515 7a387fff ths
void op_seh(void)
2516 7a387fff ths
{
2517 7a387fff ths
    T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;
2518 7a387fff ths
    RETURN();
2519 4ad40f36 bellard
}